Digital Electronics: CT 304N

Unit – 3
Combinational Logic Circuit
Dr. Anand J. Patel
Index

• Introduction
Design procedure of combinational logic
Adder
• Half Adder
• Full Adder
Subtractor
• Half Subtractor
• Full Subtractor
Code Conversion
• BCD – Excess-3 conversion
Introduction

• Logic Circuit can be classified into:

1.Combinational logic circuit
2.Sequential logic circuit
Combinational logic circuit

• Combinational logic circuits, the output at any time depend on the

input at that instant only.
• It does not depend on past condition.
• There is no delay between the input and the output except the
propagation delay.
• E.g. Subtractor, Adder, Comparator, Multiplexer,
Encoder, Decoder etc.
Sequential logic circuit

• It has memory element with the logic circuit.

• In this the output depends on the past condition of the output
in addition to the condition of the input at that instant.
• E.g. Flip-flop, Counter, Shift register etc.
Design procedure of combinational logic

• First the Truth Table is prepared.

• K-map is constructed from the Truth table
• Simplification of K-map is made and Boolean function is
written.
• Logic circuit is drawn from Boolean function
Design of combinational digital circuits
• Steps to design a combinational digital circuit:
• From the problem statement derive the truth table
• From the truth table derive the unsimplified logic expression
• Simplify the logic expression
• From the simplified expression draw the logic circuit
• Example: Design a 3-input (A,B,C) digital circuit that will give at its output (X) a logic 1
only if the binary number formed at the input has more ones than zeros.

Inputs Output
A B C X X = å (3, 5, 6, 7)
0 0 0 0 0
1 0 0 1 0 X
BC
2 0 1 0 0 A 00 01 11 10
3 0 1 1 1 0 0 0 1 0
4 1 0 0 0 1 0 1 1 1
5 1 0 1 1
6 1 1 0 1
7 1 1 1 1 X = AC + AB + BC
A B C
Adder

• It is a circuit which adds binary bits.

• There are two types of adder circuits.
1. Half Adder
2. Full Adder
Half Adder

• Definition: A Half Adder adds two binary bits.

• Block diagram of Half Adder as shown above.
• There are two input terminal which is indicated by A and B.
• There are two output terminal which is indicated by S and C.
Half Adder (1)

• We will start out simply, adding two single digit binary numbers
• Let’s make certain we can do this by hand before we construct the
circuit
• There are four possible combinations of single digit, two number
addition:
0 + 0 =0
0+1=1
1+0=1
1 + 1 = 10
Half Adder (2)

• Notice that one of the combinations of two single digit

additions is a double digit number, created by a carry:
1 + 1 = 10.
• The truth table are as shown below:

INPUTS OUTPUTS
A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Half Adder (3)

• From the truth table we can write the expression for Sum (S) and Carry (C) .
• For Sum (S) and Carry (C) summing the input combinations for which the output
is 1.
S = A’B + AB’
C = AB
• It is seen that the sum can be realized by EX-OR gate and Carry can be realized by
an AND gate.
•
Half Adder Circuit using A-O-I

• It is seen that the sum is realized by using two NOT gate, two AND gate and one
OR gate and Carry is realized by using AND gate.
Half Adder Circuit using NAND gate

• The Half adder circuit is achieved by using five number of NAND gates.
Half Adder Circuit using NOR gate

• The Half adder circuit is achieved by using five number of NOR gates.
Full Adder

• Definition: It adds three binary bits. The two binary bits are inputs(A,B) and one is
previous carry (C in).
• From the block diagram:
• There are three inputs which is indicated by A, B and Cin.
• There are two outputs which is indicated by Sum(S) and Carry (Cout).
Truth table for full adder

INPUTS OUTPUTS
A B CIN COUT S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Simplified expressions

Full-adder:
A B C S Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
Carry= A.C+A.B+B.C
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

S=A.B’.C’ + A’.B’.C+A.B.C+A’.B.C’
Full Adder

• From the truth table we can write the expression for Sum and Carry.
• For sum (S) summing up the input combination for which the output is 1.

S=
• Similarly we can write the expression for Cout

Cout = AB + BCin + ACin

Circuit of full adder

• In this a three input EX-OR gate is used to realize the sum. To realize
carry, three 2 input AND gates and one 3 input OR gate is used.
Full Adder circuit using two Half Adders

• In this circuit two EX-OR gates, two AND gates and one OR is used.
Full Adder circuit using A-O-I

It is seen that the

circuit uses the basic
gates i.e. A-O-I gates.
Full Adder circuit using NAND gate

We can realize the

circuit of full adder
also by using the
NAND gates.
4 bit parallel binary adder

• We have to make sum of A3 A2 A1 A0 and B3 B2 B1 B0.

• To add A0 and B0 half adder is sufficient as there is no carry signal to
be added.
• To add A0 and B0 a full adder is used in that case Cin input should be
grounded.
4 bit parallel binary adder
4 bit parallel binary adder

• Two signals come out of the full adder. One is the sum signal S0 and
other is the carry signal C1(Cin).
• Full adder are used to add A1 and B1, A2 and B2 & A3 and B3.
• In this case the carry signal from the previous stage is added .
• Carry from A3 is taken out .
• Thus S3 S2 S1 S0 is the sum and C4 (Cin) is the final carry.
4 bit parallel binary adder-IC 7483
• It has 4-bit binary inputs A3 A2 A1 A0 and B3 B2 B1 B0. There is
also carry input Cin from the previous stage. The output is the sum S3
S2 S1 S0 and the carry is Cout.

AUGEND SUM
DIGITS IN
BINARY
ADDED FORM
DIGITS
Half Subtractor

• Definition: It subtracts two binary bits.

• Block diagram of Half Subtractor as shown.
• There are two input terminal which is indicated by A and B.
• There are two output terminal which is indicated by Bo and D.
Truth Table for half Subtractor

• From the truth table:

• We can write the expression for difference D and borrow Bo.
• D = AB’ + A’B
• Bo = A’B
Logic Diagram of half subtractor

• In this circuit, one EX-OR gate, one NOT gate and One AND gate are
used.
• Difference is realized with the help of EX-OR gate & borrow is
realized with the help of NOT gate and AND gate.
Half subtractor using A-O-I

• Logic circuit for half subtractor can also be realized using the basic
gates i.e. A-O-I gates.
Full Subtractor

• There are three input terminals and two output terminals.

• One input is A from which the second input B has to be subtracted.
Bin is the borrow from the previous stage.
• One output is difference D and the other output is Borrow output Bo.
Truth table for Full Subtractor

• From the truth table:

• We can write the expression for difference D and borrow Bo as
follows.
D=
Bo = A’B + A’Bi + BBi
Logic circuit for full subtractor

• Difference is realized by using EX-OR gate.

• Borrow is realized by using three numbers of two input AND gate, one
NOT gate and one 3 input OR gate.
Full Subtractor using two Half Subtractors

• We can realized full subtractor using two half subtractors.

• From the truth table:
• We can write the expression for difference D and borrow Bo as
follows:
D=
Bo = Bi [ ]’ + A’B
Full subtractor using A-O-I gates.

• A full subtractor can

also be realized by
using the three
basic gates i.e. AND,
OR and NOT
(INVERT) gates.
Full subtractor using NAND gates.

• A full subtractor
can also be realized
by using the
NAND gates only.
4- bit parallel binary subtractor
4- bit parallel binary subtractor

• We have to make difference of A3 A2 A1 A0 and B3 B2 B1 B0.

• To subtract A0 and B0 half Subtractor is sufficient as there is no borrow
signal.
• To subtract A0 and B0 a full subtractor is used in that case Bi input should
be grounded(0).
• Full subtractor are used to subtract A1 and B1, A2 and B2 & A3 and B3.
• Two signals come out of the full subtractor. One is the difference signal D
and other is the Borrow signal Bo.
• In this case the borrow signal from the previous stage is subtracted. Borrow
is taken out. Thus D3 D2 D1 D0 is the difference and B4 (Borrow) is the
final borrow.
Code Converters

• There are many types of codes used in digital circuits. Many a times it
becomes necessary to convert data from one type of code to another
type of code. So there will be many types of code converters.
BCD to Excess-3 Code Converter Design procedure
1. Table4-2 is a Code-Conversion example, first, we can
list the relation of the BCD and Excess-3 codes in the
truth table.
Karnaugh map
2. For each symbol of the Excess-3 code, we use 1’s to
draw the map for simplifying Boolean function.
Circuit implementation
z = D’; y = CD + C’D’ = CD + (C + D)’
x = B’C + B’D + BC’D’ = B’(C + D) + B(C + D)’
w = A + BC + BD = A + B(C + D)
 BCD Arithmetic
Given a BCD code, we use binary arithmetic to add the digits:
8 1000 Eight
+5 +0101 Plus 5
13 1101 is 13 (> 9)
Note that the result is MORE THAN 9, so must be represented by two digits!
To correct the digit, subtract 10 by adding 6 modulo 16.
8 1000 Eight
+5 +0101 Plus 5
13 1101 is 13 (> 9)
+0110 so add 6
carry = 1 0011 leaving 3 + cy
0001 | 0011 Final answer (two digits)
If the digit sum is > 9, add one to the next significant digit
Warning: Conversion or Coding?

• Do NOT mix up conversion of a decimal number to a binary number

with coding a decimal number with a BINARY CODE.
• 1310 = 11012 (This is conversion)
• 13  0001|0011 (This is coding)
Decimal adder
BCD adder can’t exceed 9 on each input digit. K is the carry.
Rules of BCD adder
• When the binary sum is greater than 1001, we obtain a non-valid
BCD representation.

• The addition of binary 6(0110) to the binary sum converts it to the

correct BCD representation and also produces an output carry as
required.

• To distinguish them from binary 1000 and 1001, which also have a
1 in position Z8, we specify further that either Z4 or Z2 must have a
1.
C = K + Z8Z4 + Z8Z2
Implementation of BCD adder
• A decimal parallel
adder that adds n
decimal digits needs n
BCD adder stages.

• The output carry from

one stage must be
If =1
connected to the input
carry of the next
0110
higher-order stage.
Binary multiplier
• Usually there are more bits in the partial products and it is necessary to use full
adders to produce the sum of the partial products.

And
 4-bit by 3-bit binary multiplier
• For J multiplier bits and K multiplicand bits
we need (J X K) AND gates and (J − 1) K-bit
adders to produce a product of J+K bits.

• K=4 and J=3, we need 12 AND gates and

two 4-bit adders.
Magnitude comparator
• The equality relation of each pair
of bits can be expressed logically
with an exclusive-NOR function as:

A = A3A2A1A0 ; B = B3B2B1B0

xi=AiBi+Ai’Bi’ for i = 0, 1, 2, 3

(A = B) = x3x2x1x0
Magnitude comparator
• We inspect the relative magnitudes
of pairs of MSB. If equal, we
compare the next lower significant
pair of digits until a pair of unequal
digits is reached.

• If the corresponding digit of A is 1

and that of B is 0, we conclude that
A>B.

(A>B)=
A3B’3+x3A2B’2+x3x2A1B’1+x3x2x1A0B’0
(A<B)=
A’3B3+x3A’2B2+x3x2A’1B1+x3x2x1A’0B0
Decoders
• The decoder is called n-to-m-line decoder, where m≤2n .

• the decoder is also used in conjunction with other code converters

such as a BCD-to-seven_segment decoder.

• 3-to-8 line decoder: For each possible input combination, there are
seven outputs that are equal to 0 and only one that is equal to 1.
Implementation and truth table
Decoder with enable input
• Some decoders are constructed with NAND gates, it becomes more
economical to generate the decoder minterms in their
complemented form.
• As indicated by the truth table , only one output can be equal to 0
at any given time, all other outputs are equal to 1.
Demultiplexer
• A decoder with an enable input is referred to as a
decoder/demultiplexer.
• The truth table of demultiplexer is the same with decoder.
A B

D0

Demultiplexer D1
E
D2
D3
3-to-8 decoder with enable implement the 4-to-16
decoder
 Implementation of a Full Adder with a Decoder
• From table 4-4, we obtain the functions for the combinational circuit in sum of minterms:
S(x, y, z) = ∑(1, 2, 4, 7)
C(x, y, z) = ∑(3, 5, 6, 7)
Application of decoder
• It is used to convert the binary count into decimal digit in decade
counter.

• It is useful in analog to digital converter.

• It is used in computer and microprocessor for activating the address

code of memory location.

• It is used in output device like printer, modem, scanner, disk drive of

computer system.
Encoders
• Binary code of N digits can be used to store 2N distinct elements of coded
information.
• This is what encoders and decoders are used for.
• Encoders convert 2N lines of input into a code of N bits and
• Decoders decode the N bits into 2N lines.
• An encoder is the inverse operation of a decoder.
• An encoder is a combinational circuit that converts binary information in
the form of a 2N input lines into N output lines, which represent N bit code
for the input.
• For simple encoders, it is assumed that only one input line is active at a
time.
Octal to binary encoder
• We can derive the Boolean functions by table 4-7
z = D1 + D3 + D5 + D7
y = D 2 + D3 + D 6 + D 7
x = D 4 + D5 + D 6 + D 7
Octal to binary encoder
Priority encoder
• If two inputs are active simultaneously, the output produces an undefined
combination. We can establish an input priority to ensure that only one input is
encoded.
• Another ambiguity in the octal-to-binary encoder is that an output with all 0’s is
generated when all the inputs are 0; the output is the same as when D0 is equal
to 1.
• The discrepancy tables on Table 4-7 and Table 4-8 can resolve aforesaid condition
by providing one more output to indicate that at least one input is equal to 1.
Priority encoder
V=0no valid inputs
V=1valid inputs

X’s in output columns represent

don’t-care conditions
X’s in the input columns are
useful for representing a truth
table in condensed form.
Instead of listing all 16
minterms of four variables.
4-input priority encoder
0
• Implementation of 0
table 4-8 0
0
x = D2 + D3
y = D3 + D1D’2
V = D 0 + D 1 + D2 + D 3
Application of encoder

• Any digital system works in binary system. When external data to be

given is not in binary form, it is necessary to convert it into binary.

• Encoder are used in the input system of digital computer,

microprocessor, calculator etc.
Multiplexers
S = 0, Y = I0 Truth Table S Y Y = S’I0 + SI1
S = 1, Y = I1 0 I0
1 I1
4-to-1 Line Multiplexer
Quadruple 2-to-1 Line Multiplexer
• Multiplexer circuits can be combined with common selection inputs to provide
multiple-bit selection logic. Compare with Fig4-24.

I0 Y

I1
Boolean function implementation
• A more efficient method for implementing a Boolean function of n
variables with a multiplexer that has n-1 selection inputs.
F(x, y, z) = (1,2,6,7)
 4-input function with a multiplexer
F(A, B, C, D) = (1, 3, 4, 11, 12, 13, 14, 15)
Three-State Gates
• A multiplexer can be constructed with three-state gates.
Three-State Gates
• A multiplexer can be constructed with three-state gates—digital
circuits that exhibit three states.
• Two of the states are signals equivalent to logic 1 and logic 0 as in a
conventional gate.
• The third state is a high-impedance state in which:
(1) the logic behaves like an open circuit, which means that the output
appears to be disconnected,
(2) the circuit has no logic significance, and
(3) the circuit connected to the output of the three-state gate is not
affected by the inputs to the gate.
Multiplexers with three-state gates
Application of Multiplexer
• Data selection and routing

• Controlled sequencer

• Parallel to serial converter

• Logic function and waveform generator.

Example of Combinational Logic Circuits

Design of logic circuit for control of water pumping

Design of building alarm device
The End