Advanced Power Electronic For Wind-Power Generation Buffering (TH., Alejandro Montenegro León)

ADVANCED POWER ELECTRONIC FOR
WIND-POWER GENERATION BUFFERING
By
ALEJANDRO MONTENEGRO LEÓN
A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL

OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY
UNIVERSITY OF FLORIDA
2005
Copyright 2005
by
Alejandro Montenegro León

To my brother
ACKNOWLEDGMENTS
I would like to first express my gratitude to Charles Edwards, the principle
engineer at S&C Electric Co. (Chicago, IL) for his patience and the knowledge he shared
throughout the project. I would also like to acknowledge Kenneth Mattern (manager at
S&C Electric Co., Power Quality Division) for his constant encouragement and
confidence in my ability. I am grateful to S&C Electric Company in general for all of
their contribution and concern.
Additionally, I would like to thank Alexander Domijan (my supervisory committee
chair) for his funding during my graduate studies. My gratitude also goes to my
supervisory committee (Dr. Ngo, Dr. Arroyo, and Dr. Goswami) for all of their time and
effort.
I would furthermore like to acknowledge my family in Spain, for supporting me
and believing in me throughout my stay in the United States. I would finally like to
express my love and gratitude to my girlfriend, Andrea Victoriano, for her help with the
proofreading and for always being the shoulder I could lean on throughout the project
iv
TABLE OF CONTENTS
page
ACKNOWLEDGMENTS ................................................................................................. iv
LIST OF TABLES........................................................................................................... viii
LIST OF FIGURES ........................................................................................................... ix
ABSTRACT.................................................................................................................... xvii
CHAPTER
1 INTRODUCTION ........................................................................................................1
Wind-Energy Outlook ..................................................................................................1

Electrical Issues ............................................................................................................3
Solutions to Wind-Power Fluctuations.........................................................................9
State of the Art..............................................................................................................9
Objective.....................................................................................................................11
2 SYSTEM DESIGN.....................................................................................................14
Introduction.................................................................................................................14
Control Scheme ..........................................................................................................14
Positive Sequence Calculation ............................................................................14
Real Power Calculation Using dq Components ..................................................20
Phase Locked Loop .............................................................................................21
Control Algorithm Design...................................................................................26
Inner regulators ............................................................................................27
Outer regulators............................................................................................35
Per-Unit System Model ..............................................................................................56
Inverter Output-Filter Design ..............................................................................56
Harmonic content .........................................................................................57
Switching frequency.....................................................................................60
Passive filter design......................................................................................61
Passive filter damping ..................................................................................65
Direct-Current Link Capacitor Design ................................................................68
Energy Storage Design ........................................................................................69
Chopper Inductor Design ....................................................................................71
Per-Unit System Model Summary.......................................................................72
Simulated Model.........................................................................................................73
v
3 SYSTEM DESCRIPTION..........................................................................................78
System Overview........................................................................................................78
Electrical Network Model...........................................................................................80
Synchronous Machine .........................................................................................80
Voltage regulation ...............................................................................................81
Prime Mover........................................................................................................81
Synchronous Machine Control Algorithm ..........................................................83
Wind-Farm Model ......................................................................................................87
Wind-Farm Control Algorithm............................................................................90
Wind-Farm Power-Factor Correction..................................................................90
Wind-Farm Soft-Start System .............................................................................94
Power Stabilizer..........................................................................................................97
Power-Stabilizer Hardware Description..............................................................97
Interface board..............................................................................................99
Digital signal processor..............................................................................105
Field-programmable gate array ..................................................................106
Intelligent power module ...........................................................................107
Isolation interface circuit............................................................................108
Power Stabilizer Software Description .............................................................108
Description of DSP program ......................................................................109
FPGA program description ........................................................................114
4 SYSTEM PERFORMANCE ....................................................................................121
System Data ..............................................................................................................121

Power Stabilizer Transient Response .......................................................................121
Direct-Current Link Voltage Control ................................................................121
Reactive Current Control...................................................................................123
Passive Filter Performance .......................................................................................126
Voltage Regulation ...................................................................................................127
System Losses...........................................................................................................128
Power Limiter Results ..............................................................................................130
Power Limiter 1 (High Pass Filter) ...................................................................131
Power Limiter 1 (Adaptive High Pass Filter)....................................................136
Power Limiter 2.................................................................................................138
Power Limiters Comparison Study...........................................................................145
5 SUMMARY..............................................................................................................148
Conclusions...............................................................................................................148
Further Work ............................................................................................................150
APPENDIX
A MATHEMATICAL TRANSFORMATIONS..........................................................151
B MATLAB CODES ...................................................................................................158
vi
C POWER STABILIZER CONTROL MODULES ....................................................168
LIST OF REFERENCES.................................................................................................172
BIOGRAPHICAL SKETCH ...........................................................................................176
vii
LIST OF TABLES
Table page
1-1 Technical specifications of IEC and IEEE ................................................................4
1-2 Wind-farm output-power requirements.....................................................................8
1-3 Large-scale wind-power output-leveling projects...................................................10
1-4 Conceptual wind-power filtering projects...............................................................12
1-5 Basic system configurations....................................................................................13
2-1 Outer regulator assignation .....................................................................................35
2-2 Rate-of-change limits or PPA for a 10 MW wind farm ..........................................47
2-3 Generalized Harmonics of line-to-line voltage .......................................................59
2-4 L filter vs. LCL filter...............................................................................................61
2-5 LCL filter design .....................................................................................................64
2-6 LCL equivalent impedance with damping resistance .............................................65
2-7 Per-unit system........................................................................................................65
2-8 Per-unit system parameters .....................................................................................73
2-9 Designed system results and simulated system results comparison........................76
3-1 Synchronous machine output voltage profile at rated speed...................................82
3-2 Alternatives for the power stabilizer controller.....................................................106
3-3 FPGA code words .................................................................................................120
4-1 System parameters.................................................................................................122
A-1 Mathematical transformations summary ...............................................................157
C-1 Control Modules....................................................................................................168
viii
LIST OF FIGURES
Figure page
1-1 Wind-power output for two wind farms during one month. .....................................5
1-2 Power fluctuation comparison...................................................................................6
1-3 Typical power curve of a wind turbine. ....................................................................6
1-4 Wind-farm output power vs system frequency. ........................................................7
1-5 Control strategies along the power curve ..................................................................8
1-6 Wind-farm generation buffering concept ................................................................13
2-1 Unbalanced system..................................................................................................15
2-2 Space vector trajectory of an unbalanced system in the d-q-o plane ......................16
2-3 Space vector trajectory projection over the d-q plane.............................................16
2-4 Direct and quadrature components of an unbalanced system .................................17
2-5 Representation of an unbalanced system in the frequency domain.........................17
2-6 Positive-sequence extraction algorithm ..................................................................19
2-7 Voltage waveforms for an unbalanced fault event..................................................19
2-8 Response of the positive-sequence extraction algorithm ........................................20
2-9 Distortion of phase angle due to a negative sequence component ..........................22
2-10 PLL diagram............................................................................................................23
2-11 PLL simplified model..............................................................................................24
2-12 PLL system step response .......................................................................................25
2-13 Root locus for two different regulator gains ...........................................................25
2-14 PLL system response to an unbalanced system condition ......................................26
ix
2-15 PLL system response to a frequency excursion ......................................................26
2-16 System description ..................................................................................................27
2-17 Simplified system model .........................................................................................28
2-18 Electrical representation of the dq components ......................................................30
2-19 System model block diagram ..................................................................................30
2-20 Inverter current regulator-system model block diagram .........................................31
2-21 Inverter current regulator-system model simplified block diagram........................32
2-22 Simplified current control diagram .........................................................................32
2-23 Current regulator step response...............................................................................33
2-24 Chopper equivalent system .....................................................................................34
2-25 Chopper current controller ......................................................................................35
2-26 Powers' definition....................................................................................................36
2-27 System model ..........................................................................................................37
2-28 DC link equivalent system block diagram ..............................................................37
2-29 DC link simplified system block diagram...............................................................38
2-30 DC link voltage regulator step response .................................................................38
2-31 Simplified system model .........................................................................................40
2-32 Source impedance voltage drop ..............................................................................41
2-33 Transfer functions of inverter’s quadrature current component..............................42
2-34 Transfer functions of inverter’s direct current component......................................42
2-35 Voltage regulator system block diagram.................................................................44
2-36 Positive sequence extraction algorithm equivalent system .....................................44
2- 37 Voltage regulator detailed block diagram ...............................................................45
2- 38 Voltage regulator simplified control diagram .........................................................45
2- 39 System response to a 5% change in voltage reference............................................45
x
2-40 Adaptive control scheme .........................................................................................46
2-41 Power Regulator general control scheme................................................................47
2-42 Power limiter 1. Control block diagram..................................................................48
2-43 Power limiter 1. Performance using different cut-off frequencies (unlimited

power and energy) ....................................................................................................49
2-44 Power limiter 1. Performance using different cut-off frequencies (Pinverter=1.0

MW and Einverter=±8.5 MJ) .......................................................................................49
2-45 Power limiter 2. Limiters details .............................................................................50
2-47 Power limiter 2. Compensation performance.........................................................51
2-48 Power limiter 2. Inverter response for a sampling time of 2 seconds .....................52
2-49 Power limiter 2. Inverter response for different power ratings. Sampling time 2
seconds .....................................................................................................................53
2-50 Power limiter 2. Inverter response for different ESS sizes. Sampling time 2
seconds .....................................................................................................................53
2-52 Power limiter 3. Compensation performance.........................................................55
2-53 Power limiter 3. Inverter response for a sampling time of 2 seconds .....................55
2-54 Inverter topology ......................................................................................................57
2-55 Line-to-line and line-to-neutral voltage of a three phase inverter...........................57
2-56 RMS Line-to-line voltage harmonic spectrum........................................................58
2-57 Static Synchronous Generator diagram...................................................................59
2-58 LCL filter topology .................................................................................................61
2-59 LCL equivalent block diagram................................................................................62
2-60 Single phase equivalent filter model at the fundamental frequency .......................62
2-61 Single phase equivalent filter model at the hth harmonic ........................................63
2-62 LCL equivalent impedance with damping resistance .............................................66
xi
2-63 Single phase harmonic generator equivalent circuits ..............................................66
2-64 LCL gain frequency response .................................................................................67
2-65 Inverter frequency analysis .....................................................................................67
2-66 Capacitor Voltage vs. Energy Storage ....................................................................70
2-67 ESS-Chopper topology............................................................................................71
2-68 Equivalent circuit for maximum current ripple calculation ....................................72
2-69 System overview .....................................................................................................74
2-70 Per-unit electric system model ................................................................................74
2-71 Power Stabilizer Control Scheme ...........................................................................75
3-1 Equivalent system model ........................................................................................79
3-2 DC gen-set...............................................................................................................83
3-3 Two single quadrant chopper circuit .......................................................................83
3-4 Synchronous generator control system ...................................................................84
3-5 Frequency deviation ................................................................................................85
3-6 DC-GEN set control scheme ...................................................................................85
3-7 System frequency response for Δf=-1Hz ................................................................86
3-8 Frequency control equivalent system ......................................................................87
3-9 Equivalent model frequency response for Δf= - 0.01666 pu ..................................88
3-10 Dynamic model used for transient studies ..............................................................88
3-11 Static model used for steady-state studies...............................................................88
3-12 Wind-farm model ....................................................................................................89
3-13 Wind-farm controller...............................................................................................90
3-14 Wind-farm power regulator & current regulator step response (ΔP=100%) ..........91
3-15 Induction generator PQ curve .................................................................................92
3-16 Wind-farm PF correction capacitor bank ................................................................93
xii
3-17 PF correction capacitor bank current waveforms....................................................93
3-18 Capacitor bank impedance frequency scan .............................................................94
3-19 Machine control scheme operating states................................................................95
3-20 Electric power system start-up ................................................................................96
3-21 Detail of the transition from start-up mode to run mode.........................................96
3-22 Power Stabilizer system overview ..........................................................................97
3-23 Interface board overview.......................................................................................100
3-24 AC voltage scaling circuit (input [-1000+1000V], output [0 +3V]) .....................101
3-25 DC voltage scaling circuit (input [0 +1000V], output [0 +3V]) ...........................101
3-26 CT current scaling circuit (input [-5 +5A], output [0 +3V]).................................101
3-27 LEM current scaling circuit (input [-0.36 +0.36A], output [0 +3V])....................101
3-28 Power supplies’ voltage monitoring......................................................................102
3-29 System’s critical signals during turn on ................................................................103
3-30 System’s critical signals during turn off ...............................................................103
3-31 Darlington drivers .................................................................................................104
3-32 IPM status signals interface circuitry ...................................................................104
3-33 DAC circuit ...........................................................................................................105
3-34 DSP built-in PWM output performance vs. FPGA ...............................................107
3-35 IMP power circuit configuration ...........................................................................108
3-36 Isolated interface board .........................................................................................109
3-38 Power stabilizer control algorithm sampling rates ................................................110
3-37 Interconnections between the different sub-systems of the power stabilizer........111
3-39 Power stabilizer control stages..............................................................................113
3- 40 Power stabilizer start-up sequence ........................................................................113
3-41 FPGA system overview.........................................................................................116
xiii
3-42 Up/Down counter. .................................................................................................117
3-43 PWM generator .....................................................................................................117
3-44 One phase dead-time generator detailed diagram .................................................119
3-45 Dead-time generator’s waveforms ........................................................................119
3-46 Watchdog logic .....................................................................................................120
4-1 DC link voltage response for different Kp gains...................................................121
4-2 DC link voltage response for different Ki gains ...................................................122
4-3 Iqref command step change from -0.5 to 0.5 A per unit. Integral gain effect ........123
4-4 Iqref command step change from -0.5 to 0.5 A per unit. Proportional gain
effect.......................................................................................................................124
4-5 Iq current regulator output for different Kp ..........................................................124
4-6 Iqref command step change from -0.5 to 0.5 and back to -0.5 A per unit ............124
4-7 Power stabilizer harmonic injection response for Ki=18 and Kp=1 .....................125
4-8 Current regulator frequency response ...................................................................126
4-9 Front-end inverter current waveform ....................................................................126
4-10 Frequency spectrum of the LCL currents..............................................................127
4-11 Simplified system description ...............................................................................127
4-12 Power stabilizer voltage regulation performance..................................................128
4-13 Energy storage charge/discharge cycle .................................................................129
4-14 Control scheme with a losses compensation term.................................................129
4-15 Power stabilizer equivalent system .......................................................................130
4-16 Wind-power conditions under study .....................................................................130
4-17 Measured and modeled high pass filter results for Kc=0.0064 W/J,
fcut_off=0.005 Hz ......................................................................................................132
4-19 Measured high pass filter performance for different cut-off frequencies. System
parameters Kc=0.0064 W/J.....................................................................................134
xiv
4-20 Modeled high pass filter performance for different cut-off frequencies. System
parameters Kc=0.0064 W/J.....................................................................................135
4-21 Measured high pass filter performance for different energy storage sizes.
System parameters, Kc=0.0064 W/J, fcut-off=0.005 Hz. ..........................................135
4-22 Cut-off frequency trajectory of the adaptive high pass filter for a given energy
deviation .................................................................................................................136
4-23 Measured adaptive high pass filter performance for different Kf’s. System
parameters, Kc=0.0064 W/J, fcut-off-origin=0.005 Hz.................................................137
4-24 Measured adaptive high pass filter performance for different energy storage
sizes. .......................................................................................................................137
4-25 Multiple sampling concept. ...................................................................................139
4-26. Measured and modeled power limiter 2 results for Kc=0.0064, RR=2
MW/minute, A=0.3 MW/minute, I=1MW/2 seconds fcut-off=0.005 Hz. ................140
4-27 Measured power indexes activity. System parameters: Kc=0.0064 W/J, RR=2
MW/minute, A=0.3 MW/minute, I=1 MW/2 seconds, and fs=10Hz.....................141
4-28 Measured power limiter 2 response to different Kc . System parameters: RR=2

MW/minute, A=0.3 MW/minute, I=1MW/2 seconds, and fs=10Hz......................142
4-29 Measured power limiter 2 response to different ramp rate limits. ........................142
4-30 Measured power limiter 2 response to different average power fluctuation

limits.......................................................................................................................143
4-31 Effect of linear interpolation on the average power fluctuation index activity.
The sampling time of the original wind-power data is 2 seconds ..........................144
4-32 Measured power limiter 2 response to different instantaneous power fluctuation

limits.......................................................................................................................144
4-33 Measured power limiter 2 response to different sampling frequencies.................145
4-34 Measured synchronous machine output power for the different power limiter
control schemes ......................................................................................................146
4-35 Measured synchronous machine output power for the different power limiter
control schemes. .....................................................................................................147
4-36 Frequency regulator output for the different power limiters.................................147
A-1 Relationships among ds-qs, and abc axes .............................................................153
xv
A-2 Stationary ds-qs components in the time domain .....................................................153
A- 3 Relationship among ds-qs and dr-qr axes ...............................................................154
A-4 Direct and quadrature components........................................................................155
A-5 Time domain representation of abc and d-q components .....................................156
xvi
Abstract of Dissertation Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy
ADVANCED POWER ELECTRONIC FOR

WIND-POWER GENERATION BUFFERING
By
Alejandro Montenegro León
May 2005
Chair: Alexander Domijan, Jr

Major Department: Electrical and Computer Engineering
As the cost of installing and operating wind generators has dropped, and the cost of
conventional fossil-fuel-based generation has risen, the economics and political
desirability of more wind-based energy production has increased. High wind-power
penetration levels are thus expected to augment in the near future raising the need for
additional spinning reserve to counteract the effects of wind variations. This solution is
technologically viable, but it has high associated costs. Our study presents a different
solution to short-term wind-power variability, using advanced power electronic devices
combined with energy-storage systems. New control schemes (designed to filter power
swings with a minimum of energy) were designed, modeled and verified through
experimental tests. We also determined the procedure to extract the corresponding per-
unit model parameters for simulations and test purposes.
xvii
We first reviewed D-Q transformations with emphasis on modeling of the system
and control algorithm. System components were then designed using criteria similar to
those used to design medium-voltage power products.
We tested a proof-of-concept for performance of the power converter in a scaled-
down isolated system using real wind-power data. Tests were conducted under realistic
system conditions of wind-penetration level and energy-storage levels, to better
characterized the impacts and benefits of the Power Stabilizer. We described the scaled-
down isolated electric power system used in the testing. We also analyzed the
performance of the wind-farm model and the synchronous machine’s governor to gain an
insight into the model system’s limitations.
Simulation results carried out in Mathematical Laboratory (MATLAB) and Power
Systems Computer Aided Design (PSCAD) were compared to experimental data to verify
the performance of the power converter under different system conditions and algorithms.
Power limiters were also contrasted and evaluated for frequency deviations and
attenuated power fluctuations.
In summary we can say that, among all the power limiters considered in our study,
the adaptive high pass filter presented the best performance in terms of system robustness
and effectiveness.
xviii
CHAPTER 1
INTRODUCTION
Wind-Energy Outlook
Wind power has been used for at least 3000 years, mainly for milling grain,
pumping water, or driving various types of machines. However, the first attempt to use
wind turbines for producing electricity date back to the 19th century. In 1891, Poul La
Cour in Demark built an experimental wind turbine driving a dynamo. The oil crisis of
the 1970s revived interest in wind turbines. Nowadays, the power is the fastest growing
source of energy in the world and its growth rates have exceeded 30% annually over the
past decade [1]. Cumulative global wind-energy generating capacity approached 40,000
MW by the end of 2003 [2]-[3]. The main drivers for developing of the wind industry in
the United States are
• Federal Renewable Energy Policies, particularly the Production Tax Credit (PTC)
that provides a 1.5 cent per kilowatt-hour credit for electricity produced from a
wind farm during the first 10 years of operation. This wind energy PTC expired
December 31, 2003 but will be reinstated through 2005 as part of a major tax
package (H.R. 1308).
• State-level renewable energy initiatives, such as the Renewable Portfolio Standard,

or green pricing.
The Database of State Incentive for Renewable Energy [4] gives more information
on incentives. These government initiatives, together with technological advances, plus
the need for a new source of energy capable of meeting the world’s growing power
demand and the rising prices of conventional fossil fuel-based generation, make the wind
power one of the most promising industries in the future.
1
2
According to the European Wind Energy Association and Greenpeace, no barriers
exist for wind to provide 12% of the world’s electricity by 2020. The American Wind
Energy Association forecasts that wind power will provide 6% of the US’s electricity by
2020 if the wind industry maintains an annual growth rate of 18%.
The positive effects of using such types of renewable resources are well known.
However, wind-power plants, like all other energy technology, have some drawbacks that
should be mentioned. These problems can be divided into major groups: environmental
issues and interconnection issues.
Environmental issues. Most significant among these are the following:
• Sound from turbines: Some wind turbines built in the early 1980s were very
noisy. However, manufactures have been working on making the turbines quieter.
Today, an operating wind farm at a distance of 750 to 1,000 feet is no noisier than a
moderately quiet room. Research in aero-acoustics is still being carried out to
further reduce noise from wind on the blades.
• Bird death: Wind turbines are often mentioned as a risk to birds, and several
international tests have been performed. The general conclusion is that birds are
seldom bothered by wind turbines. Studies show that for example, overhead power
pole lines are far more hazardous for birds than wind turbines [2].
• Wind-tower shadow effect: Wind turbines, like other tall structures cast a shadow
on the neighboring area when the sun is visible. It may be irritating if the rotor
blades chop the sunlight, causing a flickering effect while the rotor is in motion,
especially when the sun is low in the sky.
Interconnection issues. Connecting wind turbine to operate in parallel with the
electric power system influences the system operating point (load flow, nodal voltages,
power losses, etc). These changes in the electric power system state bring up new system-
integration issues that system operators and power quality engineers must take into
account. These interconnection issues can be divided into operational issues and electrical
issues.
• Operational Issues: These include unit commitment and spinning reserve.

3
− The unit commitment problem is to schedule specific or available

generators (on or off) on the utility system to meet the required loads at a
minimum cost, subject to system constraints. The most conservative
approach to unit commitment and economic dispatch is to discount any
contribution from interconnected wind resources because of wind
variability.
− Operating reserve is further defined to be a spinning or non- spinning

reserve. Any probable load or generation variations that cannot be
forecasted, such as wind power, have to be considered when determining
the amount of operating reserve to carry out.
• Electrical issues: These factors are considered in the next section.
Electrical Issues
Wind-turbine generator-system operation has some negative influence on power
systems. This influence on the electric power system depends on wind variations and on
wind-turbine technology. Impacts on the electric power system can be grouped as
follows:
• Power quality: Voltage variations, flicker, harmonics, power-flow variations

• Voltage and angle stability
• Protection and control
The IEEE 1547 [5] and the IEC 61400-21 [6] standards are the bases to evaluating
the impact of such wind-turbine generation systems on the electric power system.
According to the IEEE 1547 [5, page 2] abstract,
This standard focuses on the technical specifications for, and testing of, the
interconnection itself. It provides requirements relevant to the performance,
operation, testing, safety considerations, and maintenance of the interconnection. It
includes general requirements, response to abnormal conditions, power quality,
islanding, and test specifications and requirements for design, production,
installation evaluation, commissioning, and periodic tests. The stated requirements
are universally needed for interconnection of distributed resources (DR), including
synchronous machines, induction machines, or power inverters/converters and will
be sufficient for most installations. The criteria and requirements are applicable to
all DR technologies, with aggregate capacity of 10 MVA or less at the point of
common coupling, interconnected to electric power systems at typical primary
and/or secondary distribution voltages.
4
According to the IEC 61400-21 [6, page 9] abstract,
The purpose of this part of IEC 61400 is to provide a uniform methodology that
will ensure consistency and accuracy in the measurement and assessment of power
quality characteristics of grid connected wind turbines (WTs). In this respect the
term power quality includes those electric characteristics of the WT that influence
the voltage quality of the grid to which the WT is connected.
This standard provides recommendations for preparing the measurements and

assessment of power quality characteristics of grid connected WTs.
Table 1-1 shows technical specifications for interconnection and power assessment
covered in both standards.
Table 1-1. Technical specifications of IEC and IEEE

Interconnection system
Power quality assessment
response to excursions
IEEE Voltage
Frequency
IEC Voltage Voltage fluctuations:
Frequency Continuous operation
Switching operation
Harmonics
As shown in Table 1-1, both standards overlooked one of the most significant
characteristics of wind farms: its variability (i.e., power fluctuations) [7], the most
important ones being
• Gusty wind variations having a spectrum of frequencies from 1-10 Hz.
• Shadow effect having a spectrum of frequencies from 1-2 Hz and producing torque
variations up to 30%.
• Complex oscillations of the turbine tower, rotor shaft, gear box, and blades with
spectrum frequencies from 2-100 Hz, and creating torque variations up to 10%.
Figure 1-1 shows actual output power data collected by NREL from two large
wind-power plants in the United States. The small wind farm has a capacity of about 35
MW, and the large one has a capacity of 150 MW.

5
40
30
Power (MW)
20
10
0
A
0 0.5 1 1.5 2 2.5 3
Time (s) 6
x 10
Trent Mesa Project. Wind power output May 2003

150
100
Power (MW)
50
0
0 0.5 1 1.5 2 2.5 3
B
Time (s) 6
x 10
Figure 1-1. Wind-power output for two wind farms during one month (May 2003). A)
Nominal capacity 35 MW. B) Nominal capacity 150 MW.
Even though the technology used in constructing the small wind farm is more than
a decade older than the large one, power fluctuations keep being an issue. Figure 1-2 is a
close-up of Figure 1-1 and shows the magnitude of these power fluctuations.
Wind turbine manufactures usually provide power curves (Figure 1-3) to
developers to determine the amount of power that will be transferred into the grid for a
single turbine, given the wind speed. However, those figures represent only the mean
values, since a series of stochastic values cannot be controlled, and create additional
power fluctuations.
Wind-output power fluctuations can have different effects on the electric power
system, but the most significant ones are voltage variation and frequency variation in
small or isolated systems.

6
40 Texas Wind Power Project. Wind power output May 2003

40
30
30
(MW)
(MW)
20
Power
20
Power
10
10
A
0
00 1 2 3 4 5 6 7 8
0 1 2 3 4
Time (s) 5 6 7 8 4
x 10
Time (s) x 10
4
Trent Mesa Project. Wind power output May 2003

80 Trent Mesa Project. Wind power output May 2003
150
70
(MW)
100
(MW)
60
Power
Power
50
50
40
B
0 1 2 3 4 5 6 7 8
0
0 1 2 3 Time
4 (s) 5 6 7 8 x 10
4
Figure 1-2. Power fluctuation comparison. A) Nominal capacity 35 MW. B) Nominal

capacity 150 MW.
Figure 1-3. Typical power curve of a wind turbine.
As the power fluctuates, the reactive power required by the turbines changes as
well, and therefore voltage variations are expected, especially when the wind farm is
7
located at weak points in the system. To compensate for such voltage variations and keep
the voltage close to its rated value, several solutions are available: simple capacitor
banks, static voltage compensator (SVC), or static compensators (STATCOM).
A different approach must be taken for frequency variations due to power
fluctuations. Normally, wind farms connected to big systems do not present a major
problem in terms of frequency variations, because of the stiffness of the system.
However, with small or isolated systems that contain slow or no automatic generation
controls, a mismatch between generated and absorbed power can significantly affect
system frequency unless spinning reserves are significant. Figure 1-4 shows the effect of
wind-power fluctuation on an isolated system with a wind penetration level of 1%.
To counter these negative effects, countries and small isolated systems with high
wind-penetration factors developed special purchase power agreement (PPA)
requirements or indexes for wind-farm developers (Table 1-2).
Figure 1-4. Wind-farm output power vs system frequency.

8
Table 1-2. Wind-farm output-power requirements

Average (max
Ramp Rate dP/dt Instantaneous
variation)
Netherlands <12 MW per min
Denmark <0.1·Pnom per min <0.05 Pnom per
60 sec period
Hawaii <2 MW per min 1 MW change <0.3MW per 60
per 2 sec sec period
scan
Germany <0.1·Pnom per min
Scotland No limit for Pnom<15 MW/min
Pnom/15 for Pnom=[15-150] MW/min
10 MW for Pnom>150 MW per min
These power requirements guarantee minimum impact on system voltage and
frequency control. However, today’s wind farms have limited capacity to reduce the rate
of change of power, especially the down ramp rate.
At high wind speeds (above the rated wind speed), active and stalled pitch controls,
among other strategies, can help keep the output power under control. However, modern
wind turbines are designed to obtain as much power as possible at low wind speeds
(Figure 1-5), making them very vulnerable to wind variations.
Figure 1-5. Control strategies along the power curve

9
Solutions to Wind-Power Fluctuations
To reduce the effects of wind-power variations and meet the PPA requirements for
electric utilities, two solutions can be considered:
• Higher spinning reserves

• Wind farm buffer
Increasing spinning reserves is a costly solution. A better approach would be to use
an energy-storage system that could deliver the required power when needed.
Work has been done in developing large-scale energy storage systems that have
overcome these issues by absorbing undesirable power fluctuations and providing firm,
dependable peaking capacity [8]. However, a less costly solution should be explored
based exclusively on power-fluctuation indexes (such as ramp rate indexes or
instantaneous fluctuation indexes).
State of the Art
Storing wind power is not a new concept; in fact, back in 1900, the father of the
modern wind turbine, Poul La Cour, tackled for the first time the problem of energy
storage. He used the electricity from the wind turbines for electrolysis and to store energy
in the form of hydrogen. However, with time, system requirements, energy storage
systems, and wind turbine ratings have changed.
Nowadays, the average wind turbine installed is around 1 MW, according to the
European Wind Energy Association, and wind-power farms usually consists of ten to
several tens of wind-turbine generators of rated power up to 2 MW. Thus, the amount of
energy storage needed to stabilize the power output change in the short term has
increased. Table 1-3 shows some recent projects dealing with output leveling of wind-
energy conversion.
Table 1-3. Large-scale wind-power output-leveling projects
Active power reference
Project name Wind farm size Energy storage system
control scheme
Subaru Project [9]. 1.65 MW *16 Vanadium–Redox Flow Battery Moving Average of wind farm output
Tomamae wind-power (Vestas). determined as
station. 1.5 MW * 5 PVRB nominal =4.000kW
(Enercon). EVRB=6.000kWh Pbattery=Pwind average (t-Δt)-Pwind(t)
S inverter=6.000kVA (for Δt=8 seconds to 8 hours)
Total Capacity
30.6 MW
King Island [10]. Energy- 250 kW*3 Vanadium–Redox Flow Battery Isochronous frequency mode over the VRB
storage system provided 850 kW*2 power range.
10
by Pinnacle VRB PVRB nominal=200kW Speed droop characteristic during instantaneous
Total Capacity PVRB short-term ( 5 minutes)=300kW and short-term load (>± 200 kW).
2.45 MW PVRB short-term (10 seconds)=400kW
EVRB =1100kWh
Oki project by Fuji 600 kW *3 Flywheel Power ramp rate limiting
Electric
Total Capacity E flywheel = 100 kW - 90 sec
1.8 MW P inverter flywheel side= 110kVA
P inverter power system side= 150kVA
11
However, small-scale concepts and technical/economic feasibility studies have
been proposed (Table 1-4). Each of these projects has a different objective (frequency
control, power smoothing, load leveling, etc.). However, they all end up using one of the
topologies and energy-storage systems shown in Table 1-5, where the flywheel or
capacitors may be replaced by some other energy-storage medium. Tables 1-3 and 1-4
show that the amount of energy needed for wind-power balancing using current
technology and current pricing is so significant, that a more flexible and integrated
approach is needed.
Our study focused on developing new power smoothing control algorithms. The
new integrated approach used a shunt-connected voltage-source converter with added
storage included on the DC link bus. The system can
• Exchange active power with the system.

• Regulate voltage at the point of common coupling
• Increase power quality and system stability
Objective
Our purpose was to develop, simulate, and implement a proof-of-concept prototype
advanced-power electronic device capable of controlling and smoothing the power
fluctuations of a wind farm using an optimal amount of energy. The wind-power
generation buffering concept is shown in Figure 1-6. The Power Stabilizer was designed
to store excess power during periods of increased wind-power generation and release
stored energy during periods of decreased generation due to wind fluctuations.
We tested the performance of the advanced electronic device on
• DC-synchronous machine set

• Passive load
• DC-asynchronous machine set
• Wind-farm buffer or also called Power Stabilizer
Table 1-4. Conceptual wind-power filtering projects
Wind farm size Energy storage system Active power reference control scheme Comments
20 MW Zinc-bromide battery Limiting instantaneous power fluctuations based Technical and economical
on a 2 seconds interval feasibility evaluation
PZBB nominal (charge) =-750kW ΔPinstantaneous (Δt=2 seconds) = ±1.3 MW [11]
PZBB nominal (discharge)=1500kW Average power levels over a 2 hour window
EZBB =1500 kWh Paverage(t- Δt=2hours)= ±200 kW
Maximum power Super-conducting magnetic Active power reference is chosen to control Simulation study [12]
oscillation 2.5 MW energy storage (SMES) system frequency
300kW Electric double layer ESS active power reference is determined by Simulation study [13]
capacitor detection power oscillation components using a
P ECS =100 kW high pass filter
12
E ECS =1.1 kWh
6GW Redox-flow battery Power balancing Feasibility study [14]

(Regenesys )
E=62004 MWh
P=255MW
45KW Flywheel The active power demand is extracted via a 2nd Practical results [15]-[16]
E flywheel= 12MJ order Butterworth high pass filter, with a 5mHz
P drive=45kW bandwidth
55kW Lead Acid Battery Power smoothing Practical results [17]
E battery=35kWh
P converter=50kVA
13
Wind Power Output Wind Power Output

10800 10800
10600 10600
10400 10400
10200
Wind power + Wind farm buffer Power
10200
10000 10000
Power (W)
Power (W)
9800 9800
9600 9600
9400 9400
9200 9200
V47
VRCC
9000 9000
Vestas
8800 8800
0 20 40 60 80 100 120 0 20 40 60 80 100 120
Time (s) Time (s)
L1 A A A A
? ?
L2 B B B B
#2 #1 #2 #1
L3 C C C C
0.69 12.47 12.47 69.0
WIND FARM
Power Stabilier Power Output

600
INVERTER
400
200
1 3 5 5
dcCur
0 2 2 2 2
g1 g3 g5 gc1
Power (W)
A A NAS
-200 ?
VnaS Chopper Reactor
300.0
B B NBS
#1 #2
-400 VnbS 1.0
C C NCS
12.47 0.48
VncS
1.0
-600 Energy Storage
Capacitor
4 6 2 5
2 2 2 2
-800 g4 g6 g2 gc2
-1000
0 20 40 60 80 100 120
Time (s)
Figure 1-6. Wind-farm generation buffering concept
Table 1-5. Basic system configurations

Voltage source inverter
ESS connected at the DC link side [19]-[21]-[24]
Wind Turbine Voltage Source
Electric System
Inverter
DC link
Synchronous Machine
ESS (flywheel)
ESS connected at the AC side [18]-[20]-[22]-[23]-[25]

Wind Turbine Electric System
System configuration Induction Machine
DC link
Voltage Source
Inverter ESS (flywheel)
Current source inverter (shunt connected) [13]

Wind Turbine Electric System
Induction Machine
Chopper (DC/DC
ECS
converter)
Current Source
Inverter ESS (capacitors)
Available options [26]

• Compressed air energy storage
• Battery storage
Energy storage system • Electro-chemical flow cell systems
• Fuel cell/electrolyser/hydrogen systems
• Kinetic energy (flywheel) storage
• Pumping water
CHAPTER 2
SYSTEM DESIGN
Introduction
One of the most difficult tasks when designing a control algorithm for a power
electronic converter is to calculate the regulators’ gains. Determination of the controllers’
parameters is based on the electric power system they are connected to, and also on the
power electronic converter topology. This chapter details the design of the different
regulators involved in the control of the Power Stabilizer and also the design of the
different components that define its topology.
The system design was carried out per unit, so results can be extrapolated to any
system size, to facilitate implementation of the control scheme in a fixed-point digital
signal processor. The system design was also compared to simulation results to assure the
correctness of the design methodology used
Control Scheme
Positive Sequence Calculation
Three-phase systems are not always balanced, especially during fault conditions,
and it is expected to have positive, negative and even zero sequence components.
However, for voltage regulation purposes, only the positive sequence component is of
importance.
Before going into detail on the positive extraction algorithm description, we will
explain first where the transformations given in Appendix A fail in coupling the different
symmetrical components. Consider the following set of phasors
14
15
Va = 0.5∠ 0°
Vb = 1.0 ∠ −120° (2-1)
Vc = 1.0 ∠ −240°
Figure 2-1 shows the time domain representation of this three-phase unbalanced system.
Figure 2-1. Unbalanced system
If we now calculate the symmetrical components of this unbalanced system, we obtain
V1 = 0.833∠ 0°
V2 = 0.167 ∠180° (2-2)
V0 = 0.167 ∠180°
The symmetrical components transformation is a good tool to determine the type of
distortion or asymmetry the system has. However, it has the drawback of having to use
phasors as input instead of time domain signals. Therefore a different transformation was
needed in order to extract the positive sequence component out of the rotating space
vector.
Figure 2-2 shows the trajectory followed by the rotating space vector of the
unbalanced system in the d-q-o plane using Clarke’s transformation. This trajectory is
16
clearly distorted from the ideal one, and the space vector no longer follows a circular path
(Figure 2-3).
Figure 2-2. Space vector trajectory of an unbalanced system in the d-q-o plane
Figure 2-3. Space vector trajectory projection over the d-q plane
Figure 2-4 shows the Vdr and Vqr components (Park’s transformation) of the
unbalanced system in the time domain for δ = 0°.

17
Figure 2-4. Direct and quadrature components of an unbalanced system
It is clear that the Vdr component is not constant any more, and it contains a 2nd
harmonic due to the negative sequence. This effect can also be explained in the frequency
domain as shown in Figure 2-5. The rotating reference frame aligns with the fundamental
frequency, w=2πf, and therefore
• a negative sequence (-w) appears as a 2nd harmonic

• a dc component appears as a 1st harmonic
• a positive sequence (w) has a constant value.
abc axis drqr axis

0.833
0.167
-w w w
dc
-2w -w dc
Figure 2-5. Representation of an unbalanced system in the frequency domain

18
Thus, it can be concluded that Clarke’s and Park’s transformations do not provide
suitable components that can be used in a voltage regulation control algorithm. It is
therefore necessary then to redefine the transformations in order to extract the desired
components.
Assuming the three-phase electric system has positive and negative sequence
components
Va = V p ⋅ cos( wt ) + Vn ⋅ cos(− wt )
2π 2π
Vb = V p ⋅ cos( wt − ) + Vn ⋅ cos(− wt + ) (2-3)
3 3
4π 4π
Vc = V p ⋅ cos( wt − ) + Vn ⋅ cos(− wt + )
3 3
Clarke’s transformation can be used to obtain
Vds = V p ⋅ cos( wt ) + Vn ⋅ cos( wt ) = Vds+ + Vds−

(2-4)
Vqs =V p ⋅ sin( wt ) − Vn ⋅ sin( wt ) = Vqs+ + Vqs−
where Vds+ and Vqs+ are the d-q components of the positive sequence, while Vds− and Vqs−
are the d-q components of the negative sequence.
If we now assume that the symmetrical components remained constant for at least a
quarter of cycle, the equations can be rewritten as
1 ⎛ ⎛ π ⎞⎞
Vds + (t ) = ⋅ ⎜⎜ Vds (t ) − Vqs ⎜ t − ⎟ ⎟⎟
2 ⎝ ⎝ 2 ⎠⎠
1 ⎛ ⎛ π⎞ ⎞
Vqs + (t ) = ⋅ ⎜⎜ Vds ⎜ t − ⎟ + Vqs (t )⎟⎟
2 ⎝ ⎝ 2⎠ ⎠
(2-5)
1 ⎛ ⎛ π ⎞⎞
Vds − (t ) = ⋅ ⎜⎜ Vds (t ) + Vqs ⎜ t − ⎟ ⎟⎟
2 ⎝ ⎝ 2 ⎠⎠
1 ⎛ ⎛ π⎞ ⎞
Vqs − (t ) = ⋅ ⎜⎜ Vds ⎜ t − ⎟ − Vqs (t )⎟⎟
2 ⎝ ⎝ 2⎠ ⎠
19
These components can now be transformed using the rotating reference frame in
order to obtain the positive sequence component. Figure 2-6 shows the block diagram of
the algorithm used to extract the positive-sequence component. The same concept could
be used if the negative sequence magnitude is needed.

θ
Vdr
Vds
Va abd dsqs
Vb
Vqs Vqr
Vc dsqs drqr
_+
Sliding window
filter
Vds+ Vdr+ V
Delay (1/f/4) 0.5 dsqs x +
magnitude
positive sequence
+ Vqr+
+ Filter
Vqs+ drqr x +
Delay (1/f/4) + 0.5
Figure 2-6. Positive-sequence extraction algorithm
Figure 2-8 shows the algorithm performance when an unbalanced fault condition
takes place at t=0.02 sec (Figure 2-7). The data used for this example is given by
Equation 2-2.
Figure 2-7. Voltage waveforms for an unbalanced fault event

20
A B
Figure 2-8. Response of the positive-sequence extraction algorithm. A) Positive sequence

using ½ and 1 cycle filters. B) Positive sequence using Vdr with 1 cycle filter
The meaning of the different plotted variables is the following:
• Vpositive-sequence magnitude is the output of the positive-sequence extraction algorithm. As

expected, its time response is only one quarter of a cycle. However, the transient
response is very abrupt an uneven.
• Vpositive-sequence magnitude (1/2 cycle filter) is the filtered signal of Vpositive-sequence magnitude using
a half cycle sliding window filter.
• Vpositive-sequence magnitude (1 cycle filter) is the filtered signal of Vpositive-sequence magnitude using a
one-cycle sliding window filter. Its transient response is the slowest but at the same
time the smoothest among the three signals.
• Vdr filtered is the filtered signal of Vdr . The one cycle sliding window filter (also
called moving average) rejects all harmonics. Therefore there is no need to use the
Vds+ and Vqs+ calculator to extract the positive sequence. However its transient
response is not as smooth as the Vpositive-sequence magnitude (1 cycle filter) one.
Real Power Calculation Using dq Components
As shown in Appendix A Park’s transformation matrix is not unitary
[ ] [ ]
t
( Tdqo ≠ Tdqo
−1
) and therefore is not power invariant.
The total instantaneous power in abc quantities can be transformed into q-d-o
quantities as shown in Equation 2-6.

21
This relationship between dqo quantities and the instantaneous power is later used
in the control system to determine the amount of direct-current component ( I dr ) needed
to meet the power fluctuation requirements.
t
⎡Va ⎤ ⎡I a ⎤
Pabc = Va ⋅ I a + Vb ⋅ I b + Vc ⋅ I c = ⎢⎢Vb ⎥⎥ ⋅ ⎢⎢ I b ⎥⎥
⎢⎣Vc ⎥⎦ ⎢⎣ I c ⎥⎦
t
⎡ ⎡Vdr ⎤ ⎤ ⎡ ⎡ I dr ⎤ ⎤
⎢
[ ]
= ⎢ Tdqo
−1 ⎢
⋅ ⎢Vqr ⎥⎥ ⎥
⎥
[ ]
⎢
⋅ ⎢ Tdqo
−1
⋅ ⎢ I qr ⎥⎥ ⎥
⎢ ⎥
⎢⎣ ⎢⎣ Vo ⎥⎦ ⎥⎦ ⎢⎣ ⎢⎣ I o ⎥⎦ ⎥⎦
⎡ I dr ⎤
[
= Vdr Vqr ] [[ ] ] ⋅ [T ]
Vo ⋅ Tdqo
−1 t
dqo
−1
⋅ ⎢⎢ I qr ⎥⎥
⎢⎣ I o ⎥⎦
⎡3 ⎤
⎢2 0⎥ 0
⎥ ⎡ dr ⎤
I
⎢
[
= Vdr Vqr ]
Vo ⋅ ⎢ 0
3
2
⎢
0 ⎥ ⋅ ⎢ I qr ⎥⎥
⎢ ⎥
⎢0 1 ⎥ ⎢⎣ I o ⎥⎦
0
⎢⎣ 3 ⎥⎦
= ⋅ (Vdr ⋅ I dr + Vqr ⋅ I qr ) + ⋅ Vo ⋅ I o
3 1 (2-6)
2 3
Phase Locked Loop
The phase angle of the utility voltage (Ө) is of vital importance for the operation of
most of the advanced power electronic devices connected to the electric utility, since it
has a direct effect on their control algorithms.
A simple and fast method to obtain the phase angle of the utility voltage is to use
Clarke’s transformation as shown in Equation 2-7.
⎡ 1 1 ⎤ ⎡X ⎤
⎢ 1 − −
2 ⎥ ⋅⎢X ⎥
a
⎡ ds ⎤ 2
X 2 ⎛ X qs ⎞
⎢X ⎥ = ⎢ ⎥ ⇒ θ = arctan⎜⎜ ⎟⎟ (2-7)
⎣ qs ⎦ 3 ⎢0 3 3⎥ ⎢ b⎥ ⎝ X ds ⎠
− ⎢X ⎥
⎣⎢ 2 2 ⎦⎥ ⎣ c ⎦
22
However, this approach is not robust since it is very sensitive to system
disturbances. The phase angle Ө distorts as the utility’s voltage becomes affected by
different power quality events, such as voltage unbalance, voltage sags, frequency
variations, etc.
Figure 2-9 shows the voltage’s phase angle under unbalanced conditions using
Equation 2-7. The angle distortion is due to the negative sequence component of the
unbalanced three-phase system.
Figure 2-9. Distortion of phase angle due to a negative sequence component
In order to lock the phase angle of the utility voltage in a robust way, a phase
locked loop (PLL) was used.
Assuming a balanced three phase system, the control model of the PLL was
obtained using Park’s transformation as shown in Equation 2-8.
⎡Vdr ⎤ ⎡ cos(θ * ) cos(θ * − 120°) cos(θ * − 240°) ⎤ ⎡Va ⎤

⎢V ⎥ = 2 ⎢− sin(θ * ) − sin(θ * − 120°) − sin(θ * − 240°)⎥ ⋅ ⎢V ⎥ =
⎢ qr ⎥ 3 ⎢ ⎥ ⎢ b⎥
⎢⎣ Vo ⎥⎦ ⎢ 1 1 1 ⎥ ⎢V ⎥
⎣ 2 2 2 ⎦ ⎣ c⎦
(2-8)
⎡ cos(θ * ) cos(θ * − 120°) cos(θ * − 240°) ⎤ ⎡ V ⋅ cos( wt ) ⎤
2⎢ ⎥
= ⎢− sin(θ * ) − sin(θ * − 120°) − sin(θ * − 240°)⎥ ⋅ ⎢⎢V ⋅ cos( wt − 120°) ⎥⎥
3⎢ 1 1 1 ⎥ ⎢V ⋅ cos( wt − 240°)⎥
⎣ 2 2 2 ⎦ ⎣ ⎦
23
Where Ө* is the PLL phase angle output, Ө is the utility’s phase angle, and w = dθ .
dt
Thus, if Ө(t=0)=0, we can substitute wt for Ө(t) and obtain
⎡Vdr ⎤ ⎡ cos(θ * ) cos(θ * − 120°) cos(θ * − 240°) ⎤ ⎡ V ⋅ cos(θ ) ⎤

⎢V ⎥ = ⎢− sin(θ * ) − sin(θ * − 120°) − sin(θ * − 240°)⎥ ⋅ ⎢V ⋅ cos(θ − 120°) ⎥ (2-9)
2
⎢ qr ⎥ 3 ⎢ ⎥ ⎢ ⎥
⎢⎣ Vo ⎥⎦ ⎢ 1 1 1 ⎥ ⎢V ⋅ cos(θ − 240°)⎥
⎣ 2 2 2 ⎦ ⎣ ⎦
Using trigonometric identities, Equation 2-9 results in
⎡Vdr ⎤ ⎡cos(θ * − θ )⎤ ⎡cos(Δθ )⎤

⎢V ⎥ = V ⋅ ⎢ sin(θ * − θ ) ⎥ = V ⋅ ⎢ sin(Δθ ) ⎥ (2-10)
⎢ qr ⎥ ⎢ ⎥ ⎢ ⎥
⎢⎣ Vo ⎥⎦ ⎢ 0 ⎥ ⎢
⎣ 0 ⎥⎦
⎣ ⎦
Where ΔӨ is the error between the utility angle and the PLL output. If the ΔӨ is set to
zero, Vdr=V and Vqr=0. Therefore, it is possible to lock the utility angle by regulating Vqr
to zero without needing any information regarding the magnitude of the utility voltage.
Figure 2-10 shows the details of the PLL algorithm used in our study. The limits of
the controller integrator and the limiter were ±30 rad/sec. Thus, the PLL was able to track
the system frequency as long as this was within 2π60±30 rad/sec or 55 to 65 Hz range.
To use linear control techniques for the design and tuning of PLL controller, it was
assumed that:
• For small values of ΔӨ, the term sin (ΔӨ) behaved linearly, i.e., sin(ΔӨ) ≈ ΔӨ.
• Wref was assumed to be a constant perturbation.
• Limiters behave linearly for small control actions, and therefore can be removed.
θ
Va Vds Vdr
abd dsqs Kp
Vb
Vqs Vqr 30
+ 30
+ 1
Vc dsqs drqr s
1 +
-30 +
Ki s
-30
W ref=2πf
Figure 2-10. PLL diagram

24
Figure 2-11 shows the PLL control loop after eliminating the non-lineal terms.
PLL controller Plant transfer

Function
Kp
θ + Δθ +
1 θ∗
Control s
- 1 +
Ki action
θ∗ s
Figure 2-11. PLL simplified model
The closed loop transfer function of Figure 2-11 determines the dynamic
characteristics and stability of the system, and can be expressed as
θ* K ps + KI
H= = 2 (2-11)
θ s + K ps + KI
The control system (Kp and Ki) was designed to satisfy two performance
objectives
• < 10% overshoot

• Settling time inside the 2% band error lower than 2 secs
The criterion to select the settling time was a tradeoff between high distortion
rejection and tracking of normal system frequency variations.
The PLL closed loop transfer function was compared to a standard second order
transfer function to determine the regulator’s gains. The obtained values were
ζ = 0.7 ( for 5% overshoot )

t s = 2 sec
2 2
⎛ 4 ⎞ ⎛ 4 ⎞
K I = ω = ⎜⎜
2
⎟⎟ = ⎜ ⎟ = 8.1
n
⎝ ζ ⋅ t s ⎠ ⎝ 0.7 ⋅ 2 ⎠
K p = 2 ⋅ ζ ⋅ ω n = 2 ⋅ 0.7 ⋅ 2.85 = 4
Figure 2-12 shows the system’s closed-loop step response for two different PI
regulators.
25
The originally designed regulator did not meet the system requirements due to the
effect of the zero introduced by the PLL regulator. This additional zero increased the
overshoot, but it had very little influence on the settling time. Thus, it was necessary to
tune the original regulator gains in order to meet the system requirements.
Figure 2-12. PLL system step response
Figure 2-13 shows the root locus of the single-input single output PLL system for
the two regulators.
Figure 2-13. Root locus for two different regulator gains

26
Figures 2-14 and 2-15 show the PLL system response to a negative sequence
condition (V2=16.6%) and a system frequency excursion (w=2π60+30 rad/sec).
Figure 2-14. PLL system response to an unbalanced system condition
A B
Figure 2-15. PLL system response to a frequency excursion. A) Angle. B) PLL error.
Control Algorithm Design
Park’s transformation was used to model the system’s equations to facilitate the
design of the control system. The usage of a rotating reference frame had the following
advantages:
• Improvement of the steady-state performance of the current controllers:

Sinusoidal signals were transformed into dc components, and accordingly it is
possible to achieve small signal errors.
• High bandwidth current controllers: Feedback signals and reference signals

were not sinusoidal, but dc.
27
• Decoupling of active and reactive power: This was very useful when trying to
control voltage at the point of coupling while meeting the system requirements in
terms of power fluctuations.
Figure 2-16 shows the overall system topology as well as the sign notation that was
used in the control system design. In general, power flowing out of the inverter will be
considered to be positive. The objective was to smooth out wind-power fluctuations using
the power stabilizer as a buffer. The energy-storage voltage was expected to change in
order to accommodate for those changes in wind power.
WIND UTILITY
FARM SYSTEM
Transformer
Inverter DC link bus
equivalent impedance Chopper
Xsource
Lxfrm Lf
Iwind Vf Cdc Ichopper
Vpcc Vdc
Cf Iinv Vinv Vchopper Vstorage
ESS
Filter
P+
Figure 2-16. System description
Inner regulators
Inverter system model. For the following set of equations, it was assumed that the
inverter behaved as an ideal controllable voltage source, neglecting the effects of the
current harmonics. System’s non-linearities, such as saturation or dead-time effects were
taken into consideration later on in the design.
The capacitor filter was neglected in the analysis, since the filter current
represented a small portion of the inverter’s current.
The system can then be represented as shown in Figure 2-17.

28
Vpcc a R L Iinv a Vinv a

Vpcc b R L Iinv b Vinv b
C VDC LINK
Vpcc c R L Iinv c Vinv c
Figure 2-17. Simplified system model
The system equations for the simplified model are
⎡Vinva ⎤ ⎡ I inva ⎤ ⎡ I inva ⎤ ⎡V pcca ⎤

⎢V ⎥ = R ⋅ ⎢ I ⎥ + L ⋅ d ⎢ I ⎥ + ⎢V ⎥ (2-12)
⎢ invb ⎥ ⎢ invb ⎥ dt ⎢
invb ⎥ ⎢ pcca ⎥
⎢⎣Vinvc ⎥⎦ ⎢⎣ I invc ⎥⎦ ⎢⎣ I invc ⎥⎦ ⎢⎣V pcca ⎥⎦
Applying Park’s transformation we get
⎡Vinv dr ⎤ ⎡ I inv dr ⎤ ⎧ ⎡ I inv dr ⎤ ⎫ ⎡V pcc dr ⎤

d ⎪ ⎥⎪
[T ]
dqo
−1 ⎢ ⎥
[ ]
⎢Vinv qr ⎥ = R Tdqo
−1 ⎢ ⎥
[ ]
⎢ I inv qr ⎥ + L dt ⎨ Tdqo
−1 ⎢
[ ]
⎢ I inv qr ⎥ ⎬ + Tdqo
−1 ⎢ ⎥
⎢V pcc qr ⎥ (2-13)
⎢Vinv o ⎥ ⎢ I inv o ⎥ ⎪ ⎢ I inv o ⎥ ⎪ ⎢ V pcc o ⎥
⎣ ⎦ ⎣ ⎦ ⎩ ⎣ ⎦⎭ ⎣ ⎦
⎡Vinvdr ⎤ ⎡Iinvdr ⎤ ⎧ ⎡Iinvdr ⎤⎫ ⎡Vpccdr ⎤

⎪ ⎥⎪
⎢ ⎥
[ ] [ ] −1 ⎢ ⎥
[ ] d −1 ⎢
[ ] −1 ⎢
[ ][ ]
⎥
⎢Vinvqr ⎥ = Tdqo ⋅ R ⋅ Tdqo ⋅ ⎢Iinvqr ⎥ + Tdqo ⋅ L ⋅ dt ⎨ Tdqo ⋅ ⎢Iinvqr ⎥⎬ + Tdqo ⋅ Tdqo ⋅ ⎢Vpccqr ⎥ (2-14)
⎢Vinvo ⎥ ⎢ Iinvo ⎥ ⎪ ⎢ Iinvo ⎥⎪ ⎢Vpcco ⎥
⎣ ⎦ ⎣ ⎦ ⎩ ⎣ ⎦⎭ ⎣ ⎦
⎡Vinv dr ⎤ ⎡ I inv dr ⎤ ⎧ ⎡ I inv dr ⎤ ⎡ I inv dr ⎤ ⎫ ⎡V pcc dr ⎤

[ ] [ ]
−1
⎪ d Tdqo ⎥⎪ ⎢
⎢ ⎥ ⎢ ⎥
⎢Vinv qr ⎥ = R ⋅ ⎢ I inv qr ⎥ + L ⋅ Tdqo ⋅⎨
⎢ ⎥
[ ]
⋅ ⎢ I inv qr ⎥ + Tdqo
−1 d⎢ ⎥
⋅ ⎢ I inv qr ⎥ ⎬ + ⎢V pcc qr ⎥ (2-15)
⎢Vinv o ⎥ ⎢ I inv o ⎥ ⎪ dt ⎢ I inv o ⎥
dt
⎢ I inv o ⎥ ⎪ ⎢ V pcc o ⎥
⎣ ⎦ ⎣ ⎦ ⎩ ⎣ ⎦ ⎣ ⎦⎭ ⎣ ⎦
⎡Vinvdr ⎤ ⎡Iinvdr ⎤ −1 ⎡I ⎤ ⎡Iinvdr ⎤ ⎡Vpccdr ⎤

⎢ ⎥ ⎢ ⎥
[ ] [ ]d Tdqo ⎢ invdr ⎥
[ ][ ]
−1 d ⎢ ⎥ ⎢ ⎥
⎢Vinvqr ⎥ = R ⋅ ⎢Iinvqr ⎥ + L ⋅ Tdqo ⋅ dt ⋅ ⎢Iinvqr ⎥ + L ⋅ Tdqo ⋅ Tdqo ⋅ dt ⎢Iinvqr ⎥ + ⎢Vpccqr ⎥ (2-16)
⎢Vinvo ⎥ ⎢ Iinvo ⎥ ⎢ Iinvo ⎥ ⎢ Iinvo ⎥ ⎢Vpcco ⎥
⎣ ⎦ ⎣ ⎦ ⎣ ⎦ ⎣ ⎦ ⎣ ⎦
29
⎡Vinv dr ⎤ ⎡ I inv dr ⎤ ⎡ I inv dr ⎤ ⎡ I inv dr ⎤ ⎡V pcc dr ⎤

[ ] [ ]
−1
⎢ ⎥ ⎢ ⎥ d Tdqo ⎢ ⎥ d ⎢ ⎥ ⎢ ⎥
⎢Vinv qr ⎥ = R ⋅ ⎢ I inv qr ⎥ + L ⋅ Tdqo ⋅ ⋅ ⎢ I inv qr ⎥ + L ⋅ ⎢ I inv qr ⎥ + ⎢V pcc qr ⎥ (2-17)
dt dt
⎢Vinv o ⎥ ⎢ I inv o ⎥ ⎢ I inv o ⎥ ⎢ I inv o ⎥ ⎢ V pcc o ⎥
⎣ ⎦ ⎣ ⎦ ⎣ ⎦ ⎣ ⎦ ⎣ ⎦
Where
⎡ cos(θ ) − sin(θ ) 1⎤ ⎡ − sin(θ ) − cos(θ )

[ ]
d Tdqo
−1
d ⎢ ⎥ ⎢
0⎤
= ⎢ cos(θ − 120°) − sin(θ − 120°) 1⎥ = ⎢ − sin(θ − 120°) − cos(θ − 120°) 0⎥⎥ ⋅
dθ
dt dt dt
⎢⎣cos(θ − 240°) − sin(θ − 240°) 1⎥⎦ ⎢⎣− sin(θ − 240°) − cos(θ − 240°) 0⎥⎦
(2-18)
dθ
ω=
dt
It can be shown that
[T ]⋅ d [Tdt ]
−1
dqo
dqo =
⎡ cos(θ * ) cos(θ * − 120°) cos(θ * − 240°) ⎤ ⎡ − sin(θ ) − cos(θ ) 0⎤ (2-19)

2 ⎢ ⎥
= ⋅ ω ⋅ ⎢− sin(θ * ) − sin(θ * − 120°) − sin(θ * − 240°)⎥ ⋅ ⎢⎢ − sin(θ − 120°) − cos(θ − 120°) 0⎥⎥
3 ⎢ 1 1 1 ⎥ ⎢− sin(θ − 240°) − cos(θ − 240°) 0⎥
⎣ 2 2 2 ⎦ ⎣ ⎦
⎡0 − 1 0 ⎤ ⎡ 0 − ω 0 ⎤
= ω ⋅ ⎢⎢1 0 0⎥⎥ = ⎢⎢ω 0 0⎥⎥
⎢⎣0 0 0⎥⎦ ⎢⎣ 0 0 0⎥⎦
Thus, the equations for the simplified model in the d-q plane are
⎡Vinv dr ⎤ ⎡ I inv dr ⎤ ⎡0 −ω 0⎤ ⎡ I inv dr ⎤ ⎡ I inv dr ⎤ ⎡V pcc dr ⎤

⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ d ⎢ ⎥ ⎢ ⎥
⎢Vinv qr ⎥ = R ⋅ ⎢ I inv qr ⎥ + L ⋅ ⎢ω 0 0⎥ ⋅ ⎢ I inv qr ⎥ + L ⋅ ⎢ I inv qr ⎥ + ⎢V pcc qr ⎥
dt
(2-20)
⎢Vinv o ⎥ ⎢ I inv o ⎥ ⎢⎣ 0 0 0⎥⎦ ⎢⎣ I inv o ⎥⎦ ⎢ I inv o ⎥ ⎢ V pcc o ⎥
⎣ ⎦ ⎣ ⎦ ⎣ ⎦ ⎣ ⎦
The zero-sequence component can be removed, since the system is a three-phase
three-wire inverter with the DC link bus isolated from the AC side (the DC link mid-
point will not be tapped to neutral). Removing the zero sequence we obtain
dI inv dr
Vinv dr = R ⋅ I inv dr + L ⋅ + V pcc dr − L ⋅ ω ⋅ I inv qr
dt
(2-21)
dI inv qr
Vinv qr = R ⋅ I inv qr + L ⋅ + V pcc qr + L ⋅ ω ⋅ I inv dr
dt
30
Equation 2-21 can be represented as a coupled electrical system as shown in Figure
2-18.
R L Iinv dr LωIinv qr
Vpcc dr Vinv dr
A
R L Iinv qr LωIinv dr
Vpcc qr Vinv qr
Figure 2-18. Electrical representation of the dq components. A) Direct circuit. B)

Quadrature circuit.
Using Laplace’s transformation we can re-write the equations as Equation 2-22.
Vinv dr ( s) = (R + Ls ) ⋅ I inv dr ( s ) + V pcc dr ( s) − L ⋅ ω ⋅ I inv qr ( s)

(2-22)
Vinv qr ( s) = (R + Ls ) ⋅ I inv qr ( s ) + V pcc qr ( s) + L ⋅ ω ⋅ I inv dr ( s)
Thus, the block diagram of the system is represented in Figure 2-19.
Iinv dr
Vinv dr + 1
- + R + Ls
Vpcc dr
ωL
ωL
- Iinv qr
Vinv qr + 1
- R + Ls
Vpcc qr
Figure 2-19. System model block diagram

31
The inverter’s critical control variable was the inverter’s current. This was due to
the fact the outer control loops, such voltage regulators, power regulators, etc, were based
on the inner current regulators. That was why the current controllers were designed to
meet two basic requirements, which were high accuracy and high bandwidth.
The inverter’s terminal-voltage needed to generate the desired inverter current can
be determined as
dI inv dr
Vinv dr = R ⋅ I inv dr + L ⋅ + V pcc dr − L ⋅ ω ⋅ I inv qr = ΔVdropdr + V pcc dr − L ⋅ ω ⋅ I inv qr
dt
(2-23)
dI inv qr
Vinv qr = R ⋅ I inv qr + L ⋅ + V pcc qr + L ⋅ ω ⋅ I inv dr = ΔVdropqr + V pcc qr + L ⋅ ω ⋅ I inv dr
dt
The voltage drop due to the filter inductance was compensated using a PI
controller. Figure 2-20 shows the inveter’s current controller implementation for the
system given in Equation 2-23.
Vˆpcc dr
ω̂L̂
Iinv dr ref
- Kp + Iinv dr Iinv dr
+ ΔVdrop dr + Vinv dr + 1
1 + + - + R + Ls
Ki -
s
Vpcc dr
ωL
ωL
Iinv qr ref Kp + + - Iinv qr Iinv qr

+ ΔVdrop qr + Vinv qr + 1
1 + + - R + Ls
- Ki
s
Vpcc qr
Vˆpcc qr
ω̂L̂
CURRENT REGULATORS SYSTEM MODEL
Figure 2-20. Inverter current regulator-system model block diagram
The character ^ over a constant or variable indicates that the quantity is estimated,
and therefore subject to measurement errors.

32
To design the current regulator gains, cross-coupling factors were assumed to
cancel each other out. Under these conditions, the simplified current regulator block
diagram is shown in Figure 2-21.
Iinv dr ref
- Kp + Iinv dr Iinv dr
+ 1
1 + R + Ls
Ki
s
Iinv qr ref Kp + Iinv qr Iinv qr

+ 1
1 + R + Ls
- Ki
s
CURRENT REGULATORS SYSTEM MODEL
Figure 2-21. Inverter current regulator-system model simplified block diagram
Figure 2-21 shows that:
• The system behaves linearly, and therefore linear control techniques can be used to
determine the regulators’ gains.
• Both regulators are identical.
• Only an estimation of L and R (filter inductance + transformer equivalent

impedance) are needed to design the current regulator.
Given the filter/transformer characteristics in p.u., the closed-loop transfer function
of Figure 2-22 is shown in Equation 2-24.
Kp +
Iref 1
+ Control Action I
1 + R + Ls
- Ki
s
Figure 2-22. Simplified current control diagram

33
I K p ⋅ s + KI
H (s) = = (2-24)
I ref Ls 2 + (R + K p )s + K I
Using the following system data, the transfer function is given in Equation 2-25.
• X=Xtransfomer+Xfilter=5%+10% = 0.15 Ω → L= 400 µH

• X/R=10 → R=0.015 Ω
Note: More on the system parameters can be found in the per-unit mode section.
K p ⋅ s + KI
H (s) = (2-25)
0.0004s + (0.015 + K p )s + K I
2
The Figure 2-23 shows the system step response for two different current regulator
gains.
Figure 2-23. Current regulator step response
Even though the current regulator with the highest gains had a faster settling time,
the control action required to obtain such a response doubled the regulator with the
lowest gains. To avoid possible system saturations the control action was kept below 1
pu.
The best PI controller performance was achieved when the plant’s dominant pole
was cancelled by the controller (Equation 2-26). Thus, the zero at - K I was assigned to
Kp
the time constant of the plant, which was, K I = R .

Kp L
34
⎛ K ⎞
K p ⋅⎜ s + I ⎟
K ⎜ K p ⎟⎠
PI = K p + I = ⎝ (2-26)
s s
The synthesis was done by selecting the integral time constant of the PI equal to
that of the load. For our study the selected values were
R
KI = = 37.5
L
K p =1
Chopper system model. The analysis of the chopper system was less complex than
the inverter one, since no transformations were involved. Again, it was assumed that the
chopper behaved as an ideal controllable voltage source and therefore the effects of the
current harmonics were neglected.
Ichopper
V chopper V storage
Figure 2-24. Chopper equivalent system
The system equations for the chopper equivalent circuit (Figure 2-24) are given in
Equaion 2-27.
dI chopper
Vstorage = L ⋅ + Vchopper
dt
(2-27)
dI chopper
Vchopper = Vstorage − L ⋅
dt
The chopper’s terminals voltage needed to generate the desired chopper current
can be determined as
Vchopper = Vstorage − ΔVdrop (2-28)

35
The voltage drop due to the chopper inductance was compensated using a simple P
controller. The gain of the controller was found by converting the continuous system into
discrete time system as shown in Equation 2-29.
ΔI chopper ( I chopperref − I chopper )

Vchopper = Vstorage − L ⋅ = Vstorage − L ⋅
dt dt (2-29)
L
Vchopper = Vstorage − K L ⋅ ΔI chopper where K L =
Δt
Where KL is the regulator’s gain and Δt is half of the sampling time period.
Figure 2-25 shows the implementation of the chopper’s current regulator.
Ichopper ref + - Vchopper

KL
- +
Ichopper Vstorage
Figure 2-25. Chopper current controller
Outer regulators
There were a total of three controllable currents, which consisted of Ichopper_ref,
Iinvdr_ref, and Iinvqr_ref.. However, there were four variables that needed to be controlled,
which were voltage at the dc link bus, voltage at the point of common coupling, voltage
at the energy storage system, and wind farm power fluctuation. Table 2-1 shows how
these variables were assigned to the respective current regulators.
Table 2-1. Outer regulator assignation

Inner current Variable to be
Comments
regulator controlled
Iinv dr ref Vstorage, PΔwind The direct current component will be responsible
for controlling the state of charge of the ESS
and for smoothing the wind farm output power
Iinv qr ref Vpcc The quadrature current component will be
deployed for voltage regulation purposes
Ichopper ref Vdc link The chopper current will regulate the DC link bus
voltage.
36
DC link Voltage regulator. The DC link bus was the bridge between the energy
storage system (chopper) and the inverter. Therefore, it was a critical variable in the
overall system. Poor DC voltage regulation could bring the system down, since the
inverter and chopper would not be able to meet their respective voltage requirements.
The DC link system can be modeled as shown in Figure 2-26.
Vpcc a R L Iinv a Vinv a Ichopper

VDC LINK Lchopper
Vpcc c R L Iinv c Vinv c Cdclink
Vstorage
Cstorage
Pout Plosses Pdc link Plosses Pchopper
P+
Figure 2-26. Powers' definition
Using the energy balance theorem we can write
Pchopper = Pdc link + Plosses + Pinvout

(2-30)
Pdc link ≈ I chopper ⋅ Vstorage − Pinvout − Plosses ( filter , inverter...)
Assuming Plosses ≈ 0 , we have
2
1 d (Vdc link )
⋅ C dc link ⋅ ≈ I chopper ⋅ Vstorage − Pinvout (2-31)
2 dt
Linearizing Equation 2-31 around the nominal point of the energy-storage voltage
(Vstorage), we can re-write the equations as
1
⋅ C dc link ⋅ (Vdc2 link )( s) ⋅ s ≈ I chopper ( s ) ⋅ Vstorage − Pinvout ( s )
2
(2-32)
2 ⋅Vstorage ⎛ P ( s) ⎞
Vdc2 link ( s ) = ⋅ ⎜ I chopper ( s ) − out ⎟
C dc link ⎜⎝ Vstorage ⎟⎠
Figure 2-27 shows the block diagram of the system model.

37
Pout
Vstorage
+ Vdc2 link
I chopper 2 ⋅Vstorage
+
Cdc link ⋅ s
Figure 2-27. System model
Considering Pinvout as a disturbance, the transfer function of the system is
1 d (Vdc2 ) 1
⋅ C dc ⋅ ≈ I chopper ⋅ Vstorage ⇒ ⋅ C dc ⋅ (Vdc2 )( s ) ⋅ s ≈ I chopper ( s ) ⋅ Vstorage
2 dt 2
(2-33)
2
Vdc ( s ) 2 ⋅Vstorage
=
I chopper ( s ) C dc ⋅ s
The system model and the DC link voltage regulator can be represented in the form of a
block diagram as shown in Figure 2-28.
Pˆout Pout
ˆ
Vstorage Vstorage
Kp + - Vdc2 link
Vdc2 link ref +
+
+ I chopper 2 ⋅Vstorage
+
- 1 + Cdc link ⋅ s
Ki s
DC LINK VOLTAGE REGULATOR SYSTEM MODEL
Figure 2-28. DC link equivalent system block diagram
Pout
Under ideal conditions the terms cancel each other out, resulting in a
Vstorage
simplified block diagram (Figure 2-29).

38
Kp Vdc2 link
Vdc2 link ref +
+ 2 ⋅Vstorage
- 1 + Cdc link ⋅ s
Ki s
DC LINK VOLTAGE REGULATOR SYSTEM MODEL
Figure 2-29. DC link simplified system block diagram
The closed-loop transfer function of the simplified DC link system is:
2 ⋅ Vstorage ⋅ (K p s + K I )
H (s ) = (2-34)
C dc link s 2 + 2 ⋅ Vstorage ⋅ K p s + K I ⋅ 2 ⋅ Vstorage
Figure 2-30 shows the system step response for two different regulator gains, using
the following system data:
• Cdc link =15700µF

• Vstorage nominal =1.533 p.u.
Figure 2-30. DC link voltage regulator step response
To avoid a possible saturation of the DC link voltage regulator, the controller with
lower gains was chosen. In this case, the control action was the chopper current, and it
was designed to always be below 1.pu.

39
Point of common coupling voltage regulator. The voltage support capability of
the inverter depended on the available line impedance back to the utility source voltage,
and its dynamics response was directly affected by the line parameters.
The regulation of the voltage at the point of common coupling was accomplished
by changing the amount of reactive current generated / absorbed (Iinv qr) by the inverter. It
was also possible to improve the voltage regulation controlling the real current
component. However, as it will be shown, the voltage regulation range was significantly
reduced.
The system model used in our study (Figure 2-31) was a simplified version of the
actual system. It consisted of the source (modeled as an infinite bus with a series
impedance), and the inverter (modeled as a controllable current source). System non-
liberalities, such as switching of the semiconductor devices, transformer saturation, etc,
were neglected.
The system of the equations for Figure 2-31 is
⎡V pcc a ⎤ ⎡ I inv a ⎤ ⎡ I inv a ⎤ ⎡Vsource a ⎤

⎢ ⎥ ⎢ ⎥ d ⎢ ⎥ ⎢ ⎥
⎢V pcc b ⎥ = Rsource ⋅ ⎢ I inv b ⎥ + Lsource ⋅ dt ⎢ I inv b ⎥ + ⎢Vsource b ⎥ (2-35)
⎢V pcc c ⎥ ⎢ I inv c ⎥ ⎢ I inv c ⎥ ⎢Vsource c ⎥
⎣ ⎦ ⎣ ⎦ ⎣ ⎦ ⎣ ⎦
Applying Park’s transformation and removing the zero-sequence component, it can be
shown that
dI inv dr
V pcc dr = Rsource ⋅ I inv dr + Lsource ⋅ + Vsource dr − Lsource ⋅ ω ⋅ I inv qr
dt
(2-36)
dI inv qr
V pcc qr = Rsource ⋅ I inv qr + Lsource ⋅ + Vsource qr + Lsource ⋅ ω ⋅ I inv dr
dt
40
EQUIVALENT
SYSTEM MODEL
V source a Rsource Lsource Iinv a Vpcc a
V source b Rsource Lsource Iinv b Vpcc b
Vsource c Rsource Lsource Iinv c Vpcc c
Vpcc a R L Iinv a Vinv a

C
Vpcc c R L Iinv c Vinv c
Figure 2-31. Simplified system model
Using Laplace’s transformation and re-organizing the terms, we obtain the transfer
functions shown in Equation 2-37
⋅ (V pcc dr ( s ) − Vsource dr ( s) )
Rsource 1
sI inv dr ( s) = − ⋅ I inv dr ( s) + w ⋅ I inv qr ( s ) +
Lsource Lsource
(2-37)
⋅ (V pcc qr ( s) − Vsource qr ( s) )
R 1
sI inv qr ( s) = − source ⋅ I inv qr ( s) − w ⋅ I inv dr ( s) +
Lsource Lsource
⋅ (V pcc dr ( s) − Vsource dr ( s ) )
1
w ⋅ I inv qr ( s ) +
Lsource
I inv dr ( s ) =
⎛ R ⎞
⎜⎜ s + source ⎟⎟
⎝ Lsource ⎠
(2-38)
1
− w ⋅ I inv dr ( s) +
Lsource
I inv qr ( s) =
⎛ R ⎞
⎝ Lsource ⎠
41
Defining the voltage drop, ΔV, as the voltage across the source impedance (Figure
2-32), it was possible to find the amount of current needed to obtain the desired voltage
drop (Equation 2-38).
ΔV
V source a Rsource Lsource Iinv a Vpcc a
V source b Rsource Lsource Iinv b Vpcc b
Vsource c Rsource Lsource Iinv c Vpcc c
Figure 2-32. Source impedance voltage drop
w 1
Lsource Lsource
I inv dr ( s) = ⋅ ΔVqr ( s) + ⋅ ΔVdr ( s )
⎛
2
Rsource ⎞ ⎛ R ⎞ w 2
⎜⎜ s + ⎟⎟ + w 2 ⎜⎜ s + source
⎟⎟ +
⎝ Lsource ⎠ ⎝ Lsource ⎠ ⎛⎜ s + Rsource ⎞⎟
⎜ Lsource ⎟⎠
⎝
(2-39)
−w 1
Lsource Lsource
I inv qr ( s) = ⋅ ΔVdr ( s ) + ⋅ ΔVqr ( s )
⎛ Rsource ⎞
2
⎛ R ⎞ w 2
⎜⎜ s + ⎟⎟ + w 2 ⎜⎜ s + source ⎟⎟ +
⎝ Lsource ⎠ ⎝ Lsource ⎠ ⎛ R ⎞
⎝ Lsource ⎠
The Bode plots of the Equation 2-39 for a system with a source impedance of 10%,
and X/R=10 are shown in Figure 2-33 and Figure 2-34.
Even thought the Bode plots of I inv dr and I inv qr look very similar, the effect on the
amount of voltage drop for a given source impedance were significantly different.
There are two ways of controlling the amount of voltage drop at the source
impedance; regulating ΔVqr ( s ) and/or ΔVdr ( s ) . However, in order to increase system
stability and gain robustness, the phase shift between the utility voltage and the voltage at
42
the point of common coupling must be as small as possible. Therefore, it was preferable
to regulate Vpcc by controlling ΔVdr ( s ) exclusively.
I inv qr ( s )
ΔVdr ( s )
I inv qr ( s )
ΔVqr ( s )
Figure 2-33. Transfer functions of inverter’s quadrature current component
I inv dr ( s)
ΔVqr ( s)
I inv dr ( s )
ΔVdr ( s )
Figure 2-34. Transfer functions of inverter’s direct current component
Comparing Figure 2-33 to Figure 2-34, it is clear that, in the low frequency range,
the cross coupling between I inv qr and ΔVdr is much greater than the direct gain between
43
I inv dr and ΔVdr . This means that the voltage can be regulated by controlling only the
quadrature current.
Thus, for instance, the steady-state bus voltage of a system with a source
impedance of 10%, and X/R=10 in terms of I inv dr and I inv qr is
⋅ (V pcc dr ( s) − Vsource dr ( s) )
Rsource 1
0=− ⋅ I inv dr ( s) + w ⋅ I inv qr ( s) +
Lsource Lsource
(2-40)
R 1
0 = − source ⋅ I inv qr ( s) − w ⋅ I inv dr ( s) +
Lsource Lsource
For I inv dr = 0 ,
2
V pcc = V pcc dr + V pcc dr =
2
(V source dr − wLsource I inv qr ) + (Vsource qr + Rsource I inv qr ) (2-41)
2 2
For I inv qr = 0 ,
2
V pcc = V pcc dr + V pcc dr =
2
(V source dr + Rsource I inv dr ) + (Vsource qr + wLsource I inv dr ) (2-42)
2 2
If I inv qr = −1 pu (capacitive), Vsource dr = 1 pu , Vsource qr = 0 pu , X source = 0.1Ω, and
X source
= 10 , then V pcc = 1.1 pu .
Rsource
The amount of I inv dr needed to obtained the same voltage would be
V pcc = 1.1 = (V source dr + Rsource I inv dr ) + (Vsource qr + wLsource I inv dr )

2 2
⇒ I inv dr = 3.67 pu
This proves that for a system where the ratio X/R>1, the PCC bus voltage can be
regulated in an efficient way by injecting only quadrature current.
The design of the voltage regulator requires the knowledge of the source
impedance. However, this impedance varies with time and on online estimation can be
very complex if transient situations are present in the system.

44
For steady-state conditions the transfer function between ΔV and I inv qr can be
reduced to just the source impedance of value Xsource=wLsource. Therefore, the control
block diagram of the voltage regulator can be interpreted as shown in Figure 2-35.
Vsource dr
V pcc ref Kp +
positive sequence + I inv dr ref I inv dr ΔVdr + V pcc
+ CURRENT SOURCE
CONTROLLER IMPEDANCE
- Ki
1 +
POSITIVE
SEQUENCE
EXTRACTION
VOLTAGE REGULATOR SYSTEM MODEL
Figure 2-35. Voltage regulator system block diagram
The current controller is represented as a second order transfer function in Equation
2-43.
K p current regulator ⋅ s + K I current regulator

H current regulator ( s) = (2-43)
0.0004 s + (0.015 + K p current
2
regulator )⋅ s + K I current regulator
For Kp=1 and Ki=36 the current controller transfer function is
I inv s + 36
H current regulator ( s ) = =
I inv ref 0.0004 s + 1.015s + 36
2
The positive sequence extraction transfer function can be modeled in continuous
time as shown in Figure 2-36.
Integrator
V pcc 1 V pcc
+ Td
positive sequence
- s
Td
Transport
delay
Figure 2-36. Positive sequence extraction algorithm equivalent system

45
For the simplified voltage regulator system, there was not need for any
transformation. Only the modeling of the positive sequence 1 cycle sliding window filter
(Td=16.666msec) was required (Figure 2- 37).
Vsource dr
V pcc ref Kp +
I inv dr ref I inv dr ΔVdr + V pcc
positive sequence
+
+
s + 36
wLsource
- 1 + 0.0004s 2 + 1.015s + 36
Ki s
1 +
Td
s -
Td
Figure 2- 37. Voltage regulator detailed block diagram
The system was further simplified assuming that the current regulator time
response was much faster than voltage regulator time response (Figure 2- 38).
Vsource dr
V pcc ref Kp +
positive sequence + I inv dr ref I inv dr ΔVdr + V pcc
+ 1 wLsource
- Ki
1 +
1 +
Td
s -
Td
Figure 2- 38. Voltage regulator simplified control diagram
Figure 2- 39 shows the system step response for a given voltage regulator under
different system conditions.
A B
Figure 2- 39. System response to a 5% change in voltage reference for Kp=2 Ki=250. A)
With saturation. B) Without saturation
46
The settling time was a function of the system impedance, and therefore it was not
possible to predict the system response without knowing the source impedance. One
solution was to use an adaptive parameter tuner capable of adjusting the regulator gains
according to the identified plant dynamics. The block diagram of the adaptive control
scheme is shown in Figure 2-40.
Adaptive
Parameter Tuner
V pcc ref Kp
positive sequence +
+ PLANT
- 1 + I inv dr ref V pcc
Ki s
1 +
Td
s -
Td
Figure 2-40. Adaptive control scheme
However, due to the difficulty in distinguishing between changes in the system
impedance, load variations, and utility voltage, a simpler but robust solution was adopted.
It consisted of a classic PI regulator, with gains that were tuned in the field. The
drawback was a slower response that could occur for any given condition.
Power regulator. The power regulator required to control the power fluctuations of
a wind farm was the most complicated control scheme among all the described so far. It
involved non-linear algorithms which made the system very sensitive to instabilities due
to non forecasted conditions.
The basic idea behind the power regulator was to determine the amount of the real
power required by the inverter in order to meet the utility’s power fluctuation limits.
A generic power regulator control scheme is shown in Figure 2-41.

47
Iwinda
Vpcca X Ramp Rate
Average Inst V storage
Iwindb + Wind
X + Power
Limiters
Centering
Vpccb algorithm
+
Iwindc
Vpccc X + -
ESA required
+ power
+ Allowedcenteringpower
PowerInverter
Reference
Figure 2-41. Power Regulator general control scheme
First the wind farm power was calculated and the compared to rate-of change limits
(Table 2-2). If limits were exceeded, the difference would be compensated by the
inverter.
The centering algorithm was a control scheme used to hold the energy storage near
its nominal value, to be ready for the next supply or absorption cycle. If the wind farm
power was causing the limiters to activate, this centering action would not take place.
That way a higher priority was given to the power limiters.
Table 2-2. Rate-of-change limits or PPA for a 10 MW wind farm

Parameter Value
Instantaneous 1 MW change per 2 second scan
Sub minute average average of 0.3MW change per 2 second
scan for any 60 second period
Ramp rate 2 MW per minute up, and down when
operationally possible
The first proposed control scheme of the power limiter consisted of a high pass
(HP) filter which canceled the high frequency power fluctuations independently of the
rate-of-change limits. Figure 2-42 shows the HP filter control block diagram. A small
bias power was added to assure the charging of the energy storage system.
This approach had three major drawbacks:

48
• Rate-of-change limits might not meet unless inverter’s power and energy
requirements were increased.
• Optimal cut-off frequency design was unknown.
• Inverter duty cycle was higher than the next approaches.

Wind
Farm
Output High Pass
Filter
Storage
Nominal
State of Charge Centering +

+ -
Storage Charge/ + Inverter
+ +
(integrator) Discharge Centering Power
Constant
Figure 2-42. Power limiter 1. Control block diagram
Wind farm power data records were used to test the power limiter control scheme
under different system conditions. Figure 2-43 and Figure 2-44 show the inverter
requirements as well as the system performance for different cut-off frequencies.
Note: Inverter size requirements cannot be extrapolated from the 15 minutes
simulation. A more detailed study must be performed using long wind-power data
records (perhaps years). It was also not cost effective to correct every possible scenario.
Therefore, the number of times and/or amount that the wind farm may exceed the power
index limits, with a Power Stabilizer installed, needs to be determined, when traded off
against inverter and storage ratings.
The main advantages of the HP power limiter were its simplicity and its stability
under unexpected power fluctuations.
The control scheme was implemented in MATLAB in order to test the power
limiter performance under different system conditions. Appendix B gives more
information on the MATLAB code.

49
Figure 2-43. Power limiter 1. Performance using different cut-off frequencies (unlimited
power and energy). A) Power to utility. B) Power-stabilizer output power. C)
Power stabilizer’s energy storage.
Figure 2-44. Power limiter 1. Performance using different cut-off frequencies (Pinverter=1.0
MW and Einverter=±8.5 MJ). A) Power to utility. B) Power-stabilizer output
power. C) Power stabilizer’s energy storage.
50
The second proposed control scheme of the power limiter consisted of a power
limiter with the three rate-of-change limiters in cascade (Figure 2-45). The ramp limit
was first applied, followed by the sub minute limit, and finally the scan-to-scan limit.
+R +S
Input Scan-to- Output
Scan
-R -S
Limiter
R S
Subminute
Limit
Calculator
Ramp Limit
Calculator
Figure 2-45. Power limiter 2. Limiters details
As mentioned earlier, the “centering” of the energy storage energy was needed so
that it could supply or absorb power from its nominal state. Therefore this energy must be
taken into account when calculating the rate-of-change limits, since it was real power
being interchanged with the system. Thus, the power limiter control scheme had two
limiters in parallel (Figure 2-46); one limiter acted upon the wind farm output only,
another limiter acted on the wind farm power plus the desired centering power.
If the inverter were big enough to supply or absorb the excess power and energy
from the wind farm, the power limiter would keep the power within that allowed by the
rate-of change limits. The problem occurred when the power or energy storage is beyond
the rating of the inverter, since the history of what is actually delivered to the utility could
be wrong. Thus, a saturation limiter was needed in order to adjust the buffer input data.
The control scheme was implemented in MATLAB in order to test the power
limiter performance under different system conditions. Appendix B gives mode
information on the MATLAB code.

51
Desired Power
+ (Wind+Storage Centering)
+ Limiter
+ Last thing to be
updated/evaluated
+
Previous scans
+ +
(BUFFER) - +
Desired -
Wind
Centering
Farm
Output
Limiter
Storage
Nominal
- +
+
Centering State of Centering
- Charge
Charge/ Power
+ ESA Required
Discharge Allowed
+ Supply/Absorb
Constant
+ +
+
+ -
+
1 PU
Inverter
Power
-1 PU
Power Limiter
Wind farm power data stored on a 2 second basis was used to test and size the
power limiter control scheme under different scenarios. The following figure shows the
system performance for a period of 15 minutes.
Zoom in
Figure 2-47. Power limiter 2. Compensation performance

52
The inverter power and energy required to meet the rate-of-change limits for the
15- minute simulation is shown in Figure 2-48.
Figure 2-48. Power limiter 2. Inverter response for a sampling time of 2 seconds. A)
Power-stabilizer output power. B) Power stabilizer’s energy storage.
To test the stability of the control algorithm, saturation effects were taken into
account. Figure 2-49 and 2-50 show the system performance for different under-rated
inverters. Rate-of-change limits were not met, but the system was stable.
It is very difficult anticipate all of the types of misbehavior that might occur in the
system, and that there could be unusual power fluctuations from the wind farm could get
the inverter into a mode where it would continue to swing the power around in an
undesirable manner. Therefore it was recommended to include some type of
“misbehavior detector” in the power limiter control scheme to protect the inverter and the
system.
53
Figure 2-49. Power limiter 2. Inverter response for different power ratings. Sampling
time 2 seconds .A) Power-stabilizer output power. B) Power stabilizer’s
energy storage.
Zoom in
Figure 2-50. Power limiter 2. Inverter response for different ESS sizes. Sampling time 2
seconds. A) Power-stabilizer output power. B) Power stabilizer’s energy
storage.
54
The third control scheme considered for the power limiter consisted of a power
limiter with the three rate-of-change limiters in parallel (Figure 2-51). The limiter’s input
was the power out to the utility instead of the wind power, plus the centering power, for a
more accurate control of the power fluctuations seen by the utility.
Each limiter determined the maximum and minimum amount of power allowed
changing per scan. Then the absolute maximum and minimum were calculated in order to
establish the centering power limits and the required power from the inverter.
Wind
Farm
Output + Power to Utility
+
+
Storage (Joules or Upper

Volts) Centering
Inverter Limit
-1
Total
Upper Inverter
+ Power
Upper -
Ramp +
Min
Limiter Lower
Inverter
Power
Upper
These should Before
not have a + Centering +
Subminute simulataneous + + -1
Limiter non-zero
Lower
output + +
Upper
Scan-to- +
Lower -
Scan Max +
Limiter Lower
Lower Centering
Centering Power
Limit
Storage -1
Setpoint
lower upper
+ upper
- Kcenter or
+ other
controller
lower
Figure 2-52 shows the response of the power limiter 2 using the same wind-power
data records used previously.
It can be concluded from Figure 2-47 and Figure 2-52 that both power limiters have
the same response under normal conditions.

55
Figure 2-52. Power limiter 3. Compensation performance
Figure 2-53. Power limiter 3. Inverter response for a sampling time of 2 seconds. A)
Power-stabilizer output power. B) Power stabilizer’s energy storage.
56
Per-Unit System Model
The reasons why to convert system variables into per unit are:
• System easily scalable

• Facilitate fixed point operations
• Power system components can be treated uniformly no matter what voltage level
The two variables selected as based values are
Vbase = V max line − neutral = 1 pu (V )

I base = I max line = 1 pu ( A)
Thus, the rest of variables can be calculated as
VRMS line neutral Vbase

• Base Impedance: Z base = = = 1Ω
I RMS line I base
• Base Power (3 phase):
Vbase I base
Pbase = Pinverter rate power = 3 ⋅ V RMS line neutral ⋅ I RMS line = 3 ⋅ ⋅ = 1 .5 W
2 2
Inverter Output-Filter Design
The purpose of inverter filter was to attenuate the high frequency switching
harmonics produced by the inverter in order to avoid disturbing other EMI sensitive
equipment on the grid.
Its optimal design is very complex and it involves coupled design constraints and
non-linear equations.
The inverter topology for which the filter would be designed was a 6-pulse 3-wire
inverter, without DC bus mid-point tapped to neutral (Figure 2-54), where power
semiconductors were considered as ideal switches.

57
Iinv a Vinv a
Iinv b Vinv b
C
Iinv c Vinv c
Figure 2-54.Inverter topology
Harmonic content
The typical line-to-neutral and line-to-line voltage of a three phase inverter using a
PWM strategy is shown in Figure 2-55.
A B
Figure 2-55. Line-to-line and line-to-neutral voltage of a three phase inverter
Figure 2-56 shows the harmonic spectrum of the line-to-line voltage under the
following conditions:
• fsw = 4860 Hz
• f1=60 Hz
switching frequency f
• Frequency Modulation, m f = = sw = 81
fundamental frequency f1
• Vdc = 2.04 pu
• Vsource max line-to-neutral = 1 pu
Vmax desired
• Peak amplitude of the control signal =
Vdc _ link 2
• Amplitude of the triangular signal = 1
58
peak amplitude of the control signal

• Amplitude modulation, ma = =1
amplitude of the triangular signal
Figure 2-56. RMS Line-to-line voltage harmonic spectrum
The main harmonic components of the line-to-line output voltage were calculated
using the tabulated table in [28] as
Vinverter rms l −l (h ) = Vdc ⋅ K (2-44)
K values for the different harmonics can be found in Table 2-3.
The front-end inverter was designed to behave as a static synchronous generator
(SSG) capable of producing a set of adjustable voltages, which may be coupled to an ac
power system to exchange independently controllable real and reactive power. This was
accomplished by the usage of a synchronous inductor which linked the inverter output to
the ac supply side (Figure 2-57).

59
Table 2-3. Generalized Harmonics of line-to-line voltage for a large and odd mf that is a
multiple of 3
K (Generalized Harmonics of Vrms l-l)
ma
h 0.2 0.4 0.6 0.8 1
1 0.122 0.245 0.367 0.490 0.612
mf ± 2 0.010 0.037 0.080 0.135 0.195
mf ± 4 0.005 0.011
2mf ± 1 0.116 0.200 0.227 0.192 0.111
2mf ± 5 0.008 0.020
3mf ± 2 0.027 0.085 0.124 0.108 0.038
3mf ± 4 0.007 0.029 0.064 0.096
4mf ± 1 0.100 0.096 0.005 0.064 0.042
4mf ± 5 0.021 0.051 0.073
4mf ± 7 0.010 0.030
synchronous
Inductor Inverter
Vsource L Vinv
SSG
Figure 2-57. Static Synchronous Generator diagram
Thus, the inverter voltage harmonics would generate current harmonics, which
amplitude would not only be a function of the inverter’s mf and ma, but the synchronous
inductor as well. The inverter current harmonics can be calculated as:
• For h=1 (fundamental frequency):

Vinverter rms l −l − Vsource rms l −l 1
I rms (h ) = ⋅ (2-45)
3 2πf1 ⋅ h ⋅ L
• For h>1 (assuming no harmonics are present in the utility bus voltage):
Vinverter rms l −l (h) 1 V ⋅K 1
I rms (h ) = ⋅ = dc ⋅ (2-46)
3 2πf1 ⋅ h ⋅ L 3 2πf1 ⋅ h ⋅ L
Where f1 is the fundamental frequency.

60
The inverter current harmonics must be attenuated in order to avoid interference
with communication circuits and other types of equipment, the increase of system losses,
resonance conditions, and malfunction of power electronic devices.
The IEEE 519 Standard [29] is a recommended practice to be used for guidance in
the design of power systems with nonlinear loads and therefore should be taken into
account on the design of the switching ripple filter. The worst case scenario is for general
distribution systems (120V through 69000V) with a TDD < 5% for current harmonics
below the 50th. TDD is the total demand distortion and is defined as
50
∑I
h=2
2
h
TDD(%) = ⋅100 (2-47)

IL
The maximum demand load, which is IL, can be estimated from data used to size
the inverter isolation transformer.
Switching frequency
The selection of the switching frequency was based on the recommendations given
by [28], which stated that:
• Because of the relative ease in filtering harmonic voltages at high frequencies, it is

always desirable to use as high a switching frequency as possible.
• In most applications, the switching frequency is selected to be either less than 6

kHz or greater than 20 kHz to be above the audible range.
• In order to avoid sub-harmonics, synchronous PWM must be used. Synchronous

PWM requires that mf be an integer.
• In the 3-wire three-phase inverters, only the harmonics in the line-to-line voltage
are of concern, and only the odd harmonics exit as sidebands, centered around mf
and its multiples, provided mf is odd.
• If mf is chosen to be an odd multiple of 3 the most dominant harmonics in the line-

to-line voltage (even harmonics of mf) will be cancelled out.
61
• For high power applications (kVA) where switching losses play a major role in the
overall system design, the switching frequency is usually selected between 3 kHz
and 5 kHz.
Taking all these elements into consideration, the optimal switching frequency
selected for the inverter and for the chopper was f sw = f1 ⋅ m f = 60 ⋅ 81 = 4860 Hz
Passive filter design
The switching ripple filter topology selected for the inverter filter was based on a
LCL network as shown in Figure 2-58.
Isolation transformer Filter or synchronous

equivalent impedance Inductor Inverter
Vsource Lt Lf Vinv
Cf Iinverter
Igrid Filter
capacitor
LCL switching ripple filter

Figure 2-58. LCL filter topology
The main advantages of the LCL filter compare to the L filter are summarized in
Table 2-4.
Table 2-4. L filter vs. LCL filter

Characteristics L filter LCL filter
Control method Hysteresis controllers Fixed switching frequency
control methods
Attenuation above 20dB 60 dB
resonance frequency ( first order system) (third order system)
I grid ( s)
Vinverter ( s )
Total line filter inductance High line inductance, and Low line inductance, and
for a given grid current therefore poor transient fast transient performance
ripple magnitude performance
62
The LCL inverter filter equations are the following:
dI inverter
Vinverter − Vc f = L f ⋅
dt
dI grid
Vc f − Vsource = Lt ⋅ (2-48)
dt
dVc f
I inverter − I grid = Cf ⋅
dt
Applying Laplace’s transform, the LCL inverter filter can be modeled as shown in
Figure 2-59.
Figure 2-59. LCL equivalent block diagram
The inverter filter was divided into two different equivalent filter models based on
the frequency under study. Thus, we have:
Equivalent filter circuit configuration at fundamental frequency. Under these
conditions the inverter was considered as an ideal sinusoidal voltage source. This was the
lineal inverter model valid for the design of the system controllers. Figure 2-60 shows the
filter equivalent system at fundamental frequency.
Vsource (f1) Lt Lf Vinv (f1)
Cf Iinverter (f1)
Igrid (f1)
Figure 2-60. Single phase equivalent filter model at the fundamental frequency
63
Equivalent filter circuit configuration for the h harmonic (for h>1). At high
frequencies the converter was considered to be a harmonic generator, while the grid can
be considered short-circuited.
Lt Lf Vinv (hf1)
Vsource (hf1)= 0
Cf I inverter (hf1)
I grid (hf1)
Figure 2-61. Single phase equivalent filter model at the hth harmonic
Thus, the current ripple attenuation, passing from the inverter side to the grid side
can be calculated as
I grid rms ( s) 1
=
Vinverter rms l −n ( s) s ⋅ Lt ⋅ C f ⋅ L f + s ⋅ ( Lt + L f )
3
I inveter rms ( s) s 2 ⋅ C f ⋅ Lt + 1
= (2-49)
Vinverter rms l −n ( s) s 3 ⋅ Lt ⋅ C f ⋅ L f + s ⋅ ( Lt + L f )
I grid rms ( s) 1
=
I inverter rms (s) s ⋅ C f ⋅ Lt + 1
2
There are different ways of designing the LCL inverter filter, as well as different
specifications or constrains. Table 2-5 is a summary of the most common parameter used
to design the inverter filter.
It can be inferred from Table 2-5 that there is no a unique approach or limit when
designing the LCL filter.
The LCL parameters selected for the inverter filter design are
X L f = 10% ⇒ L f = 265.25 μH
X C f = 3333.33% ⇒ C f = 79.577 μF
X Lt = 5% ⇒ Lt = 132.62μH ( typical transformer equivalent impedance)
Table 2-5. LCL filter design
Parameter Description Equations Limits
Current Maximum Peak to Peak For ma ≤ 1 Peak to Peak value:
ripple value ⎡ ⎛ m ⎞
⋅ ⎜1 − a ⎟ ⋅ 2 Vdc ⋅ 3 ⋅ ma ⎥
⎤ • 15%-25% of rated current [35]
⎢Vsource l −n
• 31% of rated current [32]
max
⎝ 2⎠
ΔI ripple max = Max ⎢ , 3 ⎥
Note: Maximum ⎢ 4 ⋅ Lf ⋅ fsw 4 ⋅ Lf ⋅ fsw ⎥
current ripple at ⎢ ⎥
⎣ ⎦
Vsource(t)=0 differs For ma ≈1
from Vsource(t)=Vmax Vdc
ΔI inverter ripple max ≈
7 ⋅ L f ⋅ f sw
Most significant For ma ≈1 Most significant harmonic component
I inverter rms (h = m f ± 2 ) ≈
harmonic components Vdc1 (mf±2)
⋅ 0. 2 ⋅
3 2πf1 ⋅ h ⋅ L f • 10% of rated current [30]
• 1.6% of rated current [31]
Attenuation Laplace domain I grid rms ( s) 1 • 0.2 attenuation [30]
64
of =
I inverter rms ( s) s ⋅ C f ⋅ Lt + 1
2
• 0.5 attenuation [32]
harmonic
content
Frequency domain I grid rms (h = m f − 2) Z C f ( f1 ⋅ h )
=
I inverter rms (h = m f − 2) Z C f ( f1 ⋅ h ) + Z Lt ( f1 ⋅ h )
Voltage drop across the filter during ΔVmax L f = I inverter max ⋅ 2πf1 ⋅ L f • Total value of inductance should be
normal operation lower than 10% to limit the voltage
drop and the dc link voltage[30],[33]
• 1.7% on the inverter kVA base [34]
Filter resonant frequency 1 Resonance frequency between 10 times
f resonant =
2π C f ⋅ (Lt // L f ) the line frequency and half of the
switching frequency[30][33]
Filter capacitor reactive power 1 QC f (%) ⋅ Pinveter rated power QCf:
Cf = ⋅ • <5%[30]-[33]-[34]
100 3 ⋅ 2 ⋅ π ⋅ f 1 ⋅ V source
2
rms l − n
• 15% [35]
65
The electrical characteristics of the LCL filter for the system parameters given
Table 2-7 in are summarized in Table 2-6.
Table 2-6. LCL equivalent impedance with damping resistance

Parameter Equation Stiff system
Current ripple ΔI inverter current ripple max ≈
Vdc
7 ⋅ L f ⋅ f sw 0.2264 pu (App)
(peak to peak)
Current ripple
(most V
I inverter rms ( f sw − 2 ⋅ f1 ) ≈ dc ⋅ 0.2 ⋅
1 0.00003 pu
significant 3 2π ( f sw 2 ⋅ f1 ) ⋅ L f
− (Arms)
harmonic)
Harmonic I grid rms ( f sw − 2 ⋅ f1 ) ZC f ( f sw − 2 ⋅ f1 )
attenuation =
I inverter rms ( f sw − 2 ⋅ f1 ) ZC f ( f sw − 2 ⋅ f1 ) + Z Lt ( f sw − 2 ⋅ f1 )
-18.5 dB
Max Voltage ΔVmax L f = I inverter max ⋅ 2π ⋅ f1 ⋅ L f 0.1 pu (Volts)
drop
Filter resonant f resonant =
1
2π C f ⋅ ( Lt // L f ) 1897 Hz
frequency
Filter capacitor 2
C f ⋅ 3 ⋅ 2 ⋅ π ⋅ f1 ⋅ Vsource rms l −n
3.0% VAr
QC f (%) = ⋅ 100
reactive power Pinveter rated power ( I C f MAX = 0.03 pu )
Table 2-7. Per-unit system

Variable Per unit
VMAX line− neutral 1.0
VRMS line−line 1.22474
VRMS line−neutral 0.70677
I MAX inverter nominal 1.0
I RMS inverter nominal 0.70711
Z base 1.0
Pinverter 1.5
Vdc 2.0412
Passive filter damping
To determine the system stability, the LCL inverter filter damping resistances must
be taken into account when calculating the system attenuation at resonance frequency.
The system resistors are given in Figure 2-62.

66
Vsource Vinveter
Rt Lt Lf Rf
Rt Lt Lf Rf
Rt Lt Lf Rf
Cf Cf Cf
Figure 2-62. LCL equivalent impedance with damping resistance
Using a X/R=10 for all inductors, the damping resistances of the LCL filter are
X Lf
X L f = 10% ⇒ = 10 ⇒ R f = 0.01Ω
Rf
X Lt
X Lt = 5% ⇒ = 10 ⇒ Rt = 0.005Ω
Rt
The LCL inverter filter could resonate due to harmonics generated either from the
source or from the inverter. The two equivalent circuits are
Vsource
Vcapacitor Vinveter Rt Lt Vcapacitor Lf Rf
Rt Lt Lf Rf
Cf Cf
A B
Figure 2-63. Single phase harmonic generator equivalent circuits. A) Inverter as a

harmonic generator. B) Source as a harmonic generator
Vcapacitor
Thus, the transfer functions are given in Equations 2-50 and 2-51:
V
Vcapacitor 1 (2-50)
=
Vinverter ⎛ 1 1 ⎞⎟
1 + Z Lf ⋅⎜ +
⎜ ZC ⎟
⎝ f Z Lt ⎠
Vcapacitor 1 (2-51)
=
Vsource ⎛ 1 1 ⎞
1 + Z Lt ⋅ ⎜ + ⎟
⎜ ZC Z ⎟
⎝ f Lf ⎠
67
The Bode frequency response of both models is given in Figure 2-64.
Figure 2-64. LCL gain frequency response
It can be deduced from Figure 2-64 that there is a significant gain at the resonance
frequency (small system damping resistance), and therefore harmonics close to this
frequency could be amplified by the LCL filter.
From the inverter point of view there are two sources of disturbances:
1. Voltage harmonics due to the PWM

2. Disturbances amplified by the current regulator
Figure 2-65. Inverter frequency analysis

68
Figure 2-65 shows the current regulator frequency response, the filter frequency
response, and the inverter line-to-neutral harmonic spectrum. It can be inferred from
Figure 2-65 that the current regulator attenuates any signal with a frequency > 400Hz
(cut-off frequency), and the inverter voltage harmonics do not make the LCL filter
resonate.
From the point of view of the voltage source there are two sources of disturbances:
• Large infrequent transient, such as capacitor bank switching. This type of

disturbance may ring the filter, but it will damp out in a few cycles.
• System harmonics. A detail study of the system it is required to determine if it is

likely.
Direct-Current Link Capacitor Design
The DC link bus voltage had the following constrains:
• IPM Max voltage 1200V.
• Line to line voltage 480 V. This would allow the use standard isolation
transformers
• Minimum DC link voltage = 1.1 ⋅ Vmax line −to −line = 1.1 ⋅ 480 ⋅ 2 = 750 V . Minimum
voltage to guarantee system controllability.
• IPM trip level = 900V. Capacitor switching voltage transients tend to raise the DC
link voltage and could damage the IGBT’s. A trip level of 900 V allows riding-
through the majority of the capacitor switching transients.
• Low DC-link voltage was desirable in order to reduce the switching losses.
Given these system restrictions the selected DC-link voltage was 800V. In per unit
800
V dc −link = = 2.0412 pu
⎛ 480 ⋅ 2 ⎞
⎜ ⎟
⎜ 3 ⎟
⎝ ⎠
The dimensioning of the DC link capacitor was determined by the following
constrains:
69
• Maximum permissible current stress for a required working life (current ripple)
• Existence of any zero sequence component
• System controllability ( avoid large gains)
• Max ripple voltage 10%
For a traditional STATCOM configuration, the DC-link capacitor is necessary for
an unbalanced system operation and harmonic absorption. For a configuration with
energy storage, the DC link capacitor main function is to reduce the DC current ripple
from/into the ESS and therefore a smaller DC-link capacitor could be used.
DC − link Energy
The time constant selected for our study was = 21.5 msec . Thus,
Inverter Power
the DC-link capacitor in per-unit model is
DC - link Energy DC - link Energy pu

= 22 m sec =
Inverter Power Pinverter pu
DC - link Energy pu
⇒ DC - link Energy pu = 0.033J
1.5W
1
DC - link Energy pu = ⋅ C dc −link ⋅ Vdc2 −link ⇒ C dc −link ≈ 15700 μ F
2
Energy Storage Design
The Energy Storage System (ESS) design parameters were
• The voltage at the energy storage system (ESS) was designed to vary from 95% to
0.95*50% of the DC link voltage.
Total Energy in the ESS

• = 20.45 sec
Inverter Power
Note: More on the design and size of the Power Stabilizer energy storage system
can be found in [36].
The center voltage of the ESS can be calculated as

70
1
2
(
⋅ Cstorage ⋅ Vstorage
2
max − Vstorage center =
2
) 1
2
(
⋅ Cstorage ⋅ Vstorage
2
)
center − Vstorage min
2
(2-52)
Vstorage center =
1
2
(
⋅ Vstorage max + Vstorage min
2 2
)
Thus, for a system with a Vdc nominal = 2.0412 pu , the ESS nominal voltage was
Vstorage max = 0.95 ⋅ 2.0412 = 1.9391 pu

Vstorage min = 0.95 ⋅ 0.50 ⋅ 2.0412 = 0.9695 pu
Vstorage center =
1
2
(
⋅ Vstorage
2
)
max + Vstorage min = 1.9391 ⋅
2 5
8
= 1.533 pu
Figure 2-66 shows the relationship between the capacitor voltage and the energy
storage.
The capacitance of the ESS in per-unit can be calculated from the time constant
Total Energy in the ESS

as
Inverter Power
Max Energy Max Energy pu

= 20.45 sec = ⇒ Max Energy pu = 30.67 J
Power Pinverter pu
1
Max Energy pu = ⋅ Cstorage ⋅ Vstorage
2
max ⇒ Cstorage = 16.31 F
2
Figure 2-66. Capacitor Voltage vs. Energy Storage

71
Chopper Inductor Design
The purpose of chopper inductor was to reduce the current ripple produced by the
chopper in order to guarantee the ESS working life (Figure 2-67).
The current ripple current selected for this application was 30%. Under this
condition the chopper inductance in per unit is calculated as shown in Equation 2-53.
dI chopper
ΔVchopper = Lchopper ⋅ , where ΔVchopper = Vdc −link − V storage (2-53)
dt
Cdc-link Ichopper Lchopper

Vdc-link
Vstorage
Cstorage
Figure 2-67. ESS-Chopper topology
In the worst case scenario the DC-link voltage is at its nominal value, while the
voltage at the ESS is at its minimum. Thus, the maximum voltage drop across the
chopper inductor is
Δ Vchopper max = Vdc − link nominal − Vstorage min = 2.0412 − 0.9695 = 1.0717 pu
Discretization of the chopper inductor voltage drop differential equation yields the
Equation 2-54.
ΔI chopper
ΔVchopper = Lchopper ⋅ (2-54)
Δt
1 1
Where ΔI chopper is the ripple current, and Δt = ⋅ as shown in Figure 2-68.
2 f sw
72
Tsw
Triangular
waveform
Time
Δt
Ichopper
ΔIchopper
Lchopper
Time
Cdc-link ΔIchopper
Vdc-link=2.0412 pu
Lchopper
Cstorage Vstorage=0.9695 pu
Figure 2-68. Equivalent circuit for maximum current ripple calculation
Thus, the chopper inductor in per unit is:
1 ⎫
ΔVchopper max ⋅ Δt 1.0717 ⋅ ⎪
Lchopper = = 2 ⋅ 4860
⎪
ΔI chopper ΔI chopper ⎪
⎪
⎪⎪
ΔI chopper = 0.03 ⋅ I chopper rated (30% ripple) ⎬ Lchopper = 500 μH
⎪
⎪
Pinverter nominal 1.5W ⎪
I chopper rated = = = 0.7352 pu ( A)⎪
Vdc-link 2.0412 ⎪
⎪⎭
Per-Unit System Model Summary
Table 2-8 is a summary of the per-unit system parameters used in the control and
modeling of the system.

73
Table 2-8. Per-unit system parameters

Variable Per-unit Model Specs
VMAX line− neutral 1.0V
VRMS line−line 1.22474V
VRMS line− neutral 0.70677V
I MAX inverter nominal 1.0A
I RMS inverter nominal 0.70711A
Z base 1.0Ω
Pinverter 1.5W
Vdc no min al 2.0412V
Vstorage center 1.533V
C dc link 15700 µF 21.5 msec time constant
C storage 16.31F 20.45 sec time constant (at
maximum ESS voltage)
Lchopper 500.0µH 30% current ripple
Rchopper 0.018849Ω X/R=10
Lf 265.25µH 10% Impedance
Rf 0.01Ω X/R=10
Cf 79.57 µF 3% VArs (3333.3% Impedance)
Lt 132.63µH 5% Impedance
Rt 0.05Ω X/R=10
Simulated Model
Power Systems Computer Aided Design (PSCAD) was used for the modeling and
simulation of the power stabilizer. The PSCAD model was based on the per-unit system,
so that the system performance could be compared to any given unit size. Figure 2-69
shows the main components of the system.
The PSCAD model can be divided into two main subsystems; the electric system
(Figure 2-70) and the control algorithm (Figure 2-71).

74
The majority of components used in the modeling were part of the PSCAD library.
Only the power limiter 2 had to be implemented in FORTRAN and linked to PSCAD
given the complexity of its design.

UTILITY
SYSTEM
Chopper
Xsource
Lxfrm Lf
Iwind Vf Cdc Ichopper
Vpcc Vdc
Cf Iinv Vinv Vchopper Vstorage
WIND
FARM LCL INVERTER ESS
Figure 2-69. System overview
1 3 5 5
2 2 2 2
V
Vutility g1 g3 g5 gch1
A
Iinva
R=0 Vpcca 0.000132629110.005 Vfa 0.01 0.00026525 Vpwma V_dc
15700.0
B
+
Iinvb
Vpccb 0.000132629110.005 Vfb 0.01 0.00026525 Vpwmb
C 0.0005 0.018849
Iinvc
Vpccc 0.000132629110.005 Vfc 0.01 0.00026525 Vpwmc
16310000.0
Vstorage
+
4 6 2 2
79.57
79.57
79.57
2 2 2 2
g4 g6 g2 gch2
LCL filter Inverter DC link bus Chopper
Figure 2-70. Per-unit electric system model
Table 2-9 shows the model performance as well as the designed specifications for
comparison. It can be observed that designed and simulated system closely agree.
Kp
+ 1pu
1pu +
1 -1 pu
Ki
s
-1pu
PI regulator
Iwinda
X RampRate Vstorage
V pcca Av erage Inst
Pinv erter ref erence updated

Iwindb + Wind every0.1seconds
X + Power
Limiters
Centering
V pccb algorithm
+ V pcc_offset
Iwindc Klimit
V pccc X + -
ESA required
+ power 40 kHz + -
+ Allowedcenteringpower Idrinv Vdf wLIqinv
Constant angle
PowerInverter
Reference 1.5pu
- + Max Magnitude
Idref Idref + PI regulator + - V dinv V apu + + PWMVa
V dqinv V dqinv_limited Vdinv _limited iPark V1
-1.5 pu
Vdqinv = Vdinv
2
+ Vqinv
2 Vdqinv_limited iClark V1
Current Limiter Vdinv_limited = Vdsinv - -
Vdr V pcc_offset 0
dr-qr ds -qs V bpu + +
Vqinv 1+ K 2
PWM Vb
ds-qs Vqsinv
dqinv
M M
K dqinv = K dqinv Vqinv _limited abc
- Kp Vdinv Vqinv_limited = K dqinv ⋅Vdinv_limited - -
V pcc ref + + M Iqref + + Vqinv V c pu + +
Power Limiter
PI regulator sin(theta) cos(theta) PWM Vc
+
M
+
- Ki
1 -M
- +
s
-M - -
Vpccpositivesequence
Iqr inv V qf wLIdinv
Vflata
Voltage regulator V dc
(formodulationindex
calculation) +
Vflatb + V flat
2 +
Vflatc
Current regulator Limiters & Transformations
Rotating Reference Frame transformation & positive sequence calculation Flat-top
75
Clark V1 PLL
V pcca Vds
V pccb abc PLL
sin(theta)
Clark I1 Park I1
V qs (2 sec time constant) Iinva Ids
V pccc ds -qs cos(theta)
abc ds -qs Idrinv
Iinvb Iqs To current
Vos Theta Park V1 Iinvc ds -qs dr -qr Iqr inv regulator
Vds Vds ds-qs Vdr To current Ios
V qs Vqs regulator
sin(theta) cos(theta)
dr -qr Vqr
Vqs Vds sin(theta) cos(theta)
+
Delay - Vds positivesequence Park V1 positivesequence
V drpositivesequence Slidingwindowfilter
0.5 (1cycle)
(t-1/f /4) X
ds -qs + V pcc positivesequence To PCC voltage
+ Filter
regulator
Delay + Vqspositivesequence dr -qr Vqrpositivesequence X +
0.5
(t-1/f /4)
V 2dcref + PI regulator
Iinva -
Vfa X V2dc
Iinvb + + Ichopperref + Vchopper

Vdc _link
Vchopper_limited Vchopperpu +
X
Inv erter Power + KL -
Vfb -
+ + -Vdc _link
-
Iinvc PWMchopper
X
Vfc
Vstorage Ichopper Vstorage Vdc
(formodulationindex
calculation)
Chopper Control Scheme
Figure 2-71. Power Stabilizer Control Scheme

76
Table 2-9. Designed system results and simulated system results comparison. System
conditions: V dc link =2.04 pu, V source max =1 pu, stiff system
Parameter Model response Design system/Comments
Inverter ⎡
⎢V
⎛ m ⎞
⋅ ⎜1 −
2
⎟⋅2
V ⎤
⋅ 3⋅m ⎥source max l − n
a dc
= Max⎢ ⎝ ⎠ 3 ⎥
a
current ΔI inverter ripple max

⎢ 4⋅ L ⋅ f
,
4⋅ L ⋅ f ⎥ f sw f sw
⎢ ⎥
ripple ⎣ ⎦
ΔI inverter ripple max = Max(0.198, 0.2241) = 0.2241 pu ( App)
I inverter rms (h = m f ± 2) ≈
Vdc
⋅ 0.2 ⋅
1
3 2πf1 ⋅ h ⋅ L f
I inverter rms (h = m f ± 2 ) ≈ 0.02986 pu ( A rms)
Harmonic I grid rms ( f sw − 2 ⋅ f1 ) Z C ( f sw − 2 ⋅ f1 )

= f
I inverter ( f sw − 2 ⋅ f1 ) Z C ( f sw − 2 ⋅ f1 ) + Z L ( f sw − 2 ⋅ f1 )
attenuati rms f t
I grid rms ( f sw − 2 ⋅ f1 )
on I inverter rms ( f sw − 2 ⋅ f1 )
= −18.5bB
I grid rms ( f sw − 2 ⋅ f1 ) = 0.1188 ⋅ 0.02986 = 0.0035 pu ( A rms)
Current Iqref step change [-1 1]

regulator (from capacitive to inductive)
step No PCC voltage regulator
response Stiff system
Limiters: Vmax=1.15, Vflat=1
Dc link Vdc ref step change [2.0412 2.3]

step Stiff system
response
77
Table 2-9. Continued

Parameter Model response Design system/Comments
Voltage Vpcc ref step change [1.0 1.05]
regulation Variable line impedance:
[1% 2% 4% 5% 10% 20% ]
Current Iqref =0.2sin (wt)

regulator Idref =Iess+0.2cos (wt)
bandwidth f=[120 300 420 540 660
1020]Hz
Vdc-link=2.0412pu (V)
Vsouce max l-n=1 pu (V)
Stiff system
Cut-off frequency ≈ 400 Hz

Power Power limiter 2 simulation
filtering results for a sampling time of 2
seconds
CHAPTER 3
SYSTEM DESCRIPTION
System Overview
The performance of the power advanced electronic device was tested in a test
bench based on:
• DC motor - synchronous machine set

• Passive load
• DC motor - asynchronous machine set
• Wind farm buffer
The basic idea was to reproduce the basic electrical components of a small isolated
system in order to asses the benefits of smoothing wind-power fluctuations. Figure 3-1
shows this main idea.
Bulk generation. The system model’s bulk generation was represented with a
single synchronous machine, which the main function was to control the system
frequency and voltage.
Load. The power system’s load composition was strongly dependent on the time of
day, month, and season, but also on weather. A typical load profile was studied in [37],
and can have the following approximate composition:
• Induction motors, 60 per cent

• Synchronous motors, 20 per cent
• Other ingredients (passive load, electronics...), 20 per cent
78
79
Wind Farm m odel

Electric Network Model
DCM otor Asynchronous
Generator
Line Impedance
1 st QU AD R AN T 3 phas e four w ire s y s tem Z=5%,X/R=100 3 phas e four w ire s y s tem
CHOPPER Tachometer Vphas e-phas e=480 V Vphas e-phas e=480 V
(w>1800 rpm) LOAD
PF
180 Vdc +
C ontrol signal caps
P=4.5kW
3 phas e four w ire s y s tem
Vphas e-phas e=480 V
Gate
Vr ated field= ?? DC volts
D riv er Fixed Magnetic field ??
Power=??
PFcorrec tion
1 st QU AD R AN T DC M otor
CHOPPER Tachometer
(w>1800 rpm )
3 phase input
V l-l =240 V Synchronous
C ontrolsignal
180 Vdc + Machine
Gate
V rated field= ?? DCvol ts
D riv er Fixed Magnetic fi eld ??
Power=?? SE350
Voltage R egulator
(1% v oltage regulation)
3 phase input
V l-l =240 V
GM1 LOAD 1
GM4
Va,Vb,Vc PC C
C hoke Inductor-Filter
5%base on Power 10% bas e on Power 1 3 5 5
LOAD 4 Stabilizerrated Power Stabi lizerrated Power g1

2
g3
2
g5
2
gc1
2
and Voltage and Voltage N AS
VnaS C hopper R eac tor
Va,Vb,Vc Filter Vdc link
300.0
N BS
VnbS 1.0
GM2 N CS
3% bas e on Power Vnc S
1.0
Energy Storage
LOAD 2 Stabilizerrated Power C apac itor
and Voltage 4 6 2 5
GM3 2 2 2 2
Ia,Ib,Ic IN V g4 g6 g2 gc2
LOAD 5
LOAD 6
Power Stabilizer
LOAD 3
GM5
IM1
Figure 3-1. Equivalent system model
Dynamic loads usually consume between 60 to 70 % of the total power system
energy. However, their dynamics are of special importance for voltage stability studies
due to their reactive power requirements. Thus, since only real power fluctuations were
of interest in our study, the system’s load was reduced to a one three-phase passive load.
Renewable Resources. Renewable resources are growing faster than traditional
energy sources, with the fastest growth being in wind and solar energy. It is expected that
in the near future, they will play a significant role in the generation mix.
The system’s renewable resources were modeled using a single induction generator
that would represent 15% of the system capacity. This number was very conservative
compared to other grids such as Western Denmark with a penetration level of 63% of
peak load and the Island of Crete, where wind power has a penetration level close to
40%.
80
Power Quality Devices. Because of wind power’s high penetration factor in the
near future, new advanced power electronic devices as well as grid operation procedures
have to emerge to minimize the impact of non-dispatchable wind power.
In modeling the system, only a proof of concept wind farm buffer was considered
to study different control schemes that could reduce wind-power fluctuations.
Electrical Network Model
Synchronous Machine
The first requirement of a reliable service is to have the synchronous generators
with adequate capacity to meet the load demand. Any unbalance between the generation
and load initiates a transient that causes the synchronous machine to accelerate or
decelerate due to the appearance of net torques on the rotor.
It can be shown that the interconnection of j finite machines with inertia constants
Mj can be reduced to a single finite machine with inertia H, where H can be calculated as
shown in Equation 3-1.
1
H= (3-1)
1 1 1
+ + ... +
H1 H 2 Hj
The synchronous machine selected for modeling the electrical system is a three-
phase, brushless, self excited, externally regulated, AC generator.
The ratings of the synchronous machine were
• Rated Power 7.0 kW intermittent, 5.4 kW Continuous

• Rated Voltage 240/480 3ph 60 Hz
• Rated Speed 1800 rpm
81
The system voltage selected for the model is 480V; therefore the synchronous
machine’s coils were connected in a high series Y configuration.
Voltage regulation
Load voltage regulation was mainly carried out by the generator’s exciter using an
external voltage regulator. The automatic voltage regulator received both its input power
and voltage sensing from the generator’s output terminals. The DC output voltage of the
exciter field required to maintain constant the generator’s terminal voltage was
automatically changed by the voltage regulator, which had a voltage regulation accuracy
of 1%. The voltage regulator set point was 480V, line to line.
Due to synchronous machine imperfections and asymmetries, output voltage was
not an ideal sinusoidal waveform, as shown in Table 3-1. The most significant distortions
were the second, third, fourth, and fifth harmonics, with an unbalance of approximately
1%. Such types of distortions were not very common in electric systems and may have an
impact on the control system. Simple sliding windows were used to filter/reduce their
impact.
Prime Mover
The prime movers of large generators are principally hydraulic turbines, steam
turbines, and combustion turbines. In our model the prime mover that was used to
produce the mechanical torque was a DC machine with the following specs:
• Rated Power: 7.5 HP

• Armature Voltage 240 V dc
• Field Voltage 150 V dc
• Rated Speed 1750 rpm
82
Both machines were connected in cascade through their shaft, so power could be
transferred from one machine to another. Figure 3-2 shows the system configuration as
well as the variables used in the control.
Table 3-1. Synchronous machine output voltage profile at rated speed

Synchronous Machine Voltage Synchronous Machine Voltage
Features
profile for unloaded condition profile for unloaded condition
Waveform
FFT
Unbalance
A single quadrant chopper was used for speed control of the DC machine. Chopper
circuit specs are shown in Figure 3-3.
Note: Figure 3-3 shows that the DC power supply was used by the two choppers
required in the model. One was for the prime mover of the synchronous machine, and the
other one a different DC machine that would represent wind speed variations.
83
DC Motor Synchronous Generator

7.5hp 7hp 3 phase four wire system
Vphase-phase=480 V Electric system
Encoder
(w>1800 rpm)
Single quadrant Encoder
chopper
SE350
Voltage Regulator
(1% voltage regulation) Pout, Qout (V and I)
Istator generator
W rotor2
Ia, Ib generator
single phase input
Vl-n=120 V Vab, Vbc generator
Electrical field constant=7.6 Ripple period
Interface Board
(signal conditioning and filtering)
(Output Range 0v to 3v)
(cut-off frequency=100kHz)
TO DSP
Figure 3-2. DC gen-set

300 sec
R⋅2 =
⎛ 50 ⎞ Prime mover for Prime mover for
− ln⎜ ⎟ ⋅ Cfilter
⎝ 750 ⎠ synchronous induction
BDD6 U 160 N 16 machine machine
C=2200uF C=2200uF C=2200uF

480 Volts 450V 450V 450V
Contactor R
L-L RMS 15kΩ
12 W
DC
machine
DC
machine
1 2
670 V Vdc
source
R
Fuses Rlimit Lchoke 15kΩ
12 W
FWH100 100Ω 0.83mH C=2200uF C=2200uF C=2200uF
450V 450V 450V
100W Irms=44Ams
CHOPPER1 CHOPPER2
Cfilter 3.3 mF
900 Volts
Figure 3-3. Two single quadrant chopper circuit
Synchronous Machine Control Algorithm
The control of a synchronous machine is based on three separate control systems:
• The excitation system or voltage regulator that controls the synchronous machine’s
terminal voltage.
• The governor that controls the mechanical power monitoring the shaft’s speed.
84
• The supervisory controller which sends signals to each generator in the system to
meet the load demand.
Excitation system
Vt
Rectifier
-
Vreference Vfield
Boiler + Excitation
system
Governor Vfield
Vt
Control Set points Boiler + Servomotors
Steam
Pmechanical + Machine
Speed
and Generator Pelectrical
Center Control turbine Dynamics
Actuators
-
Pelectrical
Pelectrical Pelectrical Speed Speed
Electrical
Network
Figure 3-4. Synchronous generator control system
Figure 3-4 shows a generic block diagram of the different control systems required
for the control of one generator.
In our small-scale model, only the governor and the excitation were considered,
since the master controller was designed to be quite slow, which is usually not involved
in the mechanical dynamics of the shaft.
The accurate modeling of the system’s frequency control requires the knowledge of
a series of parameters that most of the times are impracticable to get. The frequency’s
response after a disturbance depends on:
• System inertia, H
• Network power frequency characteristic, D
• Speed governor’s transfer function
• Load shedding scheme
Equation 3-2 represents the frequency deviation response of a system with inertia
H, and load frequency dependency D. Figure 3-5 shows the system frequency response
for different H and D, for a -50% load step change (ΔP).

85
dw w
= n ⋅ ΔP − D ⋅ Δw (3-2)
dt 2 ⋅ H
These two factors, H and D, dominate the system frequency deviation during the
initial seconds following a power perturbation, since large time constants are involved in
the control of the system frequency. Such parameters are usually very difficult to
determine or estimate due to the system’s non-linearity.
If all these factors were known, it could be possible to implement a control scheme
that could represent the system’s frequency response. Figure 3-6 shows a control scheme
for a synchronous machine when system frequency response parameters are known.
Figure 3-5. Frequency deviation

Ia, Ib generator
Vab, Vbc
I chopper
generator
generator
5 channels
A/D inputs
Ia, Ib generator
Vab, Vbc generator
Frequency and Power

calculation
Ichopper generator Vdc source
f grid Pout2 W rotor2
- + -
f ref Δc gate position ΔP Pref2 Tref2 Stator Current I stator ref2 +
+ - PI Servo-Valve Turbine system - Torque
Calculation PI controller PWM
controller System model model calculation
- 1/k
+ 4860Hz
Transient
Droop
+
Droop
(4%)
Figure 3-6. DC-GEN set control scheme

86
This control algorithm was further simplified, and a single frequency control
regulator was implemented to tightly control the system frequency.
Figure 3-7 shows the synchronous machine frequency response to a step change of
-1 Hz in the reference for two different gains with a 90% system load (4.5kW out of
5kW). The frequency regulator’s transfer function and gains were adjusted to simulate
any other system frequency deviation response. The only limitations were the DC motor
maximum electrical specs, which should not be exceeded in order to avoid possible
control-action saturations and system damage.
Figure 3-7. System frequency response for Δf=-1Hz
From Figure 3-7, it is also possible to identify the DC-gen set transfer function,
adjusting the system response to a second order equation. Such parameters were valid for
a particular point of operation, and should be recalculated every time the system changes.
Nevertheless, their knowledge helped in the tuning of the frequency regulator, even with
approximated coefficients. Thus, with 90% load, the system DC-Gen set transfer function
was estimated to be:

87
w( s) w( s) K ⋅ ω n2 3.0 ⋅ 225
H ( s) = = = 2 = 2
Varmature in pu ( s) d duty cycle chopper ( s ) s + 2 ⋅ ζ ⋅ ω n ⋅ s + ω n s + 33 ⋅ s + 225
2
Thus, it possible to represent the DC-Gen set frequency control scheme as shown in
Figure 3-8.
Δduty
Δw ref + Ki cycle 225 Δw
Kp + 3.0 ⋅
s s 2 + 33 ⋅ s + 225
-
Figure 3-8. Frequency control equivalent system
Figure 3-9 shows the equivalent system response to a step change of
1Hz/60Hz=0.01666pu for two different gains. As expected, the system’s behavior was
similar to the model, and it was used in the design of the frequency regulator.
Wind Farm Model
There are countless studies, books and reports on the modeling of wind turbines
and wind farms. Among them, transient studies, such as flicker assessment, harmonics
impact, fault ride-through, etc, have become one of the most popular ones. Nevertheless,
there are long term studies, such as voltage stability, protection and control, and power-
flow variations that, even though they do not require a detailed system representation, are
of vital importance for the overall electric system stability.
Transient and long term studies require different approaches when modeling the
wind turbines, mainly due to the different time constants involved in the different
analysis.
Figure 3-10 and 3-11 illustrate the different basic structures of a wind turbine for
the different types of analysis.

88
Figure 3-9. Equivalent model frequency response for Δf= - 0.01666 pu
wwind
Pitch control
β = pitch angle
1
⎛ 1 ⎞ −c6 ⋅
c p (λ , β ) = c1 ⋅ ⎜ c2 ⋅ − c3 ⋅ β − c4 ⋅ β x − c5 ⎟ ⋅ e Δ
⎝ Δ ⎠ wwind
1 1 0.035 w⋅ R
= − ;λ=
Δ λ + 0.08 ⋅ β 1 + β 3 v
wwind wgenerator
v 1 Tw dw Tg Pg
Pwind wheel = c p (λ , β ) ⋅ Pwind Blade transients Converter
Pwind = ⋅ ρ ⋅ A ⋅ v3 J⋅ = Tw − Tg − D ⋅ w Generator Grid
2 Mechanical transients dt (optional)
Wind Power Wind Wheel Power Drive train Model
Converter Generator
(optional) controller
Figure 3-10. Dynamic model used for transient studies [38]
Rs' + Rr j ( X s' + X r )
P = f (wind )
− jX c jX m
Figure 3-11. Static model used for steady-state studies [39]
According to an extensive research study undertaken by the National Renewable
Energy Laboratory (NREL) on the short-term power fluctuation of large wind-power
plants, the persistence of the wind and the output of the wind-power plant are very strong
89
within one second time step. In other words, the likelihood of wind power changing from
one level Pi to another level Pj=Pi*( ± 1.1) at the next second is very small (<1.5%) [40]-
[41]. Therefore, since only power fluctuations were of interest for our study, no fast wind
turbine dynamics were incorporated into the system model or system control. The
proposed wind-farm equivalent model is shown in Figure 3-12. A 7.5 HP DC motor acted
as a prime mover and its control was designed to assure that a 5 HP induction generator
followed a given power fluctuation profile.
DC Motor Asynchronous Generator

7.5hp 5hp
3 phase four wire system
Vphase-phase=480 V
Encoder GRID
(w>1800 rpm)
PF
Single caps
quadrant
Encoder
chopper
Vrated field= 150 DC volts

Irated=1.15 Amps
PF correction
Lfield=6.76 H
Ichopper wind farm Rfield=107 Ω
Pout, Qout (V and I)
W rotor1
τ=0.063 secs
real time
data transfer
DSP TI F2812
Ia, Ib wind farm

single phase input
wind power data DC machine controller Vl-n=120 V Vab, Vbc wind
farm
Power Electrical field constant=7.6 Ripple period
Data logging reference
Supervisory
system
Interface Board
(signal conditioning and filtering)
(Output Range 0v to 3v)
(cut-off frequency=100kHz)
Figure 3-12. Wind-farm model
Actual wind-power output data from a wind-power plant in Hawaii was used for
the analysis of the system performance. Before the data was incorporated into the control
algorithm as reference values, they were scaled down according to the system needs and
penetration factors wanted. For instance, a 10 MW rated power wind farm that represents
15% of the system total capacity would have to be scaled down as
Model system capacity = 5 kW

Wind farm penetration level = 15% ( or 750 W)
Actual wind power output data ( MW)
Induction Machine Reference Power = ⋅ 0.15
10 MW
90
The goal was to be able to reproduce any kind of power variation (or wind profile)
typical of wind farms, and its impact on the electric power system.
Wind-Farm Control Algorithm
To generate the required wind-power fluctuations, the following control algorithm
was implemented in a DSP.
Ia, Ib wind farm

I chopper Va, Vb,Vc wind farm
6 channels
A/D inputs
Vdc power
supply
s Ichopper
Pwind farm K derivative +
1 + sT
-
Pwind ref + - + I chopper ref TO CHOPPER
PI controller
+ PI controller PWM
4860Hz
Power regulator Current regulator
Figure 3-13. Wind-farm controller
A derivative control action was added to the PI controller to allow for a fast time
response. Figure 3-14 shows the wind-farm model time response to a 750W step change
(from 0% to full load). It can be deduced from the current chopper reference curve that
the power regulator’s derivative control action was of vital importance in the damping of
the output power ( P wind farm). The system time constant was around 0.25 seconds,
allowing for changes in power references every second.
Wind-Farm Power-Factor Correction
When an asynchronous machine is acting as a generator, excitation currents needed
to create the field excitation are drawn from the electric power system it is connected to.
91
Asynchronous generators are usually equipped with a power factor correction
system for phase compensation of individual machines and/or to regulate voltage at the
point of interconnection.
Figure 3-14. Wind-farm power regulator & current regulator step response (ΔP=100%).
A) Current regulator output. B) Power regulator output.
Figure 3-15 shows the PQ curve of the induction generator used for the modeling
of the wind farm. It can be inferred from Figure 3-15 that
• As the power generated increases so does the reactive power drawn from the
system.
• The PQ curve is strongly biased.
Usually, only the non-load reactive power consumed by the asynchronous
generator is compensated by means of capacitor banks. However, the wind- farm
manufacturers also offer the possibility of 100% compensation using different capacitor
92
bank steps. The largest capacitor bank is always switched on first, once the generator has
been cut-in.
Figure 3-15. Induction generator PQ curve
In order to reduce the amount of reactive current drawn from the electric power
system, a power factor correction capacitor bank was connected in shunt with the
induction machine.
The wind-farm power factor was not corrected 100% to avoid possible self-
excitation conditions during unwanted island mode operations.
The amount of required capacitance required to compensate for a given reactive
power is given by Equation 3-3.
Q3 phase
C= (3-3)
3 ⋅ 2 ⋅ π ⋅ f ⋅ Vl −2 n
Thus, a C ≈ 15 uF capacitor (per phase) was required to compensate for
Q=1300Var, which meant a reduction of approximately 70% in reactive current at the
non-load operation point. Figure 3-16 shows the location and configuration of the PF
capacitor bank.
93
Figure 3-17 shows the power factor correction capacitor bank effect on the wind-farm
output current for the non-load condition. It can be concluded that
• The required reactive current drawn from the electric power system was
significantly reduced.
• Capacitor current created undesired harmonic components that had an impact on

the total output wind-farm current.
GRID
15 uF 15 uF 15 uF
280 V 280 V 280 V
Single
quadrant
Encoder
chopper
Asynchronous Generator
DC Motor 5hp
7.5hp PF correction
Figure 3-16. Wind-farm PF correction capacitor bank
A closer look at the capacitor harmonic current content revealed that the capacitor
impedance did not decrease linearly with the frequency. Figure 3-18 shows the capacitor
impedance at different frequencies.
Figure 3-17. PF correction capacitor bank current waveforms. A) Synchronous machine

voltage. B) Capacitor bank current. C) Induction machine current. D) Wind
farm current.
94
Figure 3-18. Capacitor bank impedance frequency scan
Capacitor current distortion was mainly due to its non-linear behavior at different
frequencies. Thus, synchronous machine voltage harmonics content, in particular 2nd,
3rd, 4th, and 5th harmonics, would exaggerate this nonlinearity, making it more visible.
Wind-Farm Soft-Start System
Wind turbines use soft-start systems to smooth the connection and disconnection of
the generator to the electric power system. It helps minimize high changes of voltage and
current in the grid, while protecting the mechanical parts of the wind turbine against high
torque forces present during the start-up and shut-down.
In the majority of cases, thyristors are used as soft-starters, and these are bypasses
electro-mechanically, once the wind turbine has been started to avoid semiconductor
losses.
Induction machines’ inrush current can sometimes reach values up to eight times
their nominal current, causing protection systems to disconnect the machine from the
power grid. The same type of inrush currents was present in our model during the start-up
of the induction generator. In order to avoid this inrush current, the induction generator
was brought online at the same time the synchronous machine was brought up to the
rated speed (1800 rpm). Figure 3-19 shows a flow chart describing the procedure
95
followed to bring the entire system to nominal values, avoiding any unwanted inrush
current or transient.
The system operated in various modes, some of them stationary, and some of them
temporary. The control sequence was the following:
1. The duty cycle of the synchronous machine’s prime mover was increased linearly,
so that synchronous machine’s V/F ratio was kept as constant as possible (except
when the voltage regulator took control over the excitation field).
2. A speed regulator controlled the duty cycle of the induction machine’s prime
mover in order to track the synchronous machine’s speed during the ramp-up stage.
Thus, the induction machine’s inrush current was minimized.
3. Once both machines were closer to their nominal speed (1800 rpm), the control
system smoothly changed the mode of operation, where the synchronous machine’s
speed and induction machine’s output power were tightly controlled.
Actions
- Disable Chopper PWM1
Reset Mode
- Disable Chopper PWM2
- Initialize regulators
Actions
No Chopper DC
- Clear errors
power supply
- Enable Chopper PWM1
OK?
- Enable Chopper PWM2
Actions
- Disable all control actions
Yes Actions
- Ramp-up duty cycle of synchronous
machine's primer mover
Stop Mode Start-up Mode - Enable speed regulator of induction
machine's primer move
( speed reference induction machine equals
synchronous machine actual speed)
IM speed<90%
Chopper DC
rated speed ?
power supply
&
OK?
SM speed>99% No
rated speed?
No
IM speed>90% rated speed ?

&
SM speed>99% rated speed?
Yes
Actions
Run Mode - Frequency regulation
- Power regulation
Yes SM No
speed>120%
rated speed?
Figure 3-19. Machine control scheme operating states

96
Figure 3-20 shows the system’s performance during the start-up sequence. As
expected, the induction machine’s inrush current during the starting stage was also
insignificant.
Figure 3-21 shows a detail of the transient of the induction machine speed during
the transition between “start-up” mode and “run” mode.
Figure 3-20. Electric power system start-up. A) Machines’ duty-cycle. B) Machines’

speeds. C) Automatic voltage regulator output. D) Synchronous machine
output voltage. E) Wind-farm current.
Figure 3-21. Detail of the transition from start-up mode to run mode
97
Power Stabilizer
Power-Stabilizer Hardware Description
The main components that form part of the wind-farm buffer were:
• Interface board
• Digital Signal Processor (DSP)
• Field Programmable Gate Array (FPGA)
• Intelligent Power Module (IPM)
• Gate Drive board (isolated interface circuit)
All these components were linked to each other one way or another, and their
designs were very interrelated. The major difficulty found when designing and
implementing the Power Stabilizer system was the electrical noise. Sharp edge digital
signals in close proximity to high switching frequency power semiconductors at high
voltage levels required special care in order to make them work in “harmony”.
Figure 3-22 shows the overall power stabilizer system as well as all the major links
between all key components.
Iwind
GRID
Va, Vb, Vc
PCC
Choke Inductor- Filter
5% base on Power 10% base on Power 1 3 5 5

Stabilizer rated Power Stabilizer rated Power 2 2 2 2
g1 g3 g5 gc1
and Voltage and Voltage
Va, Vb, Vc Chopper Reactor
Filter Vdc link
3% base on Power
Ichopper Energy Storage Vstorage
Stabilizer rated Power
Capacitor
and Voltage 4 6 2 5
2 2 2 2
Ia, Ib, Ic g4 g6 g2 gc2
INV
g1 g2 g3 g4 g5 g6 gc1 gc2
Va, Vb, Vc
PCC
Va, Vb, Vc
Filter
Ia, Ib, Ic
INV
Vdc link Ichopper Vstorage
Ia, Ib, Ic wind
farm
GATE DRIVE BOARD
signal conditioning and filtering

INTERFACE BOARD Output Range 0v to 3v
Va, Vb, Vc Va, Vb, Vc Ia, Ib, Ic Vdc link Ichopper Vstorage Ia, Ib, Ic
PCC Filter INV g1 g2 g3 g4 g5 g6 gc1 gc2
wind farm
Error
signals
3 channels 3 channels 3 channels 1 channel 1 channel 1 channel 3 channels
Data Bus (PWM &
Watch Dog)
FPGA
A/D 16 inputs (12 bit)
DSP
Digital Outputs
PWM generation
System diagnosis
Power Stabilizer control algorithm Address
Reset
Synchronization signal
Figure 3-22. Power Stabilizer system overview

98
The following sequence shows how the power stabilizer’s control scheme
functions:
1. Signals from the electric system were scaled down by the interface board to the
appropriated levels before these were sent to the DSP’s A/D converter.
2. To synchronize the PWM-triangular waveform and the DSP’s interrupt service

routine frequency that executed the main control algorithm, the FPGA’s clock
signal was used as the main time base. Thus, every 25.72 µs (or eight times the
PWM switching frequency) the FPGA sent a signal to the DSP to initialize the
execution of the main control algorithm. The DSP processed the input signals and
determined the control actions required to meet particular system’s specifications.
3. Once control actions were calculated by the DSP, these were sent to the FPGA in
the form of clock cycles. The FPGA then compared these signals to a “digital”
triangular waveform (an up/down counter) in order to generate the PWM signals.
4. PWM signals were then passed through a digital dead-time generator to avoid
possible shoot-through currents that could damage the IPMs.
5. PWM signals were then sent to the interface board, where the appropriate scaling
was carried out before these were sent to the gate drive board.
6. Once the PWM signals reached the gate drive board, these were isolated from the
high power side in order to avoid noise problems.
7. IPMs executed the desired control actions.
Other signals that were involved in our design and were not shown in the overall
diagram are
• Protection signals:Trip signals due to over-current, and over-voltage conditions

were present in the interface board and they were provided for the safe operation of
the system. These signals, when active, disabled the PWM control actions without
the intervention of the DSP. The reason for such high-speed response was that the
DSPs interrupt latency could not protect hardware when responding to over-current
through interrupt service routine software.
• WatchDog: The FPGA also contained a special error signal called “WatchDog”. It
basically provided a safeguard against DSP crashes by automatically disabling
PWM control actions if it was not serviced by the DSP at regular intervals.
• Data acquisition signals: To tune and improve system performance a data

acquisition system to monitor system variables was required. Thus, the interface
99
board was equipped with two D/A converters that in real time could show the
DSP’s internal variables. Up to 8 different variables were sampled in real time.
• Data acquisition system: A secondary data acquisition system was also available
through the DSP’s JTAG controller interface with a refreshing time limited to 100
ms (close to 4000 times slower than the DAC system).
Interface board
The interface board’s main function was signaling conditioning while providing
trip signals due to over-current and/or over-voltage conditions. Figure 3-23 shows an
overview of the different functions implemented in the interface board. These functions
were
• Signals scaling (voltage and current)
• Trip signals conditioning
• Power supply voltage monitoring
• FPGA-Gate drive board interface (input and output signals)
• D/A circuit
Signals scaling. The electric power signals had to be scaled down before their
conversion into digital. The DSP ADC data sheet specified that the input range voltage
was from 0.0 V to 3.0 V. Therefore, a signal conditioning circuit was designed to bring
down voltages within ±1000 V range. Figures 3-24, 3-25, 3-26, and 3-27 show the circuit
topologies used in the scaling of the different voltages and currents present in the system.
Voltage at the DC link bus, voltage at the energy storage energy bus, and power
stabilizer currents were the only inputs with trip signals. Moreover, only the DC link
voltage’s scaling & trip circuitry was duplicated, with the purpose of avoiding system
damage due to the loss of one of the instrumentation amplifiers. The DC link voltage
would tend to rise without control, if the system used to measure its value failed.
100
J1 PHOENIX 20
1 VFILTERA
2
3 VFILTERN
4
5 VFILTERB
6 VEXTRA_ERROR
7 VFILTERN
8 DC_LINK_ERROR1
9 VFILTERC
10 DC_LINK_ERROR2
11 VFILTERN
12 VSTORAGE_ERROR
13 VPCCA
14
15 VPCCN
J4
16
17 VPCCB VEXTRA 1
18 2
19 VPCCN
PHOENIX 2
20
J3 PHOENIX 20
AREA1
1 VPCCC VFILTERAOUT
2 VFILTER, VPCC,VDCLINK, VSTORAGE
3 VPCCN VFILTERBOUT
4
5 V_DC_LINK_P1 VFILTERCOUT
6
7 V_DC_LINK_N1 VPCCAOUT
8
9 V_DC_LINK_P2 VPCCBOUT
10
11 V_DC_LINK_N2 VPCCCOUT
12
13 VSTORAGEP V_DC_LINK1
14
15 VSTORAGEN V_DC_LINK2
16
17 VEXTRAP VSTORAGE
18
19 VEXTRAN GND
20
+15V
+5V
+3.3V
GND J2
-15V 1
2
3
J5 PHOENIX 20 4
5
1 IWINDAP 6 J6
2 7
3 IWINDAN 8 1
4 9 2
5 IWINDBP 10 3
6 11 4
7 IWINDBN 12 5
8 13 6
9 IWINDCP 14 7
10 15 8
11 IWINDCN 16 9
12 17 10
13 IESAAP 18 11
14 19 12
15 IESAAN 20 13
16 IWINDA 14
17 IESABP SHROUDED LATCH HEADER FOR RIBBON CABLE STRAIGHT PIN 20 15
18 IWINDB 16
19 IESABN 17
20 IWINDC 18
19
J7 PHOENIX 20 IESAA 20
1 IESACP AREA2 IESAB SHROUDED LATCH HEADER FOR RIBBON CABLE STRAIGHT PIN 20
2
3 IESACN IWIND,IESA, ICHOPPER IESAC
4
5 ICHOPPERP ICHOPPER
6
7 ICHOPPERN GND
8
9
10
11 IESAA_ERROR_P
12
13 IESAA_ERROR_N
14
15 IESAB_ERROR_P
16
17 IESAB_ERROR_N
18
19 IESAC_ERROR_P
20
IESAC_ERROR_N
+15V
ICHOPPER_ERROR_P
+5V
ICHOPPER_ERROR_N
+3.3V
GND
-15V
J10 PHOENIX 10
1 +24V UV+24V
2 +15V UV+15V
3 +5V AREA5 UV+5V
4 +3.3V UV UV+3.3V
5 GND UV-15V
6 -15V GND
7
8 +15V OK
9
10
SHROUDED LATCH HEADER FOR RIBBON CABLE STRAIGHT PIN 20
J9
1 D0
2 D1
3 D2 J8 PHOENIX 20
4 D3
5 D4 D/A OUTPUT1 1
6 D5 2
7 D6 D/A OUTPUT2 3
8 D7 4
9 D8 AREA 3 D/A OUTPUT3 5
10 D9 D/A 6
11 D10 D/A OUTPUT4 7
12 D11 8
13 A0 D/A OUTPUT5 9
14 A1 10
15 LS D/A OUTPUT6 11
16 MS 12
17 CS1 D/A OUTPUT7 13
18 CS2 14
19 GND D/A OUTPUT8 15
20 16
GND 17
18 J13
+15V 19
20 1
+5V 2
3
GND 4
5
-15V 6
7
8
9
10
11
12
UP1A 13
UP2A 14
VP1A 15
VP2A 16
PWM_UP WP1A 17
SHROUDED LATCH HEADER FOR RIBBON CABLE STRAIGHT PIN 10 WP2A 18
J11 PWM_UN UN1A 19
UN2A 20
1 PWM_VP VP1A
2 VN2A SHROUDED LATCH HEADER FOR RIBBON CABLE STRAIGHT PIN 20
3 PWM_VN WN1A
4 WN2A
5 PWM_WP AREA4 UP1B
6 PWM BUFFER UP2B
7 PWM_WN VP1B J12
8 VP2B
9 PWM_CP WP1B 1
10 WP2B 2
PWM_CN UN1B 3
UN2B 4
GND VN1B 5
VN2B 6
WN1B 7
WN2B 8
9
GND 10
11
+15V OK 12
13
14
15
16
17
18
19
20

+3.3V
J14
1 GND
2 U_FOSA U_FOSERRORA
3 AREA6 A
4 V_FOSA IPM ERROR A V_FOSERRORA
5
6 W_FOSA W_FOSERRORA
7
8
9
10 FOSA FOSERRORA
11
12 GND
13 SHROUDED LATCH HEADER FOR RIBBON CABLE STRAIGHT PIN 10
14 +15V OK
J16
15
16 1
17 2
18 3
19 4
20 5
6
+3.3V 7
8
1 GND 9
2 U_FOSB U_FOSERRORB 10
3 AREA6 B
4 V_FOSB IPM ERROR B V_FOSERRORB
5
6 W_FOSB W_FOSERRORB
7
8
9
10 FOSB FOSERRORB
11
12 GND
13
14 +15V OK
15
16
17
18
19
20
J15
Figure 3-23. Interface board overview

101
+15V
+10V CLAMP VOLTAGE
R1 1M 3/4W
-5V TO +5V RANGE C1 D1
VFILTERA
0.1uF 50V 10% 1N914B
7
R2 C2 U1
4.99k 0.6W 1% 0.001uF 50V 10% 3 +
1 R1 R3
6 0 TO +10V RANGE 0 TO +3V RANGE
VFILTERAOUT
8 R2
R6 2 - D2 2.8k 1/4W 1% R4
4.99k 0.6W 1% 1N5817 1.2 k 0.4W 1%
R5 1M 3/4W C3 AD620
0.001uF 50V 10%
5
VFILTERN
+5V
C5
0.1uF 50V 10%
-15V
Figure 3-24. AC voltage scaling circuit (input [-1000+1000V], output [0 +3V])

+3.3V
0 TO +10V RANGE, 9V TRIP (DC +15V +15V +3.3V
LINK TRIP VOLTAGE =900 V)
16
+10V CLAMP VOLTAGE
R40 1M 3/4W
V_DC_LINK_P1 RP1A
1.0k
R41 C26 D13 C36 C34
10K 1/4W 1% 0.1uF 50V 10% 1N914B 0.1uF 50V 10% 0.1uF 50V 10%
14
7
3
C27 U7 +TRIP LEVEL VOLTAGE U9A
1
0.001uF 50V 10%
3 7 +
+
1 R1 1 13 12
DC_LINK_ERROR1
6 6 -
8 R2 U10F
2 - D14 74AHC14
12
1N5817 LM239
7
R43 AD620
10K 1/4W 1% C28
4
5
R42 1M 3/4W 0.001uF 50V 10%
V_DC_LINK_N1
R46
V_DC_LINK1
C29
0.1uF 50V 10% 0 TO +3V RANGE, 2.7V TRIP (DC 2.8k 1/4W 1% R47
-15V LINK TRIP VOLTAGE =900 V) 1.2 k 0.4W 1%
Figure 3-25. DC voltage scaling circuit (input [0 +1000V], output [0 +3V])

+15V
+10V CLAMP CURRENT
R79 1.0k 1/4W 1% C48 D27

-0.5V TO 0.5V RANGE 0.1uF 50V 10% 1N914B
7
TP1 T1 U15
IWINDAP 1 3 +
PIN1 R84 R80 1 R1 0 TO +10V RANGE R85
3 100 1/4W C49 5.49k 1% GAIN 10 6 0 TO +3V RANGE
PIN3 0.001uF 50V 10% IWINDA
TP2 8 R2
IWINDAN 2 2 - D28 2.8k 1/4W 1% R86
PIN2 1N5817 1.2 k 0.4W 1%
AC1005 AD620
4
+5V
C51
0.1uF 50V 10%
-15V
Figure 3-26. CT current scaling circuit (input [-5 +5A], output [0 +3V])
+3.3V
+15V +3.3V
16
LEM1 +15V
R97 0 TO +10V RANGE, C61 RP1E C62
IESAAP +15V +10V CLAMP CURRENT
1.0k 1/4W 1% 1V & 9V TRIP 0.1uF 50V 10% 1.0k 0.1uF 50V 10%
14
-15V
3
IESAAN M +TRIP LEVEL CURRENT U20A

7 +
C58 D33 1 3 4
5
LA 25-NP/SP14 IESAA_ERROR_P
0.1uF 50V 10% 1N914B 6 -
7
R98 C59 U19 U21B

16
137 0.6W 1% 0.001uF 50V 10% 3 + 74AHC14

12
1 R1 LM239 RP1F
7
6 1.0k
8 R2
2 - D34
3
1N5817 U20B
6
AD620 5 +
-TRIP LEVEL CURRENT 2 5 6
4
IESAA_ERROR_N
4 -
+5V
U21C
74AHC14
12
LM239
C60 R101
0.1uF 50V 10%
IESAA
-15V
0 TO +3V RANGE, 0.3V AND 2.7V TRIP 2.8k 1/4W 1% R102
1.2 k 0.4W 1%
Figure 3-27. LEM current scaling circuit (input [-0.36 +0.36A], output [0 +3V])
Power supply monitoring. During the start-up and shutdown of the system, it was
very important to have complete control in order to avoid possible unwanted turn-on of
the power semiconductors. Moreover, if one of the power supplies would fail during
102
normal operation of the power stabilizer, a shut down of the IGBT gating was required in
order to protect the rest of the system. Figure 3-28 shows the power supplies’ voltage
monitoring circuitry used in the interface board.

+3.3V
+5V +3.3V
+15V +24V
C40
C46 R63 R65 R69 0.1uF 50V 10%
R66 R70 0.1uF 50V 10% 10k 1/4W 1% 10k 1/4W 1% 10k 1/4W 1%
13k 1/4W 1% 21.5k 1/4W 1%
U14
14
1 16 U10A
2 VREF VDD 15
3 IN1 MS 14 1 2
IN2 OUT1 UV+15V
4 13
5 IN3+ OUT2 12
6 IN3- OUT3 11
R64 R72 7 IN4+ OUT4 10 74AHC14
7
1.24k 1/4 W 1% 1.24k 1/4 W 1% 8 IN4- DOUT 9
DIN GND
R76 MAX8214
1.24k 1/4 W 1%
U10B
3 4
UV+24V
R81
1.24k 1/4 W 1% 74AHC14
U10C
5 6 +15V
UV-15V
-15V
74AHC14
D19
1N914B
D21
K
Z4 R62
10k 1/4W 1%
1N914B 1N755A
A
D22
Q2
+5V +3.3V 1N914B IRF4905/TO
+5V +3.3V D23
K
+15V OK
Z2
R73 R78 C50 R82 R77
1N755A
K
3.48k 1/4W 1% 1.87k 1/4W 1% 0.1uF 50V 10% 10k 1/4W 1% 10k 1/4W 1% 1N914B R75
10k 1/4W 1% Z3
A
U16 R71
1 16 U10D 1N967B 1.0k 1/4W 1%
2 VREF VDD 15
3 IN1 MS 14 9 8 Q1
A
IN2 OUT1 UV+5V
4 13 2N7000
5 IN3+ OUT2 12
R74 R83 6 IN3- OUT3 11
1.24k 1/4 W 1% 1.24k 1/4 W 1% 7 IN4+ OUT4 10 74AHC14
8 IN4- DOUT 9
DIN GND
MAX8214
U10E
11 10
UV+3.3V
74AHC14
D25
1N914B
D26
1N914B
Figure 3-28. Power supplies’ voltage monitoring
Only when the power supplies were OK a 15 V source (labeled “+15V OK”) was
switched on, allowing the Darlington drivers of the FPGA to control the optocouples
(fault and control signals) of the IPM’s gate drive.
Figure 3-29 shows the system’s critical signals during power-up. It can be inferred
that the voltage monitoring circuit ( +15 Volts OK signal ) was a critical element to
assure that no PWM signals reached the gate drive until all the voltages were stable.
Figure 3-30 shows the system’s critical signals during shut-down. In this case no
glitches were present. However the voltage monitoring circuitry provided a clean system
shut-down, avoiding possible system malfunctions.

103
Figure 3-29. System’s critical signals during turn on. A) AC side. B) 15 volts signal. C)
FPGA’s PWM phase A. D) FPGA voltage supply.
Figure 3-30. System’s critical signals during turn off. A) AC side. B) 15 volts signal. C)
FPGA’s PWM phase A. D) FPGA voltage supply.
FPGA-Gate drive board interface. Gate drive board faults and on/off control
signals were transferred to and from the system controller (FPGA) using optocouplers, so
high and low side control signals could be referred to a common logic level. In our
application board, Darlington transistors (Figure 3-31) were used to drive the diode side
of the optocouplers.
104
+15V OK UP1A
UP2A
VP1A
VP2A
WP1A
WP2A
U31
UN1A
1 16
TO
PWM_UP IN1 OUT1
PWM_UN 2 15
IN2 OUT2 UN2A
PWM_VP 3 14
4 IN3 OUT3 13
FROM GATE DRIVE BOARD

PWM_VN IN4 OUT4 VP1A
PWM_WP 5 12
6 IN5 OUT5 11
PWM_WN IN6 OUT6 VN2A
7 10
FPGA 9
IN7
COM
OUT7
WN1A (isolated interface board)
WN2A
MC1413
UP1B
UP2B
U32
VP1B
PWM_CP 1 16
IN1 OUT1 VP2B
PWM_CN 2 15
3 IN2 OUT2 14
IN3 OUT3 WP1B
4 13
5 IN4 OUT4 12
IN5 OUT5 WP2B
6 11
7 IN6 OUT6 10
IN7 OUT7 UN1B
9
COM UN2B
K
Z6
VN1B
MC1413
1N967B
VN2B
A
WN1B
WN2B
Figure 3-31. Darlington drivers
Status signals from the IPM, once isolated by the gate drive board, are scaled down
in order to be processes by the FPGA (Figure 3-32).

+15V OK +3.3V
C41
0.1uF 50V 10%
R120
5.5k 1/4W 1%
14
U33A
R12830k 1/4W 1%
U_FOSA 1 2
U_FOSERRORA
C88
R136
FROM 0.001uF 50V 10% 10k 1/4W 1%

74AHC14
7
GATE DRIVE BOARD

R121
5.5k 1/4W 1% TO
(isolated interface board) V_FOSA
R12930k 1/4W 1%
3
U33B
4
V_FOSERRORA
FPGA
C89
R137
0.001uF 50V 10% 10k 1/4W 1%
74AHC14
R122
5.5k 1/4W 1%
U33C
R13030k 1/4W 1%
W_FOSA 5 6
W_FOSERRORA
C90
R138
0.001uF 50V 10% 10k 1/4W 1%
74AHC14
R123
5.5k 1/4W 1%
U33D
R13130k 1/4W 1%
FOSA 9 8
FOSERRORA
C91
R139
0.001uF 50V 10% 10k 1/4W 1%
74AHC14
Figure 3-32. IPM status signals interface circuitry
D/A circuit. Real time system diagnostics could be carried out by the usage of D/A
converters controlled by the DSP. The goal was to be able to identify potential problems
and to evaluate system performance. Thus, every time the DSP executed the control
algorithm, the DACs were updated with new values from the DSP.
The number of DAC-channels available was 8, and the range of output voltage was
programmable from the DSP, having a maximum of ±10V. Figure 3-33 shows the circuit
used for the control of the DAC.

105
+5V -15V +15V
C78 C76 C82

0.1uF 50V 10% 0.1uF 50V 10% 0.1uF 50V 10%
42
5
D0 28 7
VEE
VLL
VCC
29 D0 RFA
D1 D1 D/A OUTPUT1
D2 30 8
31 D2 VOA
D3 D3
D4 32 10
33 D4 RFB
D5 D5 D/A OUTPUT2
D6 35 9
36 D6 VOB
D7 D7
D8 37 12
38 D8 RFC
D9 D9 D/A OUTPUT3
D10 39 13
40 D10 VOC
D11 D11 15
RFD
U27 D/A OUTPUT4
14
AD664 (44 pin) VOD
A0 19
20 DS0
A1 DS1
23
24 QS0
25 QS1
QS2
LS\ 2
27 LS
MS\ MS
CS1 18
CS
+5V
1
26 RD
+5V TR
DGND
AGND
VREF
RST
R118
22
11
21
10k 1/4W 1%
4
GND
GND
+15V
C80 U29
0.1uF 50V 10%
2 6
+VIN VOUT
C83 8 C84
GND
0.1uF 50V 10% 5 NOISE 1uF 50V 10%
TRIM
AD587JN
4
+5V -15V +15V
C79 C77 C85

0.1uF 50V 10% 0.1uF 50V 10% 0.1uF 50V 10%
42
5
28 7
VEE
VLL
VCC
29 D0 RFA
D1 D/A OUTPUT5
30 8
31 D2 VOA
32 D3 10
33 D4 RFB
D5 D/A OUTPUT6
35 9
36 D6 VOB
37 D7 12
38 D8 RFC
D9 D/A OUTPUT7
39 13
40 D10 VOC
D11 15
RFD
U28 D/A OUTPUT8
14
AD664 (44 pin) VOD
19
20 DS0
DS1
23
24 QS0
25 QS1
QS2
2
27 LS
18 MS
CS2 CS
+5V
+5V 1
26 RD
TR
DGND
AGND
VREF
RST
R119
10k 1/4W 1%
22
11
21
+15V
C81
0.1uF 50V 10% U30
2 6
+VIN VOUT
C86 8 C87
GND
0.1uF 50V 10% 5 NOISE 1uF 50V 10%

TRIM
AD587JN
4
Figure 3-33. DAC circuit
Digital signal processor
The controller selected for this application was the DSP F2812 from Texas
Instruments.
The main features of the DSP development board are:
• TMS320F2812 Digital Signal Processor operating at 150 MHz

− 32-Bit CPU
− 18 K on chip RAM
− 12-Bit ADC, 16 Channels
− 56 Individually Programmable, Multiplexed GPIO Pins
106
• 128 K on chip FLASH ROM

• 64 K words on board RAM
• Expansion Connectors
• Onboard IEEE 1149.1 JTAG controller
Different alternatives were evaluated for the control of the power stabilizer.
However, mainly due to cost reasons and processing speed, the DSP F2812 was the
chosen option for this type of application. The alternatives under consideration are
summarized in Table 3-2.
Table 3-2. Alternatives for the power stabilizer controller

Controller Price Comments
Matlab Real Time Workshop $7,500.00 Maximum speed: 10 kHz
Matlab Real-Time Windows Target $2,000.00
Real-Time Linux Freeware Long learning curve to be
proficient at it.
National Instruments : NI PXI-8186 Real-Time $4495.00 Data acquisition system
(42 kHz single PI loop) + LabView Real- with onboard processor
Time
Microstar Laboratories: DAP5400a $4000.00 Data acquisition system
with onboard processor
Texas Instruments TMS320C2812 DSP $300.00
development kit
Field-programmable gate array
A Field Programmable Gate Array or FPGA is an integrated circuit that can be
programmed, and it is specially designed for prototyping integrated circuit designs.
In this application the FPGA developed two basic tasks:
• PWM generation ( “digital” triangular waveform, circuit comparator, and dead-

time generator)
• Error signals’ processing
Despite the fact that the DSP F2812 was capable of generating up to 10
independent PWM outputs, signals were allowed to change only twice per cycle. Figure
3-34 explains this limitation in the built-in PWM circuit.

107
As it will be elucidated later, a PWM generator was implemented in the FPGA, so
that the system’s response was improved by allowing multiple changes within a cycle.
Moreover, simple logic was included in the PWM generator so dead-time and error
signals could be taken into account before PWM signals were sent to the gate drive
board.
The basic features of the development board used with the FPGA are
• Actel APA075 ProASIC Plus FPGA

• Maximum System Gates 75000
• Embedded RAM bits 27*1024
• Maximum user I/O 158
• On board clock oscillator ( 40 Mhz)
• Eight LED’s
• Four switches
Timer value Step change
(counts)
Triangular waveform
Signal
Time
TMX320F2812
PWM output
Missed
Desired PWM pulse
output
(FPGA output)
Figure 3-34. DSP built-in PWM output performance vs. FPGA
Intelligent power module
The Intelligent Power Module or IPM is an isolated base module, composed of
several IGBTs and designed to reduce the system’s development time, thanks to its built-
in gate drive circuit. The IPM module selected for this application was the PM50RSA120
IPM from Powerex. Its main features were
• Gate Drive Circuit

108
• Protection Logic: short circuit, over current, over temperature, under voltage
• Maximum collector-emitter voltage 1200 V
• Collector Current 50 Amps
• Maximum PWM input frequency 20 kHz
• Minimum dead-time 3.0 µs
Figure 3-35 shows the power circuit configuration of the PM50RSA120. The brake
section (B) of the IPM was not used in the implementation of the power stabilizer.
B V
Figure 3-35. IMP power circuit configuration
Isolation interface circuit
One of the critical components in the design of the power stabilizer was the
interface circuit between the IPM and the low side control signals. Even though the IPM
had a built-in gate drive, there were still some interface circuit requirements that had to
be satisfied in order to avoid noise problems. The isolation interface required was
provided by optocouplers, which would be driven by the Darlingtons transistors of the
interface board. Figure 3-36 shows the isolated interface circuit used for the IPM.
Power Stabilizer Software Description
The software tools used in the programming of the FPGA and the DSP are Actel
Libero Gold Integrated Design Environment (IDE) and Texas Instruments Code
Composer Studio (CCS).
Different C code generation tools were considered in order to reduce system
development time and to increase flexibility and readability in the design. The different
109
alternatives evaluated were VisSim/Embedded Controls Developer from Visual Solutions
and Matlab embedded target for TI C2000 toolbox. However, neither one of them offered
the flexibility, readability and efficiency needed for this type of application.
U61
4 14
+20V_IN +15V_4 J16
5 1 1
+20V_IN 1 1 GND
13 2 2
COM_4 2 2 U_F0S
6 3 3
+20V_IN 4 3 3 4
4 4 V_F0S
5 5
12 6 5 5 6
+15V_3 6 6 W_F0S
TO INTERFACE BOARD
7 7
8 7 7 8
J17 8 8 BRC
11 9 9
P_20V C19 COM_3 10 9 9 10
1 N_20V 330uF 10 10 F0S
11 11
(status signals)
2 12 11 11 12
12 12 +20V
10 13 13
VOLTAGE SUPPLY 20 V F +15V_2 14 13 13 14
15 14 14 15
9 16 15 15 16
COM_2 17 16 16 17
1 18 17 17 18
COM_IN 19 18 18 19
2 8 20 19 19 20
COM_IN +15V_1 20 20
3 CONN 20 F
COM_IN 7
COM_1
M57140-01
J18 U62
UP1 1 1
2 1 1 2 1 8 V_UP1
UP2 2 2 NC1 VCC U63
3 3
4 3 3 4 R43 ??? 20 KOhms 8 1
VP1 4 4 VCC NC1
5 5 2 7 U_P
VP2 5 5 ANODE VL
6 6 20 KOhms
7 6 6 7 7 2 V_UP1
WP1 7 7 VL ANODE
8 8 RU 3 6 R44
WP2 8 8 CATHODE VO
9 9 10k
10 9 9 10 C20 C21 6 3 U_F0
UN1 10 10 SHIELD VO CATHODE
11 11 4 5 0.1uF 10uF V_UPC
UN2 11 11 NC4 GND
12 12 C22
13 12 12 13 0.1uF 5 SHIELD 4
VN1 13 13 HCNW4506 GND NC4
VN2 14 14
15 14 14 15
16 15 15 16 HCNW4506
WN1 U64
17 16 16 17
WN2 17 17
18 18 1 8 V_VP1
19 18 18 19 NC1 VCC
20 19 19 20 R45 ??? 20 KOhms
20 20 2 7 V_P
ANODE VL U65
CONN 20 F
8 1
SU 3 6 R46 VCC NC1
CATHODE VO 10k 20 KOhms
C23 C24 7 2 V_VP1
4 SHIELD 5 0.1uF 10uF V_VPC VL ANODE
NC4 GND
FROM INTERFACE BOARD HCNW4506 6 3 V_F0

VO CATHODE
C25
U66 0.1uF 5 SHIELD 4
GND NC4
(control signals) R47 ???

1
2
NC1
20 KOhms
VCC
8
7
V_WP1
W_P
HCNW4506
ANODE VL
TU 3 6 R48
CATHODE VO 10k U67
C26 C27 8 1
4 SHIELD 5 0.1uF 10uF V_WPC VCC NC1
NC4 GND 20 KOhms
HCNW4506 7 2 V_WP1
VL ANODE
U68 6 3 W_F0
VO CATHODE
1 8 V_N1 C28
NC1 VCC 0.1uF 5 SHIELD 4
R49 ??? 20 KOhms GND NC4
2 7 U_N
ANODE VL HCNW4506
RL 3 6 R50
CATHODE VO 10k
C29 C30
4 SHIELD 5 0.1uF 10uF V_NC U69
NC4 GND
HCNW4506 1 8 V_N1
NC1 VCC
R51 1.5 K 20 KOhms
2 7 BR
ANODE VL
U70
1 8 3 6 C31
NC1 VCC CATHODE VO 0.1uF
R52 1.5k 20 KOhms
2 7 V_N 4 SHIELD 5 V_NC
ANODE VL NC4 GND
HCNW4506
SL 3 6 R53
CATHODE VO 10k
C32 C33
4 SHIELD 5 0.1uF 10uF
NC4 GND
HCNW4506
U71
8 1
VCC NC1
U72
20 KOhms
1 8 7 2 V_N1
NC1 VCC VL ANODE
R54 ??? 20 KOhms
2 7 W_N 6 3 F0
ANODE VL VO CATHODE
C34
TL 3 6 R55 0.1uF 5 SHIELD 4
CATHODE VO 10k GND NC4
C35 C36
4 SHIELD 5 0.1uF 10uF HCNW4506
NC4 GND
HCNW4506
Figure 3-36. Isolated interface board
Figure 3-38 shows the name of the variables used in the programming of the DSP
and FPGA, and also the different links between the different sub-systems.
Description of DSP program
The programming of the DSP power stabilizer control and communications was
probably the most complex one in our entire project, since it required the knowledge not
only of the control algorithm, but of the system configuration as well.
To increase the readability of the code, a series of object oriented modules were
created in C. The majority of the modules were generated using the IQmath, a quasi
floating point toolset, from Texas Instruments [42], with the intention of increasing the
110
control algorithms’ accuracy. A detailed description of the main modules used in the
implementation of the control scheme can be found in Appendix C.
The power stabilizer control algorithm was split in main blocks according to the
time constants involved. These two blocks were the “power limiters control loop”, and
the “current controller loops”. Figure 3-37 explains how the control algorithm was
divided into two sections and the components that were included in each one.
On the one hand, power fluctuations due to changes in wind speed were not
expected to have significant changes within time intervals smaller than 100 milliseconds.
Thus, a control loop with a sampling frequency equal 10 Hz was used to determine the
amount of power required to filter out wind-farm power variations. On the other hand,
since the inverter performance was based on how accurately the system current was
controlled, inner current loops had a faster sampling rate.
The splitting up of the control scheme into two main loops released some time out
of the DSP, and reduced the amount of data needed to be stored.

Iwinda
X Ramp Rate Vstorage
Vpcca Average Inst
Iwindb + Wind
X + Power
Limiters
Centering
Vpccb algorithm 10Hz
+ Vpcc_offset
Iwindc Klimit
Vpccc X + -
ESA required
+ power
+ -
+ Allowedcenteringpower Idrinv Vdf wLIqinv
38880 Hz
Constant angle
PowerInverter
Reference - + Max Magnitude
Idref Idref + Vdinv Vapu
1.5 pu
PI regulator + - + + PWMVa
Vdqinv V dqinv_limited V dinv _limited iPark V1
-1.5pu
Vdqinv = V 2
+V 2 Vdqinv_lim ited iClark V1
- -
Current Limiter dinv qinv Vdinv_limited = V ds inv d -q
Vdr Vpcc_offset 0
1 + K dqinv
2 dr-qr s s V bpu + +
Vqinv Vqs inv PWMVb
M M
K dqinv = K dqinv V qinv _limited ds -qs abc
- Kp Vdinv Vqinv_limited = K dqinv ⋅Vdinv_limited - -
Vpcc ref + + M Iqref + + Vqinv V c pu + +
PI regulator sin(theta) cos(theta) PWMVc
- Ki
1
M + -M
- + +
s
- -
Vpcc positivesequence
-M
Iqr inv Vqf wLIdinv

V flata
V dc
(formodulationindex
calculation) +
Vflatb + Vflat
2 +
Vflatc
Clark I1 Park I1
Iinva Ids
Iinvb abc ds-qs Idrinv To current
Iqs
Iinvc ds-qs dr -qr Iqr inv regulator
Ios
Clark V1 PLL
V pcca Vds
V pccb abc PLL
sin(theta)
V qs (2 sec time constant)
V pccc ds -qs cos(theta)
Vos Theta Park V1

V ds Vds ds-qs Vdr To current
Vqs V qs regulator
dr -qr V qr
Vqs Vds sin(theta) cos(theta)
+
Delay - Vds positivesequence Park V1 positivesequence
Vdrpositivesequence Slidingwindowfilter
0.5 (1cycle)
(t-1/f /4) X
ds -qs + Vpcc positivesequence To PCC voltage
+ Filter
regulator
Delay + Vqs positivesequence dr -qr Vqrpositivesequence X +
0.5
(t-1/f /4)
V2dcref + PI regulator
Iinva -
V fa X V2dc
Iinvb + + Ichopperref + Vchopper

Vdc_link
V chopperpu +
X
Inv erter Power + KL - Vchopper_limited
V fb -
+ + -Vdc_link
-
Iinvc PWMchopper
X
V fc
V storage Ichopper Vstorage V dc
(formodulationindex
calculation)
Figure 3-37. Power stabilizer control algorithm sampling rates

WF1
WIND FARM
Phase C
Phase B
Phase A
3
2
1
IWINDAP
GND
GND
GND
GND
GND
GND
GND
GND
D0 D0
D1 D1 IWINDAN
D2 D2
D3 D3 IWINDBP
D/A OUTPUT8
D/A OUTPUT7
D/A OUTPUT6
D/A OUTPUT5
D/A OUTPUT4
D/A OUTPUT3
D/A OUTPUT2
D/A OUTPUT1
D4 D4
D5 D5 IWINDBN
D6 D6
D7 D7 IWINDCP
D8 D8
D9 D9 IWINDCN
D10 D10
D11 D11
D12 D12
GPIO
D13 D13
VPCCA
WR WR
VPCCN
A0 A0
A1 A1 VPCCB
A2 A2
VPCCN
LDAC LDAC
1
1
1
VPCCC
GND GND VPCCN
2
2
2
VFILTERA
VFILTERN
L6 TRAFO EQUIVALENT 5%
VFILTERB
VFILTERN
IWINDA VFILTERC
C1
IWINDA
DSP
IWINDB IWINDB VFILTERN
IWINDC IWINDC
C FILTER 10%
DSP Development Board

C3
VPCCA VPCCA
VPCCB VPCCB
VPCCC VPCCC
C FILTER 10%
VFILTERA
C5
VFILTERA
A/D
VFILTERB VFILTERB
VFILTERC VFILTERC
1
1
1
C FILTER 10%
IESAA IESAA
IESAB IESAB
IESAC IESAC
2
2
2
V_DC_LINK1 V_DC_LINK1
L7 L FILTER 10%
L4 L FILTER 10%
L2 L FILTER 10%
V_DC_LINK2 V_DC_LINK2
IESAAP
ICHOPPER ICHOPPER
IESAAN
VSTORAGE VSTORAGE
IESABP
GND GND IESABN
IESACP
IESACN
UP1A UP1
UP2A UP2
IPM1
IPM 1
VP1A VP1
VP2A VP2
PWM_D11
PWM_D10
PWM_A1
PWM_A0
RESET
PWM_LATCH
PWM_WR
SF STOP
PWM_D9
PWM_D8
PWM_D7
PWM_D6
PWM_D5
PWM_D4
PWM_D3
PWM_D2
PWM_D1
PWM_D0
GND
WP1A WP1 V_UPC
WP2A WP2 U_F0
U_P
UN1A UN1 V_UP1
UN2A UN2 V_VPC
V_F0
VN1A VN1 V_P
VN2A VN2 V_VP1
V_WPC
WN1A WN1 W_F0
WN2A WN2 W_P
V_WP1
MEASUREMENT
IPM interface board A
IPM INTERFACE A
V_NC
GND
V_N1
RESET
Measurement & Interface board
BRCA BRC BR
PWM_A1
PWM_A0
SF STOP
PWM_D9
PWM_D8
PWM_D7
PWM_D6
PWM_D5
PWM_D4
PWM_D3
PWM_D2
PWM_D1
PWM_D0
PWM_WR
PWM_D11
PWM_D10
U_N
V_N
PWM_LATCH
U_F0SA U_F0S W_N
V_F0SA V_F0S F_0
W_F0SA W_F0S
F0SA F0S
VDD
+20V +20V
HW STOP
GND GND
S1
PWM_UP PWM_UP
PWM_UN PWM_UN V_DC_LINK_P1
V_DC_LINK_P2
HW STOP BUTTON
PWM_VP PWM_VP
C2
PWM_VN PWM_VN
V_DC_LINK_N1
PWM_WP PWM_WP V_DC_LINK_N2
C DC LINK
PWM_WN PWM_WN
IPM2
IPM 2
PWM_CP PWM_CP UP1B UP1

UP2B UP2
PWM_CN PWM_CN
VP1B VP1
VP2B VP2
GND GND
WP1B WP1 V_UPC
WP2B WP2 U_F0
U_P
FPGA
UN1B UN1 V_UP1

UN2B UN2 V_VPC
UV +24V UV +24V V_F0
VN1B VN1 V_P
Figure 3-38. Interconnections between the different sub-systems of the power stabilizer
UV +15V UV +15V VN2B VN2 V_VP1
FPGA Develpment Board
V_WPC
UV +5V UV +5V WN1B WN1 W_F0
WN2B WN2 W_P
UV +3.3V UV +3.3V V_WP1
IPM interface board B
IPM INTERFACE B
V_NC
UV -15V UV -15V V_N1
BRCB BRC BR
DC_LINK_ERROR1 DC_LINK_ERROR1 U_N
V_N
DC_LINK_ERROR2 DC_LINK_ERROR2 U_F0SB U_F0S W_N
V_F0SB V_F0S F_0
VSTORAGE_ERROR VSTORAGE_ERROR W_F0SB W_F0S
FOSB F0S
IESAA_ERROR_P IESAA_ERROR_P
IESAA_ERROR_N IESAA_ERROR_N +20V +20V
IESAB_ERROR_P IESAB_ERROR_P GND GND
1
IESAB_ERROR_N IESAB_ERROR_N
IESAC_ERROR_P IESAC_ERROR_P
IESAC_ERROR_N IESAC_ERROR_N
2
ICHOPPER_ERROR_P ICHOPPER_ERROR_P
L5 L CHOPPER
ICHOPPER_ERROR_N ICHOPPER_ERROR_N ICHOPPERP

U_FOSERRORA U_FOSERRORA ICHOPPERN
V_FOSERRORA V_FOSERRORA
W_FOSERRORA W_FOSERRORA
FOSERRORA FOSERRORA
U_FOSERRORB VSTORAGEN
C4
U_FOSERRORB
V_FOSERRORB V_FOSERRORB VSTORAGEP
W_FOSERRORB W_FOSERRORB
C STORAGE
FOSERRORB FOSERRORB
+3.3V
+5V
-15V
GND
+15V
+24V
GND GND
+5V
-15V
GND
+15V
+24V
+3.3V
PWR1
POWER SUPPLY
GND
111
112
As stated in the previous chapter, the switching frequency selected for the power
stabilizer was 4860 Hz. However, the inner loop regulators had a sampling frequency that
was 8 times the PWM frequency. The goal was to reduce inverter time responses to
system transients, increasing the power stabilizer’s bandwidth. This technique is called
re-sampled uniform PWM [43], and is a digital approximation to the naturally sampled
PWM technique.
A flow chart illustrating the different stages the power stabilizer undergoes is
shown in Figure 3-39.
The time base used for the power stabilizer control algorithm was based on the
FPGA synchronization signal that would force the DSP to run at 38,880 Hz.
During the start-up of the machine, the front-end inverter of the power stabilizer
acted as a three phase rectifier, charging the DC link capacitor bank. Once the simulated
electric network was running at rated frequency and voltage, the chopper of the power
stabilizer would charge the energy storage system to 90% its nominal value. Then the
control system would reverse the power through the chopper, so the DC link voltage
could be charged to its nominal value. Once both systems, the DC link bus and the ESS,
were within a reasonable range and close to their nominal values, the power stabilizer
switched to normal mode, where power could flow in both directions.
Figure 3- 40 shows the power interchange between the electric power system and
the power stabilizer, during the different stages.

113
Modules
Data acquisition
Initialization
Watchdog reset
A/D offsets
calculation
Data convertion
A/D offsets
calculation Overcurrent
protection
Power Limiter Operation

control scheme Mode
Background Wait mode

control loop
(f=10 Hz) Vdc_link>590V?
No
Yes Yes
Charging Energy No
Vdc_link>590V?
Storage
No
105%<Energy>90% ?
Yes Yes
No
Charging DC link Vdc_link>590V?
No
DC Energy>95% ?
Yes
FPGA synchronization Run mode

signal (f=38880 Hz)
Foreground
control loop
(f=38880 Hz)
Figure 3-39. Power stabilizer control stages
DC link charge during

machines start-up sequence
STAGE 1
ESS is charge to 90% of its

nominal value
STAGE 2
DC link is charged to
STAGE 3 800Volts
Normal operation
STAGE 4
Figure 3- 40. Power stabilizer start-up sequence

114
During the Power stabilizer’s normal operation, several tasks, besides the control
algorithm, had to be carried out. These actions were
• Update control actions

• Update data logging for PC-DSP communications
• Refresh DAC
• Update FPGA PWM signals
FPGA program description
All the main system components ended up using part of the FPGA for different
purposes. However, the main functions were for PWM and error generation.
The FPGA code was split into two independent systems, one for the control of the
different machines and the other for the control of the power stabilizer. Figure 3-41
shows the main modules implemented in the FPGA (the software tool used for the
programming is ViewDraw from Actel ).
Among all these modules, only three were of vital importance for the proper
performance of the system. The main modules were
• PWM generator and the DSP synchronization

• Dead time generator
• Watchdog logic
PWM generator and DSP synchronization. The basic idea consists of using an
up/down counter as a triangular waveform generator, so the up/down counts can be
compared to voltage demand for phase a, phase b, phase c, and the chopper.
The PWM triangle count used a counter that was one more bit than the up/down
triangular count would require. For instance, for an up count of 0-1023, and a down count
of 1023-0, instead of using a 10 bits counter, the one used for this approach would be 11
bits (N bits). The higher order Nth bit was used to invert the lower order N-1 bits when it
was high (Figure 3-42). Only the lower order N-1 bits were used in the triangle
115
comparator, since a 10-bit word was sent from the DSP to the FPGA, containing
information on the voltage commands.
The format of the word sent from the DSP to the FPGA required a small code
manipulation, before it was actually compared to the up/down triangle. Since the DSP
voltage commands were represented by signed integers, a flip of the highest order bit was
all that was need to convert a signal from signed 1.x to unsigned integer. For instance, a
(10bits) #0000000000 would be converted into #1000000000, which is about half of the
count range. B#1000000000 would convert to B#0000000000, the minimum, and
B#0111111111, would be B#1111111111, the maximum.
As far as the maximum value that could be sent to the FPGA, there were a couple
of remarks; it was possible to send values that ranged between the minimum and
maximum triangle count. However, this presented the following problem; when the
values were B#0000000000 >= B#0000000000, the output was high, and when it was
B#1111111111 >= B#1111111111, the output was also high. This gave a high bias to the
output for an average around zero. This effect was canceled out by the fact the number
range was one count larger in the negative direction. The other problem was that as very
narrow notches were being generated, the underlap circuitry that prevented shoot-
throughs did a poor job of reproducing them. The device in the pole with the high duty
cycle continued to switch until the notch disappeared. Suddenly, the underlap circuit was
not required to do anything, and the voltage took a small jump in the direction of the high
duty cycle switch. The low duty cycle switch stopped conducting when the notch time
got to be shorter than the underlap time. The dead-time presented a problem in that the
current defined what the voltage ended up being during this time. However, when the low
116
duty-cycle switch stopped coming on, the problem become worse. One way to reduce
both of these effects was not to send a value that would stop the low duty cycle IGBT
from switching. This value was approximately defined as:
Maximum output voltage = 1 − 2 ⋅ dead − time ⋅ modulation frequency
Thus, if the dead-time is 2 µsec, the maximum value that can be sent to the FPGA
is 0.96 pu.
Figure 3-41. FPGA system overview

117
A B
Figure 3-42. Up/Down counter. A). Digital triangular waveform. B).Detail of the count-
fold effect.
The output of the comparators (A>=B) were cleaned up by the D flip-flops at the
outputs since the comparator outputs could transiently glitch as the logic settled, after a
rising clock-edge. These PWM state signals were then sent to dead-time generators as
shown in Figure 3-43.
finput=40 Mhz f output=10 Mhz
DSP synchronization
signal
Deadtime generator
PWM generator
Figure 3-43. PWM generator

118
The DSP synchronization pulse was a latched (and one clock delayed) signal and
generated 8 times per PWM cycle (4860Hz). It was true one clock cycle after any count,
when the least significant 8 bits were low. Therefore, the DSP control loop ran at a
frequency of 38,880Hz
Note: Due to clock limitations, the actual PWM frequency was 10MHz/211 =
4882.8 Hz, and the DSP control loop frequency was 10 MHz/28 =39063 Hz. These values
were only 0.47% off compared to the designed values.
Dead-time generator. The dead-time generator ensured that no shoot-through
conditions were given in the IPM module. The IPM minimum dead-time was 3µsec,
consequently a 4µsec dead-time was used in order to guarantee system performance
during switching conditions.
Figure 3-44 shows how the dead-time generator was implemented in the FPGA.
Two counters were turned on/off according to the PWM input signal. Their output signals
(counts) were then compared to a constant (number of counts). In this case the constant
selected was 40. Thus, the delay-time was:
constant 40
dead − time = = = 4μ sec
clock frequency 10Mhz
PWM output signals were then enabled or disabled based on a trip signal that
included information about all the possible flags/errors in the system.
Figure 3-45 shows the FPGA dead-time performance for phase A of the front-end
inverter.
119
PWM
upper IGBT
PWM
PWM
lower IGBT
CLOCK-SIGNAL
ERROR-SIGNAL
Figure 3-44. One phase dead-time generator detailed diagram
Figure 3-45. Dead-time generator’s waveforms
Watchdog logic. The F2812 DSP has a built-in watchdog timer that provides a
safeguard against CPU crashes by automatically initiating a reset if not serviced by the
CPU at regular intervals. This is a very useful tool for applications where the PWM
signals are generated from the DSP, since any CPU reset will put the PWM outputs to a
high impedance state, which should turn off the power converter. However, for our
application, the PWM generation was carried out by the FPGA, and therefore a built-in
watchdog timer had to be implemented. Figure 3-46 shows the logic used to realize the
watchdog timer that mimicked the one implemented in the DSP.

120
Watchdog
counter
29 different
error signals
Figure 3-46. Watchdog logic
The Watchdog timer was a 9-bit counter that generated an error signal (terminal
count) after 2 9 = 51 . 2 μ sec , if not serviced by the DSP. The way the DSP attended
10 Mhz
the watchdog timer was by sending a specific word to the FPGA. The following table
explains meaning of the different words used for the control of the watchdog timer, and
also the reset signals.
Table 3-3. FPGA code words

Value written
Objective Description
into the data bus
Reset error signals 0x055 This value will clear all the flip-flops
used to latch error signals
Watchdog reset 0x0AA This value will reset the watchdog timer
Front-end inverter and 0x0EE This value will disable both, the inverter
Chopper turn off signal and the chopper of the power stabilizer
Inverter turn-on signal 0x088 This value will enable the inverter part
of the power stabilizer
Chopper turn-on signal 0x033 This value will enable the chopper part
of the power stabilizer
Note: It is assumed that a DSP general purpose I/O pin was assigned to latch the
FPGA data input. The latched value was cleared by the “DSP synchronization” signal; so
that no values were held in the latch for more than one DSP control loop cycle. In this
application the GPIO had the name of DSP_WD.

CHAPTER 4
SYSTEM PERFORMANCE
System Data
Table 4-1 summarizes the system parameters used in the modeling of the power
stabilizer system. A comparison with the ideal values based on the per-unit designed
system is also included.
These differences caused a small deviation from the ideal system. However, the
overall system performance was not significantly decreased.
Power Stabilizer Transient Response
The following sections illustrate the power stabilizer response due to step-changes
in the different values. System performance was analyzed under various scenarios.
Direct-Current Link Voltage Control
One of the key variables in the overall system performance was the voltage at the
DC link bus, since PWM control actions were based on it. Thus, its value had to be
tightly controlled.
Figure 4-1 and Figure 4-2 show the DC link voltage responses to a step-change in
the voltage reference for different regulator gains.
Figure 4-1. DC link voltage response for different Kp gains
121
122
Table 4-1. System parameters

Per-unit Ideal Real
Variable
model model model
DC link time constant (sec) 0.022 0.022 0.032
ESS time constant (sec) ( @ Vess max) 20.45 20.45 22.23
Chopper current ripple (pu) 0.3 0.3 0.34
PWM (Hz) 4860 4860 4860
X/R 10 10 18
Xfilter (pu) 0.1 0.1 0.103
Xtrafo (pu) 0.06 0.06 0.074
Cfilter size (Vars pu) 0.03 0.03 0.029
Vmax line-neutral 1 391.92 391.92
I max inverter nominal 1 0.256 0.256
Vdc nominal 2.04 800 800
Vrms line-neutral 0.71 277.13 277.13
Irms inverter nominal 0.71 0.18 0.18
Zbase (Ω) 1 1536 1536
Pinverter 1.5 150 150
Vstorage max 1.94 760 760
Vstorage min 0.97 380 380
Vstorage center 1.53 600.83 600.83
Cdc link (mF) 16 0.0103 0.015
Cstorage (F) 16.323 0.0106 0.0116
Lchopper (mH) 0.5 768.18 660
Rchopper (Ω) 0.019 28.96 14.6
Lf (mH) 0.265 407.44 420
Rf (Ω) 0.01 15.36 8.2
Cf (uF) 79.58 0.052 0.050
Lt (mH) 0.159 244.46 300
Rt (Ω) 0.006 9.22 7.00
Kp current regulator 1 1 1
Ki current regulator (R/L) 37.7 37.7 18
Kc (charge/discharge 0.0064 0.00647 0.00647
constant)(Watts/Joules)
1/2*Cstorage (pu) 8.16 8.16 8.86
K=1/2*Cstorage (pu) * Kc (Watts/Volts2) 0.052 0.052 0.057
Figure 4-2. DC link voltage response for different Ki gains

123
It can be inferred from Figures 4-1 and 4-2 that the DC link voltage regulator was
very robust, and that large changes in the regulator’s gain would not affect the system
performance. In general, higher proportional gains improved DC link voltage settling
time, without causing any system overshoot as in the case of high integral gains.
However, higher gains caused control actions to saturate and could have originated
instabilities.
Reactive Current Control
The core of the Power stabilizer was the inner current regulators. Their
performance determined the overall system response. The current regulators’ robustness
is shown in Figure 4-3 and Figure 4-4. As expected, the increase in the integral and/or
proportional gains had no major impact on the current response. This was due to the
saturation of control actions, as seen in Figure 4-5. The original current regulator gains
were designed to avoid possible saturation situations due to a step change in the error of 1
pu. Figure 4-6 shows the Power stabilizer current waveform during a multiple step-
change in the reactive current reference.
Figure 4-3. Iqref command step change from -0.5 to 0.5 A per unit. Integral gain effect. A)
Inverter’s reference output voltage. B) Inverter current. C) Inverter’s Iq.
124
Figure 4-4. Iqref command step change from -0.5 to 0.5 A per unit. Proportional gain
effect
Figure 4-5. Iq current regulator output for different Kp
Figure 4-6. Iqref command step change from -0.5 to 0.5 and back to -0.5 A per unit. A)
Inverter’s reference output voltage. B) Inverter current. C) Inverter’s Iq.
125
The current control loop bandwidth was also tested and compared to the ideal
system. A variable frequency sinusoidal waveform was introduced into the control loop
references (Iqref and Idref) to study the reduction in amplitude as the frequency of the input
signal increased.
The signal references can be defined as
I d ref = I max ⋅ cos((h − 1) ⋅ wt )

I q ref = I max ⋅ sin((h − 1) ⋅ wt )
w = 2 ⋅ π ⋅ 60
Where h is the desired harmonic. For this test the amplitude selected for the signal
amplitude was 0.5 Amps per unit. Figure 4-7 shows the different current output
amplitudes for the different harmonics.
Figure 4-7. Power stabilizer harmonic injection response for Ki=18 and Kp=1
The bandwidth of the current regulators could then be compared to the ideal system
as shown in Figure 4-8. As expected the bandwidth of the real system was lower than the
ideal one due to the increase in the amount of system impedance. However, this reduction
126
in bandwidth did not have any impact in the system performance, since no harmonic
compensation was required.
Figure 4-8. Current regulator frequency response
Passive Filter Performance
LCL filter design was also tested and compared to the ideal attenuation gain. Figure
4-9 shows the current waveforms before and after the LCL filter.
Figure 4-9. Front-end inverter current waveform
The peak to peak ripple current was 0.06 A, and it was very similar to the expected
value: 0.0572 A (0.2214pu*0.22515A=0.0572A).

127
Figure 4-10 shows the frequency spectrum of Figure 4-9. It can be deduced that the
filter attenuation gain was -19 dB.
Figure 4-10. Frequency spectrum of the LCL currents
Voltage Regulation
The Power stabilizer did not just have the capacity of filtering power variations, but
voltage fluctuations as well. By controlling the amount of reactive current injected into
the system, it was possible to modify the voltage profile at the wind-farm terminals.
Figure 4-11 shows a simplified diagram of the different impedances that played a
significant role in the voltage regulation scheme.
1% from the Power 17.67% from thePower

Stabilizer point of view Stabilizer point of view
Vsource Vinveter
L=44mH Vpcc Lf = 720mH
Ipower stabilizer P=150W
V=480V 5.4% from the Wind
farm point of view
Main Vwind
Load P=750W
Figure 4-11. Simplified system description

128
If Vsource is considered to be stiff, the maximum increment in voltage at the point of
common coupling for a 150 W rated Power Stabilizer is
0.25515
ΔV = Vsource − V pcc = X line ⋅ I inverter rated rms ⋅ 2 = 0.044 ⋅ 60 ⋅ 2 ⋅ π ⋅ ⋅ 2 = 5.98 V
2
Figure 4-12 shows the voltage at the point of common coupling when the Power
Stabilizer went from full inductive to full capacitive and back to full inductive.
It can be deduced from the previous calculation, that for the given power rating, the
voltage regulation capabilities of the Power Stabilizer were modest (±0.77%).
Figure 4-12. Power stabilizer voltage regulation performance. A) Voltage at the point of
common coupling. B) Inverter Iq component.
System Losses
Due to the size of the equipment, system losses were expected to be a significant
proportion of the power ratings, compared to a full-size system. In particular, for the
Power Stabilizer, the main losses were:

129
• Conduction losses
• Switching losses
• I2R
• Core losses
• Capacitor leakage current
Because of these losses there was an expected asymmetric charge/discharge cycle
of the energy storage system. Figure 4-13 shows this effect.
To compensate for these losses the Power Stabilizer was biased such that no control
action from the energy storage regulator was needed. Figure 4-14 shows the
compensation term in the overall control algorithm.
Figure 4-13. Energy storage charge/discharge cycle. A) Chopper output power. B).
Energy storage voltage and current. C) ESS’s energy.
Losses
Power Limiter
_
+ Idref
ESS Voltage
Vd
regulator Current Limters and
PWM
Regulators Vq Transformations
Iqref
PCC Voltage
regulator
Figure 4-14. Control scheme with a losses compensation term

130
The effect of introducing a loss compensation term in the control algorithm had the
same effect as modeling the Power Stabilizer as a no-static inverter/chopper in parallel to
a resistive load (Figure 4-15). The losses were estimated to be around 20Watts for the
non-load condition.
Power Stabilizer
Losses=20Watts
Synchronous
Machine Line Impendace
Filter
Main
Load Wind
4.5 KW Farm
Figure 4-15. Power stabilizer equivalent system
Power Limiter Results
When trying to compensate for power fluctuation, two different approaches were
considered, tested, and compared in detail.
The wind-power data used for the comparison was 15 minutes of data from a wind
farm on the big island of Hawaii. The frequency scan of the data was 15 minutes, and it
corresponded to high wind conditions. The wind farm consisted of 37 Mitsubishi 250 kW
wind turbines, with a total capacity close to 10 MW (Figure 4-16).
Figure 4-16. Wind-power conditions under study

131
The time response of the induction machine’s power controller was low enough to
be able to reproduce the changes in power using step variations. However, this type of
behavior was unrealistic and therefore a linear interpolation was used between the two
consecutive scans.
Power Limiter 1 (High Pass Filter)
The transfer function of the high pass (HP) filter used in the design of the first
power limiter is shown in Equation 4-1.
s
H (s) = (4-1)
2 ⋅ π ⋅ f cut −off + s
The only parameter that needed to be determined according to the system
requirements was the cut-off frequency. Figure 4-17 shows the Power Stabilizer response
to wind-power fluctuation using a HP filter with a cut off frequency of 0.005Hz.
It can be concluded from Figure 4-17 that the Power Stabilizer had a very good
performance smoothing wind-power fluctuation as long there was enough energy storage
available. However, such a control scheme generated abrupt changes in power when the
power converter reached the energy limits. These types of situations should be avoided,
since the step changes in power could be even higher than the ones naturally produced by
the wind-farm output power.
Figure 4-18 is a zoom of the exact moment where the Power Stabilizer ran out of
energy. When the Power Stabilizer reached the minimum energy limit, the power
delivered to the utility did not only drop down to what the wind farm was producing, but
it overshot due to the energy absorbed by the Power Stabilizer (also called centering
power). That power was designed to be small in magnitude (proportional to the charge
discharge constant Kc), but still had a negative impact on the system.
132
Figure 4-17. Measured and modeled high pass filter results for Kc=0.0064 W/J,
fcut_off=0.005 Hz. A) Power to utility. B) Power stabilizer output power. C)
Power stabilizer energy level
133
Figure 4-18. Measured and modeled high pass filter results for Kc=0.0064 W/J,
fcut_off=0.005 Hz (zoom in). A) Power to utility. B) Power stabilizer output power. C)
134
In order to circumvent such types of situations we considered three different
approaches:
• Increased the cut-off frequency, so the Power Stabilizer only compensated for
higher frequency power fluctuations. Figure 4-19 shows the system response to
different cut-off frequencies. Figure 4-20 confirms the results by using the Matlab
model. It was clear that only high cut-off frequencies could help the system from
reaching the energy limits. The drawback of higher cut-off frequencies was
obvious; less power smoothing effect.
• Increased the size of the energy storage, so the system could face larger power
fluctuations for a given cut-off frequency. Figure 4-21 shows a comparison
between a system with nominal energy and a system with an extra 66% of energy.
Even with an increase of more than half in energy the power converter was unable
to compensate for large swings in wind power without running out of energy.
• Adaptive high pass filter. The idea behind this control strategy was to vary the cut-
off frequency according to the status of the energy storage. The closer the Power
Stabilizer energy storage system was to the nominal value, the more filter was
allowed (Figure 4-22).
Figure 4-19. Measured high pass filter performance for different cut-off frequencies.
System parameters Kc=0.0064 W/J. A) Power to utility. B). Power stabilizer
output power. C) Power stabilizer energy level
135
Figure 4-20. Modeled high pass filter performance for different cut-off frequencies.
System parameters Kc=0.0064 W/J. A) Power to utility. B). Power stabilizer
output power. C) Power stabilizer energy level
Figure 4-21. Measured high pass filter performance for different energy storage sizes.
System parameters, Kc=0.0064 W/J, fcut-off=0.005 Hz. A) Power to utility. B).
Power stabilizer output power. C) Power stabilizer energy level
136
f cut-off
f cut-off_origin
Energy
Energy nominal value
Figure 4-22. Cut-off frequency trajectory of the adaptive high pass filter for a given
energy deviation
Power Limiter 1 (Adaptive High Pass Filter)
The adaptive high pass filter control scheme was designed to avoid saturation
situations, yet allowing power fluctuation smoothing. In the adaptive filter control
algorithm the number of parameters that needed to be optimized were two; fcut_off_rigin and
the slope of the variable cut-off frequency. Equation 4-2 shows the relationship between
energy deviation and cut-off frequency used for the adaptive high pass filter.
f cut −off = f cut −off −origin + K f ⋅ ΔE (4-2)
Figure 4-23 shows the real system response for different Kf. The fcut_off_origin was
kept constant to 0.005 Hz.
It can be concluded from Figure 4-23 that when high pass filter parameters were
optimized the system could ride through large wind-power fluctuation without reaching
the energy limits.
Figure 4-24 shows the adaptive high pass filter response using an extra 66% of
energy. Measured results were compared to the one obtained using nominal energy
capacity. System parameters were: Kf=0.0059 Hz/J, Kc=0.0064 W/J, and a frequency of
fcut_off_origin=0.005 Hz.
137
Figure 4-23. Measured adaptive high pass filter performance for different Kf’s. System
parameters, Kc=0.0064 W/J, fcut-off-origin=0.005 Hz. A) Power to utility. B)
Figure 4-24. Measured adaptive high pass filter performance for different energy storage
sizes. System parameters, Kf=0.0059 Hz/J, Kc=0.0064 W/J, fcut_off_origin=0.005
Hz. A) Power to utility. B) Power stabilizer energy level
138
This approach seemed to work fairly well. However, it lacked applicability. Electric
power systems can be disturbed by large power swings, while small power unbalances
can be compensated without significant burden. Therefore large power fluctuations
should be tackled first, rather than the small ones due to its impact on the system.
Thus, there was a need for a better control algorithm that exclusively targeted and
compensated for large power variations, while avoiding compensation of less significant
events. The goal was to settle down the control actions given by the synchronous
machine regulator, so less stress was caused to the synchronous generator.
Power Limiter 2
This approach targeted specific indexes and therefore was more prompt to
compensate for large power fluctuation rather than low profile power changes.
The indexes considered in our study were the ones used by HECO (Hawaiian
Electric Company, Inc.), which were based on a two-second scan sampling time. The
indexes for a 10 MW wind farm were:
• Ramp Rate Power Fluctuation: RR = MWs −30 − MWs =2 MW/minute

where
RR= Ramp Rate, may be calculated once every scan
MWs-30= The instantaneous MW analog value 30 scans (60s) prior the present scan.
MWs = The instantaneous MW analog value for the present scan
• Instantaneous Power Fluctuation: I = MWs −1 − MWs =0.3 MW/2 sec
where
I= Instantaneous Power Change, calculated once every scan
MWs-1 = The instantaneous MW analog value for the previous scan (2 seconds ago)
MWs = The instantaneous MW analog value for the present scan
30
∑ MW s −1 − MWs
• Subminute Average Power Fluctuation: A1 = s =1
=1 MW/minute
30
where
Al= Subminute Average, calculated once every 30 scans
MWs-1 = The instantaneous MW analog value for the previous scan
MWs= The instantaneous MW analog value for the present scan
139
These numbers had to be scaled down according to the size of the wind farm
model. Thus, the actual power indexes considered in the model were:
• RR=(2/10)*750=150 Watts/minute
• A=(0.3/10)*750=22.5 Watts/minute
• I=(1/10)*750=75 Watts/2seconds
Note: 750 Watts is the wind-farm model rated power.
Even though indexes were based on 2-second scans, the power limiter control
scheme calculated such indexes several times per second, using a multiple-sampling
control algorithm. Figure 4-25 illustrates how these indexes, based on 2-second scans,
could be estimated more than once every two seconds. This allowed for higher refreshing
times for the inverter power reference, so that a faster and a more accurate response to
wind fluctuations were achieved.
Figure 4-26 demonstrates that the power limiter injected energy when it was really
needed. Moreover, the control system only released the necessary amount of energy to
meet the indexes, so not all the energy was consumed during the large power fluctuation.
It was also evident that since system losses were not corrected 100%, the power converter
drew some extra power from the system to compensate for the losses. In the simulation
results, only static losses (or losses independent from the inverter current) were
considered.
Wind Farm
Power
2 seconds
0.5 seconds
2 second scan
2 second
sampling rate
2 second scan
0.5 second
sampling rate
A1
A2
Figure 4-25. Multiple sampling concept. For this example a 0.5 second sampling time
was assumed
140
Figure 4-26. Measured and modeled power limiter 2 results for Kc=0.0064, RR=2
MW/minute, A=0.3 MW/minute, I=1MW/2 seconds fcut-off=0.005 Hz. A)
Power to Utility. B) Power stabilizer output power. C) Power stabilizer energy
level.
The activity of the power indexes during the 15 minute period are shown in Figure
4-27. As expected the power limiter does a very good job trying to keep the power
fluctuation indexes within the limits.
A significant number of variables could have made the power limiter behave
differently. However, only a few of them were considered for our sensibility study:
• Kc (charge and discharge constant). Nominal value Kc=0.0062 Watts/Joule
• Power limiter sampling frequency. Nominal value 10 Hz
• Power indexes. Nominal values RR=2 MW/minute, A=0.3 MW/minute, I=1 MW/2
seconds
141
Figure 4-27. Measured power indexes activity. System parameters: Kc=0.0064 W/J,
RR=2 MW/minute, A=0.3 MW/minute, I=1 MW/2 seconds, and fs=10Hz. A)
Power stabilizer output power. B) Average power fluctuation. C) Ramp rate
power change. D) Instantaneous power fluctuation.
Figure 4-28 shows the effect of increasing the charge/discharge constant. When
doing this, there was no impact on the indexes’ activity. However, large charge/discharge
constants could have caused the activation of the power indexes, since there was power
absorbed (charge) or delivered (discharge) from or to the electric power system.
Figure 4-29 shows the effect of decreasing the ramp rate limits, making them
stricter. For this type of wind-power fluctuation, the ramp rate activity was the most
important one, so that tighter limits could have made the Power Stabilizer reach the
energy limits. In general, a ramp rate limit of 1 MW/minute generated a good system
response in terms of power fluctuation magnitude and energy capacity required. Lower
ramp rate limits would have required larger energy capacity, making the Power Stabilizer
a non-cost effective solution.

142
Figure 4-28. Measured power limiter 2 response to different Kc . System parameters:

RR=2 MW/minute, A=0.3 MW/minute, I=1MW/2 seconds, and fs=10Hz. A)
Power stabilizer output power. B) Power stabilizer energy level.
Figure 4-29. Measured power limiter 2 response to different ramp rate limits. System
parameters: Kc=0.0064 W/J, A=0.3 MW/minute, I=1 MW/2 seconds, and
fs=10 Hz. A) Power to Utility. B) Power stabilizer output power. C) Power
stabilizer energy level.
143
Figure 4-30 shows the effect of decreasing the average power fluctuation limit. In
this case the tighter the average power limit was, the worse the response obtained
became. The reason for such unusual conduct was found in the way the induction power
reference was obtained. Wind-power reference was linearly interpolated between two
consecutive data samples. Thus, a control scheme using a multisampling strategy (more
than one sample per real data samples) perceived an average power fluctuation from the
original one. Figure 4-31 shows the average power fluctuation for different sampling
rates. This effect made it almost impossible to judge the pros and cons of different
average power fluctuation limits.
Figure 4-30. Measured power limiter 2 response to different average power fluctuation
limits. System parameters: Kc=0.0064 W/J, RR=2 MW/minute, I=1 MW/2
seconds, and fs=10 Hz. A) Power to Utility. B) Power stabilizer output power.
C) Power stabilizer energy level.
144
fluctuation (MW/minute)
Average power
A
Time (secs)
Zoom in
fluctuation (MW/minute)
Average power
B
Time (secs)
Figure 4-31. Effect of linear interpolation on the average power fluctuation index activity.
The sampling time of the original wind-power data is 2 seconds. A) Average
index. B) Average index zoom in.
Figure 4-32 shows the effect of reducing the instantaneous power fluctuation limit.
In general, the system responded fairly well to such limits. However, a special precaution
had to be taken when reducing such an index, since it could have caused the power
converter to continuously compensate, even for small power variations.
Figure 4-32. Measured power limiter 2 response to different instantaneous power

fluctuation limits. System parameters: Kc=0.0064 W/J, RR=2 MW/minute,
A=0.3 MW/minute, and fs=10 Hz. A) Power to Utility. B) Power stabilizer
output power. C) Power stabilizer energy level.
145
Figure 4-33 shows the effects of decreasing the sampling frequency (or refreshing
frequency) of the power limiter. In general, lower sampling frequencies did not have a
major impact on the Power Stabilizer energy. The advantage of using high sampling
frequencies was the fact that power indexes were tracked with exactitude, allowing for a
more accurate way of assuring the power fluctuations fell within the specified limits.
Figure 4-33. Measured power limiter 2 response to different sampling frequencies.

System parameters: Kc=0.0128 W/J, RR=2 MW/minute, A=0.3 MW/minute,
and I=1 MW/2 seconds. A) Power to Utility. B) Power stabilizer output
power. C) Power stabilizer energy level.
Power Limiters Comparison Study
In determining which of the power limiters had a more desirable impact on the
electric power system, one should pay attention to the system’s frequency.
In our case, since the frequency regulator of the synchronous machine was tuned to
instantaneously compensate for frequency deviations, no frequency variations were
expected. Therefore, the only good indicator available to determine the impact of the
different power limiters was the control action given by the frequency regulator.
146
Wind- farm power fluctuations tended to change the frequency regulator output due
to an unbalance in power. Thus, control actions had the tendency to displace up and down
from an average value based on the mismatch between mechanical and electrical power
(Figure 4-34).
Figure 4-34. Measured synchronous machine output power for the different power limiter
control schemes
It can be concluded from Figure 4-35 that both, the high pass filter and the adaptive
filter had good response filtering “small” power fluctuation. However, when the Power
Stabilizer capacity to absorb or supply energy was needed the most, no capacity was
available. Only the power limiter 2 and the adaptive HP filter, with 66% of extra energy,
were capable of injecting some energy to shave-off the surge in power.
Figure 4-36 shows the frequency regulator response for the different power
limiters. This graph was a consequence of Figure 4-35 one, and gives a better picture of
the benefits of each one of the different power limiters.

147
Figure 4-35. Measured synchronous machine output power for the different power limiter
control schemes. Zoom in of the largest power swing
A B
C D
Figure 4-36. Frequency regulator output for the different power limiters. A) HP filter. B)
Adaptive HP filter. C) Adaptive HP filter with 66% extra energy. D) Power
Limier 2
In conclusion, we cannot say that there is a better or worse power control scheme,
since each one of the different power limiters can serve different purposes.
CHAPTER 5
SUMMARY
Conclusions
The purpose of our study was to develop an electronic power converter capable of
compensating power fluctuations typical of wind farms. The proof-of-concept converter
was designed using similar techniques utilized in the design of medium voltage power
quality products.
The system design involved the mathematical description of the different equations
implicated in the design of the diverse regulators. Special attention was paid to the
current controllers, for being the foundation upon which the rest of the system relies on,
and to the development of new control algorithms capable of minimizing power
fluctuation while optimizing the usage of the energy storage system.
Two different power limiter control schemes have been proposed and described in
detail. A test-bench was developed to mimic a future scenario of an isolated power
system. Tests have been conducted under realistic modeled system conditions, in terms of
wind penetration factor, and cost-effective amount of energy storage. The main
conclusions of the tests carried out were:
• The shunt connected voltage source converter has shown to be an excellent

approach in terms of speed and flexibility, and power fluctuation smoothing.
• Two main alternatives for compensating wind-power fluctuations using small

amounts of energy; power limiters that target low profile power fluctuations and
power limiters that compensate according to predefined power fluctuation indexes
were studied. These alternatives are usually designed to compensate for large
power swings.
148
149
• High pass filters are not appropriate for power filter functions, due to their lack of
continuousness when running out energy.
• Adaptive high pass filters have shown to be a much better alternative to high pass
filters. However, behaviors similar to the simple high pass filter might occur if
incorrect adaptive laws are considered.
• Power limiters that target specific power fluctuation indexes have a lower duty-
cycle than the high pass filter approach and only compensate for larger power
fluctuations.
• Ramp-rate indexes are a good alternative to adaptive high pass filters.
• Instantaneous power fluctuation indexes do no have as much significance as the

ramp-rate indexes
• Average power fluctuation indexes are highly non-linear, and might create
unwanted misbehaviors that are difficult to predict.
• Both types of power limiters have shown to be beneficial for the reduction in the
control actions of the synchronous machine’s governor. Thus, reducing the stress of
the generator during power fluctuations.
In summary, among the different power limiter regulators considered in this
dissertation, the adaptive high pass filter has been shown as the most robust and reliable
when designed correctly. It forces the power converter and the energy storage system to
work continuously, getting the maximum effectiveness out the system. It even helps the
system ride through large power variations in a moderate way. A drawback for this
approach is the wear of the energy-storage system, due to high duty cycles.
The power limiter based on power fluctuation indexes serves as a very specific
solution to a specific problem or need. Its low duty-cycle profile in terms of real power
allows for better voltage regulation or voltage flicker reduction (using reactive power), in
cases where system impedance is relatively large.

150
Further Work
There is still a lot of work to be done in the area of smoothing real power
fluctuations using various types of energy storage systems. The following is a summary
of the different subjects that merit additional research:
• New control algorithms. For instance, new non-linear adaptive laws or a

combination of different power limiters based on energy levels
• Evaluation of the benefits of real power smoothing.
• Evaluation of new energy storage systems
Our research work has focused entirely on power fluctuations generated by wind
farms. However, the same concept can be applied to other producers of real-power
fluctuations, such as the continuous switching of large loads, or new non-dispatchable
distributed resources (wave, solar, etc)

APPENDIX A
MATHEMATICAL TRANSFORMATIONS
In studying of power systems, mathematical transformations are often used to
decouple variables or to help solve of difficult differential equations. The most common
and known transformation is the method of symmetrical components developed by
Fortescue in 1918 [27]. This method uses a complex transformation to represent an
unbalanced system of n phasors into n systems of balanced phasors called symmetrical
components of the original phasors. For a three-phase system, these symmetrical
components are the positive sequence component, the negative sequence component, and
a zero sequence component. This relationship can be expressed as
⎡ ⎤
⎢ ⎥
r ⎢1 1 1 ⎥
⎡X0⎤ ⎡1 1 1 ⎤ ⎡Xa ⎤ ⎢ 2⎥ ⎡X ⎤
⎢r ⎥ 1 ⎢ 1
2 ⋅π
⎛ j ⋅ 23⋅π ⎞ ⎥ ⎢ a ⎥ (A-1)
a 2 ⎥⎥ ⋅ ⎢⎢ X b ⎥⎥ = ⋅ ⎢1
j⋅
= ⋅
⎢ r 1 ⎥ 3 ⎢1 a
X e 3 ⎜e ⎟ ⋅ Xb
3 ⎢ ⎜ ⎟ ⎥ ⎢ ⎥
⎢X2⎥ ⎢⎣1 a 2 a ⎥⎦ ⎢⎣ X c ⎥⎦ ⎢ ⎝ ⎠ ⎥ ⎢X ⎥
⎣ ⎦ 2 ⎣ c⎦
⎢ ⎛ j ⋅ 23⋅π ⎞ j⋅
2 ⋅π
⎥
⎢1 ⎜e ⎟ e 3
⎥
⎜ ⎟
⎣⎢ ⎝ ⎠ ⎦⎥
Variable X of Equation A-1 may be currents, voltages, or fluxes. Written explicitly in
terms of real and imaginary components, we have
r ⎛ 1 3⎞ ⎛ 1 3⎞
X 1 = X a + ⎜⎜ − + j ⋅ ⎟ ⋅ Xb + ⎜− − j ⋅
⎟ ⎜
⎟⋅ Xc
⎝ 2 2 ⎠ ⎝ 2 2 ⎟⎠
r 1 3
X 1 = X a − ⋅ (X b + X c ) + j ⋅ (X b − X c ) (A-2)
2 2
r ⎛ 1 3⎞ ⎛ 1 3⎞
X 2 = X a + ⎜⎜ − − j ⋅ ⎟⋅ Xb + ⎜− + j ⋅
⎟ ⎜
⎟⋅ Xc
⎝ 2 2 ⎠ ⎝ 2 2 ⎟⎠
r 1 3
X 2 = X a − ⋅ (X b + X c ) − j ⋅ (X b − X c )
2 2
151
152
r r
It is evident from Equation A-2 that space vectors X 1 and X 2 are complex
conjugates of each other. For a balanced three-phase system, we have
X a = X m ⋅ cos(wt )
⎛ 2π ⎞ (A-3)
X b = X m ⋅ cos⎜ wt − ⎟
⎝ 3 ⎠
⎛ 4π ⎞
X c = X m ⋅ cos⎜ wt − ⎟
⎝ 3 ⎠
r r
Thus, the space vectors X 1 and X 2 can be expressed as
r 1 3
X1 = X a − ⋅ ( X b + X c ) + j ⋅ (X b − X c )
2 2
3 1 3
= ⋅ X a − (X a + X b + X c ) + j ⋅ ⋅ (X b − X c )
2 2 2
3 3 ⎛ ⎛ 2π ⎞ ⎛ 4π ⎞ ⎞
= ⋅ X m ⋅ cos(wt ) + j ⋅ ⋅ X m ⋅ ⎜⎜ cos⎜ wt − ⎟ − cos⎜ wt − ⎟⎟
2 2 ⎝ ⎝ 3 ⎠ ⎝ 3 ⎠ ⎟⎠
(A-4)
3 3 ⎛ ⎛ − 2π ⎞⎞
= ⋅ X m ⋅ cos(wt ) + j ⋅ ⋅ X m ⋅ ⎜⎜ − 2 ⋅ sin (wt ) ⋅ sin ⎜ ⎟ ⎟⎟
2 2 ⎝ ⎝ 3 ⎠⎠
3 3
= ⋅ X m ⋅ (cos(wt ) + j ⋅ sin (wt )) = ⋅ X m ⋅ e jwt
2 2
( )
r r * 3
(
X 2 = X 1 = ⋅ X m ⋅ e − jwt
2
)*
r
Defining X = X m ⋅ e jwt = X ds + j ⋅ X qs , the symmetrical transformation matrix
equation can be written as
r r ⎡X a ⎤
⎡ X 1 ⎤ 3 ⎡ X ⎤ ⎡1 a a2 ⎤ ⎢ ⎥ (A-5)
⎢ r ⎥ = ⎢ r *⎥ = ⎢ ⎥ ⋅ Xb
( )
⎣ X 2 ⎦ 2 ⎣ X ⎦ ⎣1 a
2
a⎦ ⎢ ⎥
⎢⎣ X c ⎥⎦
Since (a 2 ) = a , row two can be eliminated without any loss of information (Equation A-
*
6).
⎡X a ⎤
[ ]
r 2
X = 1 a a ⋅ ⎢⎢ X b ⎥⎥
2 (A-6)
3
⎢⎣ X c ⎥⎦
153
Writing the real and imaginary components in two separate rows, and adding the
zero-sequence component, we obtain the general real transformation (Equation A-7).
⎡ 1 1 ⎤
⎢1 − −
⎡ 2 ⎤
( ) 2 ⎥ ⎡X ⎤
⎢ 1 ℜ(a ) ℜ a ⎥ ⎡ X a ⎤
⎡ X ds ⎤ ⎡ X ds ⎤ 2
⎢ ⎥ a
( )
⎢ X ⎥ = 2 ⎢ 0 ℑ(a ) ℑ a 2 ⎥ ⋅ ⎢ X ⎥ ⎢X ⎥ = 2 ⎢0 3
−
3⎥ ⎢ ⎥
⋅ Xb (A-7)
⎢ qs ⎥ 3 ⎢
1 ⎥ ⎢X ⎥
⎢ b⎥ ⎢ ⎥ 3⎢ 2 ⎥ ⎢ ⎥
qs
1 1 2
⎢⎣ X o ⎥⎦ ⎢ ⎥ ⎣ c⎦ ⎣⎢ X o ⎦⎥ ⎢1 1 1 ⎥ ⎣⎢ X c ⎦⎥
⎣2 2 2 ⎦ ⎢2
⎣ 2 2 ⎥⎦
Equation A-7 is known as Clark’s transformation, and it transforms a three-phase
system to an equivalent two-phase system. Figure A-1 shows the relationships of the
different axes. Figure A-2 shows the same relationship, but in the time domain.
c axis
a axis
ds axis
w=0 w=0
ω=2 π f X
b axis
qs axis
Figure A-1. Relationships among ds-qs, and abc axes
Figure A-2 Stationary ds-qs components in the time domain

r
As shown by Figure A-1, ds-qs axes are stationary, while the space vector X
rotates at w=2πf. To achieve high bandwidth in the control algorithm, it is necessary to

154
transform the stationary variables X ds and X qs into X dr and X qr (rotating frame
reference).
r
We can deduce that an observer moving at the same speed as X will see this space
vector as a constant, unlike the time variant X ds and X qs components of the stationary
ds-qs axes. Figure A- 3 shows the geometrical relationship of the rotating dr-qr axes with
respect to the stationary ds-qs axes.
ds axis
θ
w=0
w=2 π f dr axis
X
w=2 π f
qr axis qs axis
Figure A- 3. Relationship among ds-qs and dr-qr axes
This geometrical relationship can be expressed as
⎡ X dr ⎤ ⎡ cos(θ ) sin (θ ) ⎤ ⎡ X ds ⎤ (A-8)

⎢X ⎥ = ⎢ ⎥⋅⎢ ⎥
⎣ qr ⎦ ⎣− sin(θ ) cos(θ )⎦ ⎣ X qs ⎦
r
The angle Θ is the angle between the d axis of rotating and X stationary d-q axes; it is a
function of the angular speed of the rotating dr-qr axes, that is
dθ
wt = (A-9)
dt
Figure A-4 shows the decomposition of X ds and X qs into X dr and X qr .
r
The angle δ is the angle between the dr axis and space vector X ; it is a constant
vale, and it will depend on the kinds of simplification or formulation best suited to a
155
specific application. The full transformation from stationary reference frame to rotating
reference frame, including the zero sequence, is shown in Equation A-9.
Xds sin (θ)
Xds
θ ds axis
Xds cos (θ)
δ
Xqs sin (θ)
Xqs cos (θ)
dr axis
w=2 π f
Xqs
w=2 π f
X
qr axis
qs axis
Figure A-4. Direct and quadrature components
⎡ X dr ⎤ ⎡ cos(θ ) sin (θ ) 0⎤ ⎡ X ds ⎤
⎢ X ⎥ = ⎢ − sin (θ ) cos(θ ) 0⎥ ⋅ ⎢ X ⎥ (A-9)
⎢ qr ⎥ ⎢ ⎥ ⎢ qs ⎥
⎢⎣ X o ⎥⎦ ⎢⎣ 0 0 1⎥⎦ ⎢⎣ X o ⎥⎦
Figure A-5 shows the time domain representation of the three different reference frames,
that is abc, ds-qs, and dr-qr, for δ = 0°.

156
Figure A-5. Time domain representation of abc and d-q components
In terms of the original X a , X b , and X c components,
⎡ X dr ⎤ ⎡ cos(θ ) sin (θ ) 0⎤ ⎡ X ds ⎤
⎢ X ⎥ = ⎢− sin (θ ) cos(θ ) 0⎥ ⋅ ⎢ X ⎥
⎢ qr ⎥ ⎢ ⎥ ⎢ qs ⎥
⎢⎣ X o ⎥⎦ ⎢⎣ 0 0 1⎥⎦ ⎢⎣ X o ⎥⎦
⎡ 1 1 ⎤ (A-10)
⎢1 − 2 −
2 ⎥ ⎡X ⎤
⎡ cos(θ ) sin (θ ) 0⎤ ⎢ ⎥ a
2 3 3⎥ ⎢ ⎥
= ⎢⎢− sin (θ ) cos(θ ) 0⎥⎥ ⋅ ⎢ 0 − ⋅ ⎢Xb ⎥
3 ⎢ 2 2 ⎥
⎢⎣ 0 0 1⎥⎦ ⎢ 1 1 1 ⎥ ⎢⎣ X c ⎥⎦
⎢2 2
⎣ 2 ⎥⎦
⎡ X dr ⎤ ⎡ cos(θ ) cos(θ − 120°) cos(θ − 240°) ⎤ ⎡ X a ⎤

⎢ X ⎥ = 2 ⎢− sin (θ ) − sin (θ − 120°) − sin (θ − 240°)⎥ ⋅ ⎢ X ⎥ (A-11)
⎢ qr ⎥ 3 ⎢ ⎥ ⎢ b⎥
⎢⎣ X o ⎥⎦ ⎢ 1 1 1 ⎥ ⎢X ⎥
⎣ 2 2 2 ⎦ ⎣ c⎦
In short notation
[X ] = [T ]⋅ [X ]
dqo dqo abc
(A-12)
This transformation is called Park’s transformation, and it is well-known in
synchronous machine analysis. The inverse transformation can be shown
⎡ X a ⎤ ⎡ cos(θ ) − sin (θ ) 1⎤ ⎡ X dr ⎤
⎢ X ⎥ = ⎢ cos(θ − 120°) − sin (θ − 120°) 1⎥ ⋅ ⎢ X ⎥ (A-12)
⎢ b⎥ ⎢ ⎥ ⎢ qr ⎥
⎢⎣ X c ⎥⎦ ⎢⎣cos(θ − 240°) − sin (θ − 240°) 1⎥⎦ ⎢⎣ X o ⎥⎦
157
[ ] [ ]
t
As it can be inferred from previous expression, Tdqo ≠ Tdqo
−1
, since the matrix
[T ] is not unitary. Table A-1 summarizes all the transformations that used in our study.
dqo
Table A-1. Mathematical transformations summary

Independent variables Matrix Transformations
Xa , Xb , Xc ⎡ 1 1 ⎤
⎢1 − 2 − 2 ⎥
⎡ X ds ⎤ ⎢ ⎥ ⎡X a ⎤
⎢X ⎥ = 2 ⎢0 3
−
3⎥ ⎢ ⎥
⋅ Xb
⎢ qs ⎥ 3 ⎢ 2 2 ⎥ ⎢ ⎥
⎢⎣ X o ⎥⎦ ⎢1 1 1 ⎥ ⎢⎣ X c ⎥⎦
⎢2 2 2 ⎥⎦
⎣
X ds , X qs , X o ⎡ X dr ⎤ ⎡ cos(θ ) sin (θ ) 0⎤ ⎡ X ds ⎤
⎢ X ⎥ = ⎢− sin (θ ) cos(θ ) 0⎥ ⋅ ⎢ X ⎥
⎢ qr ⎥ ⎢ ⎥ ⎢ qs ⎥
⎢⎣ X o ⎥⎦ ⎢⎣ 0 0 1⎥⎦ ⎢⎣ X o ⎥⎦
X ds , X qs X = X ds2 + X qs2
⎛ X qs ⎞
θ = arctan⎜⎜ ⎟⎟
X
⎝ ds ⎠
X dr , X qr , X o ⎡ X dr ⎤ ⎡ cos(θ ) cos(θ − 120°) cos(θ − 240°) ⎤ ⎡ X a ⎤
⎢X ⎥ = 2⎢ ⎥ ⎢ ⎥
⎢ qr ⎥ ⎢− sin(θ ) − sin(θ − 120°) − sin(θ − 240°)⎥ ⋅ ⎢ X b ⎥
3⎢ 1 1 1 ⎥ ⎢X ⎥
⎢⎣ X o ⎥⎦
⎣ 2 2 2 ⎦ ⎣ c⎦
APPENDIX B
MATLAB CODES
Power Limiter 1
The Matlab code for the control algorithm of the high pass filters is listed below
along with comments, signified by the % sign
%%%%%%%%%% Inverter size %%%%%%%%%%%%%%

load data.txt % load wind power files
Pwind=data; % input data in MW
Ts=1; % Sampling time
Erangen =10; % Energy storage positive limit-- 1e9 =Unlimited
Erangep =10; % Energy storage negative limit-- 1e9 =Unlimited
INVL=2; %Inverter power limit -- 1e9= Unlimited
wc=2*pi*0.05; % cut-off frequency
%%%%%%%%% Initialization%%%%%%%%%%%%%%%%%
nt=length(Pwind);
Kc=(0.006427/tolerance); % ESS charge/discharge constant
P0=Pwind(1,1);
IOUTF=0;
IINVRF=0;
Pcomp=0;
Pcomp_buffer=zeros(1,nt);
Pwind_old=P0;
Plosses=0.0;
%%%%%%%%%% Physical system description %%%%%%
Putility=zeros(1,nt);
Energy=zeros(1,nt);
Inverter=zeros(1,nt);
Vstorage=zeros(1,nt);
Pinverter=zeros(1,nt);
RRcounter=zeros(1,nt);
Icounter=zeros(1,nt);
OUT_OF_ENERGY=zeros(1,nt);
FULL_POWER=zeros(1,nt);
%%%%%%%% System model %%%%%%%%%%%%%%%%%%
for i=1:nt
%%%%%%%%%%%%% Electrical system%%%%%%%%%%
if i==1
Energy(i)=0;
158
159
else
Energy(i)=Energy(i-1)-(Inverter(i-1)+Plosses)*Ts;
end
%%%%%%%%%%% HP filter %%%%%%%%%%%%%%%%%
Pcomp=(1/(1+Ts*wc))*(Pwind(i)-Pwind_old+Pcomp);
Pcomp_buffer(i)=Pcomp;
Pwind_old=Pwind(i);
IINVRF=-Pcomp;
IOUTF=IINVRF;
%%%%%%% Max Power Saturation%%%%%%%%%%%%%%%
if IINVRF > INVL
IOUTF=INVL;
FULL_POWER(i)=1;
elseif IINVRF < -INVL
IOUTF=-INVL;
FULL_POWER(i)=1;
else
IOUTF=IINVRF;
end
%%%%%%%% Stop inverter due to E>Elimit%%%%%%%%%%%
if Energy(i)-IOUTF*Ts<-Erangen
IOUTF=(Energy(i)-(sign(-IOUTF)*Erangen))/Ts;
OUT_OF_ENERGY(i+1)=1*sign(-IOUTF);
Pcomp=0;
end
if Energy(i)-IOUTF*Ts>Erangep
IOUTF=(Energy(i)-(sign(-IOUTF)*Erangep))/Ts;
Pcomp=0;
end
if IOUTF > INVL
IOUTF=INVL;
FULL_POWER(i)=1;
elseif IOUTF < -INVL
IOUTF=-INVL;
FULL_POWER(i)=1;
end
%%%%%%%% Update Electrical system %%%%%%%
Inverter(i)= IOUTF+Kc*(Energy(i)-0);
Pinverter(i)=IOUTF;
Putility(i)=Pwind(i)+Inverter(i);
Vstorage(i)=Kc*(Energy(i)-0);
end
160
Power Limiter 2
The Matlab code for the control algorithm of the power limiter 2 is listed below
%%%%%%%%%%%%%% Limits Inverter size %%%%%%%%%%

Ts=2 % Sampling time
R=2.0 % Ramp Rate limit 2MW/min (2 sec scan)
A=0.3 %Average limit; 0.3MW/min (2 sec scan)
II=1.0 %Instantaneous limit 1MW/2 sec;
Erange = 1e9 % Energy storage range (MJ)-- 1e9 =Unlimited
INVL=1e9 %Inverter power limit (MW) -- 1e9= Unlimited
%%%%%%%%%%%%%% Data Input%%%%%%%%%%%%%%
%load data.txt; ( units MW)
Pwind=data;
%%%%%%%%%%%%%%% Initialization%%%%%%%%%%%%
nt=length(Pwind);
N=60/Ts; %samples per minute
Kc=1/300; % ESS charge/discharge constant
P0=Pwind(1,1);
%%%%%%%%%%%%%%%%%% Indexes %%%%%%%%%%%
J=N+1;
M=0;
%%%%%%%%%%%%%% Physical system description %%%%%%
Energy=zeros(1,nt);
RRcounter=zeros(1,nt);
Acounter=zeros(1,nt);
Icounter=zeros(1,nt);
%%%%%%%%%%%%%%%% Buffers %%%%%%%%%%%%%%
IOPF=P0*ones(1,N);% 2 sec scan buffer initialization
IAF=zeros(1,N); % Average buffer initialization
Average=0;
IOUTF=0;
ISWF=0;
IOWSF=0;
IOWF=0;
ICPAF=0;
IESARF=0;
INDPF=0;
IAWSF=0;
IAWF=0;
161
IINVRF=0;
INWS=0;
INW=0;
%%%%%%%%%%%%%%% System model %%%%%%%%%%%%
for i=1:nt
%%%%%%%%%%%%% Electrical system %%%%%%%%%%%
if i==1
Energy(i)=0;
else
Energy(i)=Energy(i-1)-Inverter(i-1)*Ts;
end
INWS=Kc*(Energy(i)-0)+Pwind(i);
INW=Pwind(i);
%%%%%%%%%%%%% Control loop %%%%%%%%%%%%%%
J=J-1; %%% 1 minute ago index
if J<1
J=N;
end
M=J+1; %%%% 2 seconds ago index
if M>N
M=1;
end
%%%%%%%%%%%%% Top Limiter %%%%%%%%%%%%%%%
IOWSF=INWS;
%%% Ramp Rate
if IOWSF-IOPF(J) > R
IOWSF= IOPF(J)+R;
RRcounter(i)=1;
elseif IOWSF-IOPF(J) < -R
IOWSF=IOPF(J)-R;
RRcounter(i)=1;
end
%%% Average
IAWSF=Average+(abs(IOPF(M)-IOWSF)-IAF(J))/N;
if IAWSF > A
if IOPF(M)> IOWSF
IOWSF=IOPF(M)-abs((A-Average)*N+IAF(J));
Acounter(i)=1;
end
if IOPF(M) < IOWSF
IOWSF=IOPF(M)+abs((A-Average)*N+IAF(J));
Acounter(i)=1;
end
end
%%% Instantaneous
if IOWSF-IOPF(M)> II
162
IOWSF=IOPF(M)+II;
Icounter(i)=1;
elseif IOWSF-IOPF(M)< - II
IOWSF=IOPF(M)-II;
Icounter(i)=1;
end
%%%%%%%%%%%%% Bottom Limiter %%%%%%%%%%%%
IOWF=INW;
%%% Ramp Rate
if IOWF-IOPF(J) > R
IOWF= IOPF(J)+R;
RRcounter(i)=1;
elseif IOWF-IOPF(J) < -R
IOWF=IOPF(J)-R;
RRcounter(i)=1;
end
%%% Average
IAWF=Average+(abs(IOPF(M)-IOWF)-IAF(J))/N;
if IAWF > A
if IOPF(M)> IOWF
IOWF=IOPF(M)-abs((A-Average)*N+IAF(J));
Acounter(i)=1;
end
if IOPF(M) < IOWF
IOWF=IOPF(M)+abs((A-Average)*N+IAF(J));
Acounter(i)=1;
end
end
%%% Instantaneous
if IOWF-IOPF(M)> II
IOWF=IOPF(M)+II;
Icounter(i)=1;
elseif IOWF-IOPF(M)< - II
IOWF=IOPF(M)-II;
Icounter(i)=1;
end
%%%%%%%%%%%%%% Inverter Power %%%%%%%%%%%%%
ICPAF=IOWSF-IOWF;
IESARF=-IOWF+INW;
IINVRF=ICPAF-IESARF;
%%%%%%%%%%%%%%% Max Power Saturation%%%%%%%%%
if IINVRF > INVL
IOUTF=INVL;
FULL_POWER(i)=1;
elseif IINVRF < -INVL
IOUTF=-INVL;
163
FULL_POWER(i)=1;
else
IOUTF=IINVRF;
end
%%%%%%%%%%%% Stop inverter due to E>Elimit%%%%%%%%
if abs(Energy(i)-IOUTF*Ts)>Erange/2
IOUTF=(Energy(i)-(sign(-IOUTF)*Erange/2))/Ts;
if IOUTF > INVL
IOUTF=INVL;
FULL_POWER(i)=1;
elseif IOUTF < -INVL
IOUTF=-INVL;
FULL_POWER(i)=1;
end
end
%%%%%%%%%% Update buffer data %%%%%%%%%%%%%%
INDPF=IINVRF-IOUTF;
Average=Average+(abs(IOPF(M)-(IOWSF-INDPF))-IAF(J))/N;
IAF(J)=abs(IOPF(M)-(IOWSF-INDPF));
IOPF(J)=IOWSF-INDPF;
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%% Electrical system %%%%%%%%%%%
Inverter(i)= IOUTF;
end
Power Limiter 3
The Matlab code for the control algorithm of the power limiter 3 is listed below
%%%%%%%%%%%% Limits Inverter size %%%%%%%%

Ts=2 % Sampling time
R=2.0 % Ramp Rate limit 2MW/min (2 sec scan)
A=0.3 %Average limit; 0.3MW/min (2 sec scan)
II=1.0 %Instantaneous limit 1MW/2 sec;
Erange = 1e9 % Energy storage range (MJ)-- 1e9 =Unlimited
INVL=1e9 %Inverter power limit -- 1e9= Unlimited
%%%%%%%%%%%%%% Data Input%%%%%%%%%
load data.txt; % Data scaled to 10 MW( units MW)
Pwind=data;
%%%%%%%%%%%%%%% Initialization%%%%%%%%%%
nt=length(Pwind);
N=60/Ts; %samples per minute
Kc=1/300; % ESS charge/discharge constant
164
P0=Pwind(1,1);
J=N+1;
M=0;
%%%%%%%%%%% Physical system description %%%%%%
Energy=zeros(1,nt);
Centering=zeros(1,nt);
Pold=P0*ones(1,N);
Avg=zeros(1,N);
Abuffer=zeros(1,N);
Average=0;
ESArp=zeros(1,nt);
ESArn=zeros(1,nt);
ESAr=zeros(1,nt);
UR=zeros(1,nt);
LR=zeros(1,nt);
UA=zeros(1,nt);
LA=zeros(1,nt);
UI=zeros(1,nt);
LI=zeros(1,nt);
UT=zeros(1,nt);
LT=zeros(1,nt);
UW=zeros(1,nt);
LW=zeros(1,nt);
UC=zeros(1,nt);
LC=zeros(1,nt);
I_counter=zeros(1,nt);
RR_counter=zeros(1,nt);
A_counter=zeros(1,nt);
for i=1:nt
%%%%%%%%%%%%% Electrical system %%%%%
if i==1
Energy(i)=0;
else
Energy(i)=Energy(i-1)-Inverter(i-1)*Ts;
end
%%%%%%%%%%%%% Control loop %%%%%%%%%%
J=J-1; %%% 1 minute ago index
if J<1
J=N;
end
M=J+1; %%%% 2 seconds ago index
if M>N
165
M=1;
end
%%%%% Ramp Rate1%%%%%%
UR(i)=Pold(J)+R;
LR(i)=Pold(J)-R;
%%%%% Subminute1%%%%%%
UA(i)=Pold(M)+(abs(A-Average)*N+Avg(J));
LA(i)=Pold(M)-(abs(A-Average)*N+Avg(J));
%%%%% Instantaneous 1%%%%%%
UI(i)=Pold(M)+II;
LI(i)=Pold(M)-II;
%%%%%%%%% Internal variables
UT(i)=min([UR(i) UA(i) UI(i)]);
LT(i)=max([LR(i) LA(i) LI(i)]);
UW(i)=Pwind(i)-UT(i);
LW(i)=Pwind(i)-LT(i);
if -UW(i)>0
UC(i)=-UW(i);
else
UC(i)=0.0;
end
if -LW(i)<0
LC(i)=-LW(i);
else
LC(i)=0.0;
end
if UW(i)>0
ESArp(i)=UW(i);
if UT(i)==UR(i)
RR_counter(i)=-1;
I_counter(i)=0;
A_counter(i)=0;
elseif UT(i)==UI(i)
I_counter(i)=-1;
A_counter(i)=0;
RR_counter(i)=0;
else
A_counter(i)=-1;
I_counter(i)=0;
RR_counter(i)=0;
end
else
ESArp(i)=0.0;
end
if LW(i)<0
ESArn(i)=LW(i);
166
if LT(i)==LR(i)
RR_counter(i)=1;
I_counter(i)=0;
A_counter(i)=0;
elseif LT(i)==LI(i)
I_counter(i)=1;
A_counter(i)=0;
RR_counter(i)=0;
else
A_counter(i)=1;
I_counter(i)=0;
RR_counter(i)=0;
end
else
ESArn(i)=0.0;
end
ESAr(i)=ESArp(i)+ESArn(i);
Centering(i)=Kc*Energy(i);
if Centering(i)>UC(i)
Centering(i)=UC(i);
end
if Centering(i)<LC(i)
Centering(i)=LC(i);
end
Inverter(i)=Centering(i)-ESAr(i);
%%%%%%%%%%%%%%% Max Power Saturation%%%
if Inverter(i) > INVL
Inverter(i)=INVL;
FULL_POWER(i)=1;
elseif Inverter(i) < -INVL
Inverter(i)=-INVL;
FULL_POWER(i)=1;
end
%%%%%%%%%%%% Stop inverter due to E>Elimit%%%%
if abs(Energy(i)-Inverter(i)*Ts)>Erange/2
Inverter(i)=(Energy(i)-(sign(-Inverter(i))*Erange/2))/Ts;
OUT_OF_ENERGY(i+1)=1*sign(-Inverter(i));
if Inverter(i) > INVL
Inverter(i)=INVL;
FULL_POWER(i)=1;
elseif Inverter(i) < -INVL
Inverter(i)=-INVL;
FULL_POWER(i)=1;
end
end
167
%%%%% Update buffer%%%

Average=Average+(abs(Pold(M)-Putility(i))-Avg(J))/N;
Abuffer(i)=Average;
Avg(J)=abs(Pold(M)-Putility(i));
Pold(J)=Putility(i);
end
APPENDIX C
POWER STABILIZER CONTROL MODULES
The following table is a summary of the main functions used in the programming
of the power stabilizer.
Table C-1. Control Modules

File Name C code
PLL.h typedef struct { _iq ds; /* Input: Vds */

_iq qs; /* Input: Vqs */
_iq e_pll; /* Variable: Error */
_iq i_pll; /* Variable: Integral output */
_iq p_pll; /*Variable: Proportional output */
_iq pi_pll; /*Variable: P-I output */
_iq theta; /* Output: PLL output (theta) */
_iq sin_theta; /* Output: sin(theta)*/
_iq cos_theta; /* Output: cos(theta) */
_iq Kp_pll; /* Parameter: P gain */
_iq Ki_pll; /* Parameter: I gain */
_iq wdt; /* System Frequency */
_iq i_pll_out_max; /* Param: Max Int output */
_iq i_pll_out_min; /* Param: Min Int output */
_iq pi_pll_out_max; /* Param: Max PI output */
_iq pi_pll_out_min; /* Param: Min PI output */
_iq deltat; /* Parameter: Time step */
void (*calc)(); /* Pointer to calc func */
} PLL;
typedef PLL *PLL_handle;
void PLL_calc(PLL_handle);
PLL.c
#include "IQmathLib.h" /* Include header for IQmath */
#include "pll.h"
void PLL_calc(PLL *v)
{
v->e_pll =_IQmpy(_IQcos(v->theta),v->qs)-
_IQmpy(_IQsin(v->theta),v->ds);
v->i_pll = v->i_pll+_IQmpy(v->Ki_pll,v->e_pll);
v->i_pll = _IQsat(v->i_pll,v->i_pll_out_max,v-
>i_pll_out_min);
v->p_pll = _IQmpy(v->e_pll,v->Kp_pll);
168
169
Table C-1. Continued

File Name C code
PLL.c v->pi_pll= v->p_pll+v->i_pll;
v->pi_pll= _IQsat(v->pi_pll,v->pi_pll_out_max, v-
>pi_pll_out_min);
v->theta= v->theta+_IQmpy(v->deltat,v->pi_pll)+v->wdt;
if (v->theta>=_IQ(3.141592654))
v->theta=v->theta-_IQ(2*3.141592654);
v->sin_theta = _IQsin(v->theta);
v->cos_theta = _IQcos(v->theta);
}
CLARKE.h typedef struct { _iq as; /* Input: phase-a variable */

_iq bs; /* Input: phase-b variable */
_iq cs; /* Input: phase-c variable */
_iq ds; /* Output: stationary d-axis variable*/
_iq qs;/* Output: stationary q-axis variable*/
_iq os;/* Output: stationary o-axis variable*/
void (*calc)(); /* Pointer to calc func */
} CLARKE;
CLARKE.c #include "IQmathLib.h" /* Include header for IQmath */

#include "clarke.h"
/* 1/sqrt(3) = 0.57735026918963 */
void clarke_calc(CLARKE *v)
{
v->ds =_IQmpy(_IQ(0.666666666),v->as)+_IQmpy(_IQ(-
0.3333333),(v->bs+v->cs));
v->qs =_IQmpy(_IQ(0.577350269),(v->bs-v->cs));
v->os =_IQmpy(_IQ(0.333333333),(v->as+v->bs+v->cs));
}
PARK.h typedef struct { _iq ds; /* Input: stationary d-axis */

_iq qs; /* Input: stationary q-axis */
_iq sin_theta; /* Input: cos(theta) */
_iq cos_theta; /* Input: sin(theta) */
_iq dr; /* Output: rotating d-axis*/
_iq qr; /* Output: rotating q-axis*/
void (*calc)(); /* Pointer to calc function */
} PARK;
typedef PARK *PARK_handle;
void park_calc(PARK_handle);
170

File Name C code
PARK.c #include "IQmathLib.h" /* Include header for IQmath*/

#include "park.h"
void park_calc(PARK *v)
{
v->dr = _IQmpy(v->ds,v->cos_theta) + _IQmpy(v->qs,v-
>sin_theta);
v->qr = _IQmpy(v->qs,v->cos_theta) - _IQmpy(v->ds,v-
>sin_theta);
}
ICLARKE.h typedef struct { _iq ds; /* Input: ds variable */

_iq qs; /* Input: qs variable */
_iq as; /* Output: stationary a-axis */
_iq bs; /* Output: stationary b-axis */
_iq cs; /* Output: stationary c-axis */
} ICLARKE;
typedef ICLARKE *ICLARKE_handle;
void iclarke_calc(ICLARKE_handle);
ICLARKE.c #include "IQmathLib.h" /* Include header for IQmath */

#include "iclarke.h"
void iclarke_calc(ICLARKE *v)
{
v->as = v->ds;
v->bs = _IQmpy(_IQ(-0.5), v->ds) +
_IQmpy(_IQ(0.8660254038),v->qs) ;
v->cs = _IQmpy(_IQ(-0.5), v->ds) + _IQmpy(_IQ(-
0.8660254038),v->qs);
IPARK.h typedef struct { _iq ds; /* Output: stationary d-axis */

_iq qs; /* Output: stationary q-axis */
_iq sin_theta; /* Input: cos(theta) */
_iq cos_theta; /* Input: sin(theta) */
_iq dr;/* Input: rotating d-axis*/
_iq qr;/* Input: rotating q-axis*/
void (*calc)();/* Pointer to calc function */
} IPARK;
typedef IPARK *IPARK_handle;
171

File Name C code
IPARK.c #include "IQmathLib.h" /* Include header for IQmath*/

#include "ipark.h"
void ipark_calc(IPARK *v)
{
v->ds = _IQmpy(v->dr,v->cos_theta) - _IQmpy(v->qr,v-
>sin_theta);
v->qs = _IQmpy(v->qr,v->cos_theta) + _IQmpy(v->dr,v-
>sin_theta);
}
PIANTIWINDUP.h typedef struct { _iq feedback; /* Input: Feedback signal */

_iq e_pi; /* Variable: Error */
_iq i_pi; /* Variable: Integral output*/
_iq p_pi; /* Variable: Proportional output */
_iq pi_pi; /* Variable: PI output */
_iq out; /* Output: PI control action */
_iq ref; /* Parameter: Reference signal */
_iq Kp_pi; /* Parameter: Proportional gain */
_iq Ki_pi; /* Parameter: Integral gain */
_iq i_pi_out_max; /* Parameter: Max Int */
_iq i_pi_out_min; /* Parameter: Min Int */
_iq pi_pi_out_max; /* Parameter: Max PI */
_iq pi_pi_out_min; /* Parameter: Min PI */
} PIANTIWINDUP;
PIANTIWINDUP.c #include "IQmathLib.h" /* Include header for IQmath*/

#include "PIantiwindup.h"
void PIantiwindup_calc(PIANTIWINDUP *v)
{
v->e_pi = v->ref-v->feedback;
v->i_pi = _IQsat(v->i_pi+_IQmpy(v->Ki_pi,v->e_pi),
v->i_pi_out_max,v->i_pi_out_min);
v->p_pi = _IQmpy(v->e_pi,v->Kp_pi);
v->pi_pi=v->p_pi+v->i_pi;
v->out=_IQsat(v->pi_pi,v->pi_pi_out_max,v-
>pi_pi_out_min);
}
LIST OF REFERENCES
[1] National Renewable Energy Laboratory. (2001, March). Renewable Energy: An

Overview. US Department of Energy. Energy Efficiency and Renewable Energy,
Merrifield,_VA._[Online]._Available:http://www.eere.energy.gov/consumerinfo/fa
ctsheets/renew_energy.html. Site last visited April 2005.
[2] AWEA's Communications Department. (2004, June). Wind Energy Outlook 2004.
American Wind Energy Association, Washington, DC. [Online]. Available:
http://www.awea.org/pubs/documents/Outlook2004.pdf. Site last visited April
2005.
[3] AWEA's Communications Department. (2004, June). Global wind power growth
continues to strengthen.[Online]. American Wind Energy Association, Washington,
DC. Available:http://www.awea.org/pubs/documents/globalmarket2004.pdf. Site
last visited April 2005.
[4] Database of State Incentive for Renewable Energy. (2005, April). Financial
Incentives. Interstate Renewable Energy Council, Raleigh, NC. [Online].
Available: http://www.dsireusa.org. Site last visited April 2005.
[5] “IEEE Standard for Interconnecting Distributed Resources with Electric Power
Systems”, IEEE Std. 1547, 2003.
[6] “Wind turbine generator systems. Part 21: Measurement and assessment of power
quality characteristics of grid connected wind turbines”. International
Electrotechnical Commission Standard 61400-21. 1999.
[7] Z. Lubosny, Wind turbine Operation in Electric Power Systems. New York:
Springer, 2003.
[8] B. Davidson and A. Price, ”Solutions to Future Market needs. The role of energy
storage,” in Proc. CIGRE, 2002, Paper 37-201.
[9] New Energy and Industrial Technology Development Organization. (2003, April).
Wind Power Stabilization Technology Development Project. NEDO, Japan.
[Online]._Available:http://www.nedo.go.jp/english/activities/2_sinenergy/3/P0303
9e.html. Site last visited April 2005.
172
173
[10] VRB Power Systems Inc. (2004, March). The VRB Energy Storage System: The
Multiple Benefits of Integrating the VRB-ESS with Wind Energy Producers- a
Case Study in MWH Applications. VRB Power Systems Inc., Vancouver, Canada.
[Online]. Available: http://www.vrbpower.com/vrb_power.html. Site last visited
April 2005.
[11] B. L. Norris, R. J. Parry, and R. M. Hudson, “An Evaluation of Windfarm

Stabilization and Load Shifting Using the Zinc-Bromide Battery (ZBB),” in Proc.
Windpower 2002, Portland, Oregon, 2002.
[12] Z. Fengquan, G. Joos, C. Abbey, and J. Lianwei, O. T. Boon, “Use of large

capacity SMES to improve the power quality and stability of wind farms,” in Proc.
Power Engineering Society General Meeting, 2004, pp. 2026–2031.
[13] T. Kinjyo, T. Senjyu, K. Uezato, H. Fujita, and T. Funabashi, ”Output levelling of

wind energy conversion system by current source ECS,” in Proc. Power
Engineering Society General Meeting, 2004. pp. 2007–2012.
[14] J. H. R. Enslin, J. Knijp, C. P. J. Jansen, and P. Bauer, “Integrated approach to

network stability and wind energy technology for on-shore and offshore
applications,” in Proc. Official proceedings international conferences ZM
Communications GmbH, 2003, pp. 185–193.
[15] F. Hardan, J. A. M. Bleijs, R. Jones, and P. Bromley, ”Bi-Directional Power

Control for Flywheel Energy Storage Systems with Vector-Controlled Induction
Machine Drive,” IEE Power Electronics and Variable Speed Drives, publ. 456, pp
477-482, September, 1998.
[16] F. Hardan, J. A. M. Bleijs, R. Jones, P. Bromley, and A. J. Ruddell, ”Application of

a Power-Controlled Flywheel Drive for Wind Power Conditioning in a
Wind/Diesel Power System,” in Proc. Ninth International Conference on Electrical
Machines and Drives, 1999, pp 65–70.
[17] H. Bindner and L.H. Hansen, “Combining wind and Energy storage to improve
grid integration,” in presented at the IEEE Nordic Workshop on Power and
Industrial Electronics, Aalborg, Danmark, 2000.
[18] R. Cardenas, R. Pena, G. Asher, and J. Clare, “Power smoothing in wind generation
systems using a sensorless vector controlled induction Machine driving a
flywheel,” IEEE Transactions on Energy Conversion, vol. 19 , pp. 206–216, March
2004.
[19] R. Cardenas, R. Pena, and J. Glare, “Control strategy for power smoothing using
vector controlled induction machine and flywheel,” Electronics Letters, vol. 36,
pp.765–766. 13 April 2000.
174
[20] R. Cardenas, G. Asher, R. Pena, and J. Clare, “Power smoothing control using
sensorless flywheel drive in wind-diesel generation systems,” in Proc. Industrial
Electronics Society, 2002, 3303–3308.
[21] R. Cardenas, R. Pena, G. Asher, J. Clare, and R. Blasco-Gimenez, “Control

Strategies for Power Smoothing Using a Flywheel Driven by a Sensorless Vector-
Controlled Induction Machine Operating in a Wide Speed Range,” IEEE
Transactions on Industrial Electronics, vol. 51, pp. 603–614, June 2004.
[22] R. Cardenas, R. Pena, J. Clare, and G. Asher, “Power smoothing in a variable speed
wind-diesel system,” in Proc. Power Electronics Specialist, 2003, pp. 754–759.
[23] I. J. Iglesias, L. Garcia-Tabares, A. Agudo, I. Cruz, and L. Arribas, “Design and

simulation of a stand-alone wind-diesel generator with a flywheel energy storage
system to supply the required active and reactive power,” in Proc. Power
Electronics Specialists Conference, 2000, pp. 1381–1386.
[24] S. Wijnbergen, S. W. H. de Haan, and J. Slootweg, “Plug 'n' play interface for
renewable generators participating in grid voltage and frequency control,” in Proc.
IEEE AFRICON, 2002, pp. 579–584.
[25] J. A. M. Bleijs, L .L. Freris, D. G. Infield, A. J. Ruddell, and G. A. Smith, “A

Wind/diesel System With Flywheel Energy Buffer,” in Proc. International Power
Conference Athens Power Tech, 1993, pp. 995–999.
[26] EPRI-DOE, “EPRI-DOE Handbook of Energy Storage for Transmission and

Distribution Applications”. EPRI, Palo Alto, CA, Report 1001834. Dec 2003.
[27] C. L. Fortescue, “Method of Symmetrical Co-Ordinates Applied to the Solution of

Polyphase Networks,” Transactions of the American Institute of Electrical
Engineers, vol. 37, pt. 2, 1918.
[28] N. Mohan, T, M. Undeland, and W, P. Robbins, Power electronics: converters,

applications, and design. New York: Wiley, 1989.
[29] “IEEE recommended practices and requirements for harmonic control in electrical
power systems,” IEEE Std. 519-1992, 12 April 1993.
[30] M. Liserre, F. Blaabjerg, and S. Hansen, “Design and control of an LCL-filter

based three-phase active rectifier,” in Proc. Industry Applications Conference,
2001, pp .299–307.
[31] M. Prodanovic and T. C. Green, “Control and filter design of three-phase inverters
for high power quality grid connection,” IEEE Transactions on Power Electronics,
vol. 18, pp. 373–80, Jan. 2003.
175
[32] R. Teodorescu, F. Blaabjerg, M. Liserre, and A. Dell'Aquila, ” A stable three-phase

LCL-filter based active rectifier without damping,” in Proc. Industry Applications
Conference, 2003, pp.1552–1557.
[33] R. Teodorescu, and F. Blaabjerg, “Flexible control of small wind turbines with grid
failure detection operating in stand-alone and grid-connected mode,” IEEE
Transactions on Power Electronics, vol. 19, pp. 1323–1332, Sept. 2004.
[34] S. Bhattacharya, T. M. Frank, D. M. Divan, and B. Banerjee, “Active filter system

implementation,” IEEE Industry Applications Magazine, 1998, vol. 4, pp.47–63.
[35] T.C.Y. Wang, Z. Ye, G. Sinha; and X. Yuan, ”Output filter design for a grid-
interconnected three-phase inverter,” in Proc. Power Electronics Specialist PESC,
2003, pp. 779–784.
[36] A. Montenegro, A. Domijan, Jr., K. E. Mattern, and C. W. Edwards, “Energy

Storage System for Wind Farm Applications: Application Methodology,” presented
at the 7th IASTED International Conference on Power and Energy Systems,
Clearwater Beach, USA, 2004.
[37] O. I. Elgerd, Electric energy systems theory. New York: McGraw-Hill, 1971.
[38] J. F. Manwell, J. G. McGowan, and A. L. Rogers, Wind Energy Explained: Theory,

Design and Application, England: John Wiley & Sons Ltd, 2002.
[39] A. E. Feijoo and J. Cidras, ” Modeling of wind farms in the load flow analysis,”
IEEE Transactions on Power Systems, vol. 15, pp. 110–115 Feb. 2000.
[40] Y. H. Wan,” Wind Power Plant Behaviors: Analyses of Long-Term Wind Power
Data,” NREL, Golden, CO., Report No. CP-500-36551, September 2004.
[41] Y. H. Wan and D. Bucaneg, “Short-Term Power Fluctuations of Large Wind Power
Plants,” NREL, Golden, CO., Report No. 33842. November 2002.
[42] Texas Intruments “C28x™ IQMath Library - A Virtual Floating Point Engine,”
Texas Intruments, Dallas, TX, Tech. Rep. SPRC087. March 2003.
[43] G. R. Walker, "Modulation and Control of Multilevel Converters," PhD

dissertation, University of Queensland, Brisbane, Australia,1999.
BIOGRAPHICAL SKETCH
Alejandro Montenegro obtained his BS degree in Electronic Engineering from the
Polytechnic University of Valencia (UPV) in 1995 and his MS in Industrial Engineering
from UPV in 2000. He has been a research assistant at the Department of Electrical
Engineering (UPV) and is currently a research assistant and a Ph.D. candidate at the
University of Florida in the Department of Electrical and Computer Engineering. His
field of interest is reliability and power quality of distribution networks using power
electronic devices.
176

Advanced Power Electronic For Wind-Power Generation Buffering (TH., Alejandro Montenegro León)

Hochgeladen von

Dokumentinformationen

Originaltitel

Copyright

Verfügbare Formate

Dieses Dokument teilen

Dokument teilen oder einbetten

Freigabeoptionen

Stufen Sie dieses Dokument als nützlich ein?

Sind diese Inhalte unangemessen?

Copyright:

Verfügbare Formate

Advanced Power Electronic For Wind-Power Generation Buffering (TH., Alejandro Montenegro León)

Hochgeladen von

Copyright:

Verfügbare Formate

ADVANCED POWER ELECTRONIC FOR

WIND-POWER GENERATION BUFFERING

ALEJANDRO MONTENEGRO LEÓN

A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL

Alejandro Montenegro León

I would like to first express my gratitude to Charles Edwards, the principle

confidence in my ability. I am grateful to S&C Electric Company in general for all of

their contribution and concern.

Additionally, I would like to thank Alexander Domijan (my supervisory committee

I would furthermore like to acknowledge my family in Spain, for supporting me

LIST OF TABLES........................................................................................................... viii

LIST OF FIGURES ........................................................................................................... ix

Wind-Energy Outlook ..................................................................................................1

4 SYSTEM PERFORMANCE ....................................................................................121

System Data ..............................................................................................................121

B MATLAB CODES ...................................................................................................158

BIOGRAPHICAL SKETCH ...........................................................................................176

1-1 Technical specifications of IEC and IEEE ................................................................4

1-2 Wind-farm output-power requirements.....................................................................8

1-3 Large-scale wind-power output-leveling projects...................................................10

1-4 Conceptual wind-power filtering projects...............................................................12

1-5 Basic system configurations....................................................................................13

2-1 Outer regulator assignation .....................................................................................35

2-2 Rate-of-change limits or PPA for a 10 MW wind farm ..........................................47

2-3 Generalized Harmonics of line-to-line voltage .......................................................59

2-4 L filter vs. LCL filter...............................................................................................61

2-5 LCL filter design .....................................................................................................64

2-6 LCL equivalent impedance with damping resistance .............................................65

2-7 Per-unit system........................................................................................................65

2-8 Per-unit system parameters .....................................................................................73

2-9 Designed system results and simulated system results comparison........................76

3-1 Synchronous machine output voltage profile at rated speed...................................82

3-2 Alternatives for the power stabilizer controller.....................................................106

3-3 FPGA code words .................................................................................................120

4-1 System parameters.................................................................................................122

A-1 Mathematical transformations summary ...............................................................157

C-1 Control Modules....................................................................................................168

1-2 Power fluctuation comparison...................................................................................6

1-3 Typical power curve of a wind turbine. ....................................................................6

1-4 Wind-farm output power vs system frequency. ........................................................7

1-5 Control strategies along the power curve ..................................................................8

1-6 Wind-farm generation buffering concept ................................................................13

2-1 Unbalanced system..................................................................................................15

2-3 Space vector trajectory projection over the d-q plane.............................................16

2-4 Direct and quadrature components of an unbalanced system .................................17

2-5 Representation of an unbalanced system in the frequency domain.........................17

2-6 Positive-sequence extraction algorithm ..................................................................19

2-7 Voltage waveforms for an unbalanced fault event..................................................19

2-8 Response of the positive-sequence extraction algorithm ........................................20

2-9 Distortion of phase angle due to a negative sequence component ..........................22

2-10 PLL diagram............................................................................................................23

2-11 PLL simplified model..............................................................................................24

2-12 PLL system step response .......................................................................................25

2-13 Root locus for two different regulator gains ...........................................................25

2-14 PLL system response to an unbalanced system condition ......................................26

2-16 System description ..................................................................................................27

2-17 Simplified system model .........................................................................................28

2-18 Electrical representation of the dq components ......................................................30

2-19 System model block diagram ..................................................................................30

2-20 Inverter current regulator-system model block diagram .........................................31

2-21 Inverter current regulator-system model simplified block diagram........................32

2-22 Simplified current control diagram .........................................................................32

2-23 Current regulator step response...............................................................................33