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Chetan Sharma,Shobhit Jaiswal, Int. J. Comp. Tech. Appl., Vol 2 (1), 160-164
Abstract: The rapid growth in integration design, physical design, design verification,
technology has been made possible by the fabrication, packaging, testing and
automation of various steps involved in the debugging. The physical design is important
design and fabrication of VLSI chips. The step in the chip designing.
main factors which decide the quality of any The process of converting the specification
chip are power consumption, area and of an electrical circuit into a layout is called
performance of the chip. The demand of the physical design process. Due to
light weighted & compact chip is increase extremely small size of the individual
day by day. This paper reviewed the components, physical design is an extremely
different techniques of compaction of any tedious and error prone process. Almost all
chip and comparison among them because phases of physical design extensively use
different techniques have different tradeoffs. Computer Aided Design (CAD) tools,
The appropriate technique is used depending means steps are partially or fully automated.
160
ISSN : 2229-6093
Chetan Sharma,Shobhit Jaiswal, Int. J. Comp. Tech. Appl., Vol 2 (1), 160-164
161
ISSN : 2229-6093
Chetan Sharma,Shobhit Jaiswal, Int. J. Comp. Tech. Appl., Vol 2 (1), 160-164
2
1-Dimensional compaction:
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ISSN : 2229-6093
Chetan Sharma,Shobhit Jaiswal, Int. J. Comp. Tech. Appl., Vol 2 (1), 160-164
(b) Scanline Technique: The scanline is an The trade off in this technique is the much
imaginary horizontal or vertical line that time consumption. Thus we use 3/2-D
1
Compaction.
4
In this method two lists are formed one is
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ISSN : 2229-6093
Chetan Sharma,Shobhit Jaiswal, Int. J. Comp. Tech. Appl., Vol 2 (1), 160-164
References:
[1] G. A. Allen et al. “A yield improvement Systems, vol. CAD-3, no.1, pp. 87-100,
rules,” IEEE Transactions on Computer [7] S. Sastry and A. Parker, “The complexity
Aided Design, vol.11, no. 11, pp.1355-1360, of two dimensional compaction of VLSI
[2] C.Bamji and E. Malavasi, “Enhancement [8] H. Xue, C. N. Di, and J. A. Jess ,“Fast
synthesis techniques for yield enhancement [9] H. Xue, C. N. Di, and J. A. Jess,”A net-
manufacturing, vol. 8:2 pp. 178-187, May analysis,” in Proc. IEEE Int. Conf. On
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