A Constant-Gain Time-Amplifier

with Digital Self-Calibration

Baoli Tong, Wei Van, and Xiaofang Zhou *

Abstract - This paper presents a closed-loop time-

amplifier (TA) with a novel self-calibration technique by A
adjusting the output capacitance of the conventional TA. The
gain of the TA is stabilized, with an input of 0.05---1 Td (one
buffer delay), over a large Process-Voltage-Temperature
(PVT) variation: from SS to FF process corner, +/-10%
supply voltage, and -40 to 80°C. The proposed TA is designed
with SMIC 0.18-Jlm mixed-signal CMOS process. Simulation
results show that the gain deviation of TA is well controlled
within 0.35% under all circumstances, with regard to the gain
in typical PVT condition, and the whole circuit consumes 600
JlA with an input signal of40 MHz. 1
,------'"
I

Index Terms - Time Amplifier (TA), Time-to-Digital (a)

Converter (TDC), Self-Calibration .lITOUT

I. INTRODUCTION
Time-amplifier (TA) is used to amplify a time interval
between two rising/falling edges to a larger one. With the
rapid development of time-to-digital converters (TDCs) in
recent years, TA emerges as a core device of them to improve
the resolution [1]-[3]. As a comparison to a voltage amplifier
in pipelined ADCs, a TA should both be very precise in its
gain independent of PVT, which requires a feedback
mechanism to stabilize it, and be very capable to handle an
input range wide enough from several picoseconds to at least a
minimum delay of one delay element under certain fabrication
process.
In the original work of TDC which applied TA to improve
resolution [1], no efforts were made to adjust the TA gain
timely according to the PVT changes and the TA was used in
open-loop form. Inevitably, the linearity of TDC will be
greatly influenced by the floating gain of the open-loop TA.
An algorithm is proposed in [2] to cancel out the influence
of the floating-gain of open-loop TAs. The time intervals of
Tin and Td are amplified by the same gain of AT and finally
cancel out the influence of AT through a division. But
meanwhile, the amplified residues ATTin and ATTd are both
quantized by Td, which limit its applications in large-sized
process, where Td is large and the quantization error is
increased.
Actually, one type of closed-loop TA has been proposed [3].
IThis work was supported by China NSF under Grant No. 60876016 and
the State Key Lab of ASIC & System under Grant No. ZD20080103.
B. Tong is with the State Key Lab of ASIC & System, Fudan University,
Shanghai, 201203 China (e-mail: 072052019@fudan.edu.en).
W. Van is with the State Key Lab of ASIC & System, Fudan University,
Shanghai, 201203 China (e-mail: 0021074@fudan.edu.en).
X. Zhou is with the State Key Lab of ASIC & System, Fudan University,
Shanghai, 201203 China (e-mail: xiaofangzhou@fudan. edu.en).
(b)
Fig. 1. Conventional TA (a) the structure of conventional TA (b) the
transfer characteristic of conventional TA
It applied DLL to adjust the gain which can be very precise.
However, the linear range of its amplification starts from
nearly 100 ps, making it useless when dealing with small
interval inputs. What's more, with analog device DLL as its
calibration device, such a TA suffers from the scaling down of
process which brings degradation to the performance of most
analog circuits including DLL.
In this paper, we present a closed-loop TA adopting real-
time digital calibration loop which can adjust TA's gain
according to PVT changes. The paper is organized as follow:
Section II describes the principle of the open-loop TA core of
this work and explains the uncertainty issues of its gain
according to PVT changes. In section III the calibration
scheme is elaborated and section IV illustrates the detailed
modules of the calibration loop. The simulation results are
given in section V, and section VI presents the conclusion.
II. PRINCIPLE OF TRADITIONAL TA
The basic model of TAwas designed exploiting the
metastablility feature of SR latch [2], [4]. The structure is
shown in Fig. l(a) with its transfer characteristic in Fig. l(b).
The small-signal gain ofTA is given by

978-1-4244-3870-9/09/$25.00 ©2009 IEEE

1133
 A
~!n
----i~!. . --------~ !
:r
A -r-------,
~!n

J -..-----,
r
r
B ----li: ~olft 1 ,' ,
,,
B
~olft
---Jt.._---,
!,::

Ao ---W ·
, '
,,
1 I....:-------i---
,,
Ao
---ij--------,
80 ~:
kamplification period::
~
i
..!E-----~oj
Bo

ClK
idol period
~ ClKN 1
TA retrieving period
!c{
Fig. 2. Timing diagram of TA's amplification procedure Ae ,i
Be iI 2T d
A eo
! 1:1!
B eo
Cri
i ;
c
CLKQC LJ
Qe QC n X QC n t 1
Fig. 4. Waveform of self-calibration procedure

compare the output interval with ATTd. If the output interval is

Fig. 3. Flow chart of proposed self-calibration algorithm
AT =~ (1)
gm~ff
where gm is transconductance of the NAND gate in
metastablility and C is the output capacitance of TA. Toff
indicates the time offset here. Obviously, gm and Toff are PVT
dependant. As a result, the gain of TA cannot remain constant
which is confirmed by the simulation results in section V.
III. CALIBRATION SCHEME
A. Principle ofcalibration
When we examine the amplification procedure, as shown in
Fig. 2, where A and B represent the TA input signals during
amplification period and Ao and Bo indicate the TA output
signals, it can be found that the idol period of the input signals
can be used to make another amplification to adjust the gain
ofTA, as long as the frequency of the input signal is not quite
high. If we can adjust the TA gain little by little in each period,
the gain will reach a stabilized state after several periods,
which just adapts the situation that PVT condition always
changes mildly.
In order to adjust TA gain to cope with the violation, we
find in (1) that C is large enough to divide into many
programmable cells so that we can add or delete one to adjust
the C, and consequently, the TA gain is regulated.
As our goal is to enlarge the linear range to Tde during the
calibration period, we can input a time interval of T; and
smaller than ATTd, we increase the output capacitor C, and
vice versa.
B. Calibration Procedure
The calibration procedure is shown in the flow chart Fig. 3
where we divide the output capacitor into an 8-bit
programmable capacitor array. Though we have made a great
room for the calibration range, we have to stop the further
adding or subtracting and force it to stay if we reach the full
scale, in this case, even the full scale of capacitors cannot
satisfy the TA gain requirement.
The timing diagram of the calibration procedure is shown in
Fig. 4, which take an AT of two as example. The switching
from amplification to calibration is controlled by a pair of
clock signals (CLK and CLKN) which is generated according
to the input signal and the calibration state. When the stop
input signal enters the idol period (low level period), the clock
signals switch the TA into calibration state; when the
calibration is completed, the clock signals switch the TA into
waiting state to wait for another input interval's coming. Ae
and Be in Fig. 4 are used to indicate input signals in
calibration state whose interval is Td while Aeo and Bco are the
corresponding output signals. Another signal Cri is generated
2Tdafter Aco to act as a criterion of a precise gain of two to
regulate Beo . If Beo comes later than Cri, it means the amplified
interval of Td is larger than 2Td and the comparison result (Ci)
will tell the programmable capacitor array state (Qc) to
decrease by one. Another clock signal (CLK Qc ) of the
programmable capacitor array controller should be generated
to suit the timing requirements of it.

1134
 .- _-..
CLKN
start.o--_ _ -_rrCLK A
So
Stop CLK B
Po
-----------I
Rese,D-........
(a)
A Fig. 7. Proposed edge arbiter
8 we use a switch to control the connection of it, as shown in
(b)
Fig. 5. Detailed structure of proposed TA
IV. DETAILED STRUCTURE OF PROPOSED T A
A. Whole structure ofproposed TA
In this work, we designed a TA with a gain of two under an
input of 0.05,,-,1 Td. Therefore, the output of TA is compared
with 2Td during the calibration period. The detailed TA
structure is shown in Fig. 5(a). It contains four additional
blocks aside from the conventional TA core with adjustable
capacitors controlled by a 8-bit Qc, as shown in Fig. 5(b).
Note that some dummies are inserted to ensure all the buffers
have the same load condition, thus all the Td are matched.
The first block is to generate the clock signals. The second
block is to generate a time interval of one Td when the TA
enters calibration period. The third block is to compare the
output interval with 2T d which is generated just like the input
interval, and then, the result is indicated by the signal Ci. If Ci
equals" 1", the output time interval is larger than 2Td and the
output capacitor should be decreased, and vice versa. The last
ctr-~~
(a) (b)
Fig. 6. Connection method of programmable capacitor cell (a) traditional
method (b) proposed method
Vdd
Stan top
Stop
Start
block is the adder/subtractor, which receives the Ci signal
from the third block and adjusts the output capacitor in Fig.
5(b).
B. Digitization ofthe output capacitor
As the adjusting of the output capacitor should be gradual,
one cell capacitance is consisted of a very small transistor. If
Fig. 6(a), the capacitance of the switch is always much larger
than one capacitor cell. Therefore, we connected the capacitor
in the way shown in Fig. 6(b). When the control signal is
switched to high level, during the rising of the input signal,
the inversion layer gradually forms and the capacitance is
large; when the control signal is switched to low level, the
source and drain clamp the gate to drain voltage to a negative
voltage and the inversion layer is nowhere exist, as a result,
the capacitance is very small.
C. Arbiter
A complementary sense amplifier based arbiter [2] is used
for comparing the time order of rising edges. To compensate
the turning off delay of the reset signal introduced by the
NOR gate, two buffers are added at the inputs. Therefore, the
signal S or P and Reset will arrive at the same time, which
helps to increase the input resolution of the arbiter to 1 ps.
V. SIMULATION RESULT
The proposed TAwas simulated by Hspice using SMIC
0.18-~m mixed-signal CMOS process. The advantage of the
calibration is testified by the measurement of the open-loop
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 TABLE I
2.6
COMPARISON OF GAIN DEVIATION FROMA T=2
c - 55, 80 deg, 1.62 V
'n; 2.4 --O-lT, 20 deg, 1.8 V Calibrated T A Uncalibrated T A
C) PVT condition
Gain violation Gain violation
«
I- 2.2
-;E-FF, -40 deg, 1.98 V
TT / 1.8 V /20 deg -3.5% -5%
"'C SS / 1.62 V / 80 deg -3% -26%
..... 2.0
(1)
FF / 1.98 V / -40 deg -4% +5%
l! o c
:9 1.8
cuu TABLE II
COMPARISON OF GAIN LINEARITY OVERTHE PVT CONDITIONS
e 1.6
::J
= = ~ Calibrated T A Uncalibrated TA
1.4
0.35% 31.69%
0.0 0.2 0.4 0.6 0.8 1.0
Normalized Input (TlTd) TABLE III
COMPARISON OF GAIN LINEARITY OVERT D
(a)
1.98,--....--y-.......---,-...-..,.--...---..._- Calibrated T A Uncalibrated T A
PVT condition
- - 55, 80 deg, 1.62 V Gain violation Gain violation
e 1.97 --o-lT, 20 deg, 1.8 V TT /1.8 V /20 deg 1.86% 2.00%
.n;
C) 1.96 ~FF, -40deg, 1.98V SS / 1.62 V / 80 deg 0.72% 1.72%
FF / 1.98 V / -40 deg 1.08% 2.23%
~ 1.95
"'C
S 1.94 as criterion. Table III shows the gain linearity of the two types
:el! 1.93 of TA over 0.05---1 T d under different PVT conditions and the
gain at the T d input is used as criterion. As can be seen, the
~ 1.92 gain of TA is well controlled around two by proposed digital
1.91 self-calibration technique, and the linearity over both the PVT
1.90--=----~~---L---------L.-------..L------....J conditions and the input range of 0.05---1 T d are improved. The
0.0 0.2 0.4 0.6 0.8 1.0 whole TA consumes about 600 ~A from a supply of 1.8 V
Normalized Input (TlTd) with an input signal of 40 MHz.
(b)
Fig. 8. Simulation results of two types of T A gain (a) uncalibrated TA VI. CONCLUSION
gain (b) calibrated TA gain
A close-loop TA was presented in this paper. It applied a
digital self-calibration technique during the idol period of
and calibrated gain under extreme PVT conditions. The open-
amplification to stabilize the gain and obtained a constant gain
loop and calibrated TAs used for test are all designed with a
independent of PVT changes within a deviation range of only
gain of two under process corner of TT, 1.8 V supply voltage,
0.35%. This TA is realized using SMIC 0.18-~m mixed-signal
and room temperature. The extreme PVT conditions are
CMOS process with a gain of two, and it is quite easy to
chosen as the following two, representing slowest and fastest
extend the gain to a larger integral one under different process
conditions separately: the first one is under process corner of
with more comparison buffers in block three in Fig. 5. It will
SS, -10% supply voltage (1.62 V), and a temperature of 80 DC,
be very helpful in improving the resolution together with
whereas the second one is under process corner of FF, + 10%
linearity of coarse-fine TDCs.
supply voltage (1.98 V), and a temperature of -40 DC. Fig. 8(a)
shows the gains of open-loop TA under above PVT conditions
REFERENCES
and Fig. 8(b) shows the calibrated gains under the same PVT
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conditions. As can be seen, the stability of the gain has been
resolution delay measurement system using time amplification," lET
greatly enhanced. Computers & Digital Techniques, vol. 1, no. 2, pp. 77-86, Mar. 2007.
Table I is concluded from Fig. 8 which shows the gain [2] M. Lee and A. A. Abidi, "A 9 b, 1.25 ps resolution coarse-fine time-to-
deviation from the goal of A T=2 of the proposed TA digital converter in 90 nm CMOS that amplifies a time residue," IEEE 1.
Solid-State Circuits, vol. 43, no. 4, pp. 769-777, Apr. 2008.
compared to conventional open-loop TA. Table II shows the [3] R. Rash~dzadeh, R: Muscedere, M. Ahmadi, and W. C. Miller, "A Delay
gain linearity of the two types ofTA over the PVT conditions , Generation Technique for Narrow Time Interval Measurement" IEEE
using average gain within 0.05---1 T, under each PVT Trans. Instrum. Meas., vol. 58, no. 7, pp. 2245-2252, JuI. 2009. '
[4] A. M. Abas et aI., "Time difference amplifier," Electron. Lett., vol. 38,
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