A B C D E

m
1 1

co
NALAA

a.
si
Hamburg 10G

ne
2 2

do
LA-6042P REV 1.0 Schematic

in
i-
is
3
Intel Arrandale / IBEX PEAK 3

2010-04-12 Rev 1.0

kn
te
w.
ww

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 1 of 58
A B C D E
 A B C D E

Compal Confidential Fan Control VGA Thermal Sensor Clock Generator

Intel Arrandale APL5607KI-TRG ADM1032ARMZ-2R RTM890N-631-GRT
Model Name : NALAA page 6 page 21 page 22

File Name : LA-6042P

m
1 PCIE-Express 16X 2.5GHz 1

rPGA-988 Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2

co
Dual Channel BANK 0, 1, 2, 3 page 11,12

page 5,6,7,8,9,10 1.5V DDRIII 800/1066 MT/s

a.
VGA (DDR3)
ATI M92 XTX,64bit with 512MB AUDIO & USB/B BT conn
DMI X4 USB port 0,1 USB port 5
ATI Park XT,64bit with 512MB page 39 page 35

si
2.5GHz
ATI Madison LP,128bit with 1GB 3IN1 RTS5138-GR Int. Camera
page 13,14,15,16,17,18,19,20,21 USB port 10 USB port 11
USB page 40 page 22

ne
5V 480MHz

2 2
LCD Conn. CRT HDMI Conn.
page 22 page 23 page 24
PCIeMini Card

do
USB
5V 480MHz
WLAN
USB port 13
PCIe 1x page 36
1.5V 2.5GHz(250MB/s)

in
PCIe port 2
page 36
Intel Ibex Peak
SATA port 1 SATA HDD0

i-
BGA-951 5V 3GHz(300MB/s) page 34

SATA port 4 SATA ODD

5V 3GHz(300MB/s) page 34
is
3 RTL8105E-VB-GR 10/100M 3
RJ45 PCIe 1x SATA port 5
page 37
RTL8111E-VB-GR Giga 1.5V 2.5GHz(250MB/s) 5V 3GHz(300MB/s)
PCIe port 1 page 37 page 25,26,27,28,29,30,31,32,33 eSATA USB
USB port 3 USB port 3
page 34 page 34
kn

5V 480MHz

3.3V 33 MHz
LPC BUS

HD Audio 3.3V/1.5V 24MHz

te

Power/B DC/DC Interface CKT. MDC 1.5 Conn HDA Codec

page 43 ALC259-GR
page 44 SPI ROM Debug Port ENE KB926 E0 page 35 page 38
w.

page 25 page 42 page 41

AUDIO & USB/B Power Circuit DC/DC Digital MIC
page 39
page 45~54
LCD Conn. AUDIO & USB/B SPK CONN
ww

4
ODD/B Touch Pad Int.KB EC ROM page 22 page 39
4

page 34 page 35 page 35 page 42

USB port 0,1
RTC Circuit page 39
page 25
LED/B Security Classification Compal Secret Data Compal Electronics, Inc.
page 43 Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 2 of 58
A B C D E
 5 4 3 2 1

NALAA Hamburg Intel Arrandale (Discrete)

B+
Ipeak=5A, Imax=3.5A, Iocp min=7.9 DESIGN CURRENT 5A +5VALW

m
SUSP
D D
N-CHANNEL DESIGN CURRENT 4A +5VS

co
SI4800

RT8205EGQW

a.
Ipeak=5A, Imax=3.5A, Iocp min=7.7 DESIGN CURRENT 5A +3VALW
WOL_EN#
P-CHANNEL DESIGN CURRENT 330mA +3V_LAN

si
AO-3413

SUSP
N-CHANNEL DESIGN CURRENT 4A +3VS
SI4800

ne
VGA_ENVDD
P-CHANNEL DESIGN CURRENT 1.5A +LCD_VDD
C AO-3413 C

BT_PWR#

do
DESIGN CURRENT 180mA +BT_VCC
P-CHANNEL
AO-3413
PCIE_OK
DESIGN CURRENT 100mA +3VS_DELAY
P-CHANNEL
AO-3413

in
VR_ON
Ipeak=48A, Imax=33.6A, Iocp min=57.28 DESIGN CURRENT 48A +CPU_CORE
ISL62883

i-
SUSP#
Ipeak=22A, Imax=15.4A, Iocp min=28.71 DESIGN CURRENT 22A +VGA_CORE
APW7138NITRL is
VTTP_EN#
B B
Ipeak=20A, Imax=14A, Iocp min=27.49 DESIGN CURRENT 20A +VTT
APW7138NITRL
kn

SYSON
Ipeak=14A, Imax=9.8A, Iocp min=18.83 DESIGN CURRENT 14A +1.5V +1.5V_CPU
RT8209BGQW SUSP
DESIGN CURRENT 12A +1.5VS
N-CHANNEL
te

SI4856 SUSP
DESIGN CURRENT 1.3A +0.75VS
SUSP#
G2992F1U
DESIGN CURRENT 1.56A +1.0VS
SUSP# APL5930KAI
w.

DESIGN CURRENT 2A +1.8VS

MP2121DQ
ww

A SUSP# A

Ipeak=7A, Imax=4.9A, Iocp min=7.7 DESIGN CURRENT 7A +1.05VS

RT8209BGQW
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 3 of 58
5 4 3 2 1
 A B C D E

Voltage Rails ( O MEANS ON X MEANS OFF ) BTO Option Table

CPU Arrandale Clarksfield

+RTCVCC +B +5VALW +1.5V +5VS
+3VL +3VALW +3VS S3 Reduce Enable Disable Enable Disable

m
+1.5VALW +1.5VS
1 power GPU Type Manhattan M9X Manhattan M9X Manhattan M9X Manhattan M9X 1

plane +VSB +VGA_CORE

co
+CPU_CORE M1@ M1@ M1@ M1@ PSM3@ PSM3@ M3@ M3@
+VTT BTO PS@ PS@ NPS@ NPS@ PS@ PS@ NPS@ NPS@
+1.05VS MANHA@ M9X@ MANHA@ M9X@ MANHA@ M9X@ MANHA@ M9X@
+1.8VS

a.
+1.0VS
Function PCH GPU
State +0.75VS
description (H5) (H7) (P5) (PX5) (M1) (925)

si
explain HM55 HM57 PM55 Park LP Park XT Madison LP M92 XTX

BTO HM55R3@ HM57R3@ PARKLP@ PARKXT@ MADISONLP@ M92XTXR3@

S0
O O O O O

ne
Function LAN HDMI Bluetooth MODEM

2 S1 (E) (C) (Y) (Q) (B) (R) 2

O O O O O description
explain 10/100M Giga HDMI Non-HDMI Bluetooth MDC

do
S3
O O O O X
BTO 8105E@ 8111E@ HDMI@ BT@ MDC@
S5 S4/AC
O O O X X
Function VRAM DC JACK

in
S5 S4/ Battery only
O O X X X
description
S5 S4/AC & Battery
don't exist
O X X X X explain 512M 1G DC JACK

i-
BTO 4PCS@ 8PCS@ 45@

EC SM Bus1 address EC SM Bus2 address

Power Device Address Power Device Address
is
3 3

+3VALW EC KB926 D3 +3VS EC KB926 D3

+3VALW Smart Battery 0001 011x b +3VS VGA THM Sensor 1001 110x b
ADM1032ARMZ
kn

+3VS PCH 0100 110x b

SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5#
PCH SM Bus address
te

Full ON HIGH HIGH HIGH

Power Device Address
+3VALW PCH S1(Power On Suspend) HIGH HIGH HIGH
+3VS Clock Generator 1101 001x b
w.

S3 (Suspend to RAM) LOW HIGH HIGH

+3VS DDR DIMM0 1001 000x b
+3VS DDR DIMM1 1001 010x b S4 (Suspend to Disk) LOW LOW HIGH
+3VS WLAN
S5 (Soft OFF) LOW LOW LOW
ww

4 4

G3 LOW LOW LOW

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 4 of 58
A B C D E
 5 4 3 2 1

For S3 Reduce
JCPUB NPS@
1 2 H_COMP3 AT23 2 1
R1 20_0402_1% COMP3 R19 0_0402_5%
BCLK A16 CLK_CPU_BCLK 30

MISC
1 2 H_COMP2 AT24 B16 CLK_CPU_BCLK# 30
R2 20_0402_1% COMP2 BCLK#

CLOCKS
1 2 H_COMP1 G16 AR30 CLK_CPU_XDP_R 1 2 CLK_CPU_XDP
COMP1 BCLK_ITP

D
R4 49.9_0402_1% AT30 CLK_CPU_XDP#_R 1 R41 @ 2 0_0402_5% CLK_CPU_XDP# SM_DRAMRST#_CPU 3 1
BCLK_ITP# SM_DRAMRST# 11,12
1 2 H_COMP0 AT26 R42 @ 0_0402_5% PS@
COMP0

1
R3 49.9_0402_1% E16 CLK_PEG 26 Q41
PEG_CLK

m
PS@ BSS138_NL_SOT23-3

G
D16 CLK_PEG# 26

2
D TP_SKTOCC# PEG_CLK# R123 D
PAD T41 AH24 SKTOCC#
A18 100K_0402_5% RST_GATE 11,30
DPLL_REF_SSCLK
A17 Unused by Clarksfield rPGA989

2
DPLL_REF_SSCLK#

1
co
+VTT 1 2 CATERR# AK14 PS@
CATERR#

THERMAL
For prevent noise issue R18 49.9_0402_1% C8
0.047U_0402_16V7K

2
F6 SM_DRAMRST#_CPU
PECI SM_DRAMRST#
1 2 30 PECI AT15 PECI
@ C414 100P_0402_50V8J
SM_RCOMP[0] AL1 SM_RCOMP_0 R6 1 2 100_0402_1% DDR3 Compensation Signals
SM_RCOMP[1] AM1 SM_RCOMP_1 R7 1 2 24.9_0402_1% Layout Note:Please these
SM_RCOMP[2] AN1 SM_RCOMP_2 R8 1 2 130_0402_1% resistors near Processor
+VTT 1 2 H_PROCHOT#_D AN26

a.
R9 68_0402_5% PROCHOT#
AN15 PM_EXTTS#0

DDR3
MISC
PM_EXT_TS#[0] +VTT
PM_EXT_TS#[1] AP15 PM_EXTTS#_R 2 1 PM_EXTTS# 11,12
R12 0_0402_5%
30 H_THERMTRIP# AK15 THERMTRIP# PM_EXTTS#0 R15 2 1 10K_0402_5%

+VTT 2 1 AT28 XDP_PRDY# PM_EXTTS#_R R13 2 1 10K_0402_5%

@ R10 68_0402_5% PRDY# XDP_PREQ#
PREQ# AP27

si
AN28 XDP_TCK
XDP_RST#_R H_CPURST# TCK XDP_TMS
1 2 AP26 RESET_OBS# TMS AP28

PWR MANAGEMENT
R36 1K_0402_5% AT27 XDP_TRST# Routed as a single daisy chain XDP_TDI_R 1 2 XDP_TDI
TRST#

JTAG & BPM

R20 0_0402_5%
AL15 AT29 XDP_TDI_R
27 PMSYNCH PM_SYNC TDI
AR27 XDP_TDO_R XDP_TDO_M 1 @ 2 XDP_TDO
TDO XDP_TDI_M R21 0_0402_5%
TDI_M AR29 2 1 +3VS

1
2 1 H_PWRGOOD1_R AN14 VCCPWRGOOD_1 TDO_M AP29 XDP_TDO_M R312 1K_0402_5%

ne
R25 0_0402_5% R23
AN25 0_0402_5%
DBR# XDP_DBRESET# 27
H_PWRGOOD AN27
30 H_PWRGOOD VCCPWRGOOD_0
C C

2
Close to JCPU AJ22 XDP_BPM#0 XDP_TDI_M 1 @ 2
DRAMPWROK BPM#[0] XDP_BPM#1 R26 0_0402_5%
27 DRAMPWROK AK13 SM_DRAMPWROK BPM#[1] AK22
AK24 XDP_BPM#2
DRAMPWROK BPM#[2] XDP_BPM#3 XDP_TDO_R
1 2 BPM#[3] AJ24 1 2
C384 1000P_0402_50V7K VTTPWROK_CPU R27 0_0402_5%

do
49 VTTPWROK_CPU AM15 VTTPWRGOOD BPM#[4] AJ25
VTTPWROK_CPU 1 2 AH22 XDP_PRDY# 1 2
C382 1000P_0402_50V7K BPM#[5] @ C132 0.1U_0402_10V6K
BPM#[6] AK23
TAPPWRGD AM26 AH23 XDP_PREQ# 1 2
TAPPWRGOOD BPM#[7] @ C93 0.1U_0402_10V6K JTAG MAPPING
XDP_TCK 1 2
AL14 @ C95 0.1U_0402_10V6K
29 BUF_PLT_RST# RSTIN#
R30 1.5K_0402_1% XDP_TMS 1 2 Scan Chain STUFF -> R20, R23, R27
@ C96 0.1U_0402_10V6K (Default) NO STUFF -> R21, R26

in
R31 XDP_TRST# 1 2
750_0402_1% IC,AUB_CFD_rPGA,R0P9 @ C130 0.1U_0402_10V6K
@ XDP_TDI 1 2 CPU Only STUFF -> R20, R21
@ C97 0.1U_0402_10V6K NO STUFF -> R23, R26, R27
XDP_TDO 1 2
@ C131 0.1U_0402_10V6K
XDP_DBRESET# 1 2 GMCH Only STUFF -> R26, R27
@ C149 0.1U_0402_10V6K NO STUFF -> R20, R21, R23

i-
EMI reverse, close to JCPU

B
is B

XDP Connector
SFF-24Pin
kn

JXDP
For S3 Reduce XDP_PREQ# 1 1
XDP_PRDY# 2 2
3 3
+3VALW XDP_BPM#0 4
XDP_BPM#1 4
5 5
6 6
1 XDP_BPM#2 7
+1.5V_CPU 7
te

PS@ XDP_BPM#3 8
C80 @ R32 1K_0402_5% 8
9 9
0.1U_0402_16V7K H_PWRGOOD 1 2 H_PWRGOOD_R 10 10
2

2 NPS@ TAPPWRGD TAPPWRGD_R

1 2 11 11
R28 @ R35 0_0402_5% CLK_CPU_XDP 12
PS@ 1.1K_0402_1% CLK_CPU_XDP# 12
13 13
5

U10 +VTT 14
VTTPWROK XDP_RST#_R 14
44,49 VTTPWROK 1 15
P

IN1 PS@ DRAMPWROK XDP_DBRESET# 15

4 16
w.

O R33 1.5K_0402_1% 16
2 IN2 17 17
G

NPS@ PS@ 2 1 XDP_TDO 18

SN74AHC1G08DCKR_SC70-5 R29 R29 51_0402_5% R14 XDP_TRST# 18
19
3

19

1
3K_0402_1% 750_0402_1% 1 XDP_TDI 20
@ XDP_TMS 20
21 21
C1 R11 22
1

0.1U_0402_16V7K 51_0402_5% 22
2 1 23 23 GND 25
@ R52 0_0402_5% 2 XDP_TCK 24 26

2
24 GND
ww

A A
@ MOLEX_52435-2472

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 5 of 58
5 4 3 2 1
 5 4 3 2 1

FAN Control Circuit

+5VS
JFAN
1A
+FAN1 1 1
2 2 2

m
3 3
D C3 2 D
10U_0805_10V4Z 4
U1 1 C4 GND
5 GND

co
1 EN GND 8 1000P_0402_50V7K
1 @ @ ACES_85204-0300N
2 VIN GND 7
+FAN1 3 6
VOUT GND
41 EN_DFAN1 4 VSET GND 5
1 R34 10K_0402_5%
10mil G996P11U_SO8 2 1 +3VS
C5
10U_0805_10V4Z

a.
2 FAN_SPEED1 41
2
C6
JCPUA 0.01U_0402_25V7K
PEG_COMP 1 1
PEG_ICOMPI B26 2 @
A26 R38 49.9_0402_1%
PEG_ICOMPO
27 DMI_PTX_CRX_N0 A24 DMI_RX#[0] PEG_RCOMPO B27

si
C23 A25 PEG_RBIAS 1 2
27 DMI_PTX_CRX_N1 DMI_RX#[1] PEG_RBIAS
B22 R39 750_0402_1%
27 DMI_PTX_CRX_N2 DMI_RX#[2] PCIE_GTX_C_CRX_N[0..15] 13
A21 K35 PCIE_GTX_C_CRX_N0
27 DMI_PTX_CRX_N3 DMI_RX#[3] PEG_RX#[0]
J34 PCIE_GTX_C_CRX_N1
PEG_RX#[1] PCIE_GTX_C_CRX_N2
27 DMI_PTX_CRX_P0 B24 DMI_RX[0] PEG_RX#[2] J33
D23 G35 PCIE_GTX_C_CRX_N3
27 DMI_PTX_CRX_P1 DMI_RX[1] PEG_RX#[3]
27 DMI_PTX_CRX_P2 B23
A22
DMI_RX[2] DMI PEG_RX#[4] G32
F34
PCIE_GTX_C_CRX_N4
PCIE_GTX_C_CRX_N5

ne
27 DMI_PTX_CRX_P3 DMI_RX[3] PEG_RX#[5]
F31 PCIE_GTX_C_CRX_N6
PEG_RX#[6] PCIE_GTX_C_CRX_N7
27 DMI_CTX_PRX_N0 D24 DMI_TX#[0] PEG_RX#[7] D35
G24 E33 PCIE_GTX_C_CRX_N8
27 DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8]
C F23 C33 PCIE_GTX_C_CRX_N9 C
27 DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9]
H23 D32 PCIE_GTX_C_CRX_N10
27 DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10]
B32 PCIE_GTX_C_CRX_N11
PEG_RX#[11] PCIE_GTX_C_CRX_N12
27 DMI_CTX_PRX_P0 D25 DMI_TX[0] PEG_RX#[12] C31

do
F24 B28 PCIE_GTX_C_CRX_N13
27 DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13]
E23 B30 PCIE_GTX_C_CRX_N14
27 DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14]
G23 A31 PCIE_GTX_C_CRX_N15
27 DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]
PCIE_GTX_C_CRX_P[0..15] 13
J35 PCIE_GTX_C_CRX_P0
PEG_RX[0] PCIE_GTX_C_CRX_P1
PEG_RX[1] H34
H33 PCIE_GTX_C_CRX_P2
PEG_RX[2] PCIE_GTX_C_CRX_P3
E22 F35

in
FDI_TX#[0] PEG_RX[3] PCIE_GTX_C_CRX_P4
D21 FDI_TX#[1] PEG_RX[4] G33
D19 E34 PCIE_GTX_C_CRX_P5
FDI_TX#[2] PEG_RX[5] PCIE_GTX_C_CRX_P6
D18 FDI_TX#[3] PEG_RX[6] F32
G21 D34 PCIE_GTX_C_CRX_P7
FDI_TX#[4] PEG_RX[7]
PCI EXPRESS -- GRAPHICS

E19 F33 PCIE_GTX_C_CRX_P8

FDI_TX#[5] PEG_RX[8] PCIE_GTX_C_CRX_P9
F21 FDI_TX#[6] PEG_RX[9] B33
Intel(R) FDI

G18 D31 PCIE_GTX_C_CRX_P10

FDI_TX#[7] PEG_RX[10] PCIE_GTX_C_CRX_P11

i-
PEG_RX[11] A32
C30 PCIE_GTX_C_CRX_P12
PEG_RX[12] PCIE_GTX_C_CRX_P13
D22 FDI_TX[0] PEG_RX[13] A28
C21 B29 PCIE_GTX_C_CRX_P14
FDI_TX[1] PEG_RX[14] PCIE_GTX_C_CRX_P15
D20 FDI_TX[2] PEG_RX[15] A30
C18 FDI_TX[3] PCIE_CTX_C_GRX_N[0..15] 13
G22 L33 PCIE_CTX_GRX_N0 C39 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N0
FDI_TX[4] PEG_TX#[0] PCIE_CTX_GRX_N1 C40 0.1U_0402_16V7K PCIE_CTX_C_GRX_N1
E20 FDI_TX[5] PEG_TX#[1] M35 1 2
F20
G19
FDI_TX[6] PEG_TX#[2] M33
M30
is
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_N3
C41
C42
1
1
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_CTX_C_GRX_N2
PCIE_CTX_C_GRX_N3
B FDI_TX[7] PEG_TX#[3] PCIE_CTX_GRX_N4 C43 0.1U_0402_16V7K PCIE_CTX_C_GRX_N4 B
PEG_TX#[4] L31 1 2
2 1 F17 K32 PCIE_CTX_GRX_N5 C44 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N5
R686 1K_0402_5% FDI_FSYNC[0] PEG_TX#[5] PCIE_CTX_GRX_N6 C45 0.1U_0402_16V7K PCIE_CTX_C_GRX_N6
E17 FDI_FSYNC[1] PEG_TX#[6] M29 1 2
J31 PCIE_CTX_GRX_N7 C46 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N7
PEG_TX#[7] PCIE_CTX_GRX_N8 C47 0.1U_0402_16V7K PCIE_CTX_C_GRX_N8
2 1 C17 FDI_INT PEG_TX#[8] K29 1 2
R688 1K_0402_5% H30 PCIE_CTX_GRX_N9 C48 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N9
kn

PEG_TX#[9] PCIE_CTX_GRX_N10 C49 0.1U_0402_16V7K PCIE_CTX_C_GRX_N10

F18 FDI_LSYNC[0] PEG_TX#[10] H29 1 2
D17 F29 PCIE_CTX_GRX_N11 C50 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N11
FDI_LSYNC[1] PEG_TX#[11] PCIE_CTX_GRX_N12 C51 0.1U_0402_16V7K PCIE_CTX_C_GRX_N12
PEG_TX#[12] E28 1 2
D29 PCIE_CTX_GRX_N13 C52 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N13
PEG_TX#[13] PCIE_CTX_GRX_N14 C53 0.1U_0402_16V7K PCIE_CTX_C_GRX_N14
PEG_TX#[14] D27 1 2
C26 PCIE_CTX_GRX_N15 C54 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N15
PEG_TX#[15]
PCIE_CTX_C_GRX_P[0..15] 13
te

L34 PCIE_CTX_GRX_P0 C55 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P0

PEG_TX[0] PCIE_CTX_GRX_P1 C56 0.1U_0402_16V7K PCIE_CTX_C_GRX_P1
PEG_TX[1] M34 1 2
M32 PCIE_CTX_GRX_P2 C57 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P2
PEG_TX[2] PCIE_CTX_GRX_P3 C58 0.1U_0402_16V7K PCIE_CTX_C_GRX_P3
PEG_TX[3] L30 1 2
M31 PCIE_CTX_GRX_P4 C59 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P4
PEG_TX[4] PCIE_CTX_GRX_P5 C60 0.1U_0402_16V7K PCIE_CTX_C_GRX_P5
PEG_TX[5] K31 1 2
M28 PCIE_CTX_GRX_P6 C61 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P6
PEG_TX[6] PCIE_CTX_GRX_P7 C62 0.1U_0402_16V7K PCIE_CTX_C_GRX_P7
H31 1 2
w.

PEG_TX[7] PCIE_CTX_GRX_P8 C63 0.1U_0402_16V7K PCIE_CTX_C_GRX_P8

PEG_TX[8] K28 1 2
G30 PCIE_CTX_GRX_P9 C64 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P9
PEG_TX[9] PCIE_CTX_GRX_P10 C65 0.1U_0402_16V7K PCIE_CTX_C_GRX_P10
PEG_TX[10] G29 1 2
F28 PCIE_CTX_GRX_P11 C66 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P11
PEG_TX[11] PCIE_CTX_GRX_P12 C67 0.1U_0402_16V7K PCIE_CTX_C_GRX_P12
PEG_TX[12] E27 1 2
D28 PCIE_CTX_GRX_P13 C68 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P13
PEG_TX[13] PCIE_CTX_GRX_P14 C69 0.1U_0402_16V7K PCIE_CTX_C_GRX_P14
PEG_TX[14] C27 1 2
ww

C25 PCIE_CTX_GRX_P15 C70 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P15

A PEG_TX[15] A

IC,AUB_CFD_rPGA,R0P9
@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 6 of 58
5 4 3 2 1
 5 4 3 2 1

JCPUC JCPUD

11 DDR_A_D[0..63] 12 DDR_B_D[0..63]

SA_CK[0] AA6 DDRA_CLK0 11 SB_CK[0] W8 DDRB_CLK0 12

SA_CK#[0] AA7 DDRA_CLK0# 11 SB_CK#[0] W9 DDRB_CLK0# 12
P7 DDR_B_D0 B5 M3
SA_CKE[0] DDRA_CKE0 11 SB_DQ[0] SB_CKE[0] DDRB_CKE0 12
DDR_A_D0 A10 DDR_B_D1 A5
SA_DQ[0] SB_DQ[1]

m
DDR_A_D1 C10 DDR_B_D2 C3
DDR_A_D2 SA_DQ[1] DDR_B_D3 SB_DQ[2]
D C7 SA_DQ[2] B3 SB_DQ[3] SB_CK[1] V7 DDRB_CLK1 12 D
DDR_A_D3 A7 Y6 DDR_B_D4 E4 V6
SA_DQ[3] SA_CK[1] DDRA_CLK1 11 SB_DQ[4] SB_CK#[1] DDRB_CLK1# 12
DDR_A_D4 B10 Y5 DDR_B_D5 A6 M2
SA_DQ[4] SA_CK#[1] DDRA_CLK1# 11 SB_DQ[5] SB_CKE[1] DDRB_CKE1 12

co
DDR_A_D5 D10 P6 DDR_B_D6 A4
SA_DQ[5] SA_CKE[1] DDRA_CKE1 11 SB_DQ[6]
DDR_A_D6 E10 DDR_B_D7 C4
DDR_A_D7 SA_DQ[6] DDR_B_D8 SB_DQ[7]
A8 SA_DQ[7] D1 SB_DQ[8]
DDR_A_D8 D8 DDR_B_D9 D2
DDR_A_D9 SA_DQ[8] DDR_B_D10 SB_DQ[9]
F10 SA_DQ[9] SA_CS#[0] AE2 DDRA_SCS0# 11 F2 SB_DQ[10] SB_CS#[0] AB8 DDRB_SCS0# 12
DDR_A_D10 E6 AE8 DDR_B_D11 F1 AD6
SA_DQ[10] SA_CS#[1] DDRA_SCS1# 11 SB_DQ[11] SB_CS#[1] DDRB_SCS1# 12
DDR_A_D11 F7 DDR_B_D12 C2
DDR_A_D12 SA_DQ[11] DDR_B_D13 SB_DQ[12]
E9 F5

a.
DDR_A_D13 SA_DQ[12] DDR_B_D14 SB_DQ[13]
B7 SA_DQ[13] F3 SB_DQ[14]
DDR_A_D14 E7 AD8 DDR_B_D15 G4 AC7
SA_DQ[14] SA_ODT[0] DDRA_ODT0 11 SB_DQ[15] SB_ODT[0] DDRB_ODT0 12
DDR_A_D15 C6 AF9 DDR_B_D16 H6 AD1
SA_DQ[15] SA_ODT[1] DDRA_ODT1 11 SB_DQ[16] SB_ODT[1] DDRB_ODT1 12
DDR_A_D16 H10 DDR_B_D17 G2
DDR_A_D17 SA_DQ[16] DDR_B_D18 SB_DQ[17]
G8 SA_DQ[17] J6 SB_DQ[18]
DDR_A_D18 K7 Unused by Clarksfield rPGA989 DDR_B_D19 J3
DDR_A_D19 SA_DQ[18] DDR_B_D20 SB_DQ[19]
J8 SA_DQ[19] G1 SB_DQ[20] DDR_B_DM[0..7] 12

si
DDR_A_D20 G7 DDR_B_D21 G5 D4 DDR_B_DM0
SA_DQ[20] DDR_A_DM[0..7] 11 SB_DQ[21] SB_DM[0]
DDR_A_D21 G10 DDR_B_D22 J2 E1 DDR_B_DM1
DDR_A_D22 SA_DQ[21] DDR_A_DM0 DDR_B_D23 SB_DQ[22] SB_DM[1] DDR_B_DM2
J7 SA_DQ[22] SA_DM[0] B9 J1 SB_DQ[23] SB_DM[2] H3
DDR_A_D23 J10 D7 DDR_A_DM1 DDR_B_D24 J5 K1 DDR_B_DM3
DDR_A_D24 SA_DQ[23] SA_DM[1] DDR_A_DM2 DDR_B_D25 SB_DQ[24] SB_DM[3] DDR_B_DM4
L7 SA_DQ[24] SA_DM[2] H7 K2 SB_DQ[25] SB_DM[4] AH1
DDR_A_D25 M6 M7 DDR_A_DM3 DDR_B_D26 L3 AL2 DDR_B_DM5
DDR_A_D26 SA_DQ[25] SA_DM[3] DDR_A_DM4 DDR_B_D27 SB_DQ[26] SB_DM[5] DDR_B_DM6
M8 SA_DQ[26] SA_DM[4] AG6 M1 SB_DQ[27] SB_DM[6] AR4
DDR_A_D27 L9 AM7 DDR_A_DM5 DDR_B_D28 K5 AT8 DDR_B_DM7

ne
DDR_A_D28 SA_DQ[27] SA_DM[5] DDR_A_DM6 DDR_B_D29 SB_DQ[28] SB_DM[7]
L6 SA_DQ[28] SA_DM[6] AN10 K4 SB_DQ[29]
DDR_A_D29 K8 AN13 DDR_A_DM7 DDR_B_D30 M4 Unused by Clarksfield rPGA989
DDR_A_D30 SA_DQ[29] SA_DM[7] DDR_B_D31 SB_DQ[30]
N8 SA_DQ[30] N5 SB_DQ[31]
C DDR_A_D31 P9 DDR_B_D32 AF3 C
DDR_A_D32 SA_DQ[31] DDR_B_D33 SB_DQ[32]
AH5 SA_DQ[32] AG1 SB_DQ[33] DDR_B_DQS#[0..7] 12
DDR_A_D33 AF5 DDR_B_D34 AJ3 D5 DDR_B_DQS#0
SA_DQ[33] DDR_A_DQS#[0..7] 11 SB_DQ[34] SB_DQS#[0]
DDR_A_D34 AK6 C9 DDR_A_DQS#0 DDR_B_D35 AK1 F4 DDR_B_DQS#1
DDR SYSTEM MEMORY A
SA_DQ[34] SA_DQS#[0] SB_DQ[35] SB_DQS#[1]

do
DDR_A_D35 AK7 F8 DDR_A_DQS#1 DDR_B_D36 AG4 J4 DDR_B_DQS#2
DDR_A_D36 SA_DQ[35] SA_DQS#[1] DDR_A_DQS#2 DDR_B_D37 SB_DQ[36] SB_DQS#[2] DDR_B_DQS#3
AF6 SA_DQ[36] SA_DQS#[2] J9 AG3 SB_DQ[37] SB_DQS#[3] L4
DDR_A_D37 AG5 N9 DDR_A_DQS#3 DDR_B_D38 AJ4 AH2 DDR_B_DQS#4

DDR SYSTEM MEMORY - B

DDR_A_D38 SA_DQ[37] SA_DQS#[3] SB_DQ[38] SB_DQS#[4]
AJ7 SA_DQ[38] SA_DQS#[4] AH7 DDR_A_DQS#4 DDR_B_D39 AH4 SB_DQ[39] SB_DQS#[5] AL4 DDR_B_DQS#5
DDR_A_D39 AJ6 AK9 DDR_A_DQS#5 DDR_B_D40 AK3 AR5 DDR_B_DQS#6
DDR_A_D40 SA_DQ[39] SA_DQS#[5] SB_DQ[40] SB_DQS#[6]
AJ10 SA_DQ[40] SA_DQS#[6] AP11 DDR_A_DQS#6 DDR_B_D41 AK4 SB_DQ[41] SB_DQS#[7] AR8 DDR_B_DQS#7
DDR_A_D41 AJ9 AT13 DDR_A_DQS#7 DDR_B_D42 AM6
DDR_A_D42 SA_DQ[41] SA_DQS#[7] DDR_B_D43 SB_DQ[42]
AL10 AN2

in
DDR_A_D43 SA_DQ[42] DDR_B_D44 SB_DQ[43]
AK12 SA_DQ[43] AK5 SB_DQ[44]
DDR_A_D44 AK8 DDR_B_D45 AK2
DDR_A_D45 SA_DQ[44] DDR_B_D46 SB_DQ[45]
AL7 SA_DQ[45] DDR_A_DQS[0..7] 11 AM4 SB_DQ[46]
DDR_A_D46 AK11 C8 DDR_A_DQS0 DDR_B_D47 AM3
SA_DQ[46] SA_DQS[0] SB_DQ[47] DDR_B_DQS[0..7] 12
DDR_A_D47 AL8 F9 DDR_A_DQS1 DDR_B_D48 AP3 C5 DDR_B_DQS0
DDR_A_D48 SA_DQ[47] SA_DQS[1] DDR_A_DQS2 DDR_B_D49 SB_DQ[48] SB_DQS[0] DDR_B_DQS1
AN8 SA_DQ[48] SA_DQS[2] H9 AN5 SB_DQ[49] SB_DQS[1] E3
DDR_A_D49 AM10 M9 DDR_A_DQS3 DDR_B_D50 AT4 H4 DDR_B_DQS2
DDR_A_D50 SA_DQ[49] SA_DQS[3] DDR_A_DQS4 DDR_B_D51 SB_DQ[50] SB_DQS[2] DDR_B_DQS3

i-
AR11 SA_DQ[50] SA_DQS[4] AH8 AN6 SB_DQ[51] SB_DQS[3] M5
DDR_A_D51 AL11 AK10 DDR_A_DQS5 DDR_B_D52 AN4 AG2 DDR_B_DQS4
DDR_A_D52 SA_DQ[51] SA_DQS[5] DDR_A_DQS6 DDR_B_D53 SB_DQ[52] SB_DQS[4] DDR_B_DQS5
AM9 SA_DQ[52] SA_DQS[6] AN11 AN3 SB_DQ[53] SB_DQS[5] AL5
DDR_A_D53 AN9 AR13 DDR_A_DQS7 DDR_B_D54 AT5 AP5 DDR_B_DQS6
DDR_A_D54 SA_DQ[53] SA_DQS[7] DDR_B_D55 SB_DQ[54] SB_DQS[6] DDR_B_DQS7
AT11 SA_DQ[54] AT6 SB_DQ[55] SB_DQS[7] AR7
DDR_A_D55 AP12 DDR_B_D56 AN7
DDR_A_D56 SA_DQ[55] DDR_B_D57 SB_DQ[56]
AM12 SA_DQ[56] DDR_A_MA[0..15] 11 AP6 SB_DQ[57]
DDR_A_D57 AN12 DDR_B_D58 AP8
SA_DQ[57] SB_DQ[58]
DDR_A_D58
DDR_A_D59
AM13
AT14
SA_DQ[58] SA_MA[0] Y3
W1
is
DDR_A_MA0
DDR_A_MA1
DDR_B_D59
DDR_B_D60
AT9
AT7
SB_DQ[59]
B DDR_A_D60 SA_DQ[59] SA_MA[1] DDR_A_MA2 DDR_B_D61 SB_DQ[60] B
AT12 SA_DQ[60] SA_MA[2] AA8 AP9 SB_DQ[61]
DDR_A_D61 AL13 AA3 DDR_A_MA3 DDR_B_D62 AR10
SA_DQ[61] SA_MA[3] SB_DQ[62] DDR_B_MA[0..15] 12
DDR_A_D62 AR14 V1 DDR_A_MA4 DDR_B_D63 AT10 U5 DDR_B_MA0
DDR_A_D63 SA_DQ[62] SA_MA[4] DDR_A_MA5 SB_DQ[63] SB_MA[0] DDR_B_MA1
AP14 SA_DQ[63] SA_MA[5] AA9 SB_MA[1] V2
V8 DDR_A_MA6 T5 DDR_B_MA2
SA_MA[6] DDR_A_MA7 SB_MA[2] DDR_B_MA3
T1 V3
kn

SA_MA[7] DDR_A_MA8 SB_MA[3] DDR_B_MA4

SA_MA[8] Y9 SB_MA[4] R1
AC3 U6 DDR_A_MA9 AB1 T8 DDR_B_MA5
11 DDR_A_BS0 SA_BS[0] SA_MA[9] 12 DDR_B_BS0 SB_BS[0] SB_MA[5]
AB2 AD4 DDR_A_MA10 W5 R2 DDR_B_MA6
11 DDR_A_BS1 SA_BS[1] SA_MA[10] 12 DDR_B_BS1 SB_BS[1] SB_MA[6]
U7 T2 DDR_A_MA11 R7 R6 DDR_B_MA7
11 DDR_A_BS2 SA_BS[2] SA_MA[11] 12 DDR_B_BS2 SB_BS[2] SB_MA[7]
U3 DDR_A_MA12 R4 DDR_B_MA8
SA_MA[12] DDR_A_MA13 SB_MA[8] DDR_B_MA9
SA_MA[13] AG8 SB_MA[9] R5
T3 DDR_A_MA14 AC5 AB5 DDR_B_MA10
SA_MA[14] 12 DDR_B_CAS# SB_CAS# SB_MA[10]
te

AE1 V9 DDR_A_MA15 Y7 P3 DDR_B_MA11

11 DDR_A_CAS# SA_CAS# SA_MA[15] 12 DDR_B_RAS# SB_RAS# SB_MA[11]
AB3 AC6 R3 DDR_B_MA12
11 DDR_A_RAS# SA_RAS# 12 DDR_B_WE# SB_WE# SB_MA[12]
AE9 AF7 DDR_B_MA13
11 DDR_A_WE# SA_WE# SB_MA[13]
P5 DDR_B_MA14
SB_MA[14] DDR_B_MA15
SB_MA[15] N1
w.

IC,AUB_CFD_rPGA,R0P9
@
ww

A A
IC,AUB_CFD_rPGA,R0P9
@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 7 of 58
5 4 3 2 1
 5 4 3 2 1

Material Note (+VTT):

JCPUF 330uF/ 6mohm, number are 3,
power x1, HW x2

+CPU_CORE Clarksfield: 65A Clarksfield: 21A (Place these capacitors under CPU socket Edge, top layer) (Place these capacitors between inductor and socket on Bottom)
+VTT
Auburndale:48A Auburndale:18A +CPU_CORE
AG35 AH14

m
VCC1 VTT0_1 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K
AG34 VCC2 VTT0_2 AH12
D D
AG33 VCC3 VTT0_3 AH11
AG32 VCC4 VTT0_4 AH10 1 1 1 1 1 1 1 1 1
C144 1 2 330U_2.5V_M_R15 C81 1 2 10U_0805_10V4K

+
AG31 VCC5 VTT0_5 J14

co
AG30 VCC6 VTT0_6 J13
AG29 H14 C159 1 2 390U_2.5V_M_R10 C83 1 2 10U_0805_10V4K C71 C72 C73 C74 C75 C76 C77 C78 C79
VCC7 VTT0_7 2 2 2 2 2 2 2 2 2
AG28 H12

+
VCC8 VTT0_8 C85 1
AG27 VCC9 VTT0_9 G14 2 10U_0805_10V4K
AG26 G13 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K
VCC10 VTT0_10 C89 1
AF35 VCC11 VTT0_11 G12 2 10U_0805_10V4K
AF34 VCC12 VTT0_12 G11
AF33 F14 C87 1 2 22U_0805_6.3V6M C88 1 2 10U_0805_10V4K
VCC13 VTT0_13

a.
AF32 VCC14 VTT0_14 F13
AF31 F12 C91 1 2 22U_0805_6.3V6M C90 1 2 10U_0805_10V4K
VCC15 VTT0_15
AF30 VCC16 VTT0_16 F11 (Place these capacitors under CPU socket, top layer)
AF29 E14 C92 1 2 10U_0805_10V4K
VCC17 VTT0_17
AF28 VCC18 VTT0_18 E12
AF27 D14 @C94
@ C94 1 2 10U_0805_10V4K +CPU_CORE
VCC19 VTT0_19
AF26 VCC20 VTT0_20 D13

1.1V RAIL POWER

AD35 D12 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K
VCC21 VTT0_21
AD34 D11

si
VCC22 VTT0_22
AD33 VCC23 VTT0_23 C14 1 1 1 1 1 1 1
AD32 VCC24 VTT0_24 C13
AD31 VCC25 VTT0_25 C12
AD30 C11 C98 C99 C100 C101 C102 C103 C104
VCC26 VTT0_26 2 2 2 2 2 2 2
AD29 VCC27 VTT0_27 B14
AD28 VCC28 VTT0_28 B12
AD27 A14 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K
VCC29 VTT0_29
AD26 VCC30 VTT0_30 A13

ne
AC35 VCC31 VTT0_31 A12
AC34 VCC32 VTT0_32 A11
AC33 VCC33
C
AC32 VCC34 (Place these capacitors on CPU cavity, Bottom Layer) C
AC31 VCC35 5/25: Add for power team request.
AC30 VCC36 VTT0_33 AF10
AC29 AE10 +CPU_CORE
VCC37 VTT0_34 +CPU_CORE
AC28 VCC38 VTT0_35 AC10
CPU CORE SUPPLY

AC27 AB10 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M

do
VCC39 VTT0_36 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
AC26 VCC40 VTT0_37 Y10
AA35 VCC41 VTT0_38 W10 1 1 1 1 1 1
AA34 U10 1 1 1 1 1 1 1 1 C105 C106 C107 C108 C109 C110
VCC42 VTT0_39 C150 C128 C127 C158 C118 C119 C117 C129
AA33 VCC43 VTT0_40 T10
AA32 VCC44 VTT0_41 J12
2 2 2 2 2 2
AA31 VCC45 VTT0_42 J11
2 2 2 2 2 2 2 2
AA30 VCC46 VTT0_43 J16
AA29 J15 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
VCC47 VTT0_44

in
AA28 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
VCC48
AA27 VCC49
AA26 VCC50
Y35 +CPU_CORE
VCC51
Y34 VCC52
Y33 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
VCC53
Y32 VCC54
Y31 VCC55 1 1 1 1 1 1
C111 C112 C113 C114 C115 C116

i-
Y30 VCC56
Y29 VCC57
Y28 VCC58 2 2 2 2 2 2
Y27 VCC59
Y26 VCC60 CRB default setting:
V35 AN33 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
VCC61 PSI# H_PSI# 53
V34 VID[6:0]=[0100111]
POWER

VCC62
V33 VCC63
V32 AK35 CPU_VID0 53
V31
V30
VCC64
VCC65
VCC66
VID[0]
VID[1]
VID[2]
AK33
AK34
is
CPU_VID1 53
CPU_VID2 53
B B
V29 VCC67 VID[3] AL35 CPU_VID3 53 VTT Rail
CPU VIDS

V28 VCC68 VID[4] AL33 CPU_VID4 53 TOP side (under inductor)

V27 VCC69 VID[5] AM33 CPU_VID5 53
V26 VCC70 VID[6] AM35 CPU_VID6 53 Auburndale +1.1VS_VTT=1.05V +CPU_CORE
U35 AM34 H_DPRSLPVR_R 1 2 H_DPRSLPVR 53
U34
VCC71 PROC_DPRSLPVR R62 0_0402_5% Clarksfield +1.1VS_VTT=1.1V
VCC72
kn

U33 330U_D2_2.5VY_R9M 330U_D2_2.5VY_R9M

VCC73
U32 VCC74 1 1 1 1
U31 VCC75 VTT_SELECT G15 H_VTTSELECT 49
U30 H_VTTSELECT = low, 1.1V C121 + C124 + C122 + C123 +
VCC76
U29 VCC77
U28 H_VTTSELECT = high, 1.05V 330U_D2_2.5VY_R9M 330U_D2_2.5VY_R9M
VCC78 2 2 2 2
U27 VCC79
U26 VCC80
R35
te

VCC81
R34 VCC82
R33 VCC83
R32 VCC84 ISENSE AN35 IMVP_IMON 53
R31 VCC85
R30 VCC86 1 2 +CPU_CORE
R29 R64 100_0402_1%
VCC87 VCCSENSE_R R65 VCCSENSE
2 0_0402_5%
SENSE LINES

R28 VCC88 VCC_SENSE AJ34 1 VCCSENSE 53

R27 AJ35 VSSSENSE_R R66 1 2 0_0402_5% VSSSENSE
VCC89 VSS_SENSE VSSSENSE 53 Check list:
w.

R26 VCC90
P35 VCC91 1 2
R67 100_0402_1%
P34
P33
VCC92 VTT_SENSE B15
A15
VTT_SENSE 49 +CPU_CORE: 4x 470uF, 12x 22uF, 16x 10uF
VCC93 VSS_SENSE_VTT VSS_SENSE_VTT 49
P32 VCC94 near CPU
P31
P30
VCC95 +VTT: 4x 330uF, 7x 22uF, 8x 10uF
VCC96
P29 VCC97
P28
ww

A VCC98 A
P27 VCC99
P26 VCC100

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title
IC,AUB_CFD_rPGA,R0P9
@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 8 of 58
5 4 3 2 1
 5 4 3 2 1

+1.5V_CPU PS@ +1.5V

Q33
1 S D 8
2 S D 7

2
PS@ 1 PS@ 3 6
R424 C179 S D
4 G D 5
470_0805_5%
10U_0805_10V4K FDS6676AS_SO8 PS@
2

m
1 R418 2 +VSB

3 1
D PS@ 220K_0402_5% D
Q46B PS@

6
2N7002KDW_SOT363-6 PS@ 1 PS@ Q46A

co
C472 R417 2N7002KDW_SOT363-6
SUSP 5 820K_0402_5%
0.1U_0402_25V6 2 SUSP
2 SUSP 44,52

1
JCPUG

AT21

a.
VAXG1
AT19 VAXG2 VAXG_SENSE AR22

SENSE
LINES
AT18 VAXG3 VSSAXG_SENSE AT22
AT16 VAXG4
2

AR21 VAXG5
R86 AR19 VAXG6
0_0402_5% AR18 VAXG7
AR16 VAXG8 GFX_VID[0] AM22

si
AP21 AP22
1

VAXG9 GFX_VID[1]

GRAPHICS VIDs
AP19 AN22 C205 1 2 0.1U_0402_16V4Z
VAXG10 GFX_VID[2]
AP18 VAXG11 GFX_VID[3] AP23
AP16 AM23 C186 1 2 0.1U_0402_16V4Z
VAXG12 GFX_VID[4]
AN21 VAXG13 GFX_VID[5] AP24

GRAPHICS
AN19 AN24 C185 1 2 0.1U_0402_16V4Z
VAXG14 GFX_VID[6]
AN18 VAXG15
AN16 C180 1 2 0.1U_0402_16V4Z

ne
VAXG16
AM21 VAXG17 GFX_VR_EN AR25
AM19 VAXG18 GFX_DPRSLPVR AT25
AM18 AM24 R687 2 1 1K_0402_5%
C
VAXG19 GFX_IMON PJ30 @ C
AM16 VAXG20
AL21 VAXG21 2 2 1 1
AL19 VAXG22
AL18 +1.5V_CPU JUMP_43X79
VAXG23

do
AL16 PJ31 @
VAXG24 1U_0402_6.3V4Z 1U_0402_6.3V4Z 22U_0805_6.3V6M
AK21 VAXG25 VDDQ1 AJ1 2 2 1 1 +1.5V
AK19 VAXG26 VDDQ2 AF1 1
JUMP_43X79

- 1.5V RAILS
AK18 VAXG27 VDDQ3 AE7 1 1 1 1 1 1 1
+ C216
AK16 VAXG28 Clarksfield: 5A VDDQ4 AE4
C133 C134 C135 C136 C137 C138 C139 390U_2.5V_M_R10
AJ21 VAXG29 VDDQ5 AC1
AJ19 VAXG30 Auburndale:3A VDDQ6 AB7
2 2 2 2 2 2 2 2
AJ18 AB4

in
VAXG31 VDDQ7
AJ16 VAXG32 VDDQ8 Y1
AH21 VAXG33 VDDQ9 W7
POWER

AH19 W4 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 22U_0805_6.3V6M

VAXG34 VDDQ10
AH18 VAXG35 VDDQ11 U1
AH16 VAXG36 VDDQ12 T7
VDDQ13 T4
VDDQ14 P1
+VTT

i-
VDDQ15 N7
VDDQ16 N4
DDR3

VDDQ17 L1
J24 VTT1_45 VDDQ18 H1
FDI

J23 VTT1_46
H25 +VTT
1 1 VTT1_47
C141 C142
(Place these capacitors under CPU socket Edge, top layer)
22U_0805_6.3V6M
2 2
22U_0805_6.3V6M
VTT0_59
is
P10
N10 1
B VTT0_60 C143 B
VTT0_61 L10
VTT0_62 K10
Clarksfield: 21A 10U_0805_10V4K
2
+VTT
+VTT Auburndale:18A
kn
1.1V

VTT1_63 J22
K26 VTT1_48 VTT1_64 J20
J27 VTT1_49 VTT1_65 J18 1
PEG & DMI

1 1 J26 H21 C145

C146 C147 VTT1_50 VTT1_66
J25 VTT1_51 VTT1_67 H20
H27 H19 22U_0805_6.3V6M
22U_0805_6.3V6M 22U_0805_6.3V6M VTT1_52 VTT1_68 2
G28 VTT1_53
2 2
te

G27 VTT1_54 (Place these capacitors under CPU socket, top layer)
G26 VTT1_55
F26 +1.8VS
VTT1_56
E26 VTT1_57 VCCPLL1 L26
1.8V

E25 VTT1_58 VCCPLL2 L27

M26 +1.8VS_H_PLL 1U_0402_6.3V4Z 4.7U_0603_6.3V6K 2 1
VCCPLL3 R71 0_0805_5%
1 1 1 1
w.

(Place these capacitors under CPU socket, top layer) Clarksfield: 1.35A C151 C152 C153 C154 C155
Auburndale: 1.35A 1U_0402_6.3V4Z
2 2 2 2 22U_0805_6.3V6M

IC,AUB_CFD_rPGA,R0P9 2.2U_0603_6.3V4Z
@
ww

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 9 of 58
5 4 3 2 1
 5 4 3 2 1

JCPUI JCPUH JCPUE

AT20 VSS1 VSS81 AE34 RSVD32 AJ13

AT17 VSS2 VSS82 AE33 RSVD33 AJ12
K27 VSS161 AR31 VSS3 VSS83 AE32
K9 VSS162 AR28 VSS4 VSS84 AE31 AP25 RSVD1

m
K6 VSS163 AR26 VSS5 VSS85 AE30 AL25 RSVD2 RSVD34 AH25
D K3 VSS164 AR24 VSS6 VSS86 AE29 AL24 RSVD3 RSVD35 AK26 D
J32 VSS165 AR23 VSS7 VSS87 AE28 AL22 RSVD4
J30 VSS166 AR20 VSS8 VSS88 AE27 AJ33 RSVD5 RSVD36 AL26

co
J21 VSS167 AR17 VSS9 VSS89 AE26 AG9 RSVD6 RSVD_NCTF_37 AR2
J19 VSS168 AR15 VSS10 VSS90 AE6 M27 RSVD7
H35 VSS169 AR12 VSS11 VSS91 AD10 L28 RSVD8 RSVD38 AJ26
H32 VSS170 AR9 VSS12 VSS92 AC8 +VREF_DQA_M3 J17 RSVD9 (SA_DIMM_VREF) RSVD39 AJ27
H28 VSS171 AR6 VSS13 VSS93 AC4 +VREF_DQB_M3 H17 RSVD10(SB_DIMM_VREF)
H26 VSS172 AR3 VSS14 VSS94 AC2 G25 RSVD11
H24 VSS173 AP20 VSS15 VSS95 AB35 G17 RSVD12
H22 AP17 AB34 E31 AP1

a.
VSS174 VSS16 VSS96 RSVD13 RSVD_NCTF_40
H18 VSS175 AP13 VSS17 VSS97 AB33 E30 RSVD14 RSVD_NCTF_41 AT2
H15 VSS176 AP10 VSS18 VSS98 AB32
H13 VSS177 AP7 VSS19 VSS99 AB31 RSVD_NCTF_42 AT3
H11 VSS178 AP4 VSS20 VSS100 AB30 RSVD_NCTF_43 AR1
H8 VSS179 AP2 VSS21 VSS101 AB29 WW41 Recommend not pull down
H5 VSS180 AN34 VSS22 VSS102 AB28 PCIE2.0 Jitter is over on ES1
H2 VSS181 AN31 VSS23 VSS103 AB27

si
G34 VSS182 AN23 VSS24 VSS104 AB26 RSVD45 AL28
G31 AN20 AB6 3.01K_0402_1% 1 @ R74 2 CFG0 AM30 AL29
VSS183 VSS25 VSS105 CFG1 CFG[0] RSVD46
G20 VSS184 AN17 VSS26 VSS106 AA10 AM28 CFG[1] RSVD47 AP30
G9 AM29 Y8 CFG2 AP31 AP32
VSS185 VSS27 VSS107 3.01K_0402_1% 1 @ R75 CFG3 CFG[2] RSVD48
G6 VSS186 AM27 VSS28 VSS108 Y4 2 AL32 CFG[3] RSVD49 AL27
G3 AM25 Y2 3.01K_0402_1% 1 @ R76 2 CFG4 AL30 AT31
VSS187 VSS29 VSS109 CFG5 CFG[4] RSVD50
F30 VSS188 AM20 VSS30 VSS110 W35 AM31 CFG[5] RSVD51 AT32
F27 AM17 W34 CFG6 AN29 AP33

ne
VSS189 VSS31 VSS111 CFG7 CFG[6] RSVD52
F25 VSS190 AM14 VSS32 VSS112 W33 AM32 CFG[7] RSVD53 AR33
F22 AM11 W32 CFG8 AK32 AT33
VSS191 VSS33 VSS113 CFG9 CFG[8] RSVD_NCTF_54
F19 AM8 W31 AK31 AT34

RESERVED
C
VSS192 VSS34 VSS114 CFG10 CFG[9] RSVD_NCTF_55 C
F16 VSS193 AM5 VSS35 VSS115 W30 AK28 CFG[10] RSVD_NCTF_56 AP35
E35 AM2 W29 CFG11 AJ28 AR35
VSS194 VSS36 VSS116 CFG[11] RSVD_NCTF_57
E32 AL34 W28 AN30 AR32
E29
VSS195
VSS196 VSS AL31
VSS37
VSS38 VSS VSS117
VSS118 W27 CFG13 AN32
CFG[12]
CFG[13]
RSVD58

do
E24 AL23 W26 CFG14 AJ32
VSS197 VSS39 VSS119 CFG15 CFG[14]
E21 VSS198 AL20 VSS40 VSS120 W6 AJ29 CFG[15] RSVD_TP_59 E15
E18 AL17 V10 CFG16 AJ30 F15
VSS199 VSS41 VSS121 CFG17 CFG[16] RSVD_TP_60
E13 VSS200 AL12 VSS42 VSS122 U8 AK30 CFG[17] KEY A2
E11 AL9 U4 CFG18 H16 D15
VSS201 VSS43 VSS123 RSVD_TP_86 RSVD62
E8 VSS202 AL6 VSS44 VSS124 U2 RSVD63 C15
E5 AL3 T35 AJ15 RSVD64
E2
VSS203
AT35 H_NCTF1 PAD T4 AK29
VSS45 VSS125
T34
Reserve via for test RSVD64
AH15 RSVD65

in
VSS204 VSS_NCTF1 H_NCTF2 VSS46 VSS126 RSVD65
D33 VSS205 VSS_NCTF2 AT1 PAD T5 AK27 VSS47 VSS127 T33
D30 VSS206 VSS_NCTF3 AR34 AK25 VSS48 VSS128 T32 B19 RSVD15 Reserve via
D26 VSS207 VSS_NCTF4 B34 AK20 VSS49 VSS129 T31 A19 RSVD16
D9 B2 AK17 T30 for test
NCTF

VSS208 VSS_NCTF5 H_NCTF6 VSS50 VSS130 RSVD17

D6 VSS209 VSS_NCTF6 B1 PAD T6 AJ31 VSS51 VSS131 T29 PAD T43 A20 RSVD17
D3 A35 H_NCTF7 PAD T7 AJ23 T28 PAD T44 RSVD18 B20
VSS210 VSS_NCTF7 VSS52 VSS132 RSVD18
C34 VSS211 AJ20 VSS53 VSS133 T27 RSVD_TP_66 AA5

i-
C32 VSS212 AJ17 VSS54 VSS134 T26 U9 RSVD19 RSVD_TP_67 AA4
C29 VSS213 AJ14 VSS55 VSS135 T6 T9 RSVD20 RSVD_TP_68 R8
C28 VSS214 AJ11 VSS56 VSS136 R10 RSVD_TP_69 AD3
C24 VSS215 AJ8 VSS57 VSS137 P8 AC9 RSVD21 RSVD_TP_70 AD2
C22 VSS216 AJ5 VSS58 VSS138 P4 AB9 RSVD22 RSVD_TP_71 AA2
C20 VSS217 AJ2 VSS59 VSS139 P2 CFG0 - PCI-Express Configuration Select RSVD_TP_72 AA1
C19 VSS218 AH35 VSS60 VSS140 N35 RSVD_TP_73 R9
C16 VSS219 AH34 VSS61 VSS141 N34 RSVD_TP_74 AG7
B31
B25
VSS220 AH33
AH32
VSS62
is VSS142 N33
N32
*1:Single PEG
0:Bifurcation enabled
C1
A3
RSVD_NCTF_23 RSVD_TP_75 AE3
B VSS221 VSS63 VSS143 RSVD_NCTF_24 B
B21 VSS222 AH31 VSS64 VSS144 N31
B18 VSS223 AH30 VSS65 VSS145 N30 RSVD_TP_76 V4
B17 VSS224 AH29 VSS66 VSS146 N29 RSVD_TP_77 V5
B13 VSS225 AH28 VSS67 VSS147 N28 RSVD_TP_78 N2
B11 VSS226 AH27 VSS68 VSS148 N27 CFG3 - PCI-Express Static Lane Reversal J29 RSVD26 RSVD_TP_79 AD5
B8 AH26 N26 J28 AD7
kn

VSS227 VSS69 VSS149 RSVD27 RSVD_TP_80

B6 VSS228 AH20 VSS70 VSS150 N6 RSVD_TP_81 W3
B4 VSS229 AH17 VSS71 VSS151 M10 *1 :Normal Operation A34 RSVD_NCTF_28 RSVD_TP_82 W2
A29 VSS230 AH13 VSS72 VSS152 L35 0 :Lane Numbers Reversed A33 RSVD_NCTF_29 RSVD_TP_83 N3
A27 VSS231 AH9 VSS73 VSS153 L32 15 -> 0, 14 -> 1, ... RSVD_TP_84 AE5
A23 VSS232 AH6 VSS74 VSS154 L29 C35 RSVD_NCTF_30 RSVD_TP_85 AD9
A9 VSS233 AH3 VSS75 VSS155 L8 B35 RSVD_NCTF_31
AG10 VSS76 VSS156 L5
te

AF8 VSS77 VSS157 L2 VSS AP34

AF4 VSS78 VSS158 K34 CFG4 - Display Port Presence
AF2 VSS79 VSS159 K33
AE35 VSS80 VSS160 K30
*1:Disabled; No Physical Display Port
attached to Embedded Display Port IC,AUB_CFD_rPGA,R0P9
0:Enabled; An external Display Port @
w.

IC,AUB_CFD_rPGA,R0P9 IC,AUB_CFD_rPGA,R0P9 device is connected to the Embedded

@ @ Display Port

*:Default
ww

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 10 of 58
5 4 3 2 1
 5 4 3 2 1

+1.5V +1.5V

1
JDDRH
2
DDR3 SO-DIMM A
+VREF_DQA
DDR_A_D0
3
VREF_DQ
VSS
VSS
DQ4 4 DDR_A_D4
DDR_A_D5
Reverse Type 7 DDR_A_DQS[0..7]

0.1U_0402_16V4Z

2.2U_0603_6.3V4Z
5 DQ0 DQ5 6 7 DDR_A_DQS#[0..7]
1 1 DDR_A_D1 7 8
DQ1 VSS DDR_A_DQS#0
9 VSS DQS0# 10 7 DDR_A_D[0..63]
+1.5V
C156

C157
DDR_A_DM0 11 12 DDR_A_DQS0
DM0 DQS0
13 VSS VSS 14 7 DDR_A_DM[0..7]
2 2 DDR_A_D2 DDR_A_D6
15 DQ2 DQ6 16

1
DDR_A_D3 17 18 DDR_A_D7 7 DDR_A_MA[0..15]
DQ3 DQ7 R80
19 VSS VSS 20

m
DDR_A_D8 21 22 DDR_A_D12 1K_0402_1%
DDR_A_D9 DQ8 DQ12 DDR_A_D13 PS@
D 23 DQ9 DQ13 24 D
25 26

2
DDR_A_DQS#1 VSS VSS DDR_A_DM1
close to JDDRH.1 27 DQS1# DM1 28

co
DDR_A_DQS1 29 30
DQS1 RESET# SM_DRAMRST# 5,12
31 VSS VSS 32
DDR_A_D10 33 34 DDR_A_D14
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 DQ11 DQ15 36 M3 is for Clarksfield
37 VSS VSS 38
DDR_A_D16 39 40 DDR_A_D20
DDR_A_D17 41
DQ16
DQ17
DQ20
DQ21 42 DDR_A_D21 For S3 Reduce
43 44

a.
DDR_A_DQS#2 VSS VSS DDR_A_DM2 +1.5V
45 DQS2# DM2 46
DDR_A_DQS2 47 48 M3@
DQS2 VSS DDR_A_D22
49 VSS DQ22 50 2 1

1
DDR_A_D18 51 52 DDR_A_D23 R94 0_0402_5% PSM3@
DDR_A_D19 DQ18 DQ23 R84
53 DQ19 VSS 54
55 56 DDR_A_D28 Q40 PSM3@ 1K_0402_1%
DDR_A_D24 VSS DQ28 DDR_A_D29 2N7002_SOT23-3 +VREF_DQA
57 DQ24 DQ29 58

si
DDR_A_D25 59 60

2
DQ25 VSS

D
61 62 DDR_A_DQS#3 +VREF_DQA_M3 3 1 2 M1@ 1
DDR_A_DM3 VSS DQS3# DDR_A_DQS3 0_0402_5% R92
63 DM3 DQS3 64

1
PSM3@ +1.5V
65 VSS VSS 66
DDR_A_D26 DDR_A_D30 PSM3@ R111

G
67 68

2
DDR_A_D27 DQ26 DQ30 DDR_A_D31 R122 RST_GATE 1K_0402_1%
69 DQ27 DQ31 70

1
71 72 100K_0402_5%
VSS VSS +V_DDR3_DIMM_REF R79

ne
2

2
1K_0402_1%
7 DDRA_CKE0 73 CKE0 CKE1 74 DDRA_CKE1 7
75 76

2
C
VDD VDD DDR_A_MA15 C
77 NC A15 78
DDR_A_MA14 +1.5V
7 DDR_A_BS2 79 BA2 A14 80

1
81 82 M3@
DDR_A_MA12 VDD VDD DDR_A_MA11 R81
83 A12/BC# A11 84 2 1

1
do
DDR_A_MA9 85 86 DDR_A_MA7 R95 0_0402_5% PSM3@ 1K_0402_1%
A9 A7 R114
87 VDD VDD 88
DDR_A_MA8 89 90 DDR_A_MA6 Q39 PSM3@ 1K_0402_1%

2
DDR_A_MA5 A8 A6 DDR_A_MA4 2N7002_SOT23-3 +VREF_DQB
91 A5 A4 92
93 94

2
VDD VDD

D
DDR_A_MA3 95 96 DDR_A_MA2 +VREF_DQB_M3 3 1 2 M1@ 1
DDR_A_MA1 A3 A2 DDR_A_MA0 0_0402_5% R93
97 A1 A0 98

1
99 100 PSM3@

in
VDD VDD PSM3@ R115

G
101 102 DDRA_CLK1 7

2
7 DDRA_CLK0 CK0 CK1 R121 1K_0402_1%
7 DDRA_CLK0# 103 CK0# CK1# 104 DDRA_CLK1# 7
105 106 100K_0402_5%
VDD VDD RST_GATE 5,30
DDR_A_MA10 107 108 DDR_A_BS1 7

2
A10/AP BA1
7 DDR_A_BS0 109 BA0 RAS# 110 DDR_A_RAS# 7
111 VDD VDD 112
7 DDR_A_WE# 113 WE# S0# 114 DDRA_SCS0# 7

i-
7 DDR_A_CAS# 115 CAS# ODT0 116 DDRA_ODT0 7
117 VDD VDD 118
DDR_A_MA13 +V_DDR3_DIMM_REF
119 A13 ODT1 120 DDRA_ODT1 7
7 DDRA_SCS1# 121 S1# NC 122
123 124 R89
VDD VDD +DDR_VREF_CA_DIMMA
125 TEST VREF_CA 126 1 2
127 128 0_0402_5%
DDR_A_D32 VSS VSS DDR_A_D36
129 DQ32 DQ36 130
DDR_A_D33 DDR_A_D37
is 0.1U_0402_16V4Z
2.2U_0603_6.3V4Z

131 DQ33 DQ37 132

133 VSS VSS 134
B DDR_A_DQS#4 DDR_A_DM4 B
135 DQS4# DM4 136
DDR_A_DQS4 137 138 1 1 Layout Note: Layout Note: Place these 4 Caps near Layout Note:
DQS4 VSS DDR_A_D38
139 VSS DQ38 140
Place near JDDRH Command and Control signals of DIMMA Place near JDDRH1.203 and 204
C161

C162

DDR_A_D34 141 142 DDR_A_D39

DDR_A_D35 DQ34 DQ39
143 DQ35 VSS 144
DDR_A_D44 2 2
145 146
kn

DDR_A_D40 VSS DQ44 DDR_A_D45 +1.5V

147 DQ40 DQ45 148
DDR_A_D41 149 150 +1.5V +0.75VS
DQ41 VSS DDR_A_DQS#5 C217 1 2 390U_2.5V_M_R10

+
151 VSS DQS5# 152
DDR_A_DM5 153 154 DDR_A_DQS5 close to JDDRH.126
DM5 DQS5 C164 1
155 VSS VSS 156 2 0.1U_0402_16V4Z C165 1 2 10U_0805_6.3V6M
DDR_A_D42 157 158 DDR_A_D46 C166 1 2 10U_0805_6.3V6M
DDR_A_D43 DQ42 DQ46 DDR_A_D47 C167 1
159 DQ43 DQ47 160 2 0.1U_0402_16V4Z C169 2 1 1U_0402_6.3V4Z
te

161 162 C168 1 2 10U_0805_6.3V6M

DDR_A_D48 VSS VSS DDR_A_D52 C170 1
163 DQ48 DQ52 164 2 0.1U_0402_16V4Z C172 2 1 1U_0402_6.3V4Z
DDR_A_D49 165 166 DDR_A_D53 C171 1 2 10U_0805_6.3V6M
DQ49 DQ53 C173 1
167 VSS VSS 168 2 0.1U_0402_16V4Z C175 2 1 1U_0402_6.3V4Z
DDR_A_DQS#6 169 170 DDR_A_DM6 C174 1 2 10U_0805_6.3V6M
DDR_A_DQS6 DQS6# DM6 C255 1
171 DQS6 VSS 172 2 68P_0402_50V8J C177 2 1 1U_0402_6.3V4Z
173 174 DDR_A_D54 C176 1 2 10U_0805_6.3V6M
DDR_A_D50 VSS DQ54 DDR_A_D55 C256 1
175 176 For EMI Request 2 68P_0402_50V8J
w.

DDR_A_D51 DQ50 DQ55 C178 1

177 DQ51 VSS 178 2 10U_0805_6.3V6M
179 180 DDR_A_D60 For EMI Request
DDR_A_D56 VSS DQ60 DDR_A_D61
181 DQ56 DQ61 182
DDR_A_D57 183 184
DQ57 VSS DDR_A_DQS#7
185 VSS DQS7# 186
DDR_A_DM7 187 188 DDR_A_DQS7
DM7 DQS7
189 VSS VSS 190
DDR_A_D58
ww

191 192 DDR_A_D62

A DQ58 DQ62 A
DDR_A_D59 193 194 DDR_A_D63
R90 1 DQ59 DQ63
2 195 VSS VSS 196
10K_0402_5% 197 198
SA0 EVENT# PM_EXTTS# 5,12
+3VS 199 VDDSPD SDA 200 PM_SMBDATA 12,22,26,36
0.1U_0402_16V4Z
2.2U_0603_6.3V4Z

201 SA1 SCL 202 PM_SMBCLK 12,22,26,36

10K_0402_5%

203 204
1 1 +0.75VS VTT VTT +0.75VS Security Classification Compal Secret Data Compal Electronics, Inc.
1

C182
C181 205 206 2009/10/01 2010/10/01 Title
GND1 BOSS1 Issued Date Deciphered Date
R91

207 208
2 2 GND2 BOSS2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
2

FOX_AS0A626-U2SN-7F_204P Custom B
@
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 11 of 58
5 4 3 2 1
 A B C D E

+1.5V +1.5V

1
JDDRL
2
Standard Type
+VREF_DQB
DDR_B_D0
3
5
VREF_DQ
VSS
VSS
DQ4 4
6
DDR_B_D4
DDR_B_D5
DDR3 SO-DIMM B
DDR_B_D1 DQ0 DQ5
7 DQ1 VSS 8 7 DDR_B_DQS#[0..7]
DDR_B_DQS#0

0.1U_0402_16V4Z
2.2U_0603_6.3V4Z 9 10
DDR_B_DM0 VSS DQS0# DDR_B_DQS0
11 DM0 DQS0 12 7 DDR_B_DQS[0..7]
1 1 13 VSS VSS 14
DDR_B_D2 15 16 DDR_B_D6 7 DDR_B_D[0..63]
DDR_B_D3 DQ2 DQ6 DDR_B_D7
17 DQ3 DQ7 18
C183

C184
19 VSS VSS 20 7 DDR_B_DM[0..7]
2 2

m
DDR_B_D8 21 22 DDR_B_D12
DDR_B_D9 DQ8 DQ12 DDR_B_D13
1 23 DQ9 DQ13 24 7 DDR_B_MA[0..15] 1
25 VSS VSS 26
DDR_B_DQS#1 27 28 DDR_B_DM1
DQS1# DM1

co
DDR_B_DQS1 29 30
DQS1 RESET# SM_DRAMRST# 5,11
31 VSS VSS 32
DDR_B_D10 33 34 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
close to JDDRL.1 35 DQ11 DQ15 36
37 VSS VSS 38
DDR_B_D16 39 40 DDR_B_D20
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 DQ17 DQ21 42
43 44

a.
DDR_B_DQS#2 VSS VSS DDR_B_DM2
45 DQS2# DM2 46
DDR_B_DQS2 47 48
DQS2 VSS DDR_B_D22
49 VSS DQ22 50
DDR_B_D18 51 52 DDR_B_D23
DDR_B_D19 DQ18 DQ23
53 DQ19 VSS 54
55 56 DDR_B_D28
DDR_B_D24 VSS DQ28 DDR_B_D29
57 DQ24 DQ29 58

si
DDR_B_D25 59 60
DQ25 VSS DDR_B_DQS#3
61 VSS DQS3# 62
DDR_B_DM3 63 64 DDR_B_DQS3
DM3 DQS3
65 VSS VSS 66
DDR_B_D26 67 68 DDR_B_D30
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 DQ27 DQ31 70
71 VSS VSS 72

ne
7 DDRB_CKE0 73 CKE0 CKE1 74 DDRB_CKE1 7
75 VDD VDD 76
2 77 78 DDR_B_MA15 2
NC A15 DDR_B_MA14
7 DDR_B_BS2 79 BA2 A14 80
81 VDD VDD 82
DDR_B_MA12 83 84 DDR_B_MA11
A12/BC# A11

do
DDR_B_MA9 85 86 DDR_B_MA7
A9 A7
87 VDD VDD 88
DDR_B_MA8 89 90 DDR_B_MA6
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 VDD VDD 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 100

in
VDD VDD
7 DDRB_CLK0 101 CK0 CK1 102 DDRB_CLK1 7
7 DDRB_CLK0# 103 CK0# CK1# 104 DDRB_CLK1# 7
105 VDD VDD 106
DDR_B_MA10 107 108
A10/AP BA1 DDR_B_BS1 7
7 DDR_B_BS0 109 BA0 RAS# 110 DDR_B_RAS# 7
111 VDD VDD 112
7 DDR_B_WE# 113 WE# S0# 114 DDRB_SCS0# 7

i-
7 DDR_B_CAS# 115 CAS# ODT0 116 DDRB_ODT0 7
117 VDD VDD 118
DDR_B_MA13 119 120
A13 ODT1 DDRB_ODT1 7 +V_DDR3_DIMM_REF
7 DDRB_SCS1# 121 S1# NC 122
123 124 R97
VDD VDD +DDR_VREF_CA_DIMMB
125 TEST VREF_CA 126 1 2 0_0402_5% Layout Note: Layout Note: Place these 4 Caps near Layout Note:
127 VSS VSS 128
DDR_B_D32 129 130 DDR_B_D36 Place near JDDRL Command and Control signals of DIMMB Place near JDDRL.203 and 204
DQ32 DQ36
DDR_B_D33 DDR_B_D37
is 0.1U_0402_16V4Z
2.2U_0603_6.3V4Z

131 DQ33 DQ37 132

133 VSS VSS 134
3 DDR_B_DQS#4 135 136 DDR_B_DM4 +1.5V 3
DQS4# DM4 1 1
DDR_B_DQS4 137 138 @ +1.5V +0.75VS
DQS4 VSS DDR_B_D38 C189 1 2 330U_B2_2.5VM_R15M

+
139 VSS DQ38 140
C187

C188

DDR_B_D34 141 142 DDR_B_D39

DDR_B_D35 DQ34 DQ39 2 2 C190 1
143 DQ35 VSS 144 2 0.1U_0402_16V4Z C191 1 2 10U_0805_6.3V6M
145 146 DDR_B_D44 C192 1 2 10U_0805_6.3V6M
kn

DDR_B_D40 VSS DQ44 DDR_B_D45 C193 1

147 DQ40 DQ45 148 2 0.1U_0402_16V4Z C195 2 1 1U_0402_6.3V4Z
DDR_B_D41 149 150 C194 1 2 10U_0805_6.3V6M
DQ41 VSS DDR_B_DQS#5 C196 1
151 VSS DQS5# 152 2 0.1U_0402_16V4Z C198 2 1 1U_0402_6.3V4Z
DDR_B_DM5 153 154 DDR_B_DQS5 C197 1 2 10U_0805_6.3V6M
DM5 DQS5 C199 1
155 VSS VSS 156 close to JDDRL.126 2 0.1U_0402_16V4Z C201 2 1 1U_0402_6.3V4Z
DDR_B_D42 157 158 DDR_B_D46 C200 1 2 10U_0805_6.3V6M
DDR_B_D43 DQ42 DQ46 DDR_B_D47 C257 1
159 DQ43 DQ47 160 2 68P_0402_50V8J C203 2 1 1U_0402_6.3V4Z
te

161 162 C202 1 2 10U_0805_6.3V6M

DDR_B_D48 VSS VSS DDR_B_D52 C258 1
163 DQ48 DQ52 164 For EMI Request 2 68P_0402_50V8J
DDR_B_D49 165 166 DDR_B_D53 C204 1 2 10U_0805_6.3V6M
DQ49 DQ53
167 VSS VSS 168 For EMI Request
DDR_B_DQS#6 169 170 DDR_B_DM6
DDR_B_DQS6 DQS6# DM6
171 DQS6 VSS 172
173 174 DDR_B_D54
DDR_B_D50 VSS DQ54 DDR_B_D55
175 176
w.

DDR_B_D51 DQ50 DQ55

177 DQ51 VSS 178
179 180 DDR_B_D60
DDR_B_D56 VSS DQ60 DDR_B_D61
181 DQ56 DQ61 182
DDR_B_D57 183 184
DQ57 VSS DDR_B_DQS#7
185 VSS DQS7# 186
DDR_B_DM7 187 188 DDR_B_DQS7
DM7 DQS7
189 VSS VSS 190
DDR_B_D58
ww

191 192 DDR_B_D62

4 DQ58 DQ62 4
DDR_B_D59 193 194 DDR_B_D63
R98 1 DQ59 DQ63
2 195 VSS VSS 196
10K_0402_5% 197 198
SA0 EVENT# PM_EXTTS# 5,11
+3VS 199 VDDSPD SDA 200 PM_SMBDATA 11,22,26,36
201 SA1 SCL 202 PM_SMBCLK 11,22,26,36
2.2U_0603_6.3V4Z 1 R99 2 203 204
1 1
10K_0402_5%
+0.75VS VTT VTT +0.75VS Security Classification Compal Secret Data Compal Electronics, Inc.
205 GND1 BOSS1 206 Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title
C207 C208 207 208
2 2 GND2 BOSS2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
0.1U_0402_16V4Z AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
FOX_AS0A626-U2RN-7F Custom B
@
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 12 of 58
A B C D E
 5 4 3 2 1

PCIE_GTX_C_CRX_P[0..15]
6 PCIE_GTX_C_CRX_P[0..15]
UV1A
PCIE_GTX_C_CRX_N[0..15]
6 PCIE_GTX_C_CRX_N[0..15] LANE Reversal LANE Reversal Close to UV1

m
PCIE_CTX_C_GRX_P[0..15]
6 PCIE_CTX_C_GRX_P[0..15]
D D

PCIE_CTX_C_GRX_N[0..15] PCIE_CTX_C_GRX_P15 AA38 Y33 PCIE_GTX_CRX_P15 CV1 1 2 0.1U_0402_16V7K PCIE_GTX_C_CRX_P15

6 PCIE_CTX_C_GRX_N[0..15] PCIE_RX0P PCIE_TX0P

co
PCIE_CTX_C_GRX_N15 Y37 Y32 PCIE_GTX_CRX_N15 CV2 1 2 0.1U_0402_16V7K PCIE_GTX_C_CRX_N15
PCIE_RX0N PCIE_TX0N

PCIE_CTX_C_GRX_P14 Y35 W33 PCIE_GTX_CRX_P14 CV3 1 2 0.1U_0402_16V7K PCIE_GTX_C_CRX_P14

PCIE_CTX_C_GRX_N14 PCIE_RX1P PCIE_TX1P PCIE_GTX_CRX_N14 CV4 0.1U_0402_16V7K PCIE_GTX_C_CRX_N14
W36 PCIE_RX1N PCIE_TX1N W32 1 2

PCIE_CTX_C_GRX_P13 W38 U33 PCIE_GTX_CRX_P13 CV5 1 2 0.1U_0402_16V7K PCIE_GTX_C_CRX_P13

a.
PCIE_CTX_C_GRX_N13 PCIE_RX2P PCIE_TX2P PCIE_GTX_CRX_N13 CV6 0.1U_0402_16V7K PCIE_GTX_C_CRX_N13
V37 PCIE_RX2N PCIE_TX2N U32 1 2

PCIE_CTX_C_GRX_P12 V35 U30 PCIE_GTX_CRX_P12 CV7 1 2 0.1U_0402_16V7K PCIE_GTX_C_CRX_P12

PCIE_CTX_C_GRX_N12 PCIE_RX3P PCIE_TX3P PCIE_GTX_CRX_N12 CV8 0.1U_0402_16V7K PCIE_GTX_C_CRX_N12
U36 PCIE_RX3N PCIE_TX3N U29 1 2

si
PCIE_CTX_C_GRX_P11 U38 T33 PCIE_GTX_CRX_P11 CV9 1 2 0.1U_0402_16V7K PCIE_GTX_C_CRX_P11
PCIE_CTX_C_GRX_N11 PCIE_RX4P PCIE_TX4P PCIE_GTX_CRX_N11 CV10 1 0.1U_0402_16V7K PCIE_GTX_C_CRX_N11
T37 PCIE_RX4N PCIE_TX4N T32 2

PCI EXPRESS INTERFACE

PCIE_CTX_C_GRX_P10 T35 T30 PCIE_GTX_CRX_P10 CV11 1 2 0.1U_0402_16V7K PCIE_GTX_C_CRX_P10
PCIE_CTX_C_GRX_N10 PCIE_RX5P PCIE_TX5P PCIE_GTX_CRX_N10 CV12 1 0.1U_0402_16V7K PCIE_GTX_C_CRX_N10
R36 PCIE_RX5N PCIE_TX5N T29 2

ne
PCIE_CTX_C_GRX_P9 R38 P33 PCIE_GTX_CRX_P9 CV13 1 2 0.1U_0402_16V7K PCIE_GTX_C_CRX_P9
PCIE_CTX_C_GRX_N9 PCIE_RX6P PCIE_TX6P PCIE_GTX_CRX_N9 CV14 1 0.1U_0402_16V7K PCIE_GTX_C_CRX_N9
P37 PCIE_RX6N PCIE_TX6N P32 2
C C
PCIE_CTX_C_GRX_P8 P35 P30 PCIE_GTX_CRX_P8 CV15 1 2 0.1U_0402_16V7K PCIE_GTX_C_CRX_P8
PCIE_CTX_C_GRX_N8 PCIE_RX7P PCIE_TX7P PCIE_GTX_CRX_N8 CV16 1 0.1U_0402_16V7K PCIE_GTX_C_CRX_N8
N36 PCIE_RX7N PCIE_TX7N P29 2

do
PCIE_CTX_C_GRX_P7 N38 N33 PCIE_GTX_CRX_P7 CV17 1 2 0.1U_0402_16V7K PCIE_GTX_C_CRX_P7
PCIE_CTX_C_GRX_N7 PCIE_RX8P PCIE_TX8P PCIE_GTX_CRX_N7 CV18 1 0.1U_0402_16V7K PCIE_GTX_C_CRX_N7
M37 PCIE_RX8N PCIE_TX8N N32 2

PCIE_CTX_C_GRX_P6 M35 N30 PCIE_GTX_CRX_P6 CV19 1 2 0.1U_0402_16V7K PCIE_GTX_C_CRX_P6

PCIE_CTX_C_GRX_N6 PCIE_RX9P PCIE_TX9P PCIE_GTX_CRX_N6 CV20 1 0.1U_0402_16V7K PCIE_GTX_C_CRX_N6
L36 PCIE_RX9N PCIE_TX9N N29 2

in
PCIE_CTX_C_GRX_P5 L38 L33 PCIE_GTX_CRX_P5 CV21 1 2 0.1U_0402_16V7K PCIE_GTX_C_CRX_P5
PCIE_CTX_C_GRX_N5 PCIE_RX10P PCIE_TX10P PCIE_GTX_CRX_N5 CV22 1 0.1U_0402_16V7K PCIE_GTX_C_CRX_N5
K37 PCIE_RX10N PCIE_TX10N L32 2

PCIE_CTX_C_GRX_P4 K35 L30 PCIE_GTX_CRX_P4 CV23 1 2 0.1U_0402_16V7K PCIE_GTX_C_CRX_P4

PCIE_CTX_C_GRX_N4 PCIE_RX11P PCIE_TX11P PCIE_GTX_CRX_N4 CV24 1 0.1U_0402_16V7K PCIE_GTX_C_CRX_N4
J36 PCIE_RX11N PCIE_TX11N L29 2

i-
PCIE_CTX_C_GRX_P3 J38 K33 PCIE_GTX_CRX_P3 CV25 1 2 0.1U_0402_16V7K PCIE_GTX_C_CRX_P3
PCIE_CTX_C_GRX_N3 PCIE_RX12P PCIE_TX12P PCIE_GTX_CRX_N3 CV26 1 0.1U_0402_16V7K PCIE_GTX_C_CRX_N3
H37 PCIE_RX12N PCIE_TX12N K32 2

PCIE_CTX_C_GRX_P2 H35 J33 PCIE_GTX_CRX_P2 CV27 1 2 0.1U_0402_16V7K PCIE_GTX_C_CRX_P2

PCIE_CTX_C_GRX_N2 PCIE_RX13P PCIE_TX13P PCIE_GTX_CRX_N2 CV28 1 0.1U_0402_16V7K PCIE_GTX_C_CRX_N2
G36 PCIE_RX13N PCIE_TX13N J32 2
is
B PCIE_CTX_C_GRX_P1 PCIE_GTX_CRX_P1 CV29 1 0.1U_0402_16V7K PCIE_GTX_C_CRX_P1 B
G38 PCIE_RX14P PCIE_TX14P K30 2
PCIE_CTX_C_GRX_N1 F37 K29 PCIE_GTX_CRX_N1 CV30 1 2 0.1U_0402_16V7K PCIE_GTX_C_CRX_N1
PCIE_RX14N PCIE_TX14N

PCIE_CTX_C_GRX_P0 F35 H33 PCIE_GTX_CRX_P0 CV31 1 2 0.1U_0402_16V7K PCIE_GTX_C_CRX_P0

PCIE_CTX_C_GRX_N0 PCIE_RX15P PCIE_TX15P PCIE_GTX_CRX_N0 CV32 1 0.1U_0402_16V7K PCIE_GTX_C_CRX_N0
E37 H32 2
kn

PCIE_RX15N PCIE_TX15N

CLOCK
26 CLK_PCIE_VGA AB35 PCIE_REFCLKP
26 CLK_PCIE_VGA# AA36 PCIE_REFCLKN
te

CALIBRATION
AJ21 Y30 RV1 1 2 1.27K_0402_1%
MANHA@ NC#1 PCIE_CALRP
AK21 NC#2
RV133 1 2 10K_0402_5% AH16 Y29 RV2 1 2 2K_0402_1% +1.0VS
NC_PWRGOOD PCIE_CALRN

AA30
w.

29,36,37,41,42 PLT_RST# PERSTB

216-0772000-PRO_FCBGA962 MADISONLP@
ww

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401849 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 18, 2010 Sheet 13 of 58
5 4 3 2 1
 5 4 3 2 1
UV1B

AU24 UV1G
TXCAP_DPA3P
TXCAM_DPA3N AV23

TX0P_DPA2P AT25
MUTI GFX AR24 LVDS CONTROL AK27
DPA TX0M_DPA2N VARY_BL VGA_PWM 22
DIGON AJ27 VGA_ENVDD 22
TX1P_DPA1P AU26
TX1M_DPA1N AV25

AR8 DVPCNTL_MVP_0 TX2P_DPA0P AT27

AU8 DVPCNTL_MVP_1 TX2M_DPA0N AR26 TXCLK_UP_DPF3P AK35 VGA_TZCLK+ 22
AP8 DVPCNTL_0 TXCLK_UN_DPF3N AL36 VGA_TZCLK- 22
AW8 DVPCNTL_1 TXCBP_DPB3P AR30 VGA_HDMI_CLK+ 24

m
AR3 DVPCNTL_2 TXCBM_DPB3N AT29 VGA_HDMI_CLK- 24 TXOUT_U0P_DPF2P AJ38 VGA_TZOUT0+ 22
D
AR1 DVPCLK TXOUT_U0N_DPF2N AK37 VGA_TZOUT0- 22 D
21 VRAM_ID0 AU1 DVPDATA_0 TX3P_DPB2P AV31 VGA_HDMI_TX0+ 24
21 VRAM_ID1 AU3 DVPDATA_1 TX3M_DPB2N AU30 VGA_HDMI_TX0- 24 TXOUT_U1P_DPF1P AH35 VGA_TZOUT1+ 22
AW3 DPB AJ36 VGA_TZOUT1- 22
21 VRAM_ID2 DVPDATA_2 TXOUT_U1N_DPF1N

co
AP6 DVPDATA_3 TX4P_DPB1P AR32 VGA_HDMI_TX1+ 24
AW5 DVPDATA_4 TX4M_DPB1N AT31 VGA_HDMI_TX1- 24 TXOUT_U2P_DPF0P AG38 VGA_TZOUT2+ 22
AU5 DVPDATA_5 TXOUT_U2N_DPF0N AH37 VGA_TZOUT2- 22
AR6 DVPDATA_6 TX5P_DPB0P AT33 VGA_HDMI_TX2+ 24
AW6 DVPDATA_7 TX5M_DPB0N AU32 VGA_HDMI_TX2- 24 TXOUT_U3P AF35
+3VS_DELAY AU6 AG36
DVPDATA_8 TXOUT_U3N
AT7 DVPDATA_9 TXCCP_DPC3P AU14
AV7 DVPDATA_10 TXCCM_DPC3N AV13
@ 10K_0402_5% 2 1 RV30 VGA_PWRSEL0 AN7 LVTMDP
DVPDATA_11
AV9 DVPDATA_12 TX0P_DPC2P AT15

a.
@ 10K_0402_5% 2 1 RV131 VGA_PWRSEL1 AT9 DVPDATA_13 TX0M_DPC2N AR14 TXCLK_LP_DPE3P AP34 VGA_TXCLK+ 22
AR10 DVPDATA_14 TXCLK_LN_DPE3N AR34 VGA_TXCLK- 22
10K_0402_5% 2 1 RV32 THERM#_VGA AW10 DPC AU16
DVPDATA_15 TX1P_DPC1P
AU10 DVPDATA_16 TX1M_DPC1N AV15 TXOUT_L0P_DPE2P AW37 VGA_TXOUT0+ 22
M9X@ 10K_0402_5% 2 1 RV33 GPIO23_CLKREQ# AP10 AU35 VGA_TXOUT0- 22
DVPDATA_17 TXOUT_L0N_DPE2N
AV11 DVPDATA_18 TX2P_DPC0P AT17
@ 10K_0402_5% 2 1 RV34 R_AC_IN AT11 AR16 AR37 VGA_TXOUT1+ 22
DVPDATA_19 TX2M_DPC0N TXOUT_L1P_DPE1P
AR12 DVPDATA_20 TXOUT_L1N_DPE1N AU39 VGA_TXOUT1- 22
@ 10K_0402_5% 2 1 RV35 GENERIC_C AW12 AU20
DVPDATA_21 TXCDP_DPD3P
AU12 AT19 AP35 VGA_TXOUT2+ 22

si
DVPDATA_22 TXCDM_DPD3N TXOUT_L2P_DPE0P
AP12 DVPDATA_23 TXOUT_L2N_DPE0N AR35 VGA_TXOUT2- 22
10K_0402_5% 1 2 RV17 VGA_ENBKL AT21
TX3P_DPD2P
TX3M_DPD2N AR20 TXOUT_L3P AN36
TXOUT_L3N AP37
DPD
TX4P_DPD1P AU22
AV21
Single channel
TX4M_DPD1N
I2C AT23
TX5P_DPD0P 216-0772000-PRO_FCBGA962
TX5M_DPD0N AR22
VGA_EDID_CLK MADISONLP@
LCD AK26

ne
22 VGA_EDID_CLK SCL
22 VGA_EDID_DATA VGA_EDID_DATA AJ26 SDA

R AD39 VGA_CRT_R 23
GENERAL PURPOSE I/O AD37
GPU_GPIO0 RB
C
21 GPU_GPIO0 AH20 GPIO_0
C
GPU_GPIO1 AH18 AE36 Near UV1
21 GPU_GPIO1 GPIO_1 G VGA_CRT_G 23
GPU_GPIO2 AN16 AD35
21 GPU_GPIO2 GPIO_2 GB
AH23 GPIO_3_SMBDATA
AJ23 AF37 VGA_CRT_R 1 2
GPIO_4_SMBCLK B VGA_CRT_B 23
R_AC_IN AH17 AE38 RV11 150_0402_1%

do
GPIO_5_AC_BATT DAC1 BB VGA_CRT_G
AJ17 GPIO_6 1 2
RV12 150_0402_1%
41 VGA_ENBKL
SOUT_GPIO8
AK17
AJ13
GPIO_7_BLON HSYNC AC36
AC38
VGA_CRT_HSYNC 21,23 CRT VGA_CRT_B 1 2
21 SOUT_GPIO8 GPIO_8_ROMSO VSYNC VGA_CRT_VSYNC 21,23
SIN_GPIO9 AH15 RV13 150_0402_1%
21 SIN_GPIO9 GPIO_9_ROMSI
AJ16 GPIO_10_ROMSCK
GPU_GPIO11 AK16 AB34 RSET 1 2
21 GPU_GPIO11 GPIO_11 RSET
GPU_GPIO12 AL16 RV18 499_0402_1%
21 GPU_GPIO12 GPIO_12
GPU_GPIO13 AM16 AD34 +AVDD_VGA
21 GPU_GPIO13 GPIO_13 AVDD
T11 PAD AM14 GPIO_14_HPD2 AVSSQ AE34
VGA_PWRSEL0

in
54 VGA_PWRSEL0 AM13 GPIO_15_PWRCNTL_0
27M_SSC AK14 AC33 +VDD1DI
22 27M_SSC GPIO_16_SSIN VDD1DI
THERM#_VGA AG30 AC34 BLM18PG121SN1D_0603
21 THERM#_VGA
AN14
GPIO_17_THERMAL_INT VSS1DI +AVDD_VGA 70mA 2 1 +1.8VS
GPIO_18_HPD3 LV1
AM17 GPIO_19_CTF 1 1 1
VGA_PWRSEL1 AL13 AC30
54 VGA_PWRSEL1 GPIO_20_PWRCNTL_1 R2
AJ14 AC31 CV33 CV35 CV34
ROMSE_GPIO22 GPIO_21_BB_EN R2B 1U_0402_6.3V4Z 10U_0603_6.3V6M
21 ROMSE_GPIO22 AK13 GPIO_22_ROMCSB
GPIO23_CLKREQ# 2 2 2
AN13 GPIO_23_CLKREQB G2 AD30
AM23 AD31 0.1U_0402_16V4Z
JTAG_TRSTB G2B

i-
T9 PAD AN23 JTAG_TDI
T12 PAD AK23 JTAG_TCK B2 AF30
T13 PAD AL24 JTAG_TMS B2B AF31
T10 PAD AM24 JTAG_TDO
AJ19 BLM18PG121SN1D_0603
AK19
GENERICA
AC32 +VDD1DI 45mA 2 1 +1.8VS
GENERIC_C GENERICB C LV2
AJ20 GENERICC Y AD32 1 1 1
AK20 GENERICD COMP AF32
AJ24 CV36 CV37 CV38
GENERICE_HPD4 DAC2 1U_0402_6.3V4Z 10U_0603_6.3V6M
AH26 GENERICF
AH24 GENERICG
is H2SYNC
V2SYNC
AD29
AC29
HSYNC_DAC2
VSYNC_DAC2
21
21
2 2 2
0.1U_0402_16V4Z
B +1.8VS B
24,30 VGA_HDMI_HPD AK24 HPD1
AG31 +VDD1DI
VDD2DI
VSS2DI AG32
1

RV20
499_0402_1% +A2VDD 45mA 1 2 +3VS_DELAY
AG33 +A2VDD LV4 0_0603_5%
A2VDD
kn

AD33 +A2VDDQ
2

+VGA_VREF AH13 A2VDDQ

+VGA_VREF VREFG
A2VSSQ AF33
1

BLM18PG121SN1D_0603
1
AA29 R2SET 1 2 +A2VDDQ 10mA 2 1 +1.8VS
RV21 CV49 R2SET RV22 715_0402_1% LV6
1 1 1
249_0402_1% 0.1U_0402_16V4Z
2 10U_0603_6.3V6M CV46 CV47 CV48
2

DDC/AUX 1U_0402_6.3V4Z
150mA AM26 VGA_CRT_CLK 23 CRT
te

PLL/CLOCK DDC1CLK 2 2 2
DDC1DATA AN26 VGA_CRT_DATA 23
+DPLL_PVDD AM32 0.1U_0402_16V4Z
DPLL_PVDD
AN32 DPLL_PVSS AUX1P AM27
300mA AUX1N AL27

+DPLL_VDDC AN31 DPLL_VDDC DDC2CLK AM19

AL19
VGA_HDMI_CLK 24
VGA_HDMI_DATA 24
HDMI
DDC2DATA
RV26 1 2 47.5_0402_1% XTALIN AV33 AN20
22 27M_CLK XTALIN AUX2P
1
w.

AU34 XTALOUT AUX2N AM20

RV31
BLM18PG121SN1D_0603 100_0402_1% AL30
DDCCLK_AUX3P
DDCDATA_AUX3N AM30
2 1 0.1U_0402_16V4Z +DPLL_PVDD +3VS_DELAY
+1.8VS
2

LV3 1 1 1 AL29
CV42 DDCCLK_AUX4P VGA_CRT_CLK RV134
21 GPU_THERMAL_D+ AF29 DPLUS DDCDATA_AUX4N AM29 2 1 4.7K_0402_5%
CV41 1U_0402_6.3V4Z AG29 THERMAL
21 GPU_THERMAL_D- DMINUS
CV40 AN21 VGA_CRT_DATA RV135 2 1 4.7K_0402_5%
2 2 2 DDCCLK_AUX5P
20mA DDCDATA_AUX5N AM21
ww

10U_0603_6.3V6M AK32 HDMI@

+TSVDD TS_FDO VGA_HDMI_DATA RV136 1
A AJ32 TSVDD DDC6CLK AJ30 2 4.7K_0402_5% A
AJ33 AJ31 HDMI@
TSVSS DDC6DATA VGA_HDMI_CLK RV137 1 2 4.7K_0402_5%
NC_DDCCLK_AUX7P AK30
NC_DDCDATA_AUX7N AK29

BLM18PG121SN1D_0603 216-0772000-PRO_FCBGA962 MADISONLP@

+1.0VS BLM18PG121SN1D_0603
2 1 0.1U_0402_16V4Z +DPLL_VDDC 2 1 0.1U_0402_16V4Z +TSVDD
LV5 1
CV43
1 1
+1.8VS
LV7 1 1 1
CV52
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title
CV44 CV45 CV51 1U_0402_6.3V4Z
2 2 2 1U_0402_6.3V4Z 2
CV50
2 2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
10U_0603_6.3V6M 10U_0603_6.3V6M DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401849 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 18, 2010 Sheet 14 of 58
5 4 3 2 1
 5 4 3 2 1

LV35 MANHA@
+DPA_VDD18 1U_0402_6.3V4Z 1 2 +1.8VS
BLM18PG121SN1D_0603
2 2 2
UV1H CV316 CV314 CV315

m
0.1U_0402_16V4Z MANHA@ 10U_0603_6.3V6M
DP C/D POWER DP A/B POWER MANHA@ 1 1 1 MANHA@
D D
LV33 MANHA@
+1.8VS 2 1 1U_0402_6.3V4Z +DPC_VDD18 +DPC_VDD18 AP20 AN24 +DPA_VDD18
NC_DPC_VDD18#1 NC_DPA_VDD18#1

co
BLM18PG121SN1D_0603 AP21 AP24
NC_DPC_VDD18#2 NC_DPA_VDD18#2
2 2 2
CV309 CV308 CV310 200mA
10U_0603_6.3V6M MANHA@ MANHA@ +1.0VS 1 2 +DPC_VDD10 AP13 AP31 +DPA_VDD10 1 2 +1.0VS
MANHA@ 1 1 1 LV8 0_0603_5% DPC_VDD10#1 DPA_VDD10#1 LV9 0_0603_5%
AT13 DPC_VDD10#2 DPA_VDD10#2 AP32
0.1U_0402_16V4Z LV36 MANHA@
+DPB_VDD18 1U_0402_6.3V4Z 1 2 +1.8VS

a.
AN17 AN27 BLM18PG121SN1D_0603
DPC_VSSR#1 DPA_VSSR#1
AP16 DPC_VSSR#2 DPA_VSSR#2 AP27 2 2 2
AP17 DPC_VSSR#3 DPA_VSSR#3 AP28
AW14 AW24 CV319 CV317 CV318
DPC_VSSR#4 DPA_VSSR#4 0.1U_0402_16V4Z MANHA@ 10U_0603_6.3V6M
AW16 DPC_VSSR#5 DPA_VSSR#5 AW26
MANHA@ 1 1 1 MANHA@

LV34 MANHA@

si
+1.8VS 2 1 1U_0402_6.3V4Z +DPD_VDD18 +DPD_VDD18 AP22 AP25 +DPB_VDD18
BLM18PG121SN1D_0603 NC_DPD_VDD18#1 NC_DPB_VDD18#1
AP23 NC_DPD_VDD18#2 NC_DPB_VDD18#2 AP26
2 2 2
CV312 CV311 CV313 BLM18PG121SN1D_0603
10U_0603_6.3V6M MANHA@ MANHA@ +1.0VS 1 2 +DPD_VDD10 AP14 AN33 +DPB_VDD10 20mA 2 1 +1.0VS
MANHA@ 1 1 1 LV10 0_0603_5% DPD_VDD10#1 DPB_VDD10#1 LV11
AP15 DPD_VDD10#2 DPB_VDD10#2 AP33 2 2 2
0.1U_0402_16V4Z HDMI@ HDMI@ HDMI@

ne
CV53 CV54 CV55
10U_0603_6.3V6M 0.1U_0402_16V4Z
1 1 1
AN19 DPD_VSSR#1 DPB_VSSR#1 AN29
AP18 DPD_VSSR#2 DPB_VSSR#2 AP29
C AP19 AP30 1U_0402_6.3V4Z C
DPD_VSSR#3 DPB_VSSR#3
AW20 DPD_VSSR#4 DPB_VSSR#4 AW30
AW22 DPD_VSSR#5 DPB_VSSR#5 AW32

do
BLM18PG121SN1D_0603
+1.8VS 2 1 +DPE_VDD18 RV36 150_0402_1%
LV12 2 2 2 2 1 AW18 AW28 1 2
DPCD_CALR DPAB_CALR RV37 150_0402_1%
CV56 CV57 CV58
10U_0603_6.3V6M 0.1U_0402_16V4Z 200mA
1 1 1 +DPE_VDD18 AH34
DP E/F POWER DP PLL POWER
AU28 +DPA_PVDD +DPA_PVDD 20mA 1 2 +1.8VS
1U_0402_6.3V4Z DPE_VDD18#1 DPA_PVDD LV13 0_0603_5%
AJ34 DPE_VDD18#2 DPA_PVSS AV27

in
100mA
+DPE_VDD10 AL33 AV29 +DPB_PVDD
DPE_VDD10#1 DPB_PVDD
AM33 DPE_VDD10#2 DPB_PVSS AR28

BLM18PG121SN1D_0603

i-
2 1 +DPE_VDD10 AN34 AU18 +DPC_PVDD BLM18PG121SN1D_0603
+1.0VS
LV15 2 2 2 AP39
DPE_VSSR#1 DPC_PVDD
AV17 +DPB_PVDD 20mA 2 1 +1.8VS
DPE_VSSR#2 DPC_PVSS LV14
AR39 DPE_VSSR#3 2 2 2
CV60 CV64 CV61 AU37
10U_0603_6.3V6M 0.1U_0402_16V4Z DPE_VSSR#4 10U_0603_6.3V6M CV59 CV62 CV63
AW35 DPE_VSSR#5
1 1 1 +DPD_PVDD 0.1U_0402_16V4Z
DPD_PVDD AV19
1U_0402_6.3V4Z 1 1 1
200mA DPD_PVSS AR18

+DPF_VDD18 AF34
AG34
is
DPF_VDD18#1
DPF_VDD18#2
1U_0402_6.3V4Z

AM37 +DPE_PVDD
B DPE_PVDD B
100mA DPE_PVSS AN38 20mA
+DPC_PVDD 1 2 +1.8VS
+DPF_VDD10 AK33 LV16 0_0603_5%
BLM18PG121SN1D_0603 DPF_VDD10#1
AK34 DPF_VDD10#2
+1.8VS 2 1 +DPF_VDD18 AL38
LV17 NC_DPF_PVDD
kn

2 2 2 NC_DPF_PVSS AM35

CV65 CV66 CV67 AF39

10U_0603_6.3V6M 0.1U_0402_16V4Z DPF_VSSR#1
AH39 DPF_VSSR#2
1 1 1
AK39 DPF_VSSR#3
1U_0402_6.3V4Z AL34 DPF_VSSR#4
AM34 DPF_VSSR#5 20mA
+DPD_PVDD 1 2 +1.8VS
LV18 0_0603_5%
te

RV38 150_0402_1%
2 1 AM39 DPEF_CALR

216-0772000-PRO_FCBGA962
MADISONLP@
BLM18PG121SN1D_0603
+DPF_VDD10
w.

+1.0VS 2 1
LV19 BLM18PG121SN1D_0603
2 2 2
+DPE_PVDD 20mA 2 1 +1.8VS
CV68 CV69 CV70 1 1 1 LV20
10U_0603_6.3V6M 0.1U_0402_16V4Z
1 1 1 0.1U_0402_16V4Z CV71 CV72 CV73
1U_0402_6.3V4Z 10U_0603_6.3V6M
2 2 2
ww

1U_0402_6.3V4Z
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401849 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 18, 2010 Sheet 15 of 58
5 4 3 2 1
 5 4 3 2 1

UV1E
+1.5VS +PCIE_VDDR_VGA
MEM I/O
PCIE 500mA
4A AC7 AA31 1 2 +1.8VS
VDDR1#1 PCIE_VDDR#1 LV21 BLM18PG121SN1D_0603
AD11 VDDR1#2 PCIE_VDDR#2 AA32
1 1 2 1 2 1 2 AF7 VDDR1#3 PCIE_VDDR#3 AA33 1 2
CV74 10U_0603_6.3V6M CV75 1U_0402_6.3V4Z CV76 1U_0402_6.3V4Z AG10 AA34 CV77 10U_0603_6.3V6M
+ CV78 VDDR1#4 PCIE_VDDR#4
1 2 1 2 1 2 AJ7 VDDR1#5 PCIE_VDDR#5 V28 1 2
390U_2.5V_M_R10 CV79 10U_0603_6.3V6M CV80 1U_0402_6.3V4Z CV81 1U_0402_6.3V4Z AK8 W29 CV82 1U_0402_6.3V4Z
VDDR1#6 PCIE_VDDR#6
1 2 1 2 1 2 AL9 VDDR1#7 PCIE_VDDR#7 W30 1 2
2 CV83 10U_0603_6.3V6M CV84 1U_0402_6.3V4Z CV85 1U_0402_6.3V4Z CV86 1U_0402_6.3V4Z
G11 VDDR1#8 PCIE_VDDR#8 Y31

m
1 2 1 2 1 2 G14 VDDR1#9 1 2
D CV87 10U_0603_6.3V6M CV88 1U_0402_6.3V4Z CV89 1U_0402_6.3V4Z G17 CV90 1U_0402_6.3V4Z D
VDDR1#10
1 2 1 2 1 2 G20 VDDR1#11 PCIE_VDDC#1 G30 1 2
CV91 10U_0603_6.3V6M CV92 1U_0402_6.3V4Z CV93 1U_0402_6.3V4Z G23 G31 CV94 1U_0402_6.3V4Z
VDDR1#12 PCIE_VDDC#2 2A

co
1 2 1 2 G26 VDDR1#13 PCIE_VDDC#3 H29 +1.0VS 1 2
CV95 1U_0402_6.3V4Z CV96 1U_0402_6.3V4Z G29 H30 CV97 1U_0402_6.3V4Z
VDDR1#14 PCIE_VDDC#4
1 2 1 2 H10 VDDR1#15 PCIE_VDDC#5 J29 1 2 1 2
CV98 1U_0402_6.3V4Z CV99 1U_0402_6.3V4Z J7 J30 CV100 10U_0603_6.3V6M CV101 0.1U_0402_16V4Z
VDDR1#16 PCIE_VDDC#6
1 2 1 2 J9 VDDR1#17 PCIE_VDDC#7 L28 1 2 1 2
CV102 1U_0402_6.3V4Z CV103 1U_0402_6.3V4Z K11 M28 CV104 1U_0402_6.3V4Z CV105 0.1U_0402_16V4Z
VDDR1#18 PCIE_VDDC#8
1 2 1 2 K13 VDDR1#19 PCIE_VDDC#9 N28 1 2
CV106 1U_0402_6.3V4Z CV107 1U_0402_6.3V4Z K8 R28 CV108 1U_0402_6.3V4Z
VDDR1#20 PCIE_VDDC#10

a.
1 2 1 2 L12 VDDR1#21 PCIE_VDDC#11 T28 1 2
CV109 1U_0402_6.3V4Z CV110 1U_0402_6.3V4Z L16 U28 CV111 1U_0402_6.3V4Z
L21
VDDR1#22 PCIE_VDDC#12
1 2
25A +VGA_CORE
VDDR1#23 CV112 1U_0402_6.3V4Z
L23 VDDR1#24 1 1
L26 VDDR1#25 VDDC#1 AA15 1 2
L7 CORE AA17 CV113 1U_0402_6.3V4Z + CV116 + CV114
VDDR1#26 VDDC#2
M11 VDDR1#27 VDDC#3 AA20 1 2 390U_2.5V_M_R10 390U_2.5V_M_R10
N11 AA22 CV115 1U_0402_6.3V4Z
VDDR1#28 VDDC#4 2 2

si
P7 VDDR1#29 VDDC#5 AA24 1 2
R11 AA27 CV118 1U_0402_6.3V4Z
VDDR1#30 VDDC#6
U11 VDDR1#31 VDDC#7 AB13
U7 VDDR1#32 VDDC#8 AB16
Y11 VDDR1#33 VDDC#9 AB18 1 2 1 2 1 2
Y7 AB21 CV120 10U_0603_6.3V6M CV121 1U_0402_6.3V4Z CV122 1U_0402_6.3V4Z
VDDR1#34 VDDC#10
VDDC#11 AB23 1 2 1 2 1 2
AB26 CV124 10U_0603_6.3V6M CV125 1U_0402_6.3V4Z CV126 1U_0402_6.3V4Z
VDDC#12

ne
VDDC#13 AB28 1 2 1 2 1 2
AC12 CV128 10U_0603_6.3V6M CV129 1U_0402_6.3V4Z CV130 1U_0402_6.3V4Z
BLM18PG121SN1D_0603 LEVEL VDDC#14
136mA VDDC#15 AC15 1 2 1 2 1 2
10U_0603_6.3V6M

1U_0402_6.3V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z
TRANSLATION AC17 CV132 10U_0603_6.3V6M CV133 1U_0402_6.3V4Z CV134 1U_0402_6.3V4Z
+1.8VS VDDC#16

POWER
C 2 1 2 2 2 1 2 +VDD_CT AF26 AC20 1 2 1 2 1 2 C
LV22 VDD_CT#1 VDDC#17 CV136 10U_0603_6.3V6M CV137 1U_0402_6.3V4Z CV138 1U_0402_6.3V4Z
AF27 VDD_CT#2 VDDC#18 AC22
CV119 CV123 CV127 CV131 CV135 AG26 AC24 1 2 1 2 1 2
VDD_CT#3 VDDC#19 CV139 10U_0603_6.3V6M CV140 1U_0402_6.3V4Z CV141 1U_0402_6.3V4Z
1U_0402_6.3V4Z AG27 VDD_CT#4 VDDC#20 AC27
1 1 1 2 1

do
VDDC#21 AD13 1 2 1 2 1 2
AD16 CV142 10U_0603_6.3V6M CV143 1U_0402_6.3V4Z CV144 1U_0402_6.3V4Z
I/O VDDC#22
60mA VDDC#23 AD18 1 2 1 2 1 2
+3VS_DELAY AF23 AD21 CV145 1U_0402_6.3V4Z CV146 1U_0402_6.3V4Z CV147 1U_0402_6.3V4Z
VDDR3#1 VDDC#24
1 2 AF24 VDDR3#2 VDDC#25 AD23 1 2 1 2 1 2
CV148 10U_0603_6.3V6M AG23 AD26 CV149 1U_0402_6.3V4Z CV150 1U_0402_6.3V4Z CV151 1U_0402_6.3V4Z
VDDR3#3 VDDC#26
1 2 AG24 VDDR3#4 VDDC#27 AF17 1 2 1 2 1 2
BLM18PG121SN1D_0603 CV152 1U_0402_6.3V4Z AF20 CV153 1U_0402_6.3V4Z CV154 1U_0402_6.3V4Z CV155 1U_0402_6.3V4Z
VDDC#28

in
+1.8VS 2 1 0.1U_0402_16V4Z +VDDR5 1 2 AF22 1 2 1 2
LV23 CV158 1U_0402_6.3V4Z VDDC#29 CV159 1U_0402_6.3V4Z CV160 1U_0402_6.3V4Z
1 1 1 170mA AF13 VDDR5#1 VDDC#30 AG16
CV156 CV157 CV161 1 2 AF15 AG18 1 2 1 2
CV162 1U_0402_6.3V4Z +VDDR5 VDDR5#2 VDDC#31 CV163 1U_0402_6.3V4Z CV164 1U_0402_6.3V4Z
AG13 VDDR5#3 VDDC#32 AG21
10U_0603_6.3V6M 1U_0402_6.3V4Z AG15 AH22 1 2 1 2
2 2 2 VDDR5#4 VDDC#33 CV165 1U_0402_6.3V4Z CV166 1U_0402_6.3V4Z
VDDC#34 M16
170mA VDDC#35 M18 1 2 1 2
AD12 M23 CV167 1U_0402_6.3V4Z CV168 1U_0402_6.3V4Z
VDDR4#1 VDDC#36

i-
+VDDR4 AF11 M26 1 2 1 2
VDDR4#2 VDDC#37 CV169 1U_0402_6.3V4Z CV170 1U_0402_6.3V4Z
AF12 VDDR4#3 VDDC#38 N15
AG11 VDDR4#4 VDDC#39 N17 1 2 1 2
N20 CV174 1U_0402_6.3V4Z CV175 1U_0402_6.3V4Z
VDDC#40
VDDC#41 N22 1 2 1 2
BLM18PG121SN1D_0603 N24 CV176 1U_0402_6.3V4Z CV177 1U_0402_6.3V4Z
0.1U_0402_16V4Z +VDDR4 BLM18PG121SN1D_0603 MEM CLK VDDC#42
+1.8VS 2 1 VDDC#43 N27 1 2 1 2
LV24 1 1 1 +1.5VS 2 1 +VDDRHA M20 R13 CV178 1U_0402_6.3V4Z CV179 1U_0402_6.3V4Z
VDDRHA VDDC#44
CV171 CV172 CV173 M9X@ LV25
is M21 VSSRHA VDDC#45
VDDC#46
R16
R18 CV181
1 2
1U_0402_6.3V4Z CV182
1 2
1U_0402_6.3V4Z
10U_0603_6.3V6M 1U_0402_6.3V4Z R21 1 2 1 2
B 2 2 2 +VDDRHB VDDC#47 CV183 1U_0402_6.3V4Z CV184 1U_0402_6.3V4Z B
V12 VDDRHB VDDC#48 R23
U12 VSSRHB VDDC#49 R26
Reserve VDDC#50 T15
VDDC#51 T17
VDDC#52 T20
kn

VDDC#53 T22
BLM18PG121SN1D_0603 PLL T24
+1.8VS 2 1 0.1U_0402_16V4Z 68mA +PCIE_PVDD AB37
VDDC#54
T27
LV27 PCIE_PVDD VDDC#55
1 1 1 VDDC#56 U16
CV186 CV187 CV188 MPV18 H7 U18
MPV18 NC_MPV18#1 VDDC#57
H8 NC_MPV18#2 VDDC#58 U21
10U_0603_6.3V6M 1U_0402_6.3V4Z U23
2 2 2 VDDC#59
VDDC#60 U26
SPV18
te

AM10 NC_SPV18 VDDC#61 V15

MANHA@ 1U_0402_6.3V4Z V17
+1.0VS 2 1
414mA +SPV10 AN9
VDDC#62
V20
LV28 BLM18PG121SN1D_0603 SPV10 VDDC#63
1 1 2 VDDC#64 V22
M9X@ CV189 CV190 CV191 AN10 V24
SPVSS VDDC#65
+VGA_CORE 2 1 VDDC#66 V27
LV37 BLM18PG121SN1D_0603 Y16
2 2 1 VDDC#67
VDDC#68 Y18
LV30 MANHA@ 10U_0603_6.3V6M 0.1U_0402_16V4Z
w.

VDDC#69 Y21
+1.8VS 2 1 0.1U_0402_16V4Z MPV18 BACK BIAS Y23
BLM18PG121SN1D_0603 VDDC#70
VDDC#71 Y26
1 1 1 +VGA_CORE AA13 BBP#1 VDDC#72 Y28
Y13 BBP#2 VDDC#73 AH27 30ohm@100MHz
CV304 CV303 CV302 AH28
10U_0603_6.3V6M MANHA@ 1U_0402_6.3V4Z
2
CV195
1
CV196 VDDC#74 RDC:0.02ohm 4A 4A
MANHA@ 2 2 2 MANHA@ +VDDCI 1U_0402_6.3V4Z
M15 1 2 +VGA_CORE
ISOLATED VDDCI#1 LV29 PBY201209T-300Y-N_2P
ww

N13 1 1 1 1
1 2 CORE I/O VDDCI#2 R12 CV197 CV198 CV199
A VDDCI#3 A
0.1U_0402_16V4Z 1U_0402_6.3V4Z T12 CV200
VDDCI#4
LV31 MANHA@ 2 2 2 2
+1.8VS 2 1 0.1U_0402_16V4Z SPV18 1U_0402_6.3V4Z 1U_0402_6.3V4Z 10U_0603_6.3V6M
BLM18PG121SN1D_0603 216-0772000-PRO_FCBGA962 MADISONLP@
1 1 1
CV307
10U_0603_6.3V6M
CV305
MANHA@
CV306
1U_0402_6.3V4Z
Security Classification Compal Secret Data Compal Electronics, Inc.
2 2 2 MANHA@ Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title
MANHA@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401849 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 18, 2010 Sheet 16 of 58
5 4 3 2 1
 5 4 3 2 1

UV1F

AB39 PCIE_VSS#1 GND#1 A3

E39 PCIE_VSS#2 GND#2 A37
F34 PCIE_VSS#3 GND#3 AA16
F39 PCIE_VSS#4 GND#4 AA18
G33 PCIE_VSS#5 GND#5 AA2
G34 PCIE_VSS#6 GND#6 AA21
H31 PCIE_VSS#7 GND#7 AA23
H34 PCIE_VSS#8 GND#8 AA26
H39 AA28

m
PCIE_VSS#9 GND#9
J31 PCIE_VSS#10 GND#10 AA6
D D
J34 PCIE_VSS#11 GND#11 AB12
K31 PCIE_VSS#12 GND#12 AB15
K34 PCIE_VSS#13 GND#13 AB17

co
K39 PCIE_VSS#14 GND#14 AB20
L31 PCIE_VSS#15 GND#15 AB22
L34 PCIE_VSS#16 GND#16 AB24
M34 PCIE_VSS#17 GND#17 AB27
M39 PCIE_VSS#18 GND#18 AC11
N31 PCIE_VSS#19 GND#19 AC13
N34 PCIE_VSS#20 GND#20 AC16
P31 PCIE_VSS#21 GND#21 AC18

a.
P34 PCIE_VSS#22 GND#22 AC2
P39 PCIE_VSS#23 GND#23 AC21
R34 PCIE_VSS#24 GND#24 AC23
T31 PCIE_VSS#25 GND#25 AC26
T34 PCIE_VSS#26 GND#26 AC28
T39 PCIE_VSS#27 GND#27 AC6
U31 PCIE_VSS#28 GND#28 AD15
U34 PCIE_VSS#29 GND#29 AD17
V34 AD20

si
PCIE_VSS#30 GND#30
V39 PCIE_VSS#31 GND#31 AD22
W31 PCIE_VSS#32 GND#32 AD24
W34 PCIE_VSS#33 GND#33 AD27
Y34 PCIE_VSS#34 GND#34 AD9
Y39 PCIE_VSS#35 GND#35 AE2
GND#36 AE6
GND#37 AF10
GND#38 AF16

ne
GND#39 AF18
AF21

F15 GND#101
GND GND#40
GND#41
GND#42
AG17
AG2
C C
F17 GND#102 GND#43 AG20
F19 GND#103 GND#44 AG22
F21 GND#104 GND#45 AG6
F23 GND#105 GND#46 AG9
F25 AH21

do
GND#106 GND#47
F27 GND#107 GND#48 AH29
F29 GND#108 GND#49 AJ10
F31 GND#109 GND#50 AJ11
F33 GND#110 GND#51 AJ2
F7 GND#111 GND#52 AJ28
F9 GND#112 GND#53 AJ6
G2 GND#113 GND#54 AK11
G6 GND#114 GND#55 AK31

in
H9 GND#115 GND#56 AK7
J2 GND#116 GND#57 AL11
J27 GND#117 GND#58 AL14
J6 GND#118 GND#59 AL17
J8 GND#119 GND#60 AL2
K14 GND#120 GND#61 AL20
K7 GND#121 GND#62 AL21
L11 GND#122 GND#63 AL23

i-
L17 GND#123 GND#64 AL26
L2 GND#124 GND#65 AL32
L22 GND#125 GND#66 AL6
L24 GND#126 GND#67 AL8
L6 GND#127 GND#68 AM11
M17 GND#128 GND#69 AM31
M22 GND#129 GND#70 AM9
M24 GND#130 GND#71 AN11
N16 AN2
N18
N2
GND#131
GND#132
GND#133
GND#72
GND#73
GND#74
is
AN30
AN6
B B
N21 GND#134 GND#75 AN8
N23 GND#135 GND#76 AP11
N26 GND#136 GND#77 AP7
N6 GND#137 GND#78 AP9
R15 GND#138 GND#79 AR5
R17 GND#139 GND#80 AW34
kn

R2 GND#140 GND#81 B11

R20 GND#141 GND#82 B13
R22 GND#142 GND#83 B15
R24 GND#143 GND#84 B17
R27 GND#144 GND#85 B19
R6 GND#145 GND#86 B21
T11 GND#146 GND#87 B23
T13 GND#147 GND#88 B25
T16 B27
te

GND#148 GND#89
T18 GND#149 GND#90 B29
T21 GND#150 GND#91 B31
T23 GND#151 GND#92 B33
T26 GND#152 GND#93 B7
U15 GND#153 GND#94 B9
U17 GND#154 GND#95 C1
U2 GND#155 GND#96 C39
U20 GND#156 GND#97 E35
w.

U22 GND#157 GND#98 E5

U24 GND#158 GND#99 F11
U27 GND#159 GND#100 F13
U6 GND#160
V11 GND#161
V16 GND#162
V18 GND#163
V21 GND#164
V23
ww

A GND#165 A
V26 GND#166
W2 GND#167
W6 GND#168
Y15 GND#169
Y17 GND#170
Y20 GND#171
Y22 GND#172 VSS_MECH#1 A39
Y24 AW1
Y27
GND#173
GND#174
VSS_MECH#2
VSS_MECH#3 AW39
Security Classification Compal Secret Data Compal Electronics, Inc.
U13 GND#175 Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title
V13 GND#176
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
216-0772000-PRO_FCBGA962 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401849 B
MADISONLP@ MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 18, 2010 Sheet 17 of 58
5 4 3 2 1
 5 4 3 2 1

MDB[0..63]
MDA[0..63] MDB[0..63] 20
MDA[0..63] 19

Park-M2 uses memory group B only

m
UV1C
D UV1D D

co
MDA0 C37 G24 MAA0 MAA[13..0]
DQA_0 MAA_0 MAA[13..0] 19 MAB[13..0]
MDA1 C35 J23 MAA1 MDB0 C5 P8 MAB0

MEMORY INTERFACE A
DQA_1 MAA_1 DQB_0 MAB_0 MAB[13..0] 20
MDA2 A35 H24 MAA2 MDB1 C3 T9 MAB1

MEMORY INTERFACE B
MDA3 DQA_2 MAA_2 MAA3 MDB2 DQB_1 MAB_1 MAB2
E34 DQA_3 MAA_3 J24 E3 DQB_2 MAB_2 P9
MDA4 G32 H26 MAA4 MDB3 E1 N7 MAB3
MDA5 DQA_4 MAA_4 MAA5 MDB4 DQB_3 MAB_3 MAB4
D33 DQA_5 MAA_5 J26 F1 DQB_4 MAB_4 N8
MDA6 F32 H21 MAA6 MDB5 F3 N9 MAB5
MDA7 DQA_6 MAA_6 MAA7 MDB6 DQB_5 MAB_5 MAB6
E32 DQA_7 MAA_7 G21 F5 DQB_6 MAB_6 U9
MDA8 MAA8 MDB7 MAB7

a.
D31 DQA_8 MAA_8 H19 G4 DQB_7 MAB_7 U8
MDA9 F30 H20 MAA9 MDB8 H5 Y9 MAB8
MDA10 DQA_9 MAA_9 MAA10 MDB9 DQB_8 MAB_8 MAB9
C30 DQA_10 MAA_10 L13 H6 DQB_9 MAB_9 W9
MDA11 A30 G16 MAA11 A_BA[2..0] MDB10 J4 AC8 MAB10
DQA_11 MAA_11 A_BA[2..0] 19 DQB_10 MAB_10
MDA12 F28 J16 MAA12 MDB11 K6 AC9 MAB11
MDA13 DQA_12 MAA_12 A_BA2 MDB12 DQB_11 MAB_11 MAB12
C28 DQA_13 MAA_13/BA2 H16 K5 DQB_12 MAB_12 AA7
MDA14 A28 J17 A_BA0 MDB13 L4 AA8 B_BA2 B_BA[2..0]
DQA_14 MAA_14/BA0 DQB_13 MAB_13/BA2 B_BA[2..0] 20
MDA15 E28 H17 A_BA1 MDB14 M6 Y8 B_BA0
MDA16 DQA_15 MAA_15/BA1 MDB15 DQB_14 MAB_14/BA0 B_BA1
D27 M1 AA9

si
MDA17 DQA_16 DQMA#0 MDB16 DQB_15 MAB_15/BA1
F26 DQA_17 DQMA_0 A32 DQMA#[7..0] 19 M3 DQB_16
MDA18 C26 C32 DQMA#1 MDB17 M5 H3 DQMB#0
DQA_18 DQMA_1 DQB_17 DQMB_0 DQMB#[7..0] 20
MDA19 A26 D23 DQMA#2 MDB18 N4 H1 DQMB#1
MDA20 DQA_19 DQMA_2 DQMA#3 MDB19 DQB_18 DQMB_1 DQMB#2
F24 DQA_20 DQMA_3 E22 P6 DQB_19 DQMB_2 T3
MDA21 C24 C14 DQMA#4 MDB20 P5 T5 DQMB#3
MDA22 A24
DQA_21
DQA_22
DQMA_4
DQMA_5 A14 DQMA#5 Close to pin Y12 MDB21 R4
DQB_20
DQB_21
DQMB_3
DQMB_4 AE4 DQMB#4
MDA23 E24 E10 DQMA#6 +1.5VS MDB22 T6 AF5 DQMB#5
MDA24 DQA_23 DQMA_6 DQMA#7 MDB23 DQB_22 DQMB_5 DQMB#6
C22 DQA_24 DQMA_7 D9 T1 DQB_23 DQMB_6 AK6

ne
MDA25 A22 MDB24 U4 AK5 DQMB#7
DQA_25 DQB_24 DQMB_7

1
MDA26 F22 C34 QSA0 MDB25 V6
DQA_26 QSA_0/RDQSA_0 QSA[7..0] 19 DQB_25
MDA27 D21 D29 QSA1 RV42 RV42 MDB26 V1 F6 QSB0
DQA_27 QSA_1/RDQSA_1 DQB_26 QSB_0/RDQSB_0 QSB[7..0] 20
MDA28 A20 D25 QSA2 40.2_0402_1% 100_0402_1% MDB27 V3 K3 QSB1
C Close to pin L18 MDA29 F20
DQA_28
DQA_29
QSA_2/RDQSA_2
QSA_3/RDQSA_3 E20 QSA3 MANHA@ M9X@ MDB28 Y6
DQB_27
DQB_28
QSB_1/RDQSB_1
QSB_2/RDQSB_2 P3 QSB2 C
+1.5VS MDA30 D19 E16 QSA4 MDB29 Y1 V5 QSB3

2
MDA31 DQA_30 QSA_4/RDQSA_4 QSA5 MDB30 DQB_29 QSB_3/RDQSB_3 QSB4
E18 DQA_31 QSA_5/RDQSA_5 E12 Y3 DQB_30 QSB_4/RDQSB_4 AB5
MDA32 C18 J10 QSA6 +MVREFDB MDB31 Y5 AH1 QSB5
DQA_32 QSA_6/RDQSA_6 DQB_31 QSB_5/RDQSB_5
1

MDA33 A18 D7 QSA7 MDB32 AA4 AJ9 QSB6

do
RV41 RV41 MDA34 DQA_33 QSA_7/RDQSA_7 MDB33 DQB_32 QSB_6/RDQSB_6 QSB7
F18 DQA_34 1 AB6 DQB_33 QSB_7/RDQSB_7 AM5

1
40.2_0402_1% 100_0402_1% MDA35 D17 A34 QSA#0 CV203 MDB34 AB1
DQA_35 QSA_0B/WDQSA_0 QSA#[7..0] 19 DQB_34
MANHA@ M9X@ MDA36 A16 E30 QSA#1 RV44 MDB35 AB3 G7 QSB#0
DQA_36 QSA_1B/WDQSA_1 DQB_35 QSB_0B/WDQSB_0 QSB#[7..0] 20
MDA37 F16 E26 QSA#2 100_0402_1% 0.1U_0402_16V4Z MDB36 AD6 K1 QSB#1
2

MDA38 DQA_37 QSA_2B/WDQSA_2 QSA#3 2 MDB37 DQB_36 QSB_1B/WDQSB_1 QSB#2

D15 DQA_38 QSA_3B/WDQSA_3 C20 AD1 DQB_37 QSB_2B/WDQSB_2 P1
+MVREFDA MDA39 E14 C16 QSA#4 MDB38 AD3 W4 QSB#3

2
MDA40 DQA_39 QSA_4B/WDQSA_4 QSA#5 MDB39 DQB_38 QSB_3B/WDQSB_3 QSB#4
F14 DQA_40 QSA_5B/WDQSA_5 C12 AD5 DQB_39 QSB_4B/WDQSB_4 AC4
1 MDA41 D13 J11 QSA#6 MDB40 AF1 AH3 QSB#5
DQA_41 QSA_6B/WDQSA_6 DQB_40 QSB_5B/WDQSB_5
1

in
MDA42 F12 F8 QSA#7 MDB41 AF3 AJ8 QSB#6
RV43 CV202 MDA43 DQA_42 QSA_7B/WDQSA_7 MDB42 DQB_41 QSB_6B/WDQSB_6 QSB#7
A12 DQA_43 AF6 DQB_42 QSB_7B/WDQSB_7 AM3
100_0402_1% 0.1U_0402_16V4Z MDA44 D11 J21 ODTA0 MDB43 AG4
2 DQA_44 ODTA0 ODTA0 19 DQB_43
MDA45 F10 G19 ODTA1 MDB44 AH5 T7 ODTB0
DQA_45 ODTA1 ODTA1 19 DQB_44 ODTB0 ODTB0 20
MDA46 A10 MDB45 AH6 W7 ODTB1
Close to pin AA12 ODTB1 20
2

MDA47 DQA_46 CLKA0 MDB46 DQB_45 ODTB1

C10 DQA_47 CLKA0 H27 CLKA0 19 AJ4 DQB_46
MDA48 G13 G27 CLKA0# +1.5VS MDB47 AK3 L9 CLKB0
DQA_48 CLKA0B CLKA0# 19 DQB_47 CLKB0 CLKB0 20
MDA49 H13 MDB48 AF8 L8 CLKB0#
DQA_49 DQB_48 CLKB0B CLKB0# 20
MDA50 CLKA1 MDB49

i-
J13 DQA_50 CLKA1 J14 CLKA1 19 AF9 DQB_49

1
MDA51 H11 H14 CLKA1# MDB50 AG8 AD8 CLKB1
DQA_51 CLKA1B CLKA1# 19 DQB_50 CLKB1 CLKB1 20
MDA52 G10 RV46 RV46 MDB51 AG7 AD7 CLKB1#
DQA_52 DQB_51 CLKB1B CLKB1# 20
MDA53 G8 K23 RASA0# 40.2_0402_1% 100_0402_1% MDB52 AK9
DQA_53 RASA0B RASA0# 19 DQB_52
MDA54 K9 K19 RASA1# MANHA@ M9X@ MDB53 AL7 T10 RASB0#
DQA_54 RASA1B RASA1# 19 DQB_53 RASB0B RASB0# 20
MDA55 K10 MDB54 AM8 Y10 RASB1#
RASB1# 20

2
MDA56 DQA_55 CASA0# +MVREFSB MDB55 DQB_54 RASB1B
G9 DQA_56 CASA0B K20 CASA0# 19 AM7 DQB_55
MDA57 A8 K17 CASA1# MDB56 AK1 W10 CASB0#
DQA_57 CASA1B CASA1# 19 DQB_56 CASB0B CASB0# 20
MDA58 C8 MDB57 AL4 AA10 CASB1#
CASB1# 20
DQA_58
is DQB_57 CASB1B

1
MDA59 E8 K24 CSA0#_0 1 MDB58 AM6
DQA_59 CSA0B_0 CSA0#_0 19 DQB_58
MDA60 A6 K27 RV52 CV205 MDB59 AM1 P10 CSB0#_0
B DQA_60 CSA0B_1 DQB_59 CSB0B_0 CSB0#_0 20 B
MDA61 C6 100_0402_1% MDB60 AN4 L10
MDA62 DQA_61 CSA1#_0 0.1U_0402_16V4Z MDB61 DQB_60 CSB0B_1
E6 DQA_62 CSA1B_0 M13 CSA1#_0 19 AP3 DQB_61
MDA63 2 MDB62 CSB1#_0
A5 K16 AP1 AD10 CSB1#_0 20

2
DQA_63 CSA1B_1 MDB63 DQB_62 CSB1B_0
AP5 DQB_63 CSB1B_1 AC10
+MVREFDA L18 K21 CKEA0
+1.5VS MVREFDA CKEA0 CKEA0 19
+MVREFSA L20 J20 CKEA1 U10 CKEB0
MVREFSA CKEA1 CKEA1 19 CKEB0 CKEB0 20
kn
+MVREFDB Y12 AA11 CKEB1
MVREFDB CKEB1 CKEB1 20
MANHA@ 1 RV48 2 243_0402_1% L27 K26 WEA0# +MVREFSB AA12
NC_MEM_CALRN0 WEA0B WEA0# 19 MVREFSB
MANHA@ 1 RV49 2 243_0402_1% N12 L15 WEA1# N10 WEB0#
NC_MEM_CALRN1 WEA1B WEA1# 19 WEB0B WEB0# 20
MANHA@ 1 RV50 2 243_0402_1% AG12 AB11 WEB1#
NC_MEM_CALRN2 WEB1B WEB1# 20
Close to pin L20 RSVD#1 AF28 Debug Only, for clock observation
1 RV51 2 243_0402_1% M12 MEM_CALRP1 RSVD#2 AG28 RV54 M9X@
+1.5VS MANHA@ 1 RV53 2 243_0402_1% M27 AL31 TESTEN AD28 RV132 2 1
NC_MEM_CALRP0 RSVD#3 TESTEN +1.5VS
MANHA@ 1 RV55 2 243_0402_1% AH12 @ @ 0_0402_5% 4.7K_0402_5%
NC_MEM_CALRP2 MAA13 +3VS_DELAY RV57 2
H23 1 51_0402_5% CV320 1 2 0.1U_0402_16V4Z AK10 M9X@ MANHA@
te

RSVD#5 CLKTESTA
1

RSVD#6 J19 2 1 1 2 AL10 CLKTESTB DRAM_RST AH11 2 1 DRAM_RST# 19,20

RV45 RV45 RV58 51_0402_5% CV321 0.1U_0402_16V4Z RV132 51_0402_5%
1

1
40.2_0402_1% 100_0402_1% T8 MAB13 @ @ 1
MANHA@ M9X@ RSVD#9 @
RSVD#11 W8
RV56 CV206 RV59
2

+MVREFSA 10K_0402_5% RV57 RV58 CV320 CV321 68P_0402_50V8J 10K_0402_5%

216-0772000-PRO_FCBGA962 4.7K_0402_5% 4.7K_0402_5% 0_0402_5% 0_0402_5% 216-0772000-PRO_FCBGA962 2 MANHA@ MANHA@
2

2
MADISONLP@ TESTEN M9X@ M9X@ M9X@ M9X@ MADISONLP@
1

w.

1
1

RV47 CV204
100_0402_1% 0.1U_0402_16V4Z CV206
RV23 0.01U_0402_25V7K
2 10K_0402_5% M9X@
2

2
ww

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401849 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 18, 2010 Sheet 18 of 58
5 4 3 2 1
 5 4 3 2 1

UV2 UV3 UV4 UV5

+VREFC_A1 M8 E3 MDA22 +VREFC_A2 M8 E3 MDA25 +VREFC_A3 M8 E3 MDA35 +VREFC_A4 M8 E3 MDA48

+VREFD_A1 H1 VREFCA DQL0 MDA19 +VREFD_A2 VREFCA DQL0 MDA30 +VREFD_A3 VREFCA DQL0 MDA32 +VREFD_A4 VREFCA DQL0 MDA51
VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7
F2 MDA21 F2 MDA24 F2 MDA38 F2 MDA55
MAA0 DQL2 MDA18 MAA0 DQL2 MDA29 MAA0 DQL2 MDA34 MAA0 DQL2 MDA54
N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8
MAA1 P7 H3 MDA23 Group2 MAA1 P7 H3 MDA26 Group3 MAA1 P7 H3 MDA37 Group4 MAA1 P7 H3 MDA50 Group6
MDA[0..63] MAA2 A1 DQL4 MDA16 MAA2 A1 DQL4 MDA31 MAA2 A1 DQL4 MDA36 MAA2 A1 DQL4 MDA52
18 MDA[0..63] P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8
MAA3 N2 G2 MDA20 MAA3 N2 G2 MDA27 MAA3 N2 G2 MDA39 MAA3 N2 G2 MDA49
MAA4 A3 DQL6 MDA17 MAA4 A3 DQL6 MDA28 MAA4 A3 DQL6 MDA33 MAA4 A3 DQL6 MDA53
P8 A4 DQL7 H7 P8 A4 DQL7 H7 P8 A4 DQL7 H7 P8 A4 DQL7 H7
MAA5 P2 MAA5 P2 MAA5 P2 MAA5 P2
MAA6 A5 MAA6 A5 MAA6 A5 MAA6 A5
R8 R8 R8 R8

m
MAA7 A6 MDA0 MAA7 A6 MDA15 MAA7 A6 MDA43 MAA7 A6 MDA63
R2 A7 DQU0 D7 R2 A7 DQU0 D7 R2 A7 DQU0 D7 R2 A7 DQU0 D7
D MAA8 MDA5 MAA8 MDA11 MAA8 MDA44 MAA8 MDA58 D
T8 A8 DQU1 C3 T8 A8 DQU1 C3 T8 A8 DQU1 C3 T8 A8 DQU1 C3
MAA9 R3 C8 MDA1 MAA9 R3 C8 MDA14 MAA9 R3 C8 MDA40 MAA9 R3 C8 MDA60
MAA10 A9 DQU2 MDA7 MAA10 A9 DQU2 MDA10 MAA10 A9 DQU2 MDA45 MAA10 A9 DQU2 MDA59
18 MAA[13..0] L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2

co
MAA11 R7 A7 MDA3 Group0 MAA11 R7 A7 MDA13 Group1 MAA11 R7 A7 MDA42 Group5 MAA11 R7 A7 MDA61 Group7
MAA12 A11 DQU4 MDA4 MAA12 A11 DQU4 MDA9 MAA12 A11 DQU4 MDA46 MAA12 A11 DQU4 MDA56
N7 A12 DQU5 A2 N7 A12 DQU5 A2 N7 A12 DQU5 A2 N7 A12 DQU5 A2
MAA13 T3 B8 MDA2 MAA13 T3 B8 MDA12 MAA13 T3 B8 MDA41 MAA13 T3 B8 MDA62
A13 DQU6 MDA6 A13 DQU6 MDA8 A13 DQU6 MDA47 A13 DQU6 MDA57
T7 A14 DQU7 A3 T7 A14 DQU7 A3 T7 A14 DQU7 A3 T7 A14 DQU7 A3
18 DQMA#[7..0] M7 A15/BA3 M7 A15/BA3 M7 A15/BA3 M7 A15/BA3
+1.5VS +1.5VS +1.5VS +1.5VS

M2 B2 A_BA0 M2 B2 A_BA0 M2 B2 A_BA0 M2 B2

18 A_BA0 BA0 VDD BA0 VDD BA0 VDD BA0 VDD
A_BA1 A_BA1 A_BA1

a.
18 A_BA1 N8 BA1 VDD D9 N8 BA1 VDD D9 N8 BA1 VDD D9 N8 BA1 VDD D9
M3 G7 A_BA2 M3 G7 A_BA2 M3 G7 A_BA2 M3 G7
18 QSA[7..0] 18 A_BA2 BA2 VDD BA2 VDD BA2 VDD BA2 VDD
VDD K2 VDD K2 VDD K2 VDD K2
VDD K8 VDD K8 VDD K8 VDD K8
VDD N1 VDD N1 VDD N1 VDD N1
J7 N9 CLKA0 J7 N9 J7 N9 CLKA1 J7 N9
18 CLKA0 CK VDD CK VDD 18 CLKA1 CK VDD CK VDD
K7 R1 CLKA0# K7 R1 K7 R1 CLKA1# K7 R1
18 QSA#[7..0] 18 CLKA0# CK VDD CK VDD 18 CLKA1# CK VDD CK VDD
K9 R9 CKEA0 K9 R9 K9 R9 CKEA1 K9 R9
18 CKEA0 CKE/CKE0 VDD +1.5VS CKE/CKE0 VDD +1.5VS18 CKEA1 CKE/CKE0 VDD +1.5VS CKE/CKE0 VDD +1.5VS

si
K1 A1 ODTA0 K1 A1 K1 A1 ODTA1 K1 A1
18 ODTA0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ 18 ODTA1 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
L2 A8 CSA0#_0 L2 A8 L2 A8 CSA1#_0 L2 A8
A_BA[2..0] 18 CSA0#_0 CS/CS0 VDDQ CS/CS0 VDDQ 18 CSA1#_0 CS/CS0 VDDQ CS/CS0 VDDQ
J3 C1 RASA0# J3 C1 J3 C1 RASA1# J3 C1
18 A_BA[2..0] 18 RASA0# RAS VDDQ RAS VDDQ 18 RASA1# RAS VDDQ RAS VDDQ
K3 C9 CASA0# K3 C9 K3 C9 CASA1# K3 C9
18 CASA0# CAS VDDQ CAS VDDQ 18 CASA1# CAS VDDQ CAS VDDQ
L3 D2 WEA0# L3 D2 L3 D2 WEA1# L3 D2
18 WEA0# WE VDDQ WE VDDQ 18 WEA1# WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9 VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1

ne
QSA2 F3 H2 QSA3 F3 H2 QSA4 F3 H2 QSA6 F3 H2
QSA0 DQSL VDDQ QSA1 DQSL VDDQ QSA5 DQSL VDDQ QSA7 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9

C DQMA#2 DQMA#3 DQMA#4 DQMA#6 C

E7 DML VSS A9 E7 DML VSS A9 E7 DML VSS A9 E7 DML VSS A9
DQMA#0 D3 B3 DQMA#1 D3 B3 DQMA#5 D3 B3 DQMA#7 D3 B3
DMU VSS DMU VSS DMU VSS DMU VSS
VSS E1 VSS E1 VSS E1 VSS E1
VSS G8 VSS G8 VSS G8 VSS G8
QSA#2 G3 J2 QSA#3 G3 J2 QSA#4 G3 J2 QSA#6 G3 J2

do
QSA#0 DQSL VSS QSA#1 DQSL VSS QSA#5 DQSL VSS QSA#7 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8 B7 DQSU VSS J8 B7 DQSU VSS J8
VSS M1 VSS M1 VSS M1 VSS M1
VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
T2 P9 DRAM_RST# T2 P9 DRAM_RST# T2 P9 DRAM_RST# T2 P9
18,20 DRAM_RST# RESET VSS RESET VSS RESET VSS RESET VSS
VSS T1 VSS T1 VSS T1 VSS T1
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9

in
1

1
J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1
RV61 L1 B9 RV62 L1 B9 RV63 L1 B9 RV64 L1 B9
NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1
L9 NCZQ1 VSSQ D8 L9 NCZQ1 VSSQ D8 L9 NCZQ1 VSSQ D8 L9 NCZQ1 VSSQ D8
E2 E2 E2 E2
2

2
VSSQ VSSQ VSSQ VSSQ
VSSQ E8 VSSQ E8 VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
8PCS@ 8PCS@ 8PCS@ 8PCS@

i-
VSSQ G1 VSSQ G1 VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9 VSSQ G9 VSSQ G9

96-BALL 96-BALL 96-BALL 96-BALL

SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
+1.5VS @ +1.5VS is +1.5VS @ +1.5VS +1.5VS @ +1.5VS +1.5VS @ +1.5VS
1

1
1

8PCS@ 8PCS@ RV67 8PCS@ RV68 8PCS@ RV69 8PCS@ RV70 8PCS@ RV71 8PCS@ RV72 8PCS@
B RV65 RV66 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% B
4.99K_0402_1% 4.99K_0402_1%
2

2
+VREFC_A2 +VREFD_A2 +VREFC_A3 +VREFD_A3 +VREFC_A4 +VREFD_A4
2

+VREFC_A1 +VREFD_A1
1

1
1 1 1 1 1 1
1

kn

1 1 RV77 CV207 RV78 CV211 RV79 CV208 RV74 CV212 RV75 CV213 RV80 CV214
RV73 CV209 RV76 CV210 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
4.99K_0402_1% 0.1U_0402_16V4Z 4.99K_0402_1% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z 2 2 2 2 2 2
2

2
2 2
2

8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@
8PCS@ 8PCS@

+1.5VS +1.5VS +1.5VS

te

+1.5VS
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
CLKA0 1 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z
RV81 56_0402_1% 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CV217

CV218

CV219

CV220

CV221

CV222

CV223

CV224

CV237

CV225

CV226

CV238

CV239

CV227

CV240

CV228

CV241

CV229

CV242

CV243

CV230
8PCS@ 1 1 1 1 1 1 1
CV231

CV215

CV232

CV216

CV233

CV235

CV236

CLKA0# 1 2 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
w.

RV82 56_0402_1%
CV234 2 2 2 2 2 2 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
8PCS@
0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 8PCS@ 8PCS@1U_0402_6.3V4Z 1U_0402_6.3V4Z
2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@
8PCS@ 8PCS@8PCS@8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@

CLKA1 1 2 +1.5VS 10U_0603_6.3V 10U_0603_6.3V +1.5VS 10U_0603_6.3V 10U_0603_6.3V

RV83 56_0402_1%
ww

1 1 1 1 1 1 1 1
A A
8PCS@
CV246 CV247 CV248 CV249 CV250 CV251 CV244 CV245
CLKA1# 1 2
RV84 56_0402_1% 2 2 2 2 2 2 2 2
1
8PCS@ CV252 10U_0603_6.3V 10U_0603_6.3V 10U_0603_6.3V 10U_0603_6.3V
0.1U_0402_16V4Z 8PCS@ 8PCS@ 8PCS@ 8PCS@
2 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401849 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 18, 2010 Sheet 19 of 58
5 4 3 2 1
 5 4 3 2 1

UV6 UV7 UV8 UV9

+VREFC_B1 M8 E3 MDB26 +VREFC_B2 M8 E3 MDB22 +VREFC_B3 M8 E3 MDB34 +VREFC_B4 M8 E3 MDB52

+VREFD_B1 VREFCA DQL0 MDB28 +VREFD_B2 VREFCA DQL0 MDB20 +VREFD_B3 VREFCA DQL0 MDB37 +VREFD_B4 VREFCA DQL0 MDB51
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7
F2 MDB27 F2 MDB21 F2 MDB32 F2 MDB55
MAB0 DQL2 MDB31 MAB0 DQL2 MDB18 MAB0 DQL2 MDB39 MAB0 DQL2 MDB48
N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8
MAB1 P7 H3 MDB25 Group3 MAB1 P7 H3 MDB19 Group2 MAB1 P7 H3 MDB35 Group4 MAB1 P7 H3 MDB53 Group6
MAB2 A1 DQL4 MDB30 MAB2 A1 DQL4 MDB17 MAB2 A1 DQL4 MDB38 MAB2 A1 DQL4 MDB49
P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8
MAB3 N2 G2 MDB24 MAB3 N2 G2 MDB23 MAB3 N2 G2 MDB33 MAB3 N2 G2 MDB54
MDB[0..63] MAB4 A3 DQL6 MDB29 MAB4 A3 DQL6 MDB16 MAB4 A3 DQL6 MDB36 MAB4 A3 DQL6 MDB50
18 MDB[0..63] P8 A4 DQL7 H7 P8 A4 DQL7 H7 P8 A4 DQL7 H7 P8 A4 DQL7 H7
MAB5 P2 MAB5 P2 MAB5 P2 MAB5 P2

m
MAB6 A5 MAB6 A5 MAB6 A5 MAB6 A5
R8 A6 R8 A6 R8 A6 R8 A6
D MAB7 MDB15 MAB7 MDB1 MAB7 MDB44 MAB7 MDB56 D
R2 A7 DQU0 D7 R2 A7 DQU0 D7 R2 A7 DQU0 D7 R2 A7 DQU0 D7
MAB8 T8 C3 MDB10 MAB8 T8 C3 MDB6 MAB8 T8 C3 MDB43 MAB8 T8 C3 MDB59
18 MAB[13..0] A8 DQU1 A8 DQU1 A8 DQU1 A8 DQU1
MAB9 R3 C8 MDB12 MAB9 R3 C8 MDB0 MAB9 R3 C8 MDB47 MAB9 R3 C8 MDB63
A9 DQU2 A9 DQU2 A9 DQU2 A9 DQU2

co
MAB10 L7 C2 MDB11 MAB10 L7 C2 MDB4 MAB10 L7 C2 MDB41 MAB10 L7 C2 MDB62
MAB11 A10/AP DQU3 MDB13 MAB11 A10/AP DQU3 MDB3 MAB11 A10/AP DQU3 MDB45 MAB11 A10/AP DQU3 MDB57
R7 A11 DQU4 A7 Group1 R7 A11 DQU4 A7 Group0 R7 A11 DQU4 A7 Group5 R7 A11 DQU4 A7 Group7
MAB12 N7 A2 MDB9 MAB12 N7 A2 MDB7 MAB12 N7 A2 MDB40 MAB12 N7 A2 MDB61
MAB13 A12 DQU5 MDB14 MAB13 A12 DQU5 MDB2 MAB13 A12 DQU5 MDB46 MAB13 A12 DQU5 MDB58
18 DQMB#[7..0] T3 A13 DQU6 B8 T3 A13 DQU6 B8 T3 A13 DQU6 B8 T3 A13 DQU6 B8
T7 A3 MDB8 T7 A3 MDB5 T7 A3 MDB42 T7 A3 MDB60
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
M7 A15/BA3 M7 A15/BA3 M7 A15/BA3 M7 A15/BA3
+1.5VS +1.5VS +1.5VS +1.5VS

B_BA0 B_BA0 B_BA0

a.
18 QSB[7..0] 18 B_BA0 M2 BA0 VDD B2 M2 BA0 VDD B2 M2 BA0 VDD B2 M2 BA0 VDD B2
N8 D9 B_BA1 N8 D9 B_BA1 N8 D9 B_BA1 N8 D9
18 B_BA1 BA1 VDD BA1 VDD BA1 VDD BA1 VDD
M3 G7 B_BA2 M3 G7 B_BA2 M3 G7 B_BA2 M3 G7
18 B_BA2 BA2 VDD BA2 VDD BA2 VDD BA2 VDD
VDD K2 VDD K2 VDD K2 VDD K2
VDD K8 VDD K8 VDD K8 VDD K8
18 QSB#[7..0] VDD N1 VDD N1 VDD N1 VDD N1
J7 N9 CLKB0 J7 N9 J7 N9 CLKB1 J7 N9
18 CLKB0 CK VDD CK VDD 18 CLKB1 CK VDD CK VDD
K7 R1 CLKB0# K7 R1 K7 R1 CLKB1# K7 R1
18 CLKB0# CK VDD CK VDD 18 CLKB1# CK VDD CK VDD
K9 R9 CKEB0 K9 R9 K9 R9 CKEB1 K9 R9

si
18 CKEB0 CKE/CKE0 VDD CKE/CKE0 VDD 18 CKEB1 CKE/CKE0 VDD CKE/CKE0 VDD
+1.5VS +1.5VS +1.5VS +1.5VS

K1 A1 ODTB0 K1 A1 K1 A1 ODTB1 K1 A1
18 ODTB0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ 18 ODTB1 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
L2 A8 CSB0#_0 L2 A8 L2 A8 CSB1#_0 L2 A8
18 CSB0#_0 CS/CS0 VDDQ CS/CS0 VDDQ 18 CSB1#_0 CS/CS0 VDDQ CS/CS0 VDDQ
J3 C1 RASB0# J3 C1 J3 C1 RASB1# J3 C1
18 RASB0# RAS VDDQ RAS VDDQ 18 RASB1# RAS VDDQ RAS VDDQ
K3 C9 CASB0# K3 C9 K3 C9 CASB1# K3 C9
18 CASB0# CAS VDDQ CAS VDDQ 18 CASB1# CAS VDDQ CAS VDDQ
L3 D2 WEB0# L3 D2 L3 D2 WEB1# L3 D2
18 WEB0# WE VDDQ WE VDDQ 18 WEB1# WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9 VDDQ E9 VDDQ E9

ne
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
QSB3 F3 H2 QSB2 F3 H2 QSB4 F3 H2 QSB6 F3 H2
QSB1 DQSL VDDQ QSB0 DQSL VDDQ QSB5 DQSL VDDQ QSB7 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9
C C
DQMB#3 E7 A9 DQMB#2 E7 A9 DQMB#4 E7 A9 DQMB#6 E7 A9
DQMB#1 DML VSS DQMB#0 DML VSS DQMB#5 DML VSS DQMB#7 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3 D3 DMU VSS B3 D3 DMU VSS B3
VSS E1 VSS E1 VSS E1 VSS E1
G8 G8 G8 G8

do
QSB#3 VSS QSB#2 VSS QSB#4 VSS QSB#6 VSS
G3 DQSL VSS J2 G3 DQSL VSS J2 G3 DQSL VSS J2 G3 DQSL VSS J2
QSB#1 B7 J8 QSB#0 B7 J8 QSB#5 B7 J8 QSB#7 B7 J8
DQSU VSS DQSU VSS DQSU VSS DQSU VSS
VSS M1 VSS M1 VSS M1 VSS M1
VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
T2 P9 DRAM_RST# T2 P9 DRAM_RST# T2 P9 DRAM_RST# T2 P9
18,19 DRAM_RST# RESET VSS RESET VSS RESET VSS RESET VSS
VSS T1 VSS T1 VSS T1 VSS T1
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9

in
1

1
J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1
RV85 L1 B9 RV86 L1 B9 RV87 L1 B9 RV88 L1 B9
4PCS@ NC/CS1 VSSQ 4PCS@ NC/CS1 VSSQ 4PCS@ NC/CS1 VSSQ 4PCS@ NC/CS1 VSSQ
243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1
L9 NCZQ1 VSSQ D8 L9 NCZQ1 VSSQ D8 L9 NCZQ1 VSSQ D8 L9 NCZQ1 VSSQ D8
E2 E2 E2 E2
2

2
VSSQ VSSQ VSSQ VSSQ
VSSQ E8 VSSQ E8 VSSQ E8 VSSQ E8

i-
VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9 VSSQ G9 VSSQ G9

96-BALL 96-BALL 96-BALL 96-BALL

SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
+1.5VS @ +1.5VS +1.5VS @ +1.5VS +1.5VS @ +1.5VS +1.5VS @ +1.5VS
is
1

1
B RV89 RV90 RV91 RV92 4PCS@ RV93 4PCS@ RV94 4PCS@ RV95 4PCS@ RV96 4PCS@ B
4.99K_0402_1% 4PCS@ 4.99K_0402_1% 4PCS@ 4.99K_0402_1% 4PCS@ 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
2

2
+VREFC_B1 +VREFD_B1 +VREFC_B2 +VREFD_B2 +VREFC_B3 +VREFD_B3 +VREFC_B4 +VREFD_B4
1

1
kn

1 1 1 1 1 1 1 1
RV97 CV253 RV98 CV254 RV99 CV255 RV100 CV256 RV101 CV257 RV102 CV258 RV103 CV259 RV104 CV260
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
4PCS@ 2 4PCS@ 2 4PCS@ 2 4PCS@ 2 4PCS@ 2 4PCS@ 2 4PCS@ 2 4PCS@ 2
2

2
4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@

+1.5VS +1.5VS +1.5VS +1.5VS

te

1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z

1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
CLKB0 1 2
RV105 56_0402_1% 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CV261

CV262

CV263

CV264

CV265

CV266

CV267

CV268

CV269

CV270

CV271

CV272

CV273

CV274

CV275

CV287

CV276

CV277

CV278

CV279

CV280

CV281

CV282

CV283

CV284

CV288

CV285

CV286
4PCS@
CLKB0# 1 2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
w.

RV106 56_0402_1% 1
4PCS@ CV289 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z +1.5VS 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
0.1U_0402_16V4Z 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@
2 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@
1
+ CV290
+1.5VS 10U_0603_6.3V 10U_0603_6.3V 390U_2.5V_M_R10 +1.5VS 10U_0603_6.3V 10U_0603_6.3V
CLKB1 1 2 4PCS@
ww

1 1 1 1 2 1 1 1 1
A RV107 56_0402_1% A

4PCS@ CV291 CV293 CV294 CV295 CV296 CV297 CV298 CV292

CLKB1# 2 2 2 2 4PCS@ 2 2 2 2
1 2
RV108 56_0402_1% 1 10U_0603_6.3V 10U_0603_6.3V 10U_0603_6.3V 10U_0603_6.3V
4PCS@ CV299 4PCS@ 4PCS@ 4PCS@
4PCS@
0.1U_0402_16V4Z 4PCS@ 4PCS@ 4PCS@ 4PCS@
2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401849 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 18, 2010 Sheet 20 of 58
5 4 3 2 1
 5 4 3 2 1

CONFIGURATION STRAPS
GPU STRAPS
+3VS_DELAY ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET
14 GPU_GPIO0 GPU_GPIO0 @ RV109
@RV109 2 1 10K_0402_5%
14 GPU_GPIO1 GPU_GPIO1 @RV110
@ RV110 2 1 10K_0402_5%
Straps Name Pin Name Net Name DESCRIPTION OF DEFAULT SETTINGS RECOMMENDED SETTINGS
14 GPU_GPIO2 GPU_GPIO2 @ RV111
@RV111 2 1 10K_0402_5%
14 SOUT_GPIO8 SOUT_GPIO8 @RV112
@ RV112 2 1 10K_0402_5% Transmitter Power Savings Enable
TX_PWRS_ENB GPIO0 GPU_GPIO0 0: 50% Tx output swing 0
14 SIN_GPIO9 SIN_GPIO9 @RV113
@ RV113 2 1 10K_0402_5% 1: Full Tx output swing

m
D 14 ROMSE_GPIO22 @RV114
@ RV114 2 1 10K_0402_5% PCI Express Transmitter De-emphasis Enable D
TX_DEEMPH_EN GPIO1 GPU_GPIO1 0: Tx de-emphasis disabled 0
14 GPU_GPIO11 GPU_GPIO11 RV115 2 1 10K_0402_5% 1: Tx de-emphasis enabled
GPU_GPIO12 @ RV116
@RV116 1 10K_0402_5%

co
14 GPU_GPIO12 2
14 GPU_GPIO13 GPU_GPIO13 @RV117
@ RV117 2 1 10K_0402_5% PCIE GNE2 ENABLED
BIF_GEN2_EN_A GPIO2 GPU_GPIO2 0 = Advertises the PCIe device as 2.5 GT/s capable at power-on 0
14,23 VGA_CRT_HSYNC HDMI@ RV119 2 1 10K_0402_5% 1 = Advertises the PCIe device as 5.0 GT/s capable at power-on.
14,23 VGA_CRT_VSYNC HDMI@ RV118 2 1 10K_0402_5%

14 VSYNC_DAC2 @ RV121
@RV121 2 1 10K_0402_5% RESERVED GPIO_8_ROMSO SOUT_GPIO8 RESERVED 0
14 HSYNC_DAC2 @RV120
@ RV120 2 1 10K_0402_5%
VGA Controller

a.
BIF_VGA DIS GPIO_9_ROMSI SIN_GPIO9 0: VGA Controller capacity enabled
1: The device will not be recognized as the system’s VGA controller 0 (Enable)

GPU by the system BIOS GPU by VBIOS RESERVED GPIO_21_BB_EN N.C RESERVED 0 (Internal pulldown)

Enable external BIOS ROM device

GPIO22 = 0 (BIOS_ROM_EN = 0) GPIO22 = 1 (BIOS_ROM_EN = 1) BIOS_ROM_EN GPIO_22_ROMCSB ROMSE_GPIO22 0 - Disable external BIOS ROM device 0

si
1 - Enable external BIOS ROM device

GPIO[13:11] MEMORY SIZE GPIO[13:11] SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT
GPU_GPIO11 a) If BIOS_ROM_EN = 1, then Config[2:0] defines the ROM type
128MB ROMIDCFG(2:0) GPIO[13:11] GPU_GPIO12 b) If BIOS_ROM_EN = 0, then Config[2:0] defines 0 0 1
0 0 0 GPU_GPIO13 the primary memory aperture size.
256MB
1 0 0
External VGA Thermal Sensor 0 0 1
(M25P05A) VIP Device Strap Enable indicates to the software driver

ne
64MB 0 - Driver would ignore the value sampled on VHAD_0 during reset
0 1 0 VIP_DEVICE_STRAP_ENA V2SYNC VSYNC_DAC2 1 - Driver would use the value sampled at reset from VHAD_0 to 0
+3VS 1 2 determine whether or not a VIP slave device is connected
RV130 0_0402_5% 1
C C

CV300 RESERVED H2SYNC HSYNC_DAC2 RESERVED 0

0.1U_0402_16V4Z
2 AUD[1:0]:

do
UV11 00 - No audio function;
1 8 AUD[1] HSYNC VGA_CRT_HSYNC 01 - Audio for DisplayPort only;
VDD SCLK EC_SMB_CK2 26,41
14 GPU_THERMAL_D+ AUD[0] VSYNC VGA_CRT_VSYNC 10 - Audio for DisplayPort and HDMI if dongle is detected; 1 1
1 2 7 EC_SMB_DA2 26,41 11 - Audio for both DisplayPort and HDMI.
D+ SDATA
CV301 3 6
D- ALERT# THERM#_VGA 14
2200P_0402_50V7K RESERVED GENERICC GENERIC_C RESERVED 0
2
14 GPU_THERMAL_D- 4 THERM# GND 5

in
ADM1032ARMZ-2REEL_MSOP8

AMD RESERVED CONFIGURATION STRAPS

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET

i-
+3VS +3VS
M9X@
CV330 H2SYNC GENERICC
2

0.1U_0402_16V7K
RV138 1 2
100K_0402_5% PULLUP PADS ARE NOT REQUIRED FOR THESE STRAPS BUT IF THESE GPIOS ARE USED,
M9X@
3

THEY MUST NOT CONFLICT DURING RESET

S
M9X@
is
1

G
1 2 2 QV1 R46
RV60 47K_0402_5% AO3413_SOT23 0_0603_5%
1

B D B
M9X@ D M9X@ MANHA@ GPIO_8_ROMSO GPIO_21_BB_EN
1

1 2 2 QV2
52 PCIE_OK
2

RV125 0_0402_5% G 2N7002_SOT23-3 100mA

From 1.5V-->1.1VSP Chip 1 S M9X@ 2 1 +3VS_DELAY
3

CV180 CV331
kn

0.1U_0402_16V4Z 0.01U_0402_25V7K
2 M9X@ M9X@

STRAPS PIN GPU VRAM size Vendor Part Number# Compal Part Number# VRAM_ID 2,1,0

512M 64Mx16 (x4) HYN H5TQ1G63BFR-12C SA000032400 000

+1.8VS
te

Park M2 512M 64Mx16 (x4) SAM K4W1G1646E-HC12 SA000035700 001

1

RV124 RV123 RV122 M92 XTX 1G 128Mx16 (x4) HYN 0 1 0 (Reserve)

10K_0402_5% 10K_0402_5% 10K_0402_5%
@ @ @
1G 128Mx16 (x4) SAM K4W2G1646B-HC12 SA00003MQ00 0 1 1 (Reserve)
2

2
w.

VRAM_ID2 14
VRAM_ID1 14 VRAM_ID[2:0] DVPDATA
VRAM_ID0 14 (2,1,0) 1G 64Mx16 (x8) HYN H5TQ1G63BFR-12C SA000032400 100
1

RV128 RV127 RV126 Madison M2 1G 64Mx16 (x8) SAM K4W1G1646E-HC12 SA000035700 101
10K_0402_5% 10K_0402_5% 10K_0402_5%
@ @ @ M96 LP
ww

2G 128Mx16 (x8) HYN 1 1 0 (Reserve)

2

A A

2G 128Mx16 (x8) SAM K4W2G1646B-HC12 SA00003MQ00 1 1 1 (Reserve)

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401849 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 18, 2010 Sheet 21 of 58
5 4 3 2 1
 A B C D E F G H

Clock Generator +3VS_CK505

1
For SED For SED
R110
For SED For SED 10K_0402_5%
FBMH1608HM601-T_0603 FBMH1608HM601-T_0603
+3VS 1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VS_CK505 +1.05VS 1 2 10U_0805_10V4Z 0.1U_0402_16V4Z +1.05VS_CK505

2
R100 1 1 1 1 R101 1 1 1 1 CK_PWRGD

1
C252 Q35B

3
C209 C210 C211 C212 C251 C219 C220 C221 C222 47P_0402_50V8J 2N7002KDW_SOT363-6

m
@ R401 47P_0402_50V8J

2
0_0603_5% 2 2 2 2 2 2 2 2
1 1
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 5
CLK_ENABLE# 53
1

co

4
FBMH1608HM601-T_0603
1 2 0.1U_0402_16V4Z +1.05VS_CK505
+1.5VS +1.5VS_CK505
R120
+1.05VS_CK505 +3VS_CK505
1 1 1
For SED +1.5VS_CK505 +3VS_CK505
C213 C214 C215
U5 Silego Have Internal Pull-Up

a.
2 2 2 +3VS_CK505
For prevent noise coupling 1U_0402_6.3V6K 0.1U_0402_16V4Z 1 32
VDD_USB_48 SCL PM_SMBCLK 11,12,26,36
2 31 H_STP_CPU# 10K_0402_5% 2 1 R105
VSS_48M SDA PM_SMBDATA 11,12,26,36
3 30 CPU_SEL 1 2
26 CLK_DOT DOT_96 REF_0/CPU_SEL CLK_14M_PCH 26
4 29 33_0402_5% R102
26 CLK_DOT# DOT_96# VDD_REF
5 28 CLK_XTAL_IN
VDD_27 XTAL_IN
14 27M_CLK 1 R391 2 33_0402_5% 27M_CLK_R 6 27MHZ XTAL_OUT 27 CLK_XTAL_OUT

si
14 27M_SSC 1 R143 2 33_0402_5% 27M_SSC_R 7 27MHZ_SS VSS_REF 26 10K_0402_5% 2 @ 1 R119 +1.05VS
1 2 CLK_48M_CR_R 8 25 CK_PWRGD
40 CLK_48M_CR USB_48 CKPWRGD/PD#
R390 33_0402_5%
9 VSS_27M VDD_CPU 24
10 23 CPU_SEL 10K_0402_5% 2 1 R106
26 CLK_SATA SATA CPU_0 CLK_BCLK 26
26 CLK_SATA# 11 SATA# CPU_0# 22 CLK_BCLK# 26
12 VSS_SRC VSS_CPU 21 IDT Have Internal Pull-Down
13 20

ne
26 PCH_CLK_DMI SRC_1 CPU_1
26 PCH_CLK_DMI# 14 SRC_1# CPU_1# 19
15 18 CLK_XTAL_OUT
H_STP_CPU# VDD_SRC_IO VDD_CPU_IO
16 CPU_STOP# VDD_SRC 17 +1.5VS_CK505 Routing the CPU_SEL CPU_0/0# CPU_1/1#
2 Y1 2
33 CLK_XTAL_IN 1 2 trace at
TGND
2 2 least 10mil 0 (Default) 133MHz 133MHz
RTM890N-631-GRT_QFN_32P _5X5 14.318MHZ_16PF_7A14300083

do
C223 C224
22P_0402_50V8J 22P_0402_50V8J 1 100MHz 100MHz
1 1

For EMI request

in
1 2
LCD/PANEL BD. Conn. INT_MIC_CLK 1 2 1 2 @ R159 0_0402_5%
INVT_PWM 41

R387 C125 INVT_PWM_R 1 2 VGA_PWM 14

10_0402_5% 10P_0402_50V8J R160 0_0402_5%

1
@ @
+LCD_VDD +3VS R45

i-
10K_0402_5%
For ESD request
1

D19

2
+3VS INT_MIC_CLK 3
R107 R108 W=60mils 1
150_0603_5% 100K_0402_5% +3VS_LVDS_CAM INT_MIC_DATA 2 for GPU PD 10K
6 2

0.1U_0402_16V4Z near JLVDS AZ5125-02S.R7G_SOT23-3 +3VS_DELAY

2
Q1A
C228
0.1U_0402_16V7K
is 1
C225
2
3

S
3 2N7002KDW_SOT363-6 VGA_EDID_CLK 3
2 1
1 G
Q17 0_0603_5% JLVDS R153 4.7K_0402_5%
2 1
R109
2
47K_0402_5%
2
AO3413_SOT23 R388 1
W=20mils VGA_EDID_DATA
1 +3VS 2 2 2 1 1 2 1
3

D USB20_P11_R 4 4 3 R154 4.7K_0402_5%

VGA_TXCLK+ 14
1

C229 +LCD_VDD USB20_N11_R 3

0.01U_0402_25V7K
W=60mils 6 6 5 5 VGA_TXCLK- 14
8 8 7
kn

Q1B 2 7
14 VGA_ENVDD 5 14 VGA_TXOUT0+ 10 10 9 9 VGA_TZCLK+ 14
2N7002KDW_SOT363-6 12 12 11
14 VGA_TXOUT0- 11 VGA_TZCLK- 14
1 14 14 13 L1 1.5A
14 VGA_TXOUT1+
4

13
2

16 16 15 VGA_EDID_CLK 14 +LCDVDD_R 2 1 +LCD_VDD

14 VGA_TXOUT1- 15
C233 18 18 17 VGA_EDID_DATA 14 1 0_0805_5% 1
14 VGA_TXOUT2+ 17
R112 0.1U_0402_16V4Z 20 20 19 INT_MIC_CLK
2 14 VGA_TXOUT2- 19 INT_MIC_CLK 38
10K_0402_5% 22 22 21 INT_MIC_DATA C226 C227
21 INT_MIC_DATA 38 +3VS
te

24 24 23 0.1U_0402_16V4Z 4.7U_0805_10V4Z
14 VGA_TZOUT0+
1

23 INVT_PWM_R 2 2
14 VGA_TZOUT0- 26 26 25 25
for GPU PD 10K 14 VGA_TZOUT1+ 28 28 27 27
14 VGA_TZOUT1- 30 30 29 29 1 1
32 31 +LCDVDD_R
14 VGA_TZOUT2+ 32 31
34 33 BKOFF#_R C231 C232
14 VGA_TZOUT2- 34 33
36 36 35 680P_0402_50V7K 0.1U_0402_16V4Z
35 @ 2 2
38 38 37 +LCD_INV
w.

37 BKOFF#_R
Reserve for EMI request +LCD_INV 40 40 39 39 2 1 BKOFF# 41
42 GND GMD 41 R392

1
R78 0_0402_5% For EMI request 33_0402_5%
1 2 ACES_87242-4001-09 Rated Current MAX:1000mA
@ L2 2 1 B+ R113
L55 @ 1 1 FBMA-L11-201209-221LMA30T_0805 1 10K_0402_5%
C236

2
ww

29 USB20_N11 1 2 USB20_N11_R C234 C235 680P_0402_50V7K

4 1 2 4
68P_0402_50V8J 0.1U_0402_25V6 @
2 2 2
29 USB20_P11 4 3 USB20_P11_R
4 3
WCM-2012-900T_0805

R96 0_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
1 2 Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 22 of 58
A B C D E F G H
 A B C D E

CRT CONNECTOR

1
D3 D4 D5

+3VS

m
1 DAN217_SC59 DAN217_SC59 DAN217_SC59 1

3
@ @ @

co
L3
1 2 CRT_R_L
14 VGA_CRT_R
NBQ100505T-800Y-N_2P

L4
1 2 CRT_G_L

a.
14 VGA_CRT_G
NBQ100505T-800Y-N_2P

L5
1 2 CRT_B_L
14 VGA_CRT_B

4.7P_0402_50V8C

4.7P_0402_50V8C

4.7P_0402_50V8C

4.7P_0402_50V8C

4.7P_0402_50V8C

4.7P_0402_50V8C
NBQ100505T-800Y-N_2P
150_0402_1%

150_0402_1%

150_0402_1%
1 1 1 1 1 1
1

si
R138 R139 R140 C238 C239 C240 C241 C242 C243
2 2 2 2 2 2 +5VS
D6 +CRT_VCC_R +CRT_VCC
2

2
2 F1 30mil
1 1 2
3 RB491D_SOT23-3 1

ne
1.1A_6V_MINISMDC110F-2
If=1A C237
@ 0.1U_0402_16V4Z
2 2 2

do
+CRT_VCC

1 2 2 1 JCRT
C244 0.1U_0402_16V4Z R141 10K_0402_5% 6 RGND
5
1

11 ID0
CRT_R_L 1
P
OE#

D_CRT_HSYNC HSYNC Red

14,21 VGA_CRT_HSYNC 2 4 1 2 7

in
A Y L6 10_0402_5% CRT_DDC_DAT GGND
12 SDA
G

U6 CRT_G_L 2
SN74AHCT1G125GW_SOT353-5 D_CRT_VSYNC VSYNC Green
1 2 8
3

L7 10_0402_5% HSYNC BGND

13 Hsync

10P_0402_50V8J

10P_0402_50V8J
CRT_B_L 3
+CRT_VCC Blue
1 1 +CRT_VCC 9 +5V
VSYNC 14
C245 C246 Vsync

i-
4 res
5
1

@ @ 10
2 2 CRT_DDC_CLK SGND
15
P
OE#

SCL
14,21 VGA_CRT_VSYNC 2 A Y 4 5 GND
G

U7 16
SN74AHCT1G125GW_SOT353-5 GND
17
3

GND
For EMI Request
is @ SUYIN_070546FR015S263ZR
3 3
kn

+3VS +CRT_VCC
2

R146 R147
te

2K_0402_1% 2K_0402_1%
2

Q2A
1

14 VGA_CRT_DATA 1 6 CRT_DDC_DAT
5

Q2B 2N7002KDW_SOT363-6

14 VGA_CRT_CLK 4 3 CRT_DDC_CLK
w.

1 1
1 1 2N7002KDW_SOT363-6
C249 C250
C247 C248 470P_0402_50V8J 470P_0402_50V8J
33P_0402_50V8K 33P_0402_50V8K @ 2 2 @
@ 2 2 @
ww

4 4

For EMI Request

For EMI Request

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title
SCHEMATIC,MB A6042
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 23 of 58
A B C D E
 5 4 3 2 1

HDMI@
R228
1K_0402_5%
+3VS HDMI_HPD_R 1 2 HDMI_HPD

2
+5VS HDMI@ 2 HDMI@

1
HDMI@ R186 C265
R172 100K_0402_5% 0.1U_0402_16V4Z
2.2K_0402_5% 2
PMEG2010AEH_SOD123 HDMI@ F2 HDMI@ HDMI@ 1

1
1

5
+5VS 2 1 2 1 +HDMI_5V_OUT U9 C264

2
D53 1.1A_6V_MINISMDC110F-2 1 0.1U_0402_16V4Z

P
OE#
1

m
C259 4 2
14,30 VGA_HDMI_HPD Y A
D HDMI@ D

G
0.1U_0402_16V4Z
2 HDMI@

3
co
R177 74AHCT1G125GW_SOT353-5
100K_0402_5%

2
a.
VGA_DVI_TXC- 1 2 R157 HDMI_R_CK-
@ 0_0402_5%
L8
1 1 2 2

si
4 4 3 3
HDMI@ OCE2012120YZF_0805
VGA_DVI_TXC+ 1 2 R173 HDMI_R_CK+
@ 0_0402_5%

HDMI_R_CK- 1 HDMI@ 2
VGA_DVI_TXD0- 1 2 R175 HDMI_R_D0- R197 499_0402_1%

ne
@ 0_0402_5% HDMI_R_CK+ 1 HDMI@ 2
L9 R195 499_0402_1%
1 2 HDMI_R_D0- 1 HDMI@ 2
C
1 2 R203 499_0402_1% C
HDMI_R_D0+ 1 HDMI@ 2
4 3 R201 499_0402_1%
CV322 0.1U_0402_16V7K HDMI@ VGA_DVI_TXC- 4 3 HDMI_R_D1- 1 HDMI@ 2
14 VGA_HDMI_CLK- 1 2

do
CV323 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD0- HDMI@ OCE2012120YZF_0805 R198 499_0402_1%
14 VGA_HDMI_TX0-
CV324 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD1- VGA_DVI_TXD0+ 1 2 R180 HDMI_R_D0+ HDMI_R_D1+ 1 HDMI@ 2
14 VGA_HDMI_TX1-
CV325 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD2- @ 0_0402_5% R202 499_0402_1%
14 VGA_HDMI_TX2-
HDMI_R_D2- 1 HDMI@ 2
R205 499_0402_1%
CV326 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXC+ HDMI_R_D2+ 1 HDMI@ 2
14 VGA_HDMI_CLK+
CV327 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD0+ VGA_DVI_TXD1- 1 2 R182 HDMI_R_D1- R206 499_0402_1%
14 VGA_HDMI_TX0+
CV328 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD1+ @ 0_0402_5%
14 VGA_HDMI_TX1+

in

1
CV329 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD2+ L10 D
14 VGA_HDMI_TX2+ 1 2
1 2 +5VS 2 Q24
1 2 G 2N7002_SOT23-3
S HDMI@

3
4 4 3 3
HDMI@ OCE2012120YZF_0805
VGA_DVI_TXD1+ 2 R183 HDMI_R_D1+

i-
1
@ 0_0402_5%

VGA_DVI_TXD2- 1 2 R187 HDMI_R_D2-

@ 0_0402_5%
L11
1 1 2 2
is
B B
4 4 3 3
HDMI@ OCE2012120YZF_0805
VGA_DVI_TXD2+ 1 2 R188 HDMI_R_D2+
@ 0_0402_5%
HDMI Connector
kn

+3VS +HDMI_5V_OUT JHDMI

HDMI_HPD 19 HP_DET
+HDMI_5V_OUT 18 +5V
17 DDC/CEC_GND
HDMI_SDATA 16 SDA
te

HDMI_SCLK 15 SCL
1

14 Reserved
R184 R185 13
2.2K_0402_5% 2.2K_0402_5% HDMI_R_CK- CEC
12 CK- GND 20
HDMI@ HDMI@ 11 21
CK_shield GND
2

14 VGA_HDMI_CLK HDMI_R_CK+ 10 22
2

CK+ GND
G

HDMI_R_D0- 9 23
D0- GND
8
w.

HDMI_SCLK HDMI_R_D0+ D0_shield

3 1 7 D0+
2

Q19 HDMI_R_D1- 6 D1-

G

BSH111_SOT23-3 Q18 5
HDMI@ BSH111_SOT23-3 HDMI_R_D1+ D1_shield
4 D1+
14 VGA_HDMI_DATA 3 1 HDMI@ HDMI_SDATA HDMI_R_D2- 3 D2-
2 D2_shield
S

HDMI_R_D2+ 1 D2+
ww

A A
@ SUYIN_100042MR019S153ZL

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 24 of 58
5 4 3 2 1
 5 4 3 2 1

C287
CMOS Setting, near DDR Door 15P_0402_50V8J
JCMOS 2 1
+RTCVCC 1 2PCH_RTCRST# 1 2

10M_0402_5%
R282 20K_0402_1% Y3

1
1 2 3 NC OSC 4

R283
C288 1U_0402_6.3V4Z
iME Setting. J2
2 NC OSC 1 U11A
1 2PCH_SRTCRST# 1 2 32.768KHZ_12.5PF_Q13MC14610002

2
R284 20K_0402_1% PCH_RTCX1 B13 D33
RTCX1 FWH0 / LAD0 LPC_AD0 41,42
1 2 2 1 PCH_RTCX2 D13 B33
RTCX2 FWH1 / LAD1 LPC_AD1 41,42

m
C289 1U_0402_6.3V4Z C290 15P_0402_50V8J C32
FWH2 / LAD2 LPC_AD2 41,42
D
FWH3 / LAD3 A32 LPC_AD3 41,42 D
PCH_RTCRST# C14 RTCRST#
FWH4 / LFRAME# C34 LPC_FRAME# 41,42

co
+RTCVCC PCH_SRTCRST# D17 SRTCRST#
A34

RTC

LPC
SM_INTRUDER# LDRQ0#
Integrated SUS 1.05V VRM Enable 1
R285
2
1M_0402_5%
A16 INTRUDER# LDRQ1# / GPIO23 F34

High - Enable Internal VRs 1 2 PCH_INTVRMEN A14 AB9 SERIRQ

INTVRMEN SERIRQ SERIRQ 41,42
PCH_INTVRMEN (must be always pulled high) R275 330K_0402_5%
1 2 +3VS
R286 10K_0402_5%

a.
AZ_BITCLK A30 HDA_BCLK
SATA0RXN AK7
AZ_SYNC D29 AK6
HDA_SYNC HDA_SYNC SATA0RXP
AK11
PCH_SPKR SATA0TXN
This signal has a weak internal pull down. 28,38 PCH_SPKR P1 SPKR SATA0TXP AK9
H=>On Die PLL is supplied by 1.5V
AZ_RST#
*L=>On Die PLL is supplied by 1.8V C30 HDA_RST#

si
SATA1RXN AH6 SATA_PRX_C_DTX_N1 34
SATA1RXP AH5 SATA_PRX_C_DTX_P1 34
HDA_SDO 38 AZ_SDIN0_HD G30 HDA_SDIN0 SATA1TXN AH9 SATA_PTX_DRX_N1 34 1ST HDD
SATA1TXP AH8 SATA_PTX_DRX_P1 34
This signal has a weak internal pull down. 35 AZ_SDIN1_MD F30 HDA_SDIN1
This signal can't PU SATA2RXN AF11
E32 AF9

IHDA
HDA_SDIN2 SATA2RXP
AF7

ne
SATA2TXN
F32 HDA_SDIN3 SATA2TXP AF6
Flash Descriptor Security Overide Desktop Only
SATA3RXN AH3
C Low = Enabled AZ_SDOUT B29 AH1 C
HDA_SDO SATA3RXP
HDA_DOCK_EN# High = Disabled * SATA3TXN AF3
SATA3TXP AF1
41 PWRME_CTRL# H32

SATA
HDA_DOCK_EN# / GPIO33

do
SATA4RXN AD9 SATA_PRX_C_DTX_N4 34

2
J30 HDA_DOCK_RST# / GPIO13 SATA4RXP AD8 SATA_PRX_C_DTX_P4 34
35 AZ_BITCLK_MD R287 1 MDC@ 2 33_0402_5% R118 AD6 SATA ODD
SATA4TXN SATA_PTX_DRX_N4 34
38 AZ_BITCLK_HD R288 1 2 33_0402_5% AZ_BITCLK 1K_0402_5% AD5
SATA4TXP SATA_PTX_DRX_P4 34
1 1 @
@ @ PCH_JTAG_TCK M3 AD3 SATA_PRX_C_DTX_N5 34
1

C126 C140 JTAG_TCK SATA5RXN

for EMI request SATA5RXP AD1 SATA_PRX_C_DTX_P5 34
10P_0402_50V8J 10P_0402_50V8J PCH_JTAG_TMS K3 AB3 eSATA
SATA_PTX_DRX_N5 34

in
2 2 JTAG_TMS SATA5TXN
SATA5TXP AB1 SATA_PTX_DRX_P5 34
PCH_JTAG_TDI K1 JTAG_TDI

JTAG
35 AZ_SYNC_MD R289 1 MDC@ 2 33_0402_5% PCH_JTAG_TDO J2 AF16
R290 1 JTAG_TDO SATAICOMPO +3VS
38 AZ_SYNC_HD 2 33_0402_5% AZ_SYNC
PCH_JTAG_RST# J4 AF15 SATAICOMP 1 2
TRST# SATAICOMPI +1.05VS
35 AZ_RST_MD# R291 1 MDC@ 2 33_0402_5% R295 37.4_0402_1%
R292 1 2 33_0402_5% AZ_RST# SATA_LED# R301 2 1 10K_0402_5%

i-
38 AZ_RST_HD#

35 AZ_SDOUT_MD R293 1 MDC@ 2 33_0402_5% PCH_SPI_CLK BA2 PCH_GPIO21 R303 1 2 10K_0402_5%

R294 1 SPI_CLK
38 AZ_SDOUT_HD 2 33_0402_5% AZ_SDOUT
PCH_SPI_CS0# AV3 PCH_GPIO19 R306 1 2 10K_0402_5%
SPI_CS0#
ITPM Enabled Internal: Pull down 20k AY3 T3 SATA_LED#
+3VS SPI_CS1# SATALED# SATA_LED# 43

SPI_MOSI
High = Enabled
2 @ 1PCH_SPI_MOSI
is AY1 Y9 PCH_GPIO21
B Low = Disabled (Default) R273 1K_0402_5% SPI_MOSI SATA0GP / GPIO21 B

SPI
PCH_SPI_MISO AV1 V1 PCH_GPIO19
SPI_MISO SATA1GP / GPIO19

IBEXPEAK-M QV20 A0_FCBGA1071

HM55R1@
kn

+3VALW +3VALW +3VALW +3VALW

+3VS
4MB
1

@ @ @
R386 R363 @ R643 1 U13
200_0402_5% 200_0402_5% R536 20K_0402_5% 8 4
200_0402_5% C293 VCC VSS
+RTCBATT
te

0.1U_0402_16V4Z 3
2

1
PCH_JTAG_TMS PCH_JTAG_TDO PCH_JTAG_TDI PCH_JTAG_RST# 2
7 HOLD
1

@ @ @ +RTCVCC D13
R355 R535 @ R364 PCH_SPI_CS0# 1 BAS40-04_SOT23-3
R537 10K_0402_5% S
100_0402_5% 100_0402_5% for EMI request
100_0402_5% PCH_SPI_CLK 6

2
C
w.

+CHGRTC
2

PCH_SPI_MOSI 5 2 PCH_SPI_MISO
R385 D Q
10_0402_5% MX25L3205DM2I-12G SO8 1
C291
0.1U_0402_16V4Z
2

1 2
1 2 PCH_JTAG_TCK C86
R156 51_0402_5%
ww

10P_0402_50V8J
A A
06/01 change R156 from 4.7K to 51 ohm 2
PCH JTAG Enable PCH JTAG Disable (Default)
PCH Pin RefDes ES1 ES2 ES1 ES2
PCH_JTAG_TDO R358 No Install 200ohm No Install No Install
R535 No Install 100ohm No Install No Install
PCH_JTAG_TMS R355 200ohm 200ohm No Install No Install Security Classification Compal Secret Data Compal Electronics, Inc.
R354 100ohm 100ohm No Install No Install 2009/10/01 2010/10/01 Title
PCH_JTAG_TDI R536 200ohm 200ohm 20Kohm No Install Issued Date Deciphered Date
R537 100ohm 100ohm 10Kohm No Install
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
PCH_JTAG_TCK R156 51ohm 51ohm 51ohm 51ohm Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
PCH_JTAG_RST# R643 20Kohm 20Kohm No Install No Install B B
R353 10Kohm 10Kohm No Install No Install
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 25 of 58
5 4 3 2 1
 5 4 3 2 1

+3VS
+3VALW 2 R229 1 2.2K_0402_5%
2 R230 1 2.2K_0402_5% R231 4.7K_0402_5%

5
Q3B R232 4.7K_0402_5%

PCH_SMBDATA 3 4 PM_SMBDATA 11,12,22,36

2
Q3A 2N7002KDW_SOT363-6

PCH_SMBCLK 6 1 PM_SMBCLK 11,12,22,36

2N7002KDW_SOT363-6

m
D U11B D

co
BG30 B9 EC_LID_OUT# EC_LID_OUT# 41
37 PCIE_PRX_C_LANTX_N1 PERN1 SMBALERT# / GPIO11
For LAN 37 PCIE_PRX_C_LANTX_P1
C276 2
BJ30 PERP1
37 PCIE_PTX_C_LANRX_N1 1 0.1U_0402_16V7K PCIE_PTX_LANRX_N1 BF29
PETN1 SMBCLK H14 PCH_SMBCLK
37 PCIE_PTX_C_LANRX_P1 C273 2 1 0.1U_0402_16V7K PCIE_PTX_LANRX_P1 BH29
PETP1 PCH_SMBDATA +3VS
SMBDATA C8
36 PCIE_PRX_WLANTX_N2 AW30 PERN2
For WLAN 36 PCIE_PRX_WLANTX_P2
C274 2
BA30 PERP2
1 0.1U_0402_16V7K PCIE_PTX_WLANRX_N2 BC30 J14 PCH_GPIO60 2 R233 1 2.2K_0402_5%

a.
36 PCIE_PTX_C_WLANRX_N2 PETN2 SML0ALERT# / GPIO60 +3VALW
36 PCIE_PTX_C_WLANRX_P2 C275 2 1 0.1U_0402_16V7K PCIE_PTX_WLANRX_P2 BD30 2 R234 1 2.2K_0402_5%
PETP2

5
C6 PCH_SMLCLK0 Q4B
SML0CLK
AU30

SMBus
PERN3 PCH_SMLDATA0 PCH_SMLDATA1
AT30 PERP3 SML0DATA G8 3 4 EC_SMB_DA2 21,41
AU32 PETN3

2
AV32 Q4A 2N7002KDW_SOT363-6
PETP3 PCH_GPIO74
SML1ALERT# / GPIO74 M14

si
BA32 PCH_SMLCLK1 6 1
PERN4 EC_SMB_CK2 21,41
BB32 E10 PCH_SMLCLK1
PERP4 SML1CLK / GPIO58 2N7002KDW_SOT363-6
BD32 PETN4
BE32 G12 PCH_SMLDATA1 +3VALW
PETP4 SML1DATA / GPIO75

PCI-E*
BF33 PCH_SMLCLK0 2.2K_0402_5% 2 1 R237
PERN5 PCH_SMLDATA0 2.2K_0402_5% R238
BH33 PERP5 CL_CLK1 T13 2 1

Controller
BG32 PCH_GPIO60 10K_0402_5% 2 1 R239

ne
PETN5 PCH_GPIO74 10K_0402_5% R240
BJ32 PETP5 CL_DATA1 T11 2 1
EC_LID_OUT# 10K_0402_5% 2 1 R241

Link
BA34 T9 1 @ 2 +3VALW
C
PERN6 CL_RST1# R260 10K_0402_5% C
AW34 PERP6
BC34 PETN6
BD34 PETP6
H1 CLKREQ_PEG# 1 2
PEG_A_CLKRQ# / GPIO47

do
AT34 R243 10K_0402_5%
PERN7
AU34 PERP7
AU36 PETN7 CLKOUT_PEG_A_N AD43 CLK_PCIE_VGA# 13
AV36 PETP7 CLKOUT_PEG_A_P AD45 CLK_PCIE_VGA 13 VGA
NC BG34 AN4 CLK_PEG# 5
PERN8 CLKOUT_DMI_N

PEG
BJ34 PERP8 CLKOUT_DMI_P AN2 CLK_PEG 5
BG36

in
PETN8
BJ36 PETP8
CLKOUT_DP_N / CLKOUT_BCLK1_N AT1
CLKOUT_DP_P / CLKOUT_BCLK1_P AT3
37 CLK_LAN# AK48 CLKOUT_PCIE0N
LAN 37 CLK_LAN AK47 CLKOUT_PCIE0P

From CLK BUFFER

CLKIN_DMI_N AW24 PCH_CLK_DMI# 22
CLKREQ_LAN# P9 BA24 PCH_CLK_DMI 22
37 CLKREQ_LAN# PCIECLKRQ0# / GPIO73 CLKIN_DMI_P

i-
+3VS AM43 AP3
36 CLK_WLAN# CLKOUT_PCIE1N CLKIN_BCLK_N CLK_BCLK# 22
PCH_GPIO20
WLAN 36 CLK_WLAN AM45 CLKOUT_PCIE1P CLKIN_BCLK_P AP1 CLK_BCLK 22 FROM CLK GEN FOR: 133/100/96/14.318 MHZ
1 2
10K_0402_5% R246 CLKREQ_WLAN# U4
36 CLKREQ_WLAN# PCIECLKRQ1# / GPIO18
CLKIN_DOT_96N F18 CLK_DOT# 22
1 2 CLKREQ_WLAN# E18 CLK_DOT 22
CLKIN_DOT_96P
10K_0402_5% R248
is
AM47
AM48
CLKOUT_PCIE2N
B CLKOUT_PCIE2P B
CLKIN_SATA_N / CKSSCD_N AH13 CLK_SATA# 22
PCH_GPIO20 N4 AH12 CLK_SATA 22
+3VALW PCIECLKRQ2# / GPIO20 CLKIN_SATA_P / CKSSCD_P @
CLK_14M_PCH 1 @ 2 2 1
1 2 CLKREQ_LAN# AH42 P41 CLK_14M_PCH 22 R70 100_0402_5% C206 100P_0402_50V8J
10K_0402_5% R244 CLKOUT_PCIE3N REFCLK14IN
AH41
kn

CLKOUT_PCIE3P
1 2 PCH_GPIO25 PCH_GPIO25 A8 J42
PCIECLKRQ3# / GPIO25 CLKIN_PCILOOPBACK CLK_PCILOOP 29
10K_0402_5% R245

1 2 PCH_GPIO26 AM51 AH51 PCH_X1

10K_0402_5% R249 CLKOUT_PCIE4N XTAL25_IN
AM53 CLKOUT_PCIE4P XTAL25_OUT AH53
te

1 2 PCH_GPIO44 PCH_GPIO26 M9 AF38 XCLK_RCOMP 1 2 +1.05VS

10K_0402_5% R250 PCIECLKRQ4# / GPIO26 XCLK_RCOMP R252 90.9_0402_1%

1 2 PCH_GPIO56 AJ50 T45

10K_0402_5% R251 CLKOUT_PCIE5N CLKOUTFLEX0 / GPIO64
AJ52 CLKOUT_PCIE5P
PCH_GPIO44 H6 P43
Clock Flex

PCIECLKRQ5# / GPIO44 CLKOUTFLEX1 / GPIO65

w.

AK53 CLKOUT_PEG_B_N CLKOUTFLEX2 / GPIO66 T42

AK51 CLKOUT_PEG_B_P
PCH_GPIO56 P13 N50
PEG_B_CLKRQ# / GPIO56 CLKOUTFLEX3 / GPIO67
ww

IBEXPEAK-M QV20 A0_FCBGA1071

A A
HM55R1@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 26 of 58
5 4 3 2 1
 5 4 3 2 1

m
D D

U11C

co
FDI_RXN0 BA18
6 DMI_CTX_PRX_N0 BC24 DMI0RXN FDI_RXN1 BH17
6 DMI_CTX_PRX_N1 BJ22 DMI1RXN FDI_RXN2 BD16
6 DMI_CTX_PRX_N2 AW20 DMI2RXN FDI_RXN3 BJ16
6 DMI_CTX_PRX_N3 BJ20 DMI3RXN FDI_RXN4 BA16
FDI_RXN5 BE14
6 DMI_CTX_PRX_P0 BD24 DMI0RXP FDI_RXN6 BA14
BG22 BC12

a.
6 DMI_CTX_PRX_P1 DMI1RXP FDI_RXN7
6 DMI_CTX_PRX_P2 BA20 DMI2RXP
6 DMI_CTX_PRX_P3 BG20 DMI3RXP FDI_RXP0 BB18
FDI_RXP1 BF17
6 DMI_PTX_CRX_N0 BE22 DMI0TXN FDI_RXP2 BC16
6 DMI_PTX_CRX_N1 BF21 DMI1TXN FDI_RXP3 BG16
+3VALW BD20 AW16
6 DMI_PTX_CRX_N2 DMI2TXN FDI_RXP4
6 DMI_PTX_CRX_N3 BE18 DMI3TXN FDI_RXP5 BD14

si
FDI_RXP6 BB14
1 2 PCH_SUSPWRDN BD22 BD12
6 DMI_PTX_CRX_P0 DMI0TXP FDI_RXP7
R316 10K_0402_5% BH21
6 DMI_PTX_CRX_P1 DMI1TXP
1 2 PCH_LOW_BAT# BC20
6 DMI_PTX_CRX_P2 DMI2TXP
R318 10K_0402_5% BD18 BJ14 1 2
6 DMI_PTX_CRX_P3 DMI3TXP FDI_INT
1 2 IBEX_RI# R689 1K_0402_5%

DMI
FDI
R320 10K_0402_5% BF13 1 2
DMI_COMP FDI_FSYNC0 R690 1K_0402_5%
1 2 BH25

ne
+1.05VS DMI_ZCOMP
R311 49.9_0402_1% BH13
PM_PWROK FDI_FSYNC1
2 1 BF25 DMI_IRCOMP
R329 10K_0402_5% BJ12
C 2 1 PWROK Close to PCH FDI_LSYNC0 C
R322 10K_0402_5% BG14
LAN_RST# FDI_LSYNC1
2 1
R323 10K_0402_5%

do
2 @ 1 EC_SWI# 2 1 +3VALW
0_0402_5% R256 R313 10K_0402_5%

+3VS XDP_DBRESET# T6 J12 EC_SWI#

5 XDP_DBRESET# SYS_RESET# WAKE# EC_SWI# 37
0.1U_0402_16V4Z
1 2

in
C230 M6 Y1 PM_CLKRUN# 2 1 +3VS
41,53 VGATE SYS_PWROK CLKRUN# / GPIO32
5

R319 8.2K_0402_5%
2
P

41 PM_PWROK IN2

System Power Management

4 PWROK B17
VGATE O PWROK
1 IN1
G

U12 1 2 K5 P8 SUS_STAT# PADT38

PADT38
3

SN74AHC1G08DCKR_SC70-5 R321 0_0402_5% MEPWROK SUS_STAT# / GPIO61

i-
LAN_RST# A10 F3 SUS_CLK PADT39
PADT39
LAN_RST# SUSCLK / GPIO62

5 DRAMPWROK
isD9 DRAMPWROK SLP_S5# / GPIO63 E4 PM_SLP_S5# 41

PCH_RSMRST# C16 H7
RSMRST# SLP_S4# PM_SLP_S4# 41
B B
PCH_SUSPWRDN M1 P12
41 PCH_SUSPWRDN SUS_PWR_DN_ACK / GPIO30 SLP_S3# PM_SLP_S3# 41

41 PBTN_OUT# P5 PWRBTN# SLP_M# K8

kn

+3VALW 1 2 PCH_ACIN P7 N2
R324 330K_0402_5% ACPRESENT / GPIO31 TP23

D26 PCH_LOW_BAT# A6 BJ10

BATLOW# / GPIO72 PMSYNCH PMSYNCH 5
41,43,45 ACIN 1 2
te

CH751H-40PT_SOD323-2 IBEX_RI# F14 F6

RI# SLP_LAN# / GPIO29

IBEXPEAK-M QV20 A0_FCBGA1071

+3VALW HM55R1@

1 2
w.

R691 1K_0402_5% 0_0402_5% @1 2 R325

Q26 1 PCH_RSMRST#
C

41 EC_RSMRST# 3
E

2 1
MMBT3906_SOT23-3 R326
10K_0402_5%
B
2

+3VALW 2 1
R327
ww

A A
1

4.7K_0402_5%
D15A D15B
BAV99DW-7_SOT363 BAV99DW-7_SOT363

Security Classification Compal Secret Data Compal Electronics, Inc.

6

1 2
RSMRST# circuit R328
2.2K_0402_5%
Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 27 of 58
5 4 3 2 1
 5 4 3 2 1

U11D
T48 L_BKLTEN SDVO_TVCLKINN BJ46
T47 L_VDD_EN SDVO_TVCLKINP BG46

Y48 L_BKLTCTL SDVO_STALLN BJ48

SDVO_STALLP BG48
AB48 L_DDC_CLK
Y45 L_DDC_DATA SDVO_INTN BF45
SDVO_INTP BH45
AB46 L_CTRL_CLK
V48 L_CTRL_DATA

m
AP39 LVD_IBG SDVO_CTRLCLK T51
D PAD T42 LVD_VBGAP41 T53 D
LVD_VBG SDVO_CTRLDATA
AT43 LVD_VREFH

co
AT42 LVD_VREFL DDPB_AUXN BG44
DDPB_AUXP BJ44
DDPB_HPD AU38

LVDS
AV53 LVDSA_CLK#
AV51 LVDSA_CLK DDPB_0N BD42
DDPB_0P BC42
BB47 LVDSA_DATA#0 DDPB_1N BJ42

Digital Display Interface

BA52 BG42

a.
LVDSA_DATA#1 DDPB_1P
AY48 LVDSA_DATA#2 DDPB_2N BB40
AV47 LVDSA_DATA#3 DDPB_2P BA40
DDPB_3N AW38
BB48 LVDSA_DATA0 DDPB_3P BA38
BA50 LVDSA_DATA1
AY49 LVDSA_DATA2
AV48 LVDSA_DATA3 DDPC_CTRLCLK Y49

si
DDPC_CTRLDATA AB49

AP48 LVDSB_CLK#
AP47 LVDSB_CLK DDPC_AUXN BE44
DDPC_AUXP BD44
AY53 LVDSB_DATA#0 DDPC_HPD AV40
AT49 LVDSB_DATA#1
AU52 BE40

ne
LVDSB_DATA#2 DDPC_0N
AT53 LVDSB_DATA#3 DDPC_0P BD40
DDPC_1N BF41
AY51 LVDSB_DATA0 DDPC_1P BH41
C AT48 BD38 C
LVDSB_DATA1 DDPC_2N
AU50 LVDSB_DATA2 DDPC_2P BC38
AT51 LVDSB_DATA3 DDPC_3N BB36
DDPC_3P BA36

do
AA52 CRT_BLUE DDPD_CTRLCLK U50
AB53 CRT_GREEN DDPD_CTRLDATA U52
AD53 CRT_RED

DDPD_AUXN BC46
V51 BD46

in
CRT_DDC_CLK DDPD_AUXP
V53 CRT_DDC_DATA DDPD_HPD AT38

DDPD_0N BJ40
Y53 CRT_HSYNC DDPD_0P BG40
Y51 CRT_VSYNC DDPD_1N BJ38
DDPD_1P BG38

CRT
DDPD_2N BF37
2 R266 1CRT_IREF

i-
AD48 DAC_IREF DDPD_2P BH37
AB51 CRT_IRTN DDPD_3N BE36
1K_0402_1% BD36
DDPD_3P

PCH Strap Pin IBEXPEAK-M QV20 A0_FCBGA1071

HM55R1@

Internal: Pull down 20k

+3VS
Internal: Pull down 20k NO REBOOT Strap
is +1.8VS_PCH_NAND During Reset: Low Danbury Technology Enabled
B Initial: Low High = Enabled B
During Reset: HZ
PCH_SPKR Low= Disable NV_ALE Low = Disabled (Default)
Initial: Low 2 @ 1 NV_ALE
@ PCH_SPKR
High= Enable R267 1K_0402_5%
NV_ALE 29
1 2 PCH_SPKR 25,38
R269 1K_0402_5%
Internal: Pull up 20k 2 @ 1 NV_CLE
kn

NV_CLE 29
Boot BIOS Strap R268 1K_0402_5% DMI Termination Voltage
During Reset: High
Initial: High PCI_GNT#1 PCI_GNT#0 Boot BIOS Loaction Internal: Pull down 20k Low= Set to Vss (Default)
During Reset: Low NV_CLE High= Set to Vcc
1K_0402_5% 2 @ 1 R270 PCI_GNT#0
PCI_GNT#0 29 0 0 LPC (Default) Initial: Low
1K_0402_5% 2 @ 1 R271 PCI_GNT#1
PCI_GNT#1 29 0 1 Reserved (NAND)
te

Internal: Pull up 20k 1 0 PCI

During Reset: High
Initial: High 1 1 SPI
2 @ 1 PCI_GNT#3
PCI_GNT#3 29
R272 1K_0402_5% A16 Swap Override Strap
w.

Internal: Pull up 20k

During Reset: High Low= A16 swap override Enable
Initial: High PCI_GNT#3 High= A16 swap override Disable
ww

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 28 of 58
5 4 3 2 1
 5 4 3 2 1

U11E
H40 AD0 NV_CE#0 AY9

m
N34 AD1 NV_CE#1 BD1
D C44 AD2 NV_CE#2 AP15 D
A38 AD3 NV_CE#3 BD8
C36 AD4

co
J34 AD5 NV_DQS0 AV9
A40 AD6 NV_DQS1 BG8
D45 AD7
E36 AD8 NV_DQ0 / NV_IO0 AP7
H48 AD9 NV_DQ1 / NV_IO1 AP6
E40 AD10 NV_DQ2 / NV_IO2 AT6
C40 AD11 NV_DQ3 / NV_IO3 AT9
M48 BB1

a.
AD12 NV_DQ4 / NV_IO4
M45 AD13 NV_DQ5 / NV_IO5 AV6
F53 AD14 NV_DQ6 / NV_IO6 BB3
M40 AD15 NV_DQ7 / NV_IO7 BA4

NVRAM
M43 AD16 NV_DQ8 / NV_IO8 BE4
J36 AD17 NV_DQ9 / NV_IO9 BB6
K48 AD18 NV_DQ10 / NV_IO10 BD6
F40 AD19 NV_DQ11 / NV_IO11 BB7
+3VS

si
C42 AD20 NV_DQ12 / NV_IO12 BC8
RP1 K46 BJ8
PCI_REQ#1 AD21 NV_DQ13 / NV_IO13
1 8 M51 AD22 NV_DQ14 / NV_IO14 BJ6
2 7 PCI_REQ#2 J52 BG6
PCI_PIRQD# AD23 NV_DQ15 / NV_IO15
3 6 K51 AD24
4 5 PCI_IRDY# L34 BD3 NV_ALE NV_ALE 28 1 @ 2
AD25 NV_ALE NV_CLE R253 0_0402_5%
F42 AD26 NV_CLE AY6 NV_CLE 28
8.2K_0804_8P4R_5% J40

ne
AD27 +3VS
G46 AD28
RP2 F44 AU2 1 @ 2
PCI_PIRQH# AD29 NV_RCOMP R276 32.4_0402_1%
1 8 M47 AD30

PCI
C 2 7 PCI_TRDY# H36 AV7 C
AD31 NV_RB#

5
3 6 PCI_FRAME# U8
4 5 PCI_PIRQA# J50 AY8 1 PLT_RST#

P
C/BE0# NV_WR#0_RE# IN1
G42 C/BE1# NV_WR#1_RE# AY5 5 BUF_PLT_RST# 4 O

do
8.2K_0804_8P4R_5% H47 2
C/BE2# IN2

G
G34 C/BE3# NV_WE#_CK0 AV11

1
RP3 BF5 SN74AHC1G08DCKR_SC70-5

3
PCI_STOP# PCI_PIRQA# NV_WE#_CK1
1 8 G38 PIRQA#
2 7 PCI_PIRQE# PCI_PIRQB# H51 R129
PCI_PIRQC# PCI_PIRQC# PIRQB# 100K_0402_5%
3 6 B37 PIRQC# USBP0N H18 USB20_N0 39
4 5 PCI_PIRQG# PCI_PIRQD# A44 J18 USB-RIGHT1 @
USB20_P0 39

2
PIRQD# USBP0P
A18 USB20_N1 39

in
8.2K_0804_8P4R_5% PCI_REQ#0 USBP1N
PCI_REQ#1
F51 REQ0# USBP1P C18 USB20_P1 39 USB-RIGHT2
A46 REQ1# / GPIO50 USBP2N N20
PCI_REQ#2 B45 P20
PCI_REQ#3 REQ2# / GPIO52 USBP2P
M53 REQ3# / GPIO54 USBP3N J20 USB20_N3 34
USBP3P L20 USB20_P3 34 eSATA-USB
28 PCI_GNT#0 F48 GNT0# USBP4N F20
28 PCI_GNT#1 K45 GNT1# / GPIO51 USBP4P G20
GNT2#: Not pull low, internal pull up 20K

i-
F36 GNT2# / GPIO53 USBP5N A20 USB20_N5 35
28 PCI_GNT#3 H53 GNT3# / GPIO55 USBP5P C20 USB20_P5 35 BT
USBP6N M22
PCI_PIRQE# B41 N22
PCI_PIRQF# PIRQE# / GPIO2 USBP6P
K53 PIRQF# / GPIO3 USBP7N B21
PCI_PIRQG# A36 D21
PCI_PIRQH# PIRQG# / GPIO4 USBP7P
A48 PIRQH# / GPIO5 USBP8N H22
+3VS J22
USBP8P
is
USB
RP4 TP_PCI_RST# K6 E22
T37 PAD PCIRST# USBP9N
1 8 PCI_REQ#3 F22
B PCI_PIRQF# PCI_SERR# USBP9P B
2 7 E44 SERR# USBP10N A22 USB20_N10 40
3 6 PCI_PIRQB# PCI_PERR# E50 C22 Card reader(3 in 1)
PERR# USBP10P USB20_P10 40
4 5 PCI_REQ#0 G24
USBP11N USB20_N11 22
8.2K_0804_8P4R_5% PCI_IRDY# USBP11P H24 USB20_P11 22 Int. Camera
A42 IRDY# USBP12N L24
H44 M24 +3VALW
kn

PCI_DEVSEL# PAR USBP12P

F46 DEVSEL# USBP13N A24 USB20_N13 36
PCI_FRAME# C46 C24 WLAN
FRAME# USBP13P USB20_P13 36
USB_OC#0 2 1
+3VS PCI_PLOCK# D49 10K_0402_5% R696
RP5 PLOCK# USB_OC#5
USBRBIAS# B25 2 1
1 8 PCI_DEVSEL# PCI_STOP# D41 10K_0402_5% R692
PCI_PERR# PCI_TRDY# STOP# USBBIAS USB_OC#6
2 7 C48 TRDY# USBRBIAS D25 2 1 Within 500 mils 2 1
te

3 6 PCI_SERR# R278 22.6_0402_1% 10K_0402_5% R693

4 5 PCI_PLOCK# M7 EXP_CPPE# 2 1
PME# USB_OC#0 10K_0402_5% R694
OC0# / GPIO59 N16 USB_OC#0 39,41
8.2K_0804_8P4R_5% D5 J16 USB_OC#1
13,36,37,41,42 PLT_RST# PLTRST# OC1# / GPIO40 USB_OC#1 34,41 RP6
F16 USB_OC#2
OC2# / GPIO41 USB_OC#3 USB_OC#3
N52 CLKOUT_PCI0 OC3# / GPIO42 L16 4 5
1 2 PLT_RST# P53 E14 USB_OC#4 USB_OC#2 3 6
R695 100K_0402_5% CLKOUT_PCI1 OC4# / GPIO43
2 1 CLK_SIO P46 G16 USB_OC#5 USB_OC#1 2 7
w.

42 CLK_PCI_DDR 22_0402_5% R280 CLKOUT_PCI2 OC5# / GPIO9

2 1 CLK_EC P51 CLKOUT_PCI3 OC6# / GPIO10 F12 USB_OC#6 USB_OC#4 1 8
41 CLK_PCI_EC 33_0402_5% R281
26 CLK_PCILOOP 2 1 CLK_PCH P48 CLKOUT_PCI4 OC7# / GPIO14 T15 EXP_CPPE#
22_0402_5% R279 10K_0804_8P4R_5%

IBEXPEAK-M QV20 A0_FCBGA1071

HM55R1@
ww

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 29 of 58
5 4 3 2 1
 5 4 3 2 1

+3VS

1 2 PCH_GPIO1
10K_0402_5% R214
1 2 BT_DET#
8.2K_0402_5% R215
1 2 PCH_GPIO6
10K_0402_5% R218
1 2 PCH_GPIO17
10K_0402_5% R220 U11F

m
1 2 PCH_GPIO16
D 10K_0402_5% R221 Y3 AH45 D
14,24 VGA_HDMI_HPD BMBUSY# / GPIO0 CLKOUT_PCIE6N
1 2 PCH_GPIO38 CLKOUT_PCIE6P AH46
10K_0402_5% R255 GPIO8 PCH_GPIO1 C38 TACH1 / GPIO1

co
1 2 THM_ALT# Not pull down
10K_0402_5% R259 PCH_GPIO6 D37 TACH2 / GPIO6
1 2 PCH_GPIO48 Internal: Pull up 20k CLKOUT_PCIE7N AF48

MISC
10K_0402_5% R257 EC_SCI# J32 AF47
During Reset: High 41 EC_SCI# TACH3 / GPIO7 CLKOUT_PCIE7P
1 2 PCH_GPIO39
10K_0402_5% R216 Initial: High EC_SMI# F10
41 EC_SMI# GPIO8
1 2 EC_SCI#
10K_0402_5% R224 GPIO15 PCH_GPIO12 K9 U2 GATEA20

a.
LAN_PHY_PWR_CTRL / GPIO12 A20GATE GATEA20 41
a Strong pull up may be needed
+3VALW PCH_GPIO15 T7
for GPIO Functionality GPIO15
1 2 EC_SMI# Internal: Pull down 20k PCH_GPIO16 AA2 AM3
SATA4GP / GPIO16 CLKOUT_BCLK0_N / CLKOUT_PCIE8N CLK_CPU_BCLK# 5
R225 10K_0402_5%
During Reset: Low
1 2 PCH_GPIO57 PCH_GPIO17 F38 TACH0 / GPIO17 CLKOUT_BCLK0_P / CLKOUT_PCIE8P AM1 CLK_CPU_BCLK 5
R226 10K_0402_5% Initial: Low

si
1 2 PCH_GPIO15 35 BT_DET#
BT_DET# Y7 SCLOCK / GPIO22 PECI BG10 PECI 5

GPIO
R227 1K_0402_5%
1 2 PCH_GPIO28 On-Die PLL VR H10 GPIO24 RCIN# T1 KB_RST#
KB_RST# 41
R242 10K_0402_5%
1 2 RST_GATE High = Enabled (Default) 2 @ 1 PCH_GPIO27 AB12 BE10
GPIO27 PROCPWRGD H_PWRGOOD 5

CPU
R223 10K_0402_5% PCH_GPIO27 R274 1K_0402_5%
Low = Disabled
1 2 PCH_GPIO12 PCH_GPIO28 V13 GPIO28 THRMTRIP# BD10 THRMTRIP_PCH# 1 2 H_THERMTRIP# 5
10K_0402_5% R219 R212 56_0402_1%

ne
35,36 BT_PWR# M11 STP_PCI# / GPIO34

35 BT_RST# V6 SATACLKREQ# / GPIO35

C 1 2 C
+VTT
PROJECT_ID0 AB7 BA22 R210 56_0402_1%
SATA2GP / GPIO36 TP1
GPIO39:
CIR_EN# : Pull-High PROJECT_ID1 AB13 AW22
SATA3GP / GPIO37 TP2

do
for non-support CIR PCH_GPIO38 V3 SLOAD / GPIO38 TP3 BB22

GPIO45: PCH_GPIO39 P3 AY45

SDATAOUT0 / GPIO39 TP4
LVDS_SEL : GND for
Dual-Channel Panel H3 PCIECLKRQ6# / GPIO45 TP5 AY46
RST_GATE F1 AV43
5,11 RST_GATE

in
PCIECLKRQ7# / GPIO46 TP6
PCH_GPIO48 AB6 AV45
SDATAOUT1 / GPIO48 TP7
THM_ALT# AA4 AF13
41 THM_ALT# SATA5GP / GPIO49 TP8
GPIO57:
OPTIMUS_EN# : Pull-High PCH_GPIO57 F8 M18
GPIO57 TP9
for non-support OPTIMUS

i-
TP10 N18

A4 VSS_NCTF_1 TP11 AJ24

+3VS +3VS A49

NCTF
VSS_NCTF_2

RSVD
A5 VSS_NCTF_3 TP12 AK41
A50 VSS_NCTF_4
1

PROJECT_ID A52 VSS_NCTF_5 TP13 AK42

R217 R254 A53 VSS_NCTF_6
Name ID1 ID0 10K_0402_5% 10K_0402_5%
is B2
B4
VSS_NCTF_7 TP14 M32
B VSS_NCTF_8 B
NBQAA 11.6/13.3" L L B52 N32
2

PROJECT_ID1 VSS_NCTF_9 TP15

B53 VSS_NCTF_10
NBQAA 14" L H PROJECT_ID0 BE1 M30
VSS_NCTF_11 TP16
BE53 VSS_NCTF_12
1

NWQAA 16" H L BF1 VSS_NCTF_13 TP17 N30

R261 R262 BF53
kn

10K_0402_5% 10K_0402_5% VSS_NCTF_14

*NALAA 17.3" H H BH1 VSS_NCTF_15 TP18 H12
@ @ BH2 VSS_NCTF_16
BH52 AA23
2

VSS_NCTF_17 TP19
BH53 VSS_NCTF_18
BJ1 VSS_NCTF_19 NC_1 AB45
BJ2 VSS_NCTF_20
BJ4 VSS_NCTF_21 NC_2 AB38
te

BJ49 VSS_NCTF_22
BJ5 VSS_NCTF_23 NC_3 AB42
BJ50 VSS_NCTF_24
BJ52 VSS_NCTF_25 NC_4 AB41
BJ53 VSS_NCTF_26
D1 VSS_NCTF_27 NC_5 T39
D2 VSS_NCTF_28 Not pull low
D53
w.

VSS_NCTF_29 internal pull up

E1 VSS_NCTF_30 INIT3_3V# P6
E53 VSS_NCTF_31
TP24 C10 Internal: Pull up 20k
IBEXPEAK-M QV20 A0_FCBGA1071
During Reset: High
HM55R1@ Initial: High
ww

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 30 of 58
5 4 3 2 1
 5 4 3 2 1

+1.05VS +3VS
+1.05VS U11G POWER +3VS_VCCADAC
L12
AB24 VCCCORE[1] VCCADAC[1] AE50 2 1
1 1 1 AB26 69mA 1 2 1 BLM18PG181SN1D_0603
C295 C294 VCCCORE[2]
AB28 VCCCORE[3] VCCADAC[2] AE52

m
+ C473 10U_0805_10V4Z 1U_0402_6.3V4Z AD26 C296 C297 C298
VCCCORE[4]

CRT
D 330U_6.3V_M AD28 AF53 0.01U_0402_25V7K 0.1U_0402_16V4Z 10U_0805_10V4Z D
2 2 VCCCORE[5] VSSA_DAC[1] 2 1 2
AF26 VCCCORE[6]
2

VCC CORE
AF28 VCCCORE[7] VSSA_DAC[2] AF51

co
AF30 VCCCORE[8] close to AE50
AF31 VCCCORE[9]
AH26 VCCCORE[10]
12/16: Add for power team request. AH28 VCCCORE[11]
AH30 VCCCORE[12]
AH31 VCCCORE[13] > 1mA VCCALVDS AH38
AJ30 VCCCORE[14]
AJ31 AH39

a.
VCCCORE[15] VSSA_LVDS

+1.05VS 1432mA
VCCTX_LVDS[1] AP43
59mA VCCTX_LVDS[2] AP45
AT46

LVDS
VCCTX_LVDS[3]
AK24 VCCIO[24] VCCTX_LVDS[4] AT45
+3VS

si
BJ24 VCCAPLLEXP 40mA
VCC3_3[2] AB34

AN20 VCCIO[25] 375mA VCC3_3[3] AB35

AN22 2

HVCMOS
VCCIO[26] 0.1U_0402_16V4Z
AN23 VCCIO[27] VCC3_3[4] AD35
AN24 C303

ne
VCCIO[28]
AN26 VCCIO[29] 1
AN28 VCCIO[30] close to AB34
BJ26 VCCIO[31]
C BJ28 C
VCCIO[32]
AT26 VCCIO[33]
AT28 VCCIO[34]
+1.05VS AU26 VCCIO[35]

do
AU28 VCCIO[36]
1 2 AV26 VCCIO[37]
C304 10U_0805_10V4Z AV28 196mA VCCVRM[2] AT24 +PCH_VRM
VCCIO[38]
1 2 AW26 VCCIO[39]
C305 1U_0402_6.3V4Z AW28 3062mA
VCCIO[40] +VTT

DMI
1 2 BA26 VCCIO[41] VCCDMI[1] AT16
C306 1U_0402_6.3V4Z BA28 61mA
VCCIO[42] +PCH_VCCDMI +PCH_VRM +1.8VS
1 2 BB26 AU16 1 2

in
C307 1U_0402_6.3V4Z VCCIO[43] VCCDMI[2] R335 0_0603_5%
BB28 VCCIO[44] 1
1 2 BC26 C309 2 1
VCCIO[45]

PCI E*
C308 1U_0402_6.3V4Z BC28 1U_0402_6.3V4Z R336 0_0402_5%
VCCIO[46]
BD26 VCCIO[47] 2
BD28 VCCIO[48] close to AT16
BE26 VCCIO[49] VCCPNAND[1] AM16
BE28 VCCIO[50] VCCPNAND[2] AK16

i-
BG26 VCCIO[51] VCCPNAND[3] AK20
BG28 AK19 +1.8VS_PCH_NAND +1.8VS
VCCIO[52] VCCPNAND[4]
BH27 VCCIO[53] VCCPNAND[5] AK15
156mA VCCPNAND[6] AK13 1
R338
2
0_0603_5%
AN30 VCCIO[54] VCCPNAND[7] AM12 2

NAND / SPI
AN31 VCCIO[55] VCCPNAND[8] AM13
+3VS AM15 C311
VCCPNAND[9] 0.1U_0402_16V4Z
2
C310
1
0.1U_0402_16V4Z
AN35
is
VCC3_3[1] 375mA close to Ak13 1

B B

+PCH_VRM AT22 VCCVRM[1] +3VS

BJ18 VCCFDIPLL 37mA VCCME3_3[1] AM8
VCCME3_3[2] AM9
FDI

AM23 85mA AP11

kn

+1.05VS VCCIO[1] VCCME3_3[3] 2

VCCME3_3[4] AP9
C313 0.1U_0402_16V4Z
1
close to AM8
IBEXPEAK-M QV20 A0_FCBGA1071
HM55R1@
te
w.
ww

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 31 of 58
5 4 3 2 1
 5 4 3 2 1

U11J POWER +1.05VS

AP51 VCCACLK[1] VCCIO[5] V24

52mA VCCIO[6] V26 1
C316
AP53 VCCACLK[2] 3062mA VCCIO[7] Y24
VCCIO[8] Y26
1U_0402_6.3V4Z
2
AF23 VCCLAN[1] VCCSUS3_3[1] V28
VCCSUS3_3[2] U28
VccLAN may be grounded if Intel LAN is disabled AF24 VCCLAN[2] 320mA VCCSUS3_3[3] U26
U24

m
VCCSUS3_3[4]
D VCCSUS3_3[5] P28 D
2 1 +TP_PCH_VCCDSW Y20 P26 +3VALW
C320 0.1U_0402_16V4Z DCPSUSBYP VCCSUS3_3[6]
VCCSUS3_3[7] N28

co
Near AD38 VCCSUS3_3[8] N26
+1.05VS AD38 VCCME[1] VCCSUS3_3[9] M28
1 1 1 VCCSUS3_3[10] M26 2 2
@ AD39 L28 C321 C325

USB
C391 C322 C318 VCCME[2] VCCSUS3_3[11]
VCCSUS3_3[12] L26
If two VccME rails can be 22U_0805_6.3V6M 22U_0805_6.3V6M 1U_0402_6.3V4Z AD41 J28 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 VCCME[3] VCCSUS3_3[13] 1 1
J26
combined, only total 2 x 22 µF and AF43
VCCSUS3_3[14]
H28
2 x 1 µF caps are necessary VCCME[4] VCCSUS3_3[15]

a.
163mA VCCSUS3_3[16] H26
AF41 VCCME[5] VCCSUS3_3[17] G28
1849mA VCCSUS3_3[18] G26
AF42 VCCME[6] VCCSUS3_3[19] F28
Near V39 VCCSUS3_3[20] F26
V39 E28 +3VALW +5VALW
VCCME[7] VCCSUS3_3[21]

Clock and Miscellaneous

1 1 1 VCCSUS3_3[22] E26
@ V41 C28

CH751H-40PT_SOD323-2
VCCME[8] VCCSUS3_3[23]

si
C447 C323 C324 C26
VCCSUS3_3[24]

1
22U_0805_6.3V6M 22U_0805_6.3V6M 1U_0402_6.3V4Z V42 B27
2 2 2 VCCME[9] VCCSUS3_3[25] D16 R344
VCCSUS3_3[26] A28
Y39 VCCME[10] VCCSUS3_3[27] A26
100_0402_1%
Y41 U23

2
VCCME[11] VCCSUS3_3[28] +3VS +5VS
Y42 V23 +1.05VS

ne
VCCME[12] VCCIO[56]

1
F24 +PCH_VCC5REFSUS 2 1
V5REF_SUS C326 1U_0402_6.3V4Z D17 R346
+VCCRTCEXT
> 1mA
C 1 2 V9 DCPRTC CH751H-40PT_SOD323-2 C
C327 0.1U_0402_16V4Z 100_0402_1%

2
+1.05VS L17 1 2 196mA > 1mA K49 +PCH_VCC5REF +PCH_VCC5REF
10UH_LB2012T100MR_20% V5REF
1 AU24

do
+PCH_VRM

PCI/GPIO/LPC
VCCVRM[3]
1 1
1

C328 + C329 +3VS C330

220U_6.3V_M_R15 1U_0402_6.3V4Z R347 +1.05VS_PCHDPLL_A
68mA VCC3_3[8] J38
BB51 VCCADPLLA[1]
0_0603_5% BB53 L38 1U_0402_6.3V4Z
2 2 @ VCCADPLLA[2] VCC3_3[9] 2
2
69mA M36 C333
2

L18 1 +1.05VS_PCHDPLL_B VCC3_3[10] 0.1U_0402_16V4Z

2
10UH_LB2012T100MR_20%
BD51 VCCADPLLB[1] 375mA

in
1 BD53 VCCADPLLB[2] VCC3_3[11] N36
1
1
C331 + C332 1U_0402_6.3V4Z AH23 P36
+1.05VS VCCIO[21] VCC3_3[12]
220U_6.3V_M_R17 1U_0402_6.3V4Z 1 1 1 AJ35 VCCIO[22]
AH35 VCCIO[23] VCC3_3[13] U35
2 2 C334 C335 C336 +3VS
1U_0402_6.3V4Z AF34 3062mA
2 2 2 VCCIO[2]
VCC3_3[14] AD13 2 1

i-
1U_0402_6.3V4Z AH34 C337 0.1U_0402_16V4Z
VCCIO[3]
AF32 VCCIO[4]
+VCCSST VCCSATAPLL[1] AK3 For HDA power rail to +1.5V
1
C338
2
0.1U_0402_16V4Z
V12 DCPSST 31mA VCCSATAPLL[2] AK1

+1.05VS

B
1
C341 0.1U_0402_16V4Z
is
2 +V1.1A_INT_VCCSUS Y22 DCPSUS
VCCIO[9] AH22 @ U54 APL5508-25DC-TRL_SOT89-3
B
+3VALW
+3VALW 163mA 2 IN OUT 3 +1.5VALW
P18 VCCSUS3_3[29] 196mA VCCVRM[4] AT20 +PCH_VRM
@ 1

1
C2 GND @
1 2 U19

SATA
VCCSUS3_3[30]

PCI/GPIO/LPC
C343 0.1U_0402_16V4Z AH19 +1.05VS 1U_0603_10V6K C7
kn
VCCIO[10] 1 4.7U_0805_10V4Z
U20 1

2
VCCSUS3_3[31] C342 2
VCCIO[11] AD20
U22 1U_0402_6.3V4Z
VCCSUS3_3[32]
VCCIO[12] AF22
+3VS 2
375mA VCCIO[13] AD19
1
C344
2
0.1U_0402_16V4Z
V15 VCC3_3[5] 3062mA VCCIO[14] AF20
AF19
te

VCCIO[15]
V16 VCC3_3[6] VCCIO[16] AH20
+VTT Y16 AB19
VCC3_3[7] VCCIO[17]
VCCIO[18] AB20
1 2 VCCIO[19] AB22
C345 4.7U_0603_6.3V6K +1.05VS
> 1mA VCCIO[20] AD22
1 2 AT18 V_CPU_IO[1]
C346 0.1U_0402_16V4Z AA34 +PCH_VCCME1 R351 0_0402_5%
w.

1 2
CPU

VCCME[13]
1 2 VCCME[14] Y34 +PCH_VCCME2 R352 1 2 0_0402_5%
C347 0.1U_0402_16V4Z AU18 1849mA Y35 +PCH_VCCME3 R353 1 2 0_0402_5%
V_CPU_IO[2] VCCME[15]
VCCME[16] AA35 +PCH_VCCME4 R354 1 2 0_0402_5%
+RTCVCC
RTC

1 2 A12 2mA 6mA L30 +VCCSUSHDA R82 1 2 0_0402_5% +3VALW VCCSUSHDA can be
VCCRTC VCCSUSHDA
HDA

C351 0.1U_0402_16V4Z
either 1.5V or 3.3V
ww

A 1 @ R83 1 2 0_0402_5% +1.5VALW A

1 2 IBEXPEAK-M QV20 A0_FCBGA1071 C350
C348 1U_0402_6.3V4Z HM55R1@
1U_0402_6.3V4Z For HDA power rail to +3.3V(default) / +1.5V
2
1 2
C349 0.1U_0402_16V4Z
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 32 of 58
5 4 3 2 1
 5 4 3 2 1

U11I
AY7 VSS[159] VSS[259] H49
B11 H5 U11H
VSS[160] VSS[260]
B15 VSS[161] VSS[261] J24 AB16 VSS[0]
B19 VSS[162] VSS[262] K11
B23 VSS[163] VSS[263] K43 AA19 VSS[1] VSS[80] AK30
B31 VSS[164] VSS[264] K47 AA20 VSS[2] VSS[81] AK31
B35 VSS[165] VSS[265] K7 AA22 VSS[3] VSS[82] AK32
B39 VSS[166] VSS[266] L14 AM19 VSS[4] VSS[83] AK34
B43 VSS[167] VSS[267] L18 AA24 VSS[5] VSS[84] AK35

m
B47 VSS[168] VSS[268] L2 AA26 VSS[6] VSS[85] AK38
D B7 VSS[169] VSS[269] L22 AA28 VSS[7] VSS[86] AK43 D
BG12 VSS[170] VSS[270] L32 AA30 VSS[8] VSS[87] AK46
BB12 VSS[171] VSS[271] L36 AA31 VSS[9] VSS[88] AK49

co
BB16 VSS[172] VSS[272] L40 AA32 VSS[10] VSS[89] AK5
BB20 VSS[173] VSS[273] L52 AB11 VSS[11] VSS[90] AK8
BB24 VSS[174] VSS[274] M12 AB15 VSS[12] VSS[91] AL2
BB30 VSS[175] VSS[275] M16 AB23 VSS[13] VSS[92] AL52
BB34 VSS[176] VSS[276] M20 AB30 VSS[14] VSS[93] AM11
BB38 VSS[177] VSS[277] N38 AB31 VSS[15] VSS[94] BB44
BB42 VSS[178] VSS[278] M34 AB32 VSS[16] VSS[95] AD24
BB49 M38 AB39 AM20

a.
VSS[179] VSS[279] VSS[17] VSS[96]
BB5 VSS[180] VSS[280] M42 AB43 VSS[18] VSS[97] AM22
BC10 VSS[181] VSS[281] M46 AB47 VSS[19] VSS[98] AM24
BC14 VSS[182] VSS[282] M49 AB5 VSS[20] VSS[99] AM26
BC18 VSS[183] VSS[283] M5 AB8 VSS[21] VSS[100] AM28
BC2 VSS[184] VSS[284] M8 AC2 VSS[22] VSS[101] BA42
BC22 VSS[185] VSS[285] N24 AC52 VSS[23] VSS[102] AM30
BC32 VSS[186] VSS[286] P11 AD11 VSS[24] VSS[103] AM31

si
BC36 VSS[187] VSS[287] AD15 AD12 VSS[25] VSS[104] AM32
BC40 VSS[188] VSS[288] P22 AD16 VSS[26] VSS[105] AM34
BC44 VSS[189] VSS[289] P30 AD23 VSS[27] VSS[106] AM35
BC52 VSS[190] VSS[290] P32 AD30 VSS[28] VSS[107] AM38
BH9 VSS[191] VSS[291] P34 AD31 VSS[29] VSS[108] AM39
BD48 VSS[192] VSS[292] P42 AD32 VSS[30] VSS[109] AM42
BD49 VSS[193] VSS[293] P45 AD34 VSS[31] VSS[110] AU20
BD5 P47 AU22 AM46

ne
VSS[194] VSS[294] VSS[32] VSS[111]
BE12 VSS[195] VSS[295] R2 AD42 VSS[33] VSS[112] AV22
BE16 VSS[196] VSS[296] R52 AD46 VSS[34] VSS[113] AM49
BE20 VSS[197] VSS[297] T12 AD49 VSS[35] VSS[114] AM7
C BE24 T41 AD7 AA50 C
VSS[198] VSS[298] VSS[36] VSS[115]
BE30 VSS[199] VSS[299] T46 AE2 VSS[37] VSS[116] BB10
BE34 VSS[200] VSS[300] T49 AE4 VSS[38] VSS[117] AN32
BE38 VSS[201] VSS[301] T5 AF12 VSS[39] VSS[118] AN50

do
BE42 VSS[202] VSS[302] T8 Y13 VSS[40] VSS[119] AN52
BE46 VSS[203] VSS[303] U30 AH49 VSS[41] VSS[120] AP12
BE48 VSS[204] VSS[304] U31 AU4 VSS[42] VSS[121] AP42
BE50 VSS[205] VSS[305] U32 AF35 VSS[43] VSS[122] AP46
BE6 VSS[206] VSS[306] U34 AP13 VSS[44] VSS[123] AP49
BE8 VSS[207] VSS[307] P38 AN34 VSS[45] VSS[124] AP5
BF3 VSS[208] VSS[308] V11 AF45 VSS[46] VSS[125] AP8
BF49 P16 AF46 AR2

in
VSS[209] VSS[309] VSS[47] VSS[126]
BF51 VSS[210] VSS[310] V19 AF49 VSS[48] VSS[127] AR52
BG18 VSS[211] VSS[311] V20 AF5 VSS[49] VSS[128] AT11
BG24 VSS[212] VSS[312] V22 AF8 VSS[50] VSS[129] BA12
BG4 VSS[213] VSS[313] V30 AG2 VSS[51] VSS[130] AH48
BG50 VSS[214] VSS[314] V31 AG52 VSS[52] VSS[131] AT32
BH11 VSS[215] VSS[315] V32 AH11 VSS[53] VSS[132] AT36
BH15 VSS[216] VSS[316] V34 AH15 VSS[54] VSS[133] AT41

i-
BH19 VSS[217] VSS[317] V35 AH16 VSS[55] VSS[134] AT47
BH23 VSS[218] VSS[318] V38 AH24 VSS[56] VSS[135] AT7
BH31 VSS[219] VSS[319] V43 AH32 VSS[57] VSS[136] AV12
BH35 VSS[220] VSS[320] V45 AV18 VSS[58] VSS[137] AV16
BH39 VSS[221] VSS[321] V46 AH43 VSS[59] VSS[138] AV20
BH43 VSS[222] VSS[322] V47 AH47 VSS[60] VSS[139] AV24
BH47 VSS[223] VSS[323] V49 AH7 VSS[61] VSS[140] AV30
BH7 VSS[224] VSS[324] V5 AJ19 VSS[62] VSS[141] AV34
C12
C50
VSS[225] VSS[325] V7
V8
is AJ2
AJ20
VSS[63] VSS[142] AV38
AV42
B VSS[226] VSS[326] VSS[64] VSS[143] B
D51 VSS[227] VSS[327] W2 AJ22 VSS[65] VSS[144] AV46
E12 VSS[228] VSS[328] W52 AJ23 VSS[66] VSS[145] AV49
E16 VSS[229] VSS[329] Y11 AJ26 VSS[67] VSS[146] AV5
E20 VSS[230] VSS[330] Y12 AJ28 VSS[68] VSS[147] AV8
E24 VSS[231] VSS[331] Y15 AJ32 VSS[69] VSS[148] AW14
E30 Y19 AJ34 AW18
kn

VSS[232] VSS[332] VSS[70] VSS[149]

E34 VSS[233] VSS[333] Y23 AT5 VSS[71] VSS[150] AW2
E38 VSS[234] VSS[334] Y28 AJ4 VSS[72] VSS[151] BF9
E42 VSS[235] VSS[335] Y30 AK12 VSS[73] VSS[152] AW32
E46 VSS[236] VSS[336] Y31 AM41 VSS[74] VSS[153] AW36
E48 VSS[237] VSS[337] Y32 AN19 VSS[75] VSS[154] AW40
E6 VSS[238] VSS[338] Y38 AK26 VSS[76] VSS[155] AW52
E8 VSS[239] VSS[339] Y43 AK22 VSS[77] VSS[156] AY11
te

F49 VSS[240] VSS[340] Y46 AK23 VSS[78] VSS[157] AY43

F5 VSS[241] VSS[341] P49 AK28 VSS[79] VSS[158] AY47
G10 VSS[242] VSS[342] Y5
G14 Y6 IBEXPEAK-M QV20 A0_FCBGA1071
VSS[243] VSS[343] HM55R1@
G18 VSS[244] VSS[344] Y8
G2 VSS[245] VSS[345] P24
G22 VSS[246] VSS[346] T43
G32 AD51
w.

VSS[247] VSS[347]
G36 VSS[248] VSS[348] AT8
G40 VSS[249] VSS[349] AD47
G44 VSS[250] VSS[350] Y47
G52 VSS[251] VSS[351] AT12
AF39 VSS[252] VSS[352] AM6
H16 VSS[253] VSS[353] AT13
H20 VSS[254] VSS[354] AM5
ww

A H30 VSS[255] VSS[355] AK45 A

H34 VSS[256] VSS[356] AK39
H38 VSS[257] VSS[366] AV14
H42 VSS[258]

Security Classification Compal Secret Data Compal Electronics, Inc.

IBEXPEAK-M QV20 A0_FCBGA1071 2009/10/01 2010/10/01 Title
HM55R1@
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 33 of 58
5 4 3 2 1
 5 4 3 2 1

SATA HDD Conn. SATA ODD Conn

+5VS
Place closely JHDD SATA CONN.
1.2A

1 1 1 1
C356 C357 C358 C359
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2

m
JODDB
D 14 +5VS D
GND
SSD HDD need 400mA for 3V(PHISON) GND 13
+3VS 12 1.1A
12

co
+3VS rail reserve for SSD 11 11
10 10
1 1 1 9 9
C363 C364 1 C365 C366 8
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 8
7 7
@ @ @ @ 6 SATA_PRX_DTX_P4 C375 1 2 0.01U_0402_25V7K
2 2 2 6 SATA_PRX_C_DTX_P4 25
5 SATA_PRX_DTX_N4 C376 1 2 0.01U_0402_25V7K
2 5 SATA_PRX_C_DTX_N4 25
4

a.
4 SATA_PTX_C_DRX_N4 C377 1
3 3 2 0.01U_0402_25V7K SATA_PTX_DRX_N4 25
2 SATA_PTX_C_DRX_P4 C378 1 2 0.01U_0402_25V7K
2 SATA_PTX_DRX_P4 25
1 1
JHDD @ ACES_88058-120N

GND 1

si
2 SATA_PTX_C_DRX_P1 C369 1 2 0.01U_0402_25V7K
A+ SATA_PTX_DRX_P1 25
3 SATA_PTX_C_DRX_N1 C367 1 2 0.01U_0402_25V7K
A- SATA_PTX_DRX_N1 25
GND 4
5 SATA_PRX_DTX_N1 C368 1 2 0.01U_0402_25V7K
B- SATA_PRX_C_DTX_N1 25
6 SATA_PRX_DTX_P1 C370 1 2 0.01U_0402_25V7K
B+ SATA_PRX_C_DTX_P1 25
GND 7

ne
V33 8 +3VS
V33 9
V33 10
C 11 C
GND
GND 12
GND 13
V5 14 +5VS

do
V5 15
V5 16
GND 17
Reserved 18
GND 19
V12 20
24 GND V12 21
23 22

in
GND V12

@ SUYIN_127072FR022G210ZR_RV

i-
+USB_VCCB
W=60mils
eSATA/USB +5VALW 2A +USB_VCCB W=60mils
U15 220U_6.3V_M_R15 1000P_0402_50V7K
1
2
GND VOUT 8
7
is 1 1 1
B VIN VOUT B
3 VIN VOUT 6
USB_EN# 4 5 C379 +
39,41 USB_EN# EN FLG USB_OC#1 29,41
C380 C381
RT9715BGS_SO8 2 2
1 2
C383
4.7U_0805_10V4Z 0.1U_0402_16V4Z
kn

@
2
@ D18
2
1
3
eSATA/USB Conn
JESATA
te

AZC199-02S.R7G_SOT23-3 1 USB
USB20_N3_R VBUS
2 D-
USB20_P3_R 3 D+
4 GND
Reserve for EMI request
5 GND
@ R72 0_0402_5% C385 1 2 0.01U_0402_25V7K SATA_PTX_C_DRX_P5 6
25 SATA_PTX_DRX_P5 A+ ESATA
1 2 C386 1 2 0.01U_0402_25V7K SATA_PTX_C_DRX_N5 7
w.

25 SATA_PTX_DRX_N5 A-
8 GND
C387 1 2 0.01U_0402_25V7K SATA_PRX_DTX_N5 9
25 SATA_PRX_C_DTX_N5 B-
L52 C388 1 2 0.01U_0402_25V7K SATA_PRX_DTX_P5 10
25 SATA_PRX_C_DTX_P5 B+
29 USB20_N3 4 3 USB20_N3_R 11
4 3 GND
12 GND
29 USB20_P3 1 2 USB20_P3_R 13
1 2 GND
ww

A 14 GND A
WCM-2012-900T_0805 15 GND
@ R85 0_0402_5% @ TYCO_1759576-1
1 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 34 of 58
5 4 3 2 1
 5 4 3 2 1

BlueTooth Interface MDC 1.5 Conn.

+3VS +3VS
+3VALW 1 2 +MDC_VCC
MDC@ R50 0_0603_5% 1 1 1

2
BT@ 2 +1.5VALW 1 2
R361 C396 @ R51 0_0603_5% C393 C392 C395

1
100K_0402_5% 0.1U_0402_16V7K @ 1000P_0402_50V7K 0.1U_0402_16V4Z 4.7U_0805_10V4Z
R44 2 MDC@ 2 MDC@ 2 MDC@
For HDA power rail to +3.3V(default) / +1.5V

3
1 S

m
0_0603_5%

1
G
D 30,36 BT_PWR# 1 2 2 D
BT@R362
BT@R362 47K_0402_5% 1

2
BT@ D Q28 BT@

co
C390 AO3413_SOT23 JMDC
0.01U_0402_25V7K
2
+BT_VCC 1 GND1 RES0 2 +MDC_VCC
25 AZ_SDOUT_MD 3 IAC_SDATA_OUT RES1 4
(MAX=200mA) 5 GND2 3.3V 6 +3VALW
+BT_VCC Bluetooth Connector 25 AZ_SYNC_MD 7 IAC_SYNC GND3 8
1 25 AZ_SDIN1_MD 2 1 AZ_SDIN1_MD_R 9 IAC_SDATA_IN GND4 10
R369 33_0402_5% MDC@ 11 12

a.
25 AZ_RST_MD# IAC_RESET# IAC_BITCLK AZ_BITCLK_MD 25
C398 C399 JBT

2
4.7U_0805_10V4Z 0.1U_0402_16V4Z 1
BT@ 2 BT@ 1 R368
2

GND
GND
GND
GND
GND
GND
2 10_0402_5%
29 USB20_P5 3 3
4 @
29 USB20_N5 4
30 BT_RST# 1 BT@ 2 BT_RESET# 5 7 ACES_88018-124G

13
14
15
16
17
18

1
R366 0_0402_5% 5 G1 @
30 BT_DET# 6 6 G2 8 1

si
C400
C397 @ ACES_87213-0600G Connector for MDC Rev1.5 10P_0402_50V8J
0.1U_0402_16V4Z @
BT@ 2

For EMI

ne
C please close to JKB
TP On&Off BTN Conn. C

KEYBOARD KSO16 1
C401
2
100P_0402_50V8J

do
KSO17 1 2 JTPB
CONN. KSO2
C402
1
100P_0402_50V8J
2
1
2
1
2
KSO0
KSI6
C404 100P_0402_50V8J 3
KSO1 3
1 2 4 4
C405 100P_0402_50V8J 5
KSI[0..7] KSO0 GND
KSI[0..7] 41 1 2 GND 6
C406 100P_0402_50V8J

in
KSO[0..17] KSO4 1 2 @ P-TWO_161011-04021
KSO[0..17] 41
C407 100P_0402_50V8J
KSO3 1 2
C408 100P_0402_50V8J
JKB KSO5 1 2
JKB34 1 2 C409 100P_0402_50V8J
34
33
KSO16 R372 300_0402_5%
+3VS
KSO14 1
C410
2
100P_0402_50V8J
TP On&Off BTN On M/B

i-
32 KSO17 KSO6
31 1 2
C411 100P_0402_50V8J
30 KSO7 SW4
29 1 2
KSO2 C412 100P_0402_50V8J KSI6 1 3 KSO0
28 KSO1 KSO13
27 1 2
KSO0 C413 100P_0402_50V8J 2 4
26 KSO4 KSO8
25 1 2
KSO3
is
C415 100P_0402_50V8J NTC017-DA1J-D160T

6
5
24 KSO5 KSO9
23 1 2
B KSO14 C416 100P_0402_50V8J B
22 KSO6 KSO10
21 1 2
KSO7 C417 100P_0402_50V8J
20 KSO13 KSO11
19 1 2
KSO8 C418 100P_0402_50V8J
18 KSO9 KSO12 1 2
kn

17 KSO10 C419 100P_0402_50V8J

16 KSO11 KSO15 1 2
15
14
13
KSO12
KSO15 KSI7
C420
1
100P_0402_50V8J
2
Touch PAD Connector
KSI7 C421 100P_0402_50V8J
12 KSI2 KSI2
11 1 2
KSI3 C422 100P_0402_50V8J
10
te

KSI4 KSI3 1 2 JTOUCH

9 KSI0 C423 100P_0402_50V8J
8 +5VS 1 1
KSI5 KSI4 1 2 2
7 41 TP_CLK 2
KSI6 C424 100P_0402_50V8J 3
6 41 TP_DATA 3
KSI1 KSI0 1 2 4
5 43 SW_L 4
JKB4 2 1 +3VS C425 100P_0402_50V8J 5 7
4 43 SW_R 5 G7
CAPS_LED# R376 300_0402_5% KSI5 1 2 6 8
3 CAPS_LED# 41 6 G8
C427 100P_0402_50V8J
w.

2 NUM_LED# KSI6 @ P-TWO_161021-06021

1 NUM_LED# 41 1 2 2
C429 100P_0402_50V8J 1
ACES_88170-3400 KSI1 1 2 3
@ C431 100P_0402_50V8J
CAPS_LED# 1 2 D57
C433 100P_0402_50V8J AZ5125-02S.R7G_SOT23-3
NUM_LED# 1 2
ww

C435 100P_0402_50V8J
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 35 of 58
5 4 3 2 1
PCIe Mini Card-WLAN

+3VS +1.5VS
MAX : 2.75A For SED For SED
0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 1 1 1 1

1
CM1 CM2 CM3 C253 CM7 CM8 CM9 C254
47P_0402_50V8J 47P_0402_50V8J

2
2 2 2 2 2 2

m
@ @
0.01U_0402_25V7K 4.7U_0805_10V4Z 0.01U_0402_25V7K 4.7U_0805_10V4Z

co
+1.5VS +3VS

JWLAN
1 1 2 2
3 3 4 4
BT_CTRL 5 6

a.
5 6
26 CLKREQ_WLAN# 7 7 8 8
9 9 10 10
1

D
26 CLK_WLAN# 11 11 12 12
30,35 BT_PWR# 2 Q25 13 14
26 CLK_WLAN 13 14
G 2N7002_SOT23-3 15 16
15 16
S 17 18
3

17 18 WL_OFF#
19 19 20 20 WL_OFF# 41

si
21 22 PLT_RST#
21 22 PLT_RST# 13,29,37,41,42
26 PCIE_PRX_WLANTX_N2 23 23 24 24
26 PCIE_PRX_WLANTX_P2 25 25 26 26
WLAN&BT Combo module circuits 27 27 28 28
29 29 30 30 PM_SMBCLK 11,12,22,26
BT BT 26 PCIE_PTX_C_WLANRX_N2 31 31 32 32 PM_SMBDATA 11,12,22,26
on module on module 26 PCIE_PTX_C_WLANRX_P2 33 33 34 34
35 36

ne
35 36 USB20_N13 29
Enable Disable 37 37 38 38 USB20_P13 29
+3VS 39 39 40 40
41 41 42 42
BT_CRTL HI LO 43 43 44 44
45 45 46 46
47 47 48 48
BT_PWR# LO HI 41 E51_TXD 1 2 49 49 50 50

do
R16 1 2 0_0402_5% 51 52
41 E51_RXD 51 52
R17 0_0402_5%
53 GND1 GND2 54
Debug card using
@ FOX_AS0B226-S40N-7F

in
i-
is
kn
te
w.
ww

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 36 of 58
 5 4 3 2 1

UL1

26 PCIE_PRX_C_LANTX_P1 CL1 1 2 0.1U_0402_16V7K PCIE_PRX_LANTX_P1 22 HSOP LED3/EEDO 31 LL1,CL13 will be changed to CL4,CL5,CL6,CL7 close to Pin 27,39,47,48
37 LAN_SK_LINK# +LAN_VDD10
LED1/EESK 2.2uH&4.7uF after EVT test
26 PCIE_PRX_C_LANTX_N1 CL2 1 2 0.1U_0402_16V7K PCIE_PRX_LANTX_N1 23 HSON LED0 40 LAN_ACTIVITY#
LL1 +3V_LAN
17 30 RL2 2 1 10K_0402_5% +LAN_REGOUT 1 2
26 PCIE_PTX_C_LANRX_P1 HSIP EECS/SCL
18 32 RL1 2 1 10K_0402_5% 2.2UH +-5% NLC252018T-2R2K-N 1 2
26 PCIE_PTX_C_LANRX_N1 HSIN EEDI/SDA
1 2 0.1U_0402_16V4Z CL4
Layout Note: LL1 must be 1 2
+3V_LAN RL19 0_0402_5% 16 1 LAN_MDI0+ within 200mil to Pin36, CL13 CL9 0.1U_0402_16V4Z CL5
26 CLKREQ_LAN# CLKREQB MDIP0
2 LAN_MDI0- CL13,CL9 must be within 4.7U_0603_6.3V6K 0.1U_0402_16V4Z 1 2
EC_SWI# MDIN0 LAN_MDI1+ 200mil to LL1 2 1 0.1U_0402_16V4Z CL6
1 2 13,29,36,41,42 PLT_RST# 25 PERSTB MDIP1 4

m
@RL3
@ RL3 100K_0402_5% 5 LAN_MDI1- +LAN_REGOUT: Width =60mil 1 2
MDIN1 LAN_MDI2+ 0.1U_0402_16V4Z CL7
D 26 CLK_LAN 19 REFCLK_P NC/MDIP2 7 D
20 8 LAN_MDI2- 1 2
26 CLK_LAN# REFCLK_N NC/MDIN2
10 LAN_MDI3+ 8111E@ 0.1U_0402_16V4Z CL10
NC/MDIP3 LAN_MDI3-

co
+3VS NC/MDIN3 11 CL10 Close to Pin12
LAN_X1 43 CKXTAL1
LAN_X2 44 13 +LAN_VDD10
CKXTAL2 DVDD10
1

DVDD10 29
RL6 +LAN_VDD10 +LAN_EVDD10
DVDD10 41 CL19,CL20,CL21,CL22 close to Pin 3,13,29,45
1K_0402_1% EC_SWI# 28
27 EC_SWI# LANWAKEB
2 1
ISOLATEB 26 27 LL2 0_0603_5% +LAN_VDD10

a.
+3V_LAN 1 2
2

ISOLATEB ISOLATEB DVDD33

DVDD33 39
CL18 CL17 1 2
14 12 +3V_LAN 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z CL19
8111E@ RL11 1 NC/SMBCLK AVDD33 +3V_AVDDXTAL 2 1
2 10K_0402_5% 15 NC/SMBDATA AVDD33 42 1 2
RL7 +3V_LAN RL22 1 2 1K_0402_5% 38 47 0.1U_0402_16V4Z CL20
15K_0402_5% GPO/SMBALERT AVDD33
AVDD33 48 Close to Pin 21 1 2
0.1U_0402_16V4Z CL21
ENSWREG 33 1 2

si
ENSWREG 0.1U_0402_16V4Z CL22
EVDD10 21 +LAN_EVDD10
+LAN_VDDREG 34 VDDREG 1 2
35 3 +LAN_VDD10 8111E@ 0.1U_0402_16V4Z CL23
VDDREG AVDD10 +3V_LAN +LAN_VDDREG
AVDD10 6 1 2
RTL8105E RTL8111E 9 8111E@ 0.1U_0402_16V4Z CL24
AVDD10
1 2 46 RSET AVDD10 45 2 1 1 2
Pin14 NC NC RL5 2.49K_0402_1% 0_0603_5% LL3 1 2 8111E@ 0.1U_0402_16V4Z CL25
24 36 +LAN_REGOUT CL23,CL24,CL25 Close to Pin6,9,41

ne
GND REGOUT CL28 CL29
Pin15 NC 10k PD 49 PGND ,respectively
4.7U_0603_6.3V6K 0.1U_0402_16V4Z
RTL8105E-VB-GR QFN _6X6 2 1
Pin38 1k PU
C C
8105E@

+3VALW TO +3V_LAN

do
+3VALW +3V_LAN
+3VALW YL1
+3V_AVDDXTAL +3V_LAN
LAN_X1 2 1 LAN_X2 RL8 0_0402_5%
2

Vgs=-4.5V,Id=3A,Rds<97mohm
RL25 25MHZ_20PF_7A25000012 RL4 +LAN_VDD10
100K_0402_5% 2 1 1 0_0402_5% @RL9
@ RL9 0_0402_5%
CL12 Reserved For 1.05V Crystal

in
0.1U_0402_16V7K QL1 CL26 CL27 1
1

S
27P_0402_50V8J 27P_0402_50V8J ENSWREG
1 G 2 2 CL11
41 WOL_EN# 1 2 2
RL16 47K_0402_5% 0.1U_0402_16V4Z
D RL23 2
1
1

CL14 AO3413_SOT23 0_0402_5% CL11 close to pin42

0.01U_0402_25V7K +3V_LAN @
2

i-
1 1
CL15 CL8
4.7U_0805_10V4Z 1U_0402_6.3V4Z

@ 2 2 For EMI Request

CL43 2
LAN Conn.
1 68P_0402_50V8J
is JLAN
B B
LAN_ACTIVITY# 2 1 LAN_ACTIVITY#_R 12
RL10 150_0402_5% Amber LED-

+3V_LAN 2 1 11 Amber LED+ SHLD4 16

RL17 150_0402_5%
UL3 RJ45_MIDI3- 8 15
PR4- SHLD3
kn

LAN_MDI0+ 1 16 RJ45_MIDI0+ RJ45_MIDI3+ 7

LAN_MDI0- TD+ TX+ RJ45_MIDI0- PR4+
2 TD- TX- 15
3 14 RJ45_MIDI1- 6
CT CT PR2-
4 NC NC 13
5 12 RJ45_MIDI2- 5
NC NC PR3-
6 CT CT 11
LAN_MDI1+ 7 10 RJ45_MIDI1+ RJ45_MIDI2+ 4
LAN_MDI1- RD+ RX+ RJ45_MIDI1- PR3+
8 9
te

RD- RX- RJ45_MIDI1+ 3 PR2+

LFE8456E-R RJ45_MIDI0- 2
8105E@ PR1-
SHLD2 14
RJ45_MIDI0+ 1
UL4 PR1+
8111E@ 8111E@ LAN_SK_LINK# 2 1 LAN_SK_LINK#_R 10 13
RL14 150_0402_5% Green LED- SHLD1
1 TCT1 MCT1 24 2 1 1 2
w.

LAN_MDI3- 2 23 RJ45_MIDI3- CL46 1000P_0402_50V7K RL21 75_0402_1% 9

LAN_MDI3+ TD1+ MX1+ RJ45_MIDI3+ For EMI Request Green LED+
3 TD1- MX1- 22 2 1
8111E@ 8111E@ CL44 68P_0402_50V8J LIYO_101005-00803-3
4 21 2 1 1 2 2 1 @
LAN_MDI2- TCT2 MCT2 RJ45_MIDI2- CL45 1000P_0402_50V7K RL20 75_0402_1% +3V_LAN
5 TD2+ MX2+ 20
LAN_MDI2+ 6 19 RJ45_MIDI2+ RL18 150_0402_5%
TD2- MX2-
7 18 2 1 1 2 RJ45_GND CL36 1 2 1000P_1808_3KV7K LANGND
TCT3 MCT3
ww

LAN_MDI1- 8 17 RJ45_MIDI1- CL42 1000P_0402_50V7K RL15 75_0402_1% 1 1

A LAN_MDI1+ TD3+ MX3+ RJ45_MIDI1+ CL37 CL38 A
9 TD3- MX3- 16

10 15 2 1 1 2 RJ45_GND 0.1U_0402_16V4Z 4.7U_0603_6.3V6K

LAN_MDI0- TCT4 MCT4 RJ45_MIDI0- CL41 1000P_0402_50V7K RL13 75_0402_1% 2 2
11 TD4+ MX4+ 14
LAN_MDI0+ 12 13 RJ45_MIDI0+
TD4- MX4-
1
Place these components
colsed to LAN chip CL34 SUPERWORLD_SWG150401
Security Classification Compal Secret Data Compal Electronics, Inc.
0.1U_0402_25V6 8111E@ Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401849 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 18, 2010 Sheet 37 of 58
5 4 3 2 1
 5 4 3 2 1

600 mA RA2 Pin36 Pin25

+PVDD1 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z +5VS
1 1 0_0603_5% 1 1
CA57 CA45
CA56 CA44 Pin37 Pin24

2
+DVDD_IO
2 2 2 2 Pin38

2
+3VS 1 2 0.1U_0402_16V4Z @ JA1 10U_0805_10V4Z 10U_0805_10V4Z
RA19 0_0603_5% JUMP_43X39 Pin39

1
1 1 place close to chip
+1.5VS 1 2 CA2 CA1

m
@ RA20 0_0603_5% @ RA11
D 10U_0805_10V4Z 0_0603_1% D
2 2 +3VS_DVDD +PVDD2 2 1 0.1U_0402_16V4Z +5VS
1 1 1 1
ALC259-GR

co
35 mA CA59
+3VS 2 1 0.1U_0402_16V4Z CA61 @ CA60 @ @ CA58
RA1 0_0603_5% 1 1 0.1U_0402_16V4Z 10U_0805_10V4Z 10U_0805_10V4Z
2 2 2 2
CA8 CA7 +AVDD
10U_0805_10V4Z RA3
2 2 68 mA 10U_0805_10V4Z 0.1U_0402_16V4Z 2 1 +5VS
0_0603_5%

a.
39

46

25

38
1 1 1 1

9
place close to chip UA1 CA3 CA4 CA5 CA6
Pin48 Pin13

DVDD_IO

PVDD1

PVDD2

AVDD1

AVDD2
DVDD
2 2 2 2 place close to chip
10U_0805_10V4Z 0.1U_0402_16V4Z ANALOG

si
23 40 Pin1 Pin12
LINE1_L SPK_OUT_L+ SPKL+ 39
24 LINE1_R SPK_OUT_L- 41 SPKL- 39
DIGITAL
14 45 SPKR+ 39
15
LINE2_L SPK_OUT_R+
44 (Include Themal PAD) Moat
LINE2_R SPK_OUT_R- SPKR- 39
CA21 4.7U_0805_10V4Z
2 1 21 32 RA4 75_0402_1%

ne
39 MIC1_R_L MIC1_L HP_OUT_L HP_L 39
Ext. Mic 2 1 22 33 RA5 75_0402_1%
39 MIC1_R_R MIC1_R HP_OUT_R HP_R 39
CA22 4.7U_0805_10V4Z 16 MIC2_L
Beep sound
C Close to UA1 17 MIC2_R
C

SYNC 10 AZ_SYNC_HD 25
EC_MUTE#
22 INT_MIC_DATA 2 GPIO0/DMIC_DATA BCLK 6 AZ_BITCLK_HD 25
1

do
For EMI Request
RA29 2 1 INT_MIC_CLK_R 3
22 INT_MIC_CLK GPIO1/DMIC_CLK
4.7K_0402_5% L58 5 AZ_SDOUT_HD 25
FBMA-L10-160808-301LMT_0603 SDATA_OUT RA6 33_0402_5%
41 EC_MUTE#
EC_MUTE# 4 8 AZ_SDIN0_HD_R 1 2 AZ_SDIN0_HD 25
EC Beep
2

PD# SDATA_IN RA7

41 EC_BEEP# 1 2
47K_0402_5%
25 AZ_RST_HD# 11 47

in
RESET# EAPD
For EMI Request 48
Close to UA1 1 2 MONO_IN 12 PCBEEP
SPDIFO PCI Beep RA8
CA13
CA12 100P_0402_50V8J 20 1 2 1 2 MONO_IN
MONO_OUT 25,28 PCH_SPKR
47K_0402_5%
@ CA62 100P_0402_50V8J SENSE_A 13 0.1U_0402_16V4Z
AZ_BITCLK_HD SENSE A
1 2 2 1 MIC2_VREFO 29
@ RA27 100_0402_5%

i-
18 SENSE B
MIC1_VREFO_R 30 +MIC1_VREFO_R CA43 10U_0805_10V4Z
1 2 36 CBP LDO_CAP 28 1 2

1
@ CA63 0.01U_0402_25V4Z CA15 1
AZ_RST_HD# 2 1 +3VS 2.2U_0603_6.3V4Z 35 27 AC_VREF
@ RA28 4.7K_0402_5% CBN VREF RA12 CA18
+MIC1_VREFO_L 31 19 AC_JDREF2 RA9 1 20K_0402_1% 10K_0402_5% 0.1U_0402_16V4Z
MIC1_VREFO_L JDREF 2
1 1

2
43
42
PVSS2
is
CPVEE 34 1
CA14
2
2.2U_0603_6.3V4Z CA17 CA16 @
B CA47 1 PVSS1 B
2 0.1U_0603_50V7K 49 DVSS2 AVSS1 26 10U_0805_10V4Z
2 2
7 DVSS1 AVSS2 37
CA48 1 2 0.1U_0603_50V7K 0.1U_0402_16V4Z
ALC259-GR_QFN48_7X7
CA49 1 2 0.1U_0603_50V7K place close to chip
DGND AGND
kn

CA50 1 2 0.1U_0603_50V7K

1 2
RA18 0_0603_5%
te

Sense Pin Impedance Codec Signals Function

place close to chip
39.2K PORT-I (PIN 32, 33) Headphone out
w.

39 MIC_SENSE 2 1 SENSE_A
RA10 20K_0402_1%
20K PORT-B (PIN 21, 22) Ext. MIC
SENSE A
10K PORT-C (PIN 23, 24) 39 NBA_PLUG
RA21 39.2K_0402_1%
ww

A A
5.1K (PIN 48)

39.2K PORT-E (PIN 14, 15)

SENSE B 20K PORT-F (PIN 16, 17)

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

10K PORT-H (PIN 20) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 38 of 58
5 4 3 2 1
Speaker Connector HeadPhone/LINE Out JACK

placement near Audio Codec UA1 HP_R

38 HP_R
HP_L
38 HP_L

m
SPKR+ LA4 1 2 FBMA-L11-160808-800LMT_2P SPK_R1
38 SPKR+
1

co
CA25
@ 10U_0805_10V4Z DA5 AZ5125-02S.R7G_SOT23-3
2 2
CA27 2
1 1U_0402_6.3V4Z 1
@ 3
CA26 1
@ 10U_0805_10V4Z JSPK

a.
SPKR- 2 SPK_R2 SPK_R1
38 SPKR- 1 2 1 1
LA5 FBMA-L11-160808-800LMT_2P SPK_R2 2
SPK_L1 2
3
SPKL+ LA2
SPK_L2 4
3
4
Ext.MIC/LINE IN JACK
38 SPKL+ 1 2 FBMA-L11-160808-800LMT_2P SPK_L1
1 ACES_85204-0400N
2 @

si
CA19 1 placement near Audio Codec UA1
@ 10U_0805_10V4Z 2 3
2 CA24
1U_0402_6.3V4Z DA4 AZ5125-02S.R7G_SOT23-3 RA22
1
@ 2.2K_0402_5%
CA20 1
2 1 +MIC1_VREFO_R
@ 10U_0805_10V4Z
SPKL- 2 SPK_L2 RA23
1 2

ne
38 SPKL-
LA3 FBMA-L11-160808-800LMT_2P 1K_0402_5%
2 1 MIC1_R
38 MIC1_R_R
2 1 MIC1_L
38 MIC1_R_L
1K_0402_5%
RA24

do
2 1 +MIC1_VREFO_L
RA25
2.2K_0402_5%

USB Board

in
Audio & USB Sub-Board Conn.

i-
Reserve for EMI request
@ R73 0_0402_5%
1 2
L53

29 USB20_N0
is 1 1 2 2 USB20_N0_R +USB_VCCA

W=60mils JUSBB
W=60mils 29 USB20_P0 4 3 USB20_P0_R
4 3 1
+5VALW
U14
2A +USB_VCCA WCM-2012-900T_0805 2
3
@ R87 0_0402_5% 4
1 8
kn

GND VOUT USB20_N0_R 5

2 VIN VOUT 7 1 2 6
3 6 USB20_P0_R
VIN VOUT 7
34,41 USB_EN# 4 EN FLG 5 USB_OC#0 29,41 8
1 Reserve for EMI request 9
RT9715BGS_SO8 USB20_N1_R
C362 @ R77 0_0402_5% USB20_P1_R 10
4.7U_0805_10V4Z 11
1 2 12
2 @
te

L54 HP_R 13
HP_L 14
USB20_N1_R 15
29 USB20_N1 1 1 2 2 16
MIC1_L
MIC1_R 17
USB20_P1_R NBA_PLUG 18
29 USB20_P1 4 4 3 3 38 NBA_PLUG 19
MIC_SENSE
w.

38 MIC_SENSE 20
WCM-2012-900T_0805
1 1 @ ACES_85201-20051
@ R88 0_0402_5%
1 2 CA64 CA65
0.1U_0402_16V4Z 0.1U_0402_16V4Z
@ 2 2 @
ww

For EMI Request

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 39 of 58
 5 4 3 2 1

@
CC2
100P_0402_50V8J
2 1

m
D D
RC1
6.19K_0402_1% UC1

co
2 1 1 REFE
17 CR_LED#
GPIO0 CR_LED# 43
USB20_N10 2
+3VS_CR 29 USB20_N10 DM
USB20_P10 3 24 CLK_48M_CR < 48MHz >
29 USB20_P10 DP CLK_IN CLK_48M_CR 22

+3VS 1 2 4 3V3_IN XD_D7 23

RC4 0_0603_5% +VCC_3IN1 5
V1_8 CARD_3V3 MSBS
6 22

a.
V18 SP14 SD_DATA2_MS_DATA5
1 1 1 SP13 21
CC1 CC3 CC4 7 20 MS_DATA1_SD_DATA3
4.7U_0805_10V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z XD_CD# SP12
SP11 19
SDWP_MSCLK_R 1 2 SDWP_MSCLK 8 18 SDCMD
2 2 2 RC24 0_0402_5% MSCD# SP1 SP10 MS_DATA0_SD_DATA5
9 SP2 SP9 16
1 SD_DATA1 10 15 MS_DATA2_SDCLK 1 2 MS_DATA2_SDCLK_R
SP3 SP8

EPAD
SD_DATA0 11 14 RC22 0_0402_5%
SP4 SP7

si
CC10 MS_DATA3_SD_DATA7 12 13 SDCD# 1 CC9
SP5 SP6 10P_0402_50V8J
10P_0402_50V8J
2 RTS5138-GR_QFN24_4X4 @
@

25
2

For EMI request

ne
For EMI request

C C

do
< 3 in 1 Card Reader >
JREAD
1 SDWP_MSCLK_R
SD-WP SD_DATA1
SD-DAT1 2
3 SD_DATA0
SD-DAT0
SD-GND 4
5

in
MS-GND MSBS
MS-BS 6
7 MS_DATA2_SDCLK_R
SD-CLK MS_DATA1_SD_DATA3
MS-DAT1 8
9 MS_DATA0_SD_DATA5
MS-DAT0
SD-VCC 10 +VCC_3IN1
MS-DAT2 11
SD-GND 12 1 1
MSCD# CC6 CC5

i-
MS-INS 13
14 MS_DATA3_SD_DATA7
MS-DAT3 SDCMD 0.1U_0402_16V4Z 1U_0402_6.3V4Z
SD-CMD 15
2 2
MS-SCLK 16
MS-VCC 17
SD-DAT3 18
MS-GND 19
22 20 SD_DATA2_MS_DATA5
GND1 SD-DAT2
23 GND2 SD-CD 21
is SDCD#
B @ TAITW_R009-025-LR_NR B
kn
te
w.
ww

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401849 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 18, 2010 Sheet 40 of 58
5 4 3 2 1
 5 4 3 2 1

+3VL
+3VL
for EMI request 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 1 1 2 2 C442
CLK_PCI_EC C436 1 2
C437 C438 C439 C440 C441

1
0.1U_0402_16V4Z 1000P_0402_50V7K 0.1U_0402_16V4Z
R377 2 2 2 2 1 1

111
125
0.1U_0402_16V4Z 1000P_0402_50V7K

22
33
96

67
10_0402_5%

9
U19

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
2
1

m
D C443 D
10P_0402_50V8J 1 21
2 30 GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F
30 KB_RST# 2 KBRST#/GPIO01 BEEP#/PWM2/GPIO10 23 EC_BEEP# 38

co
25,42 SERIRQ 3 SERIRQ# FANPWM1/GPIO12 26
25,42 LPC_FRAME# 4 LFRAME# ACOFF/FANPWM2/GPIO13 27 ACOFF 47
25,42 LPC_AD3 5 LAD3
+3VL 25,42 LPC_AD2 7 LAD2 PWM Output
R378 8 63 BATT_TEMPA
25,42 LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMPA 46
47K_0402_5% BATT_TEMPA
ECRST#
25,42 LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64 1
C445
2
100P_0402_50V8J
2 1 ADP_I/AD2/GPIO3A 65 ADP_I 47
CLK_PCI_EC 12 AD Input 66 ACIN_D 1 2

a.
29 CLK_PCI_EC PCICLK AD3/GPIO3B ADP_V 47
2 1 13 75 C446 100P_0402_50V8J
13,29,36,37,42 PLT_RST# PCIRST#/GPIO05 AD4/GPIO42
C444 0.1U_0402_16V4Z ECRST# 37 76
ECRST# SELIO2#/AD5/GPIO43
30 EC_SCI# 20 SCI#/GPIO0E
43 WL_BT_LED# 38 CLKRUN#/GPIO1D
DAC_BRIG/DA0/GPIO3C 68 VTTP_EN 49
For EMI request EN_DFAN1/DA1/GPIO3D 70 EN_DFAN1 6
DA Output IREF/DA2/GPIO3E 71 IREF 47

si
KSI[0..7] KSI0 55 72
35 KSI[0..7] KSI0/GPIO30 DA3/GPIO3F CHGVADJ 47
2 1 KB_RST# KSI1 56
@ C452 0.1U_0402_16V4Z KSO[0..17] KSI2 KSI1/GPIO31
35 KSO[0..17] 57 KSI2/GPIO32
KSI3 58 83
KSI3/GPIO33 PSCLK1/GPIO4A EC_MUTE# 38
KSI4 59 84 +5VS
KSI4/GPIO34 PSDAT1/GPIO4B USB_EN# 34,39
2 1 PLT_RST# KSI5 60 85
@ C453 0.1U_0402_16V4Z KSI6 KSI5/GPIO35 PSCLK2/GPIO4C TP_CLK
61 KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D 86 1 2
KSI7 62 87 TP_CLK 4.7K_0402_5% R379

ne
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK 35
KSO0 39 88 TP_DATA TP_DATA 1 2
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA 35
2 1 PLT_RST# KSO1 40 4.7K_0402_5% R381
@ C260 33P_0402_50V8K KSO2 KSO1/GPIO21
41 KSO2/GPIO22
C KSO3 42 97 VGATE C
KSO3/GPIO23 SDICS#/GPXOA00 VGATE 27,53 +3VALW
KSO4 43 98
KSO4/GPIO24 SDICLK/GPXOA01 WOL_EN# 37
KSO5
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
LID_SW# 1
PWRME_CTRL# 25
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 2 LID_SW#_R 43

do
KSO7 46 SPI Device Interface R103 1K_0402_1% LID_SW#_R 2 1
+3VL KSO8 KSO7/GPIO27 47K_0402_5% R383
47 KSO8/GPIO28
KSO9 48 119
KSO9/GPIO29 SPIDI/RD# EC_SI_SPI_SO 42
1 2 KSO1 KSO10 49 120
KSO10/GPIO2A SPIDO/WR# EC_SO_SPI_SI 42
R380 47K_0402_5% KSO11 50 SPI Flash ROM 126
KSO11/GPIO2B SPICLK/GPIO58 SPI_CLK 42
1 2 KSO2 KSO12 51 128 SYSON 1 2
KSO12/GPIO2C SPICS# SPI_CS# 42
R382 47K_0402_5% KSO13 52 4.7K_0402_5% R5
KSO14 KSO13/GPIO2D
53

in
KSO15 KSO14/GPIO2E VR_ON
to avoid EC entry ENE test mode 54 KSO15/GPIO2F CIR_RX/GPIO40 73 1 2
KSO16 81 74 10K_0402_5% R37
KSO17 KSO16/GPIO48 CIR_RLC_TX/GPIO41
82 KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 89 FSTCHG 47
BATT_CHGI_LED#/GPIO52 90 BATT_FULL_LED# 43
RP7 91 +3VL
CAPS_LED#/GPIO53 CAPS_LED# 35
+3VL 1 8 EC_SMB_CK1 EC_SMB_CK1 77 GPIO 92
46 EC_SMB_CK1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 BATT_CHG_LOW_LED# 43
2 7 EC_SMB_DA1 EC_SMB_DA1 78 93 1 2
46 EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 PWR_ON_LED# 43
EC_SMB_CK2 EC_SMB_CK2 SM Bus R341 330K_0402_5%

i-
+3VS 3 6 21,26 EC_SMB_CK2 79 SCL2/GPIO46 SYSON/GPIO56 95 SYSON 51
4 5 EC_SMB_DA2 EC_SMB_DA2 80 121 VR_ON D21
21,26 EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 53
127 ACIN_D ACIN_D 2 1
AC_IN/GPIO59 ACIN 27,43,45
2.2K_0804_8P4R_5%
CH751H-40PT_SOD323-2
27 PM_SLP_S3# 6 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 100 EC_RSMRST# 27
27 PM_SLP_S5# 14 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 101 EC_LID_OUT# 26
30 EC_SMI# 15 EC_SMI#/GPIO08 EC_ON/GPXO05 102 EC_ON 43
30 THM_ALT# 16
17
LID_SW#/GPIO0A
is EC_SWI#/GPXO06 103
104 PM_PWROK 27
+3VALW

B SUSP#/GPIO0B ICH_PWROK/GPXO06 B
18 PBTN_OUT#/GPIO0C GPO BKOFF#/GPXO08 105 BKOFF# 22

1
27 PCH_SUSPWRDN 19 EC_PME#/GPIO0D GPIO WL_OFF#/GPXO09 106 WL_OFF# 36
25 107 @
22 INVT_PWM EC_THERM#/GPIO11 GPXO10
28 108 EC_SEL R125
6 FAN_SPEED1 FAN_SPEED1/FANFB1/GPIO14 GPXO11
29 100K_0402_5% EC SEL EC Version
FANFB2/GPIO15
30
kn

36 E51_TXD

2
EC_TX/GPIO16 EC_SEL
36 E51_RXD 31 EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110 PM_SLP_S4# 27
R337 100K_0402_5% 32 112 High KB926D3
43 ON/OFFBTN# ON_OFF/GPIO18 ENBKL/GPXID2 VGA_ENBKL 14

1
1 2 VTTP_EN 34 114
43 PWR_SUSP_LED# PWR_LED#/GPIO19 GPXID3 USB_OC#1 29,34
35 NUM_LED# 36 NUMLED#/GPIO1A GPI GPXID4 115
116 R124 Low KB926E0
GPXID5 SUSP# 44,47,50,52,54
R342 100K_0402_5% 117 100K_0402_5%
GPXID6 PBTN_OUT# 27
1 2 E51_TXD 118 USB_OC#0 29,39

2
GPXID7
te

CRY1 122
CRY2 XCLK1 +EC_V18R
123 XCLK0 V18R 124
AGND

R389
GND
GND
GND
GND
GND

CRY1 1 2CRY2 C448

4.7U_0805_10V4Z
@ 10M_0402_5% KB926QFE0_LQFP128_14X14
11
24
35
94
113

69
w.

1 1
1

C449 C450
18P_0402_50V8J

Y4
18P_0402_50V8J
OSC

OSC

2 2
ww

A A
NC

NC
2

Security Classification Compal Secret Data Compal Electronics, Inc.

32.768KHZ_12.5PF_Q13MC14610002 2009/10/01 2010/10/01 Title
Issued Date Deciphered Date
SCHEMATIC,MB A6042
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 41 of 58
5 4 3 2 1
 SPI Flash (256KB) LPC Debug Port
Please place the PAD under DDR DIMM.

+3VL
+3VS H1

1 20mils 6 5
C451 U22

m
8 VCC VSS 4
0.1U_0402_16V4Z 7 4
2 25,41 SERIRQ PLT_RST# 13,29,36,37,41
3 W

co
7 HOLD 25,41 LPC_AD3 8 3 LPC_AD2 25,41

41 SPI_CS# 1 S
25,41 LPC_AD1 9 2 LPC_AD0 25,41
41 SPI_CLK 6 C

41 EC_SO_SPI_SI 5 D Q 2 EC_SI_SPI_SO 41 25,41 LPC_FRAME# 10 1 CLK_PCI_DDR 29

a.
MX25L2005CMI-12G SO8

2
@ DEBUG_PAD R393
1

22_0402_5%
R394
10_0402_5%

1
2

si
2

1 reserve for EMI, close to U22 C457

22P_0402_50V8J
C454 1
10P_0402_50V8J
2
reserve for EMI

ne
do
in
i-
is
kn
te
w.
ww

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 42 of 58
 5 4 3 2 1

Power Button Circuit Debug Button ISPD

+3VL
PCB ZZZ

2
R395
TOP side
100K_0402_5%

m
JPOWER

1
ON/OFFBTN# @ SW2
D
1 1 ON/OFFBTN# 41
ON/OFFBTN#
D
2 2 1 3

2
PCB 0CK LA-6042P
3 3

co
D58
4 4 2 4
G1 5 AZ5125-02S.R7G_SOT23-3 51_ON# 45
NTC017-DA1J-D160T
G2 6

6
5
UV1 UV1
@ ACES_85201-0405N 1 GPU

6
Q6A
2N7002KDW_SOT363-6

a.
41 EC_ON 2 another at page 44 debug phase using
PARK LP PARK LP R3

2
PARKLP@ PARKLPR3@

1
R396
10K_0402_5% UV1 UV1

si
PARK XT PARK XT R3
PARKXT@ PARKXTR3@

UV1

DC-IN LED Control Circuit

ne
C ACIN_LED# C
MADISON LP R3
6

MADISONLPR3@
LED/B Conn.

do
Q35A UV1 UV1
2 2N7002KDW_SOT363-6
27,41,45 ACIN
1

JLEDB
1 1
2 M92 XTX M92 XTX R3
2 M92XTX@ M92XTXR3@
41 LID_SW#_R 3

in
ACIN_LED# 3
4
HDD LED Control Circuit 41 PWR_ON_LED# 5
4
5
41 PWR_SUSP_LED# 6 6
HDD_LED# 7 PJP1
7
+3VS 40 CR_LED# 8
9
8 DC-IN
41 BATT_FULL_LED# 9
HDD_LED# 10
41 BATT_CHG_LOW_LED# 10
2

i-
35 SW_L 11 11 GND 17
R404 12 18
35 SW_R 12 GND
3

10K_0402_5% 13 DC JACK
41 WL_BT_LED# 13
+3VALW 14 45@
Q9B 14
+5VS 15
1

2N7002KDW_SOT363-6 15
5 +5VALW 16 16
6

1 @ ACES_85201-1605N U11
4

Q9A
is C218
PCH
B 2N7002KDW_SOT363-6 0.1U_0402_16V4Z B
25 SATA_LED# 2
2
1

HM55 R3
For EMI request, Close to Conn. HM55R3@
kn

U11 U11

Screw Hole PCB Fedical Mark PAD

H2 H3 H4 H5 HM57 R1 HM57 R3
te

CPU FD1 FD2 FD3 FD4 HM57R1@ HM57R3@

H_4P7 H_4P2 H_4P2X4P7 H_4P2X4P7 @ @ @ @

1

@ @ @ @
1

UL1
Others LAN
H10 H11 H12 H13 H14 H16 H17 H18
w.

VGA
H_2P9 H_3P2 H_2P9X3P4 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 RTL8111E-VB-GR QFN 48P LAN CONTROLLER
1

@ @ @ @ @ @ @ @ 8111E@

H19 H20 H21 H22 H23 H24

H30 H31
ww

A A
MDC
H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_6P8
1

H_3P3 H_3P3 @ @ @ @ @ @
1

@ @

H25 H26 H27

Security Classification Compal Secret Data Compal Electronics, Inc.
H36 H37 2009/10/01 2010/10/01 Title
H_3P3X2P7N H_2P7N H_3P3X2P7N
Issued Date Deciphered Date
MINI CARD SCHEMATIC,MB A6042
1

@ @ @
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H_3P3 H_3P3 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1

@ @ B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 43 of 58
5 4 3 2 1
 A B C D E

+3VALW TO +3VS +5VALW TO +5VS +1.5V to +1.5VS

+3VALW +3VS Vgs=-0V,Id=9A,Rds=18.5mohm +5VALW +5VS
4.7U_0805_10V4Z +1.5V +1.5VS
4.7U_0805_10V4Z
1 1 1 1 Vgs=10V,Id=14.5A,Rds=6mohm
Q29 C459 C460 4.7U_0805_10V4Z Q30 C461 C462 1 1

470_0805_5%

470_0805_5%
8 1 8 1 Q31 C463 C464
D S D S

470_0805_5%
7 D S 2 7 D S 2 8 D S 1

2
2 2 2 2

m
6 3 R406 6 3 R407 7 2
D S D S D S 2 2 R408
1 5 D G 4 5 D G 4 6 D S 3 1
1U_0402_6.3V4Z 1U_0402_6.3V4Z 5 4
SI4800BDY_SO8 D G
1 R409 2 +VSB SI4800BDY_SO8 1 R410 2 +VSB 1U_0402_6.3V4Z

3 1

3 1

co
0.022U_0402_25V7K

0.01U_0402_25V7K
47K_0402_5% 47K_0402_5% FDS6676AS_SO8 1 R411
4.7U_0805_10V4Z

4.7U_0805_10V4Z
1 1 1 1 2 +VSB

3 1
1

6
C466 Q10A Q11A 220K_0402_5%

4.7U_0805_10V4Z
1 1

6
0.1U_0402_25V6
C465 R412 2N7002KDW_SOT363-6 C467 C468 R413 2N7002KDW_SOT363-6 FDS6676AS Q12A

C470
330K_0402_5% 200K_0402_5% C469 R414 2N7002KDW_SOT363-6
2 2 SUSP 2 2 @ SUSP 5 820K_0402_5%
2 5 2
2 2 SUSP
2 5

2
Q10B Q11B

2
2N7002KDW_SOT363-6 2N7002KDW_SOT363-6 Q12B

a.

4
2N7002KDW_SOT363-6

si
For S3 Reduce
+3VALW

ne
2
2 R425 2
100K_0402_5%
PS@
0.75VR_EN# 52

1
do

3
Q44B
2N7002KDW_SOT363-6 PS@
PS@
5,49 VTTPWROK 1 2 0.75VR_EN 5
R158 100K_0402_5%

in

4
PS@

6
Q44A
2N7002KDW_SOT363-6

SUSP 2

1
i-
is
3 3

For S3 Reduce +0.75VS +5VALW

2

2
kn

R421 R421 R422

47_0805_5% 470_0805_5% 100K_0402_5%
PS@ NPS@ No Use
1

1
SUSP
9,52 SUSP
3

6
Q6B
te

2N7002KDW_SOT363-6 Q5B Q5A

2N7002KDW_SOT363-6 2N7002KDW_SOT363-6
5 SUSP 5 2
41,47,50,52,54 SUSP#
another at page43

2
4

1
R423
10K_0402_5%
w.

1
ww

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 44 of 58
A B C D E
 A B C D

VS
VIN PR1
PL1 VIN 1M_0402_1%
PF1 SMB3025500YA_2P
DC301001M80 DC_IN_S1 1 2 DC_IN_S2 1 2
1 2

1
1
PJP1 N1 PR3

1000P_0402_50V7K

1000P_0402_50V7K

680P_0402_50V7K
1 10A_125V_451010MRL PR2 5.6K_0402_5% PR4

m
+

680P_0402_50V7K

100P_0402_50V8J

100P_0402_50V8J
84.5K_0402_1% 10K_0402_1%

1
1 1

PC5
2 1 2 ACIN 27,41,43

2
+

1
PC1

PC2

PC3

PC4

PC6
PR5

8
3 22K_0402_1% PU1A

co
2

2
-
@ 1 2 3

P
2
@ + PACIN
- 4 O 1 PACIN 47
2 -

G
@ SINGA_2DW-0005-B03

1
PR6 LM393DG_SO8

4
PC7 20K_0402_1% PC8 PD1 PR7
0.068U_0402_10V6K .1U_0402_16V7K GLZ4.3B_LL34-2 10K_0402_1%

2
2

a.
2

2
2 1 +CHGRTC
PR8
VIN 10K_0402_1%
3.3V Vin Detector

si
PD2
High 18.384 17.901 17.430
RLS4148_LL34-2 Low 17.728 17.257 16.976

1
BATT+ 2 1

1
PD3 PR9 PR10
RLS4148_LL34-2 PQ1 68_1206_5% 68_1206_5%

ne
TP0610K-T1-E3_SOT23-3
PR11

2
200_0603_5%
2
CHGRTCP 1 2 N1 3 1 VS 1 2 2

PR12
1

1K_1206_5%
1

1
PC10 PD4

do
PR13 PC9 0.1U_0603_25V7K 2 1 N3 1 2
100K_0402_1% 0.22U_0603_25V7K VIN B+
2

2
RLS4148_LL34-2 PR14
2

1K_1206_5%
43 51_ON# 1 2
PR15 1 2
22K_0402_1%
RTC Battery PR16

in
1K_1206_5%

1
1

PR19 PR20
PR17
200_0603_5%
- PBJ1 + PR21
560_0603_5%
PR22
560_0603_5%
VL
100K_0402_1%
1 2
2.2M_0402_5%
2 1
PR18
499K_0402_1%
PU2 G920AT24U_SOT89-3 2 1 1 2 1 2
3.3V +RTCBATT

2
i-
2

3 2 N2
+CHGRTC OUT IN PD5

8
@ MAXEL_ML1220T10 RB715F_SOT323-3 PU1B
1

GND
2 5

P
48 EN0 +
PC11 PC12 1 7
10U_0805_10V4Z 1 O
47 ACON 3 6 2 1 +CHGRTC
2

1
G
1U_0805_25V4Z
SP093MX0000 LM393DG_SO8 PR23 PR24

1
is 10K_0402_1% 499K_0402_1% PC14

1
PR26 1000P_0402_50V7K
PC13 @ PR25
@PR25 191K_0402_1%

2
3 3

1000P_0402_50V7K 66.5K_0402_1%

2
1

2
PJ1 PJ2 PJ3 PC15
+3VALWP 2 1 +3VALW 2 1 +1.8VSP 2 1 +1.8VS 1000P_0402_50V7K

2
2 1 2 1 2 1
kn

@ JUMP_43X118 @ JUMP_43X118 @ JUMP_43X79

(5A,200mils ,Via NO.= 10 (2A,80mils ,Via NO.= 4) PR27

1
PJ4 D 47K_0402_1%
OCP= 7.7A) 2 1 PQ2 2 2 1 PACIN
+1.5VP 2 1 +1.5V
PJ5 SSM3K7002FU_SC70-3 G
+5VALWP 2 1 +5VALW @ JUMP_43X118 S

3
2 1
@ JUMP_43X118 (14A,600mils ,Via NO.= 30

1
te

(5A,200mils ,Via NO.= 10) OCP=22.4A)

OCP=7.9A)
PJ7 PJ9

+VSBP 2 2 1 1 +VSB +3VLP 2 2 1 1 +3VL 2 +5VALWP

@ JUMP_43X39 @ JUMP_43X39
(100mA,40mils ,Via NO.= 2) PQ3
(120mA,40mils ,Via NO.= 1) Precharge detector DTC115EUA_SC70-3
w.

3
PJ12
15.97V/14.84V FOR
2
PJ11
1
2 2 1 1 ADAPTOR
2 1 @ JUMP_43X118
@ JUMP_43X118 PJ14
+1.0VSP 2 2 1 1 +1.0VS
PJ13 PJ15
ww

+VTTP 2 1 +VTT @ JUMP_43X79 +VGA_COREP 2 1 +VGA_CORE

2 1 2 1
4
(2A,80mils ,Via NO.= 4) 4

@ JUMP_43X118 @ JUMP_43X118
(18A,720mils ,Via NO.=36
OCP=28.55A) (22A,1040mils ,Via NO.=52
PJ17 OCP=24.18A)
PJ16 +0.75VSP 2 1 +0.75VS
2 1
+1.05VSP 2 2 1 1 +1.05VS
@ JUMP_43X79
Security Classification Compal Secret Data Compal Electronics, Inc.
@ JUMP_43X79 (1.5A,60mils ,Via NO.= 4) Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title
(7.0A,280mils ,Via NO.=14)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401849
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 18, 2010 Sheet 45 of 58
A B C D
 A B C D

m
1 1
VMB
PF2 PL2
PH1 under CPU botten side :
PJP2 15A_65V_451015MRL SMB3025500YA_2P
CPU thermal protection at 90 degree C

co
1 BATT_S1 1 2 1 2
1 BATT+
2 2
3 BATT_P3 1 2 1 2
Recovery at 56 degree C
3 +3VLP
4 BATT_P4 PR28 PR29
4

1
BATT_P5 1K_0402_1% 47K_0402_1%
5 5 PH2 near main Battery CONN :

1
10 6 EC_SMDA PC16 PC17
GND 6 EC_SMCA @PC18
@ PC18 1000P_0402_50V7K 0.01U_0402_25V7K
11 7 BAT. thermal protection at 90 degree C

2
GND 7

1
12 8 0.1U_0402_25V6K

2
GND 8

a.
PR30
13 GND 9 9
1K_0402_1%
Recovery at 56 degree C
@ SUYIN_200045MR009G171ZR

2
VL

PD7
1

si
PJSOT24C_SOT23-3

1
PD6 2

1
PJSOT24C_SOT23-3 1 PR31
3 PC19 23.7K_0402_1%
PR32 0.1U_0603_25V7K

2
6.49K_0402_1% PR33
2

2
2 1 23.7K_0402_1%
+3VLP

2
ne
PR34

1
1

11.3K_0402_1%
PR35 PU4
2
1K_0402_1% 1 8 2

1
VCC TMSNS1

1
2 7
2

GND RHYST1
2

PR36 PR37 PH1

do
BATT_TEMPA 41 3 OT1 TMSNS2 6
100_0402_1% 100_0402_1% 100K_0402_1%_NCP15WF104F03RC

1
4 5

2
OT2 RHYST2 PR40
1

48 VS_ON G718TM1U_SOT23-8 11.3K_0402_1%

EC_SMB_DA1 41

2
EC_SMB_CK1 41

in

1
PH2
100K_0402_1%_NCP15WF104F03RC

2
i-
PQ4
TP0610K-T1-E3_SOT23-3

B+ 3
is 1 +VSBP
3 3
100K_0402_1%

0.22U_0603_25V7K

0.1U_0603_25V7K
1

1
PR41

PC20

PC21

@ @
2

2
kn
2

VL PR42
22K_0402_1%
1 2
2

PR43
100K_0402_1%
te

PR44
1

0_0402_5% D
1 2 2 PQ5
48 POK
G SSM3K7002FU_SC70-3
.1U_0402_16V7K

S
3
1

@ PC22

w.
2

ww

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401849 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 18, 2010 Sheet 46 of 58
A B C D
 A B C D

@ PC154
@PC154
10U_1206_25V6M
B+
Arrandale -- non mount,PQ9 PQ6
1 2 Clarksfield --mount PQ9 1
AO4407A_SO8
8
@ PC153
@PC153 2 7

PQ7 P2 PQ8 P3 PR45

B+ 10U_1206_25V6M
1 2 CHG_B+
3 6
5
AO4407A_SO8 AO4407A_SO8 0.02_2512_1% PJ18
VIN 8 1 1 8 1 4 2 1

4
2 1
7 2 2 7

PC23 1000P_0402_25V8J

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
6 3 3 6 2 3 @ JUMP_43X118 CSIN
5 5 @PQ9
@ PQ9 AO4407A_SO8
1 8

m
CSIP 2 7

4
1
1 1

3 6

1
PQ11 TP0610K-T1-E3_SOT23-3 5

5600P_0402_25V7K
PQ10 PR46 PR47 10_0603_5%

co
2
0.1U_0603_25V7K
DTA144EUA_SC70-3 200K_0402_1% 3 1 1 2 DCIN

4
P3

PC28
2
1

PC24

PC25

PC26
2 PR49

1
PC27
PR50 PQ12 47K_0402_1%

1
PR48 100K_0402_1% DTC115EUA_SC70-3 @ 1 2

2
47K_0402_1% VIN

2
PR51 PD8
2

2
100K_0402_1% 2 FSTCHG PR52 PD9
1

2
1

a.
PD10 2 1 2 1 10K_0402_1% 1 2 ACOFF
1SS355_SOD323-2 3
1 2 6251VDD SUSP# 41,44,50,52,54 1SS355_SOD323-2

1
2.2U_0603_6.3V6K
RB715F_SOT323-3 PR54

PC29
2 PR53 200K_0402_1%

3
1

1
PQ13 10K_0402_1% 1 2 VIN
DTC115EUA_SC70-3 2 1 PU5 PC31
41 FSTCHG 0.1U_0603_25V7K

2
100K_0402_1%

si
1 2 1 24 DCIN 2 1 PQ15 PD11
3

VDD DCIN
1

1
DTC115EUA_SC70-3 2 1 2

PR56
PC30
PR55 .1U_0402_16V7K 2 23 1SS355_SOD323-2
ACSET ACPRN
1

D 150K_0402_1% PR57
2 PQ14 20_0603_5%
2

1
G SSM3K7002FU_SC70-3 6251_EN CSON D
3 EN CSON 22 1 2

1
S PC32 PC33 2 PACIN
3

5
6
7
8
0.047U_0603_16V7K 0.1U_0603_25V7K

ne
G

AO4466_SO8
SSM3K7002FU_SC70-3

4 21 1 2 CSOP S PQ16

3
CELLS CSOP PR58 SSM3K7002FU_SC70-3
PC35 6800P_0402_25V7K 20_0603_5%

PQ17
2 2
1 2 5 ICOMP CSIN 20 2 1
1

2
D PR59 4
PQ18

2 PC36 PR60 6.81K_0402_1% PC37 20_0603_5%

G 1 2 1 2 6 19 0.1U_0603_25V7K
1 2

1
VCOMP CSIP PL3 PR63

do
S
3

0.01U_0402_25V7K 1 2 PR62 47K_0402_1% PR61 10U_LF919AS-100M-P3_4.5A_20% 0.02_1206_1% BATT+

3
2
1
PR64 1 2 7 18 LX_CHG 2.2_0603_1% 1 2 CHG 1 4
ICM PHASE

4.7_1206_5%
22K_0402_5% @PC38
@ PC38 100P_0402_50V8J

5
6
7
8

PR65
PACIN 1 2 1 2 2 3
45 PACIN

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M
PC39 6251VREF 8 17 DH_CHG
PR66 .1U_0402_16V7K VREF UGATE PR67 PC40
45 ACON 41 ADP_I

AO4466_SO8
154K_0402_1% 2.2_0603_1% 0.1U_0603_25V7K

1
PC125

PC41

PC42

PC155
2 1 9 16 BST_CHG 1 2 BST_CHGA 2 1

in
41 IREF CHLIM BOOT
1

1
PR68 4

680P_0603_50V8J
0.01U_0402_25V7K

24K_0402_1% PD12

2
PQ19

PC43
6251VREF 1 2 6251aclim 10 15 6251VDDP RB751V-40TE17_SOD323-2 @
ACLIM VDDP
1

2
1

1
PC44

ACOFF 2 PQ20 PR69 1 26251VDD

41 ACOFF

3
2
1
DTC115EUA_SC70-3 120K_0402_1% PR70 11 14 DL_CHG
VADJ LGATE

2
20K_0402_1% PR71
2

4.7_0603_5%

i-
2

12 13 PC45
3

1
GND PGND 4.7U_0805_6.3V6K

ISL6251AHAZ-T_QSOP24

PR72
15.4K_0402_1%
1 2
41 CHGVADJ
is 1

3
PR73 3

31.6K_0402_1%
VIN
2

CP mode
kn

1
Iada=0~4.737A(90W) CP= 92%*Iada; CP=4.36A
PR74
Vaclim=0.736V(90W) PR70=53.6k PR49=0.015 309K_0402_1%

PR75

2
10K_0402_1%
1 2
ADP_V 41
te

CC=0.25A~3A CHGVADJ=(Vcell-4)/0.10627

1
IREF=1.016*Icharge Vcell CHGVADJ

1
PR76
47K_0402_1% PC46
IREF=0.254V~3.048V 4V 0V .1U_0402_16V7K

2
VCHLIM need over 95mV 4.2V 1.882V 2
w.

4.35V 3.2935V
ww

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401849 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 18, 2010 Sheet 47 of 58
A B C D
 5 4 3 2 1

2VREF_51125

m
1U_0603_10V6K
D D

co
PC47

2
PR77 PR78

a.
13K_0402_1% 30K_0402_1%
1 2 1 2

PR79 PR80
B++
20K_0402_1% 19.1K_0402_1%
1 2 1 2 B++

si
@ PJ19

ENTRIP2

ENTRIP1
B+ 2 2 1 1 +3VLP
PR81 PR82
JUMP_43X118 150K_0402_1% 150K_0402_1%
10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M
1 2 1 2
1

1
PC48

PC49
ne
1
PC156

4.7U_0805_10V6K
2

1
PU6

5
6
7
8
PC50

ENTRIP2

REF
FB2

FB1

ENTRIP1
TONSEL
2

8
7
6
5

1
C C
25 PQ22
PQ21 P PAD AO4466_SO8

2
AO4466_SO8

do
7 VO2 VO1 24 POK 46 4
4
8 23 PC52
PR83 VREG3 PGOOD PR84 .1U_0402_16V7K
1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2

3
2
1
2.2_0603_1% BOOT2 BOOT1 2.2_0603_1%
1
2
3

PL4 PC51 UG_3V 10 21 UG_5V PL5

4.7U_LF919AS-4R7M-P3_5.2A_20% .1U_0402_16V7K UGATE2 UGATE1 4.7UH_SIL104R-4R7PF_5.7A_30% +5VALWP

in
1 2 LX_3V 11 20 LX_5V 1 2
+3VALWP PHASE2 PHASE1
1

8
7
6
5

5
6
7
8

1
4.7_1206_5%

4.7_1206_5%
LG_3V 12 19 LG_5V
LGATE2 LGATE1
PR85

PR86
SKIPSEL
PQ23 PQ24

VREG5
220U_6.3V_M

220U_6.3V_M
1 @ AO4712_SO8 AO4712_SO8 @

GND
1
45 EN0

VIN
RT8205EGQW_WQFN24_4X4

NC
EN
2

2
+ +
PC53

PC54
Ipeak=5A

i-
4 4
PR87

13

14

15

16

17

18
1

1
Imax=3.5A
680P_0603_50V8J

680P_0603_50V8J
499K_0402_1%
2 2
PC55

PC56
B+ 1 2
F=305KHz
2

1
2
3

3
2
1

2
1
100K_0402_5%
@ @

1
1U_0402_6.3V6K

PR88
Total Capacitor 220u 1 2 VL
is PC57

1
ESR 15m ohm

PC58
4.7U_0805_10V6K
@ PR89

2
B 0_0402_5% B

2
ENTRIP1 ENTRIP2 B++ Ipeak=5A

1
Imax=3.5A
kn

0.1U_0603_25V7K
F=245KHz

2
PC59
1

D D
2VREF_51125
PQ25
SSM3K7002FU_SC70-3 G
2 2
G
PQ26
SSM3K7002FU_SC70-3
Total Capacitor 220u
S S ESR 15m ohm
3

te

VL 2 1
1

PR90
w.

100K_0402_1%

46 VS_ON
VS 1 2 2 PQ27
DTC115EUA_SC70-3
42.2K_0402_1%

0.01U_0402_16V7K

PR91
1

100K_0402_1%
1
PR92

PC60

ww 3

A A

@
2
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401849 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 18, 2010 Sheet 48 of 58
5 4 3 2 1
 A B C D

m
1 PL6 1

B+ HCB4532KF-800T90_1812

1 +VTTP_B+

co
2

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
5 VTTPWROK_CPU VTTPWROK +5VS
5,44

3.4K_0402_1%
1 2
1

1
PR182
0_0402_5%
PC61

PC62

PC63

PR93
PR94 2.2_0603_1%
2

2
1 2 1 2

a.
PR95 PR181

BST_+VTTP
2.43K_0402_1% 4.53K_0402_1% PC64

DH_+VTTP
LX_+VTTP
1 2 1 2 0.1U_0603_25V7K
+5VALW

DH_+VTTP

5
PR96
0_0402_5% PR97 PQ28

16

15

si
8

1
PU7 4.7_0603_5%
1 2 TPCA8030-H_SOP-ADV8-5

PHASE

BOOT
UG
GND

PGOOD
+VTTP_VCC

2
4
3 VIN PVCC 14 1 2 PC65
+VTTP_VCC 2.2U_0603_6.3V6K

ne 3
2
1
4 13 DL_+VTTP PL7
VCC LG 1.0UH_PCMC104T-1R0MN_20A_20%
1

PC66 1 2
2

2.2U_0603_6.3V6K
+VTTP 2

APW7138NITRL_SSOP16
12
2

PGND

4.7_1206_5%

390U_2.5V_M
TPCA8028-H_SOP-ADVANCE8-5
1

1
do
PQ29
+

PR99

PC67
1 2 5 11 SE_+VTTP 1 2
41 VTTP_EN EN ISEN PR98
PR100 2
10.5K_0402_1%

FSET
0_0402_5%

2
NC

VO
FB
4

680P_0603_50V8J
.1U_0402_16V7K

1
6

10
1

PC69
in
3
2
1

2
PC68

+VTTP
FB_+VTTP
2

Material Note:
33.2K_0402_1%

0.01U_0402_16V7K
1

1
390uF/ 10m ohm, number are 3,
1
PR101

57.6K_0402_1%

i-
PR102

power x1, HW x2
@ PC70
2
1

@
2200P_0603_50V7K
2

H_VTTVID1= Low, 1.1V @ PC71

Clarksfield 1.1V 33P_0402_50V8J
H_VTTVID1= High, 1.05V
2

Arrandale 1.05V Ipeak=20A

Imax=14A
PC72

is
2

3 @ F=231KHz 3

1 2 1 2+VTTP
PR103 PR104
+3VS 3.32K_0402_1% 0_0402_5% Total Capacitor 1170u
2

+3VS
180K_0402_1%

@ PR105 ESR 3.33m ohm

kn
@ PR107

40.2K_0402_1% PR106 1 2
VTT_SENSE 8
2

4.42K_0402_1% PR108 PJ20

100K_0402_5%

10_0402_5% +VTTP +1.05VS

2 1 Arrandale -- mount,
1

2 1
@ PR109

Clarksfield --non mount @

2N7002W-T/R7_SOT323-3

@ PR111 1 2 @ JUMP_43X79
VSS_SENSE_VTT 8
2

4.7K_0402_5% D PR110 (7.0A,280mils ,Via NO.=14)

1

@ PQ30

1 2 2 10_0402_5%
G
te

S
3
1
1

1
.1U_0402_16V7K

1 2 2
8 H_VTTSELECT
@ PC73
0.01U_0402_16V7K

@ PR112
3

2
PMBT2222A_SOT23-3
@ PQ31

10K_0402_5%
100K_0402_5%

w.
1
@ PC74
@ PR113

2
1

ww

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401849 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 18, 2010 Sheet 49 of 58
A B C D
 A B C D

PJ21
Arrandale -- non mount, @
1.05V_B+ 2 2 1 1 B+ Clarksfield --mount

4.7U_0805_25V6-K

4.7U_0805_25V6-K
@ JUMP_43X118

m
1

1
1 1

PC75

PC76
5
6
7
8

co
2

2
AO4466_SO8
@ @

PQ32
@PR114
@ PR114
255K_0402_1% 4 @
1 2
@ PR115
@PR115
0_0402_5% @PR116
@ PR116

a.
SUSP# 1 2 BST_1.05V1 2

3
2
1
2.2_0603_1% @PC78
@ PC78

1
0.1U_0603_25V7K @PL8
@ PL8

15

14
1
@PC77
@PC77 @PU8
@ PU8 1.8UH_SIL104R-1R8PF_9.5A_30%
.1U_0402_16V7K 1 2 1 2

BOOT
NC
EN/DEM
+1.05VSP

4.7_1206_5%
2 13 DH_1.05V
TON UGATE

1
si PR117
@PR118
@ PR118 3 12 LX_1.05V
VOUT PHASE

5
6
7
8

220U_6.3V_M
100_0603_1% 1

PC79
FDS6670AS_NL_SO8
+5VALW
1 2 4 11 1 2 Ipeak=7A

D
D
D
D
+5VALW VDD CS

PQ33
@PR119
@ PR119 @ +

2
5 FB VDDP 10 10K_0402_1% Imax=4.9A
@
F=315KHz

1
2

PC81
680P_0603_50V8J
6 9 DL_1.05V 4 @
PGOOD LGATE G

PGND
@PC80
@ PC80

ne
GND
4.7U_0603_6.3V6K

2
1

S
S
S
RT8209BGQW_WQFN14_3P5X3P5 @PC82
@PC82
@ Total Capacitor 220u

3
2
1
2 4.7U_0805_10V6K ESR 15m ohm 2

2
@PR120
@ PR120
4.02K_0402_1%

do
1 2
1

@ PR121
@PR121
10K_0402_1%
2

in
i-
PR122
15K_0402_1%
1 2
SUSP# 41,44,47,52,54
2

1
PR123
316K_0402_1%
is PC83
0.22U_0402_10V4Z

2
3 3

PR124
402K_0402_1% PU9
1

+1.8VSP 2 1 1 FB EN/SYNC 10

PC84 2 9 PL9
GND GND
kn

0.1U_0402_16V7K 2.2UH_FMJ-0630T-2R2 HF_8A_20%

1 2 3 SW SW 8 1 2 +1.8VSP
PJ25
+5VALW 2 2 1 1 4 IN IN 7

22U_0805_6.3V6M

22U_0805_6.3V6M
0.1U_0402_25V6

10U_0805_10V4Z

10U_0805_10V4Z

@ JUMP_43X79 1 2 5 6
BS POK
1

B340A_SMA2
PR125 PR126
1

1
PC85

PC86

PC87

PD13

PC88

PC89
0_0402_5% 11 4.7_1206_5%
TP
te

1 2
MP2121DQ-LF-Z_QFN10_3X3 @
2

2
2

PC90
680P_0603_50V7K

2
w.
ww

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401849 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 18, 2010 Sheet 50 of 58
A B C D
 5 4 3 2 1

PJ22
1.5V_B+ 2 1 B+
2 1

4.7U_0805_25V6-K

4.7U_0805_25V6-K
@ JUMP_43X118

m
1

1
PC91

PC92
D D

TPCA8030-H_SOP-ADV8-5
5

co
PQ34
PR127
255K_0402_1% 4
1 2
PR128
0_0402_5%

a.
1 2 BST_1.5V 1 2
41 SYSON

3
2
1
PR129

1
2.2_0603_1% PC94 PL10

15

14
1
@PC93
@ PC93 PU10 0.1U_0603_25V7K 1.0UH_PCMC104T-1R0MN_20A_20%
.1U_0402_16V7K 1 2 1 2

EN/DEM

BOOT
NC
+1.5VP

si 4.7_1206_5%
DH_1.5V

TPCA8028-H_SOP-ADVANCE8-5
2 TON UGATE 13

PR130

220U_6.3V_M
PR131 3 12 LX_1.5V 1
VOUT PHASE

5
100_0603_1%

PQ35
+

PC95
+5VALW 1 2 4 11 1 2 +5VALW
VDD CS PR132
Ipeak=14A

2
5 10 12.1K_0402_1%
FB VDDP 2
Imax=9.8A

ne
1

680P_0603_50V8J
6 9 DL_1.5V 4
PGOOD LGATE F=313KHz

PGND

PC97
PC96

GND
4.7U_0603_6.3V6K
2

2
1
C C
RT8209BGQW_WQFN14_3P5X3P5 PC98 Total Capacitor 610u

3
2
1
4.7U_0805_10V6K

2
ESR 6m ohm

do
PR133
10K_0402_1%
1 2

in
10K_0402_1%
1
PR134

i-
2

is
B B
kn
te
w.
ww

A A

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2009/10/01 Deciphered Date 2010/10/01
SCHEMATIC,MB A6042
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401849 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 18, 2010 Sheet 51 of 58
5 4 3 2 1
 A B C D

+1.5V

1
PJ23

1
@ JUMP_43X79

m
1 1

2 2
PU11

co
1 VIN VCNTL 6 +5VALW

4.7U_0805_6.3V6K
2 GND NC 5

1
3 VREF NC 7

1
1K_0402_1%
PC100

PR135
@ PR136 4 8 PC99

2
VOUT NC

a.
0_0402_5% 1U_0603_10V6K

2
1 2 9
9,44 SUSP

2
TP
G2992F1U_SO8

0.1U_0402_10V7K
PR137
+0.75VSP

1
D

1K_0402_1%
0_0402_5%

si
PQ36

PR138

PC102
SSM3K7002FU_SC70-3
1 2 2
44 0.75VR_EN# G

1
S

3
1
PC103

2
@ PC101 10U_0805_6.3V6M

2
.1U_0402_16V7K

ne
2 2

do
+1.5V

in
+5VALW
1

PJ24
1

@ JUMP_43X79
2

i-
2

1 PC104
1U_0603_6.3V6M
2
1

PC105
4.7U_0805_6.3V6K PU12
6
is
2

VCNTL
3 5 VIN VOUT 3 +1.0VSP 3

PR139 9 4
VIN VOUT

22U_0805_6.3V6M
0.01U_0402_25V7K
10K_0402_5%

1
1 2 8 PR140
41,44,47,50,54 SUSP# EN

PC106

PC107
7 2 1.82K_0402_1%
GND

POK FB

2
1

kn
2
PC108 APL5930KAI-TRG_SO8
1

.1U_0402_16V7K
2

PR141
7.32K_0402_1%
PR185 PX5@ PR141
4.7K_0402_1% 4.75K_0402_1%
te

+3VS 1 2 M9X@

PR141
7.32K_0402_1%
21 PCIE_OK
M1@
w.
ww

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 52 of 58
A B C D
 8 7 6 5 4 3 2 1

CPU_VID0 2 1 PR142 1K_0402_1% CPU_VID0 2 1 @ PR143 1K_0402_1% +CPU_B+

PL11
CPU_VID1 2 1 PR144 1K_0402_1% CPU_VID1 2 1 @ PR145 1K_0402_1% HCB4532KF-800T90_1812
1 2 B+
CPU_VID2 2 1 PR146 1K_0402_1% CPU_VID2 2 1 @ PR147 1K_0402_1%

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M
2200P_0402_50V7K
CPU_VID3 CPU_VID3

470P_0603_50V8J
PR150 0_0402_5% 1@ PR148 1K_0402_1% PR149 1K_0402_1%

0.1U_0603_25V7K
2 2 1

100U_25V_M

100U_25V_M

68U_25V_M_R0.36

68U_25V_M_R0.36
H 8 CPU_VID0 1 2 1 1 1 1 H
PR153 0_0402_5% CPU_VID4 2 1@ PR151 1K_0402_1% CPU_VID4 2 1 PR152 1K_0402_1%

1
+ + + +

PC109

PC112

PC116

PC113

PC111

PC114

PC158

PC157

@ PC115
8 CPU_VID1 1 2

PC110
PR156 0_0402_5% CPU_VID5 2 1 PR154 1K_0402_1% CPU_VID5 2 1 @ PR155 1K_0402_1%
8 CPU_VID2 1 2

2
5
PR159 0_0402_5% CPU_VID6 CPU_VID6 2 2 2 2
2 1@ PR157 1K_0402_1% 2 1 PR158 1K_0402_1% @
1 2 PQ37
8 CPU_VID3
PR162 0_0402_5% H_DPRSLPVR 2 1 PR160 1K_0402_1% H_DPRSLPVR 2 1 @ PR161 1K_0402_1%
TPCA8030-H_SOP-ADV8-5

m
8 CPU_VID4 1 2
PR164 0_0402_5% H_PSI# 2 1 PR163 1K_0402_1%
8 CPU_VID5 1 2 4
PR165 0_0402_5%
1 2 +VTT
Arrandale -- non mount,@
8 CPU_VID6
Clarksfield --mount

co
PC117

3
2
1
PR166 2.2_0603_1% 0.22U_0603_25V7K
PR167 0_0402_5% BOOT2 1 2 BOOT2_2 1 2
1 2 PL12
41 VR_ON
UGATE2 0.36UH_PCMC104T-R36MN1R17_30A_20%
G PR168 0_0402_5% G
1 2 PHASE2 4 1 +CPU_CORE
8 H_DPRSLPVR
3 2 V2N
22 CLK_ENABLE#

a.
10K_0402_5%
PR169
4.7_1206_5%
@ PQ38

TPCA8028-H_SOP-ADVANCE8-5

1
PQ39

3.65K_0805_1%
+3VS PR172 TPCA8028-H_SOP-ADVANCE8-5 PR171

PR170

PR173
1.91K_0402_1% 1_0402_5%
1 2 CLK_ENABLE# @ PR175
LGATE2 4 4 0_0402_5%

2
2

1 2 V1N
PR174
1.91K_0402_1% @ PR176
PR177 VSUM+ 0_0402_5%

3
2
1

3
2
1

si
1
V3N

680P_0603_50V8J
0_0402_5% 1 2
27,41 VGATE
1

PC118
1 2 VSUM-

2
@ PR178 1K_0402_1%
F
1 2 ISEN2 F
+VTT
PR179 0_0402_5%
8 H_PSI# 1 2
PR180

ne
1 2 ISL62883HRZ-T_QFN40_5X5~D +CPU_B+
147K_0402_1%
+5VALW +5VALW

10U_1206_25V6M

10U_1206_25V6M
PC119

0.1U_0603_25V7K
1U_0603_10V6K
40
39
38
37
36
35
34
33
32
31

1
@ PC121

@ PC122
PU13 1 2 Arrandale -- 2 phase 1H1L

1
@ PC120
1U_0603_10V6K
@ PQ40
CLK_EN#
DPRSLPVR

VID6
VID5
VID4
VID3
VID2
VID1
VID0
VR_ON

2
@ PR184 @ PC124 Clarksfield --2 phase 1H2L

2
1

@ PC123
30 PR183 0_0603_5% 0.22U_0603_25V7K TPCA8030-H_SOP-ADV8-5

2
BOOT2 PU14
UGATE2 29 0_0402_5%
1 28 5 1 BOOST_CPU3 1 2 1 2 4

do
2
PGOOD PHASE2 VCC BOOT
2 27

1
PSI# VSSP2 UGATE_CPU3
3 RBIAS LGATE2 26 6 FCCM UGATE 8
4 25 @ PL13
VR_TT# VCCP PHASE_CPU3 0.36UH_PCMC104T-R36MN1R17_30A_20%
5 24 2 7

3
2
1
E NTC PWM3 PWM PHASE E
6 VW LGATE1 23
7 22 3 4 LGATE_CPU3 4 1 +CPU_CORE
COMP VSSP1 GND LGATE
8 FB PHASE1 21
9 @ ISL6208CRZ-T_QFN8 3 2 V3N
ISEN3
UGATE1

PR190
4.7_1206_5%
1 2 10 PR186 0_0402_5%
BOOT1
ISUM+

ISEN2

1
ISEN1

ISUM-
VSEN
249K_0402_1%

1000P_0402_50V7K

IMON
8.06K_0402_1%

1U_0603_10V6K

in
1 2

TPCA8028-H_SOP-ADVANCE8-5
VDD
RTN

1
VIN

3.65K_0805_1%
PC126 41 @ PR187
AGND
1

1
PQ42
PC127

PC128

22P_0402_50V8J @ PQ41 @ @ PR192 1_0402_5%

PR189

PR188

TPCA8028-H_SOP-ADVANCE8-5 10K_0402_5%
11
12
13
14
15
16
17
18
19
20

PR194
2

2
@ PR191
562_0402_1% PC130 4 4 @ @ PR193

2
@ 1 2 1 2 0_0402_5%
2

2
1
2V1N

680P_0603_50V8J
1

PC129
390P_0402_50V7K
PR196 PR195 0_0402_5% @ PR197 VSUM-

3
2
1

3
2
1

2
i-
2.55K_0402_1% 1 2 0_0402_5%
1 2 1 2 @ 1 2 V2N
8 IMVP_IMON
PC131 PR198 0_0402_5%
D 10P_0402_50V8J 1 2 +CPU_B+ D
0.22U_0603_25V7K

1 2 1 2 @ PR200 0_0402_5% VSUM+

1 2 PR201 1_0402_5% ISEN3
ISEN3
PC132 PR199 1 2 +5VALW +CPU_B+
150P_0402_50V8J 412K_0402_1% ISEN2 1 2
1

1
PC133

PC134

PC135
1U_0603_10V6K

0.22U_0603_25V7K

PR202 0_0402_5%
is
PC137 0.22U_0402_6.3V6K

PC138 0.22U_0402_6.3V6K

ISEN1 1 2 PR204
2

470P_0603_50V8J
8.66K_0402_1%
BOOT1

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M
Layout Note: PR203 0_0402_5%
PC136 0.22U_0402_6.3V6K

2
1

PQ43
PH3 place near
1

1
PC139
VSSSENSE
Arrandale -- non mount,@

PC140

PC141

PC142
Phase1 L-MOS TPCA8030-H_SOP-ADV8-5
2

Clarksfield --mount
2

2
VSUM+ UGATE1 4
@
kn

+CPU_CORE 1 2
PC143
1

@ PR205 10_0402_5% PR207 2.2_0603_1% 0.22U_0603_25V7K

0.047U_0402_16V7K

C C

3
2
1
1
VSUM-

2.61K_0402_1%

2 BOOT1_1
0.22U_0603_10V7K

1 1 2
PR208

PL14
@ PR206 0.36UH_PCMC104T-R36MN1R17_30A_20%
1

1
PC144

PC145

1 2 82.5_0402_1%
8 VCCSENSE
2

PHASE1 4 1 +CPU_CORE
2

PR209 0_0402_5%
2

2
1

3 2 V1N
te

TPCA8028-H_SOP-ADVANCE8-5
1

5
PC146

TPCA8028-H_SOP-ADVANCE8-5
PQ44

@ PQ45

4.7_1206_5%
330P_0402_50V7K
2

1
10K_0402_5%
PR210

3.65K_0805_1%
PC147
2

1
0.01U_0402_25V7K PR213
1_0402_5%

PR212
330P_0402_50V7K

LGATE1 4 4
1

2
11K_0402_1%

PR211
@ PR216

2
1

PC149

PR215

PC148 PH4 0_0402_5%

2
1000P_0402_50V7K 1 2 1 2 V2N
PR217 0_0402_5% 10K_0402_1%_ERTJ0EG103FA
w.
2

3
2
1

3
2
1

680P_0603_50V8J
1 2 PR214 @ PR218 VSUM-
8 VSSSENSE
2

B B

PC150
1.2K_0402_1% 0_0402_5%
1 2 V3N

2
@ PR219 10_0402_5%
1 2 1 2 1 2 VSUM- VSUM+
@ PC152 @ PR249 ISEN1
Layout Note:
1200P_0402_50V7K 100_0402_1%
Place near Phase1 Choke
ww
.1U_0402_16V7K
1

PC151
2

A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 53 of 58
8 7 6 5 4 3 2 1
 5 4 3 2 1

B+ 1 2 B+_core
PL17 LX_VCORE
HCB4532KF-800T90_1812

10U_1206_25VAK

4.7U_0805_25V6-K
10U_1206_25VAK
DH_VCORE

1
PC170
PR250 0_0603_5%

PC168

PC169
1 2 1 2
BST_VCORE

2
PC171
0.1U_0603_25V7K

m
D D
+5VALW

co
TPCA8030-H_SOP-ADV8-5
5
PR251

PQ48
0_0603_5%

27138_VCC

16

15
1

2
8

1
PU16
PR252 4

PHASE

BOOT
UG
GND

PGOOD
4.7_0603_5%

a.
3 VIN PVCC 14 1 2 PC172

3
2
1
2.2U_0603_6.3V6K
PL18

2.2U_0603_6.3V6K
PC173
7138_VCC 4 13 DL_VCORE +VGA_COREP
VCC LG 0.56U_PCMC104T-R56MN_25A_20%

si
1 2
APW7138NITRL_SSOP16

1
TPCA8028-H_SOP-ADVANCE8-5

TPCA8028-H_SOP-ADVANCE8-5
12

2
PGND

390U_2.5V_M
@PR254
@ PR254
4.7_1206_5%

10U_1206_25VAK

10U_1206_25VAK
PR253 1

PQ50

PC174

1
1 2 5 11 ISEN_VCORE 1 2 +

1 2
EN ISEN

2
41,44,47,50,52 SUSP#

PQ49

PC176

PC177
4 4 @

ne

0_0402_5%
680P_0603_50V8J
0_0402_5% PR255

FSET

2
1

@ PC175

PR256
.1U_0402_16V7K

9.76K_0402_1%

NC

VO
FB
PC178

2
C C
2

10

3
2
1

3
2
1

1
do
PR257
10_0402_5% +VGA_CORE

57.6K_0402_1%
1 2
1

1
1

1
@ PR258

PR259
@ PC179 49.9K_0402_1% @PC180
@ PC180

1000P_0402_50V7K
22P_0402_50V8J 0.01U_0402_25V7K

in
2

2
2
1

1
4.22K_0402_1%

@ PC182
1

1000P_0402_50V7K
@ PC181

PR260
2200P_0402_25V7K
2

2
1

2
PC185
PR261
VFB(0.6)=Vout*Rbottom/(Rtop+Rbottom) 5.9K_0402_1% PR262 PR262 PR262
12K_0402_1% 28K_0402_1% 28K_0402_1%

i-
2

@
2
M9X@ PX5@ M1@
voltage

1
SEL1 SEL0

SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3
Madison

4.22K_0402_1%
M96 & M92 PR265 PR266
& Park

1
D 10K_0402_1% D 10K_0402_1%

PQ51

PQ52
2 1 2 2 1 2
L L 1.2 1.2
is PR263

S
G VGA_PWRSEL1 14
S
G VGA_PWRSEL0 14

3
B B
1

1
.1U_0402_16V7K

.1U_0402_16V7K
L H 1.12 1.0

PC183

PC184
Ipeak=22A

2
H L 0.95 0.95 Imax=15.4A
kn

F=231KHz
H H 0.9 0.9
Total Capacitor 1050u
FSW=1/(75E-12*57.6K)=231.48KHz
ESR 2.3m ohm
te

Madison,M96 Park,M92

Imax=18.23A Imax=12.81A
Ipeak=26.05A Ipeak=18.30A
Iocp=24.18A Iocp=24.18A
w.

PR262=7.15K PR262=5.36K
PQ45=unpop PQ45=unpop
ww

A A

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2009/10/01 Deciphered Date 2010/10/01
SCHEMATIC,MB A6042
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401849 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 18, 2010 Sheet 54 of 58
5 4 3 2 1
NO DATE PAGE MODIFICATION LIST PURPOSE
--------------------------------------------------------------------------------------------------------------------------------
2009/10/20 45-56 Release
2009/11/17 50 Change PL9 to SH00000FD10 BOM modify
2009/11/17 54 Change PC177 to unmount circuit modify
2009/11/17 53 Change PH4 to SL200001000 circuit modify
2009/11/17 47,51 Change PC24,PC25,PC26,PC91,PC92 to SE000006R80 circuit modify

m
2009/12/15 48 Change PR92 to 42.2K ohm circuit modify
2009/12/15 49 Change PR95 to 2.43K ohm,PR101,PC71,PC72 to unmount circuit modify

co
PR98 to 6.49K ohm
2009/12/15 51 Change PR132 to 6.19K ohm circuit modify
2009/12/15 52 Add PR185 HW request
2009/12/15 54 Change PR258,PC179,PC181 to unmount circuit modify

a.
2009/12/25 48 Change PL4,PL5 to SH000006380(4 mm high) Thermal request
2009/12/28 53 Change PC111,PC114 to 68U DFB request
2010/01/05 46 Change PR31,PR33 to 19.6K ohm,PR34 to 8.66K ohm OTP modify
PR40 to 7.87K ohm

si
2010/01/05 53 Change PR196 to 2.55K ohm,PR204 to 8.66K ohm circuit modify
2010/02/03 47 Change PC24,PC25,PC26 to 10U_1206,PR67 to 2.2 ohm EMI request
PC153,PC154 to mount,

Add PC125,PC155

ne
2010/02/03 48 Change PR83,PR84 to 2.2 ohm,PQ27 to DTC115EUA_SC70-3 EMI request
Add PC156
Change PL4,PL5 to SH16247AM10(4.7uH_H4.5) circuit modify
2010/02/03 53 Add PC157,PC158 circuit modify

do
2010/02/26 46 Change PR31,PR33 to 23.7K ohm,PR34,PR40 to 11.3K ohm Thermal request
PD6,PD7 to mount EMI request
2010/02/26 47 Change PR45 to 20m ohm,PR68 to 24K ohm cp point modify to 75W
2010/02/26 48 Change PL5 to SH000006380(4 mm high) Thermal request

in
2010/02/26 53 Change PC111,PC114 to 100U circuit modify for noise issue
2010/03/16 47 Change PC24,PC25,PC26 to 4.7U_0805, For PCB noise issue
PC153,PC154 to unmount,

2010/03/18 53 Change PC157,PC158 to mount,PC113,PC141 to unmount circuit modify for camera noise issue

i-
2010/04/02 49 Change PR98 to 10.5K ohm circuit modify(cut in AON6718L)
2010/04/02 50 Change PR122 to 15K ohm,PC83 to 0.22uF HW request
2010/04/02 51 Change PR132 to 12.1K ohm circuit modify(cut in AON6718L)
2010/04/02 53
is
Change PC113,PC141 to mount EMI request (for ISN)
2010/04/02 54 Change PR255 to 9.76K ohm circuit modify(cut in AON6718L)
kn
te
w.
ww

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401849 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 18, 2010 Sheet 55 of 58
 5 4 3 2 1

PIR (Product Improve Record)

NALAA LA-6042P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.1 TO 0.2
NO DATE PAGE MODIFICATION LIST NO DATE PAGE MODIFICATION LIST
------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------
1 2009/12/14 41 Delete R402, PCH_SUSPWRDN connect to EC directly 32 2009/12/22 43 Change H36, H37 footprint from H_3P8 to H_3P3

m
D 2 2009/12/14 43 Change JLEDB pin define as customer request 33 2009/12/22 25,41 Change Net name from PWRME_CTRL to PWRME_CTRL# D

3 2009/12/14 30 Delete R222 and net PCH_GPIO45, PCH GPIO45 connector to GND for LVDS_SEL 34 2009/12/23 16 Change CV114, CV116 from polymer cap to OSCON cap (SF000002000, H=5.9)

co
(Dual-Channel)
35 2009/12/23 36 Change control circuit of BT/WLAN combo Mini Card
4 2009/12/14 34,35,39 Delete JODDB, JBT and JUSBB support pin
a. Delete R22 and Net BT_PWR#_R at JWLAN pin5
5 2009/12/14 43 Change JPOWER Pin2 from GND to NC
a. Add Q25 and Net BT_CTRL at JWLAN pin5
6 2009/12/14 37 Add schematic for co-lay Giga LAN
36 2009/12/23 38 Change RA26 from resistor 33_0603 to L58 bead 300 ohm FBMA-L10-160808-301LMT

a.
a. Add CL10 at +3VLAN (SM010017710)
b. Add CL23, CL24, CL25 at +LAN_VDD10 37 2009/12/24 24 Add R228 and HDMI_HPD_R at U9 pin1 to prevent ESD issue
c. Add RL11 PD resistor at Pin15 38 2009/12/25 21 Add PJ6 between +3VS and +3VS_DELAY
d. Add BOM structure 8105E@ at UL1 39 2009/12/25 45~55 Update PWR portion

si
e. Change Transformer design for Giga LAN 40 2009/12/28 16 Change CV114, CV116 P/N from SF000002000 (330U,6.3V,15m ohm) to
SF000002O00 (390U,2.5V,10m ohm)
7 2009/12/14 22 Change U5 (CLK Gen) P/N from SA00003HQ00 to SA00003HQ10
41 2009/12/28 8,9,11,16,20 Change C159, C216, C217, CV78, CV290 footprint from C_PXC6P3VC220MF60 to
8 2009/12/14 39 Change DA4, DA5 footprint from PJDLC05_SOT23-3 to PACDN042Y3R_SOT23-3 C_MP2VU390MC5R7
9 2009/12/15 36 Add R22 and Net BT_PWR#_R at JWLAN Pin5 for BT/WLAN combo Mini Card 42 2009/12/28 35 Change R44 BOM structure from BT@ to @

ne
10 2009/12/15 25 Change U13 (PCH ROM) footprint from WIESO_G6179-100000_8P to M25P80-VMW6TP_SO843 2009/12/28 30 Update Note for GPIO39,45,57 and project ID
, and delete BOM structure
C 44 2009/12/28 34 Change JODDB footprint from P-TWO_161021-12021_12P-T to ACES_88058-120N_12P-TC
11 2009/12/15 34,39 Change U14, U15 P/N from SA00002XX00 to SA000033H00
45 2009/12/28 14 Add test pad T11 at UV1.AM14
12 2009/12/15 43 Change H36, H37 footprint from H_3P3 to H_3P8

do
46 2009/12/28 45~55 Update PWR portion
13 2009/12/15 35 Reverse JBT pin definition
47 2009/12/30 6 Change C4 from SE068102J80 to SE074102K80, keep @
14 2009/12/16 31 Add C473 (SF000002000) on +1.05VS plane for PWR request
48 2009/12/30 35 Delete R361 BOM structure for BT/WLAN combo card
15 2009/12/16 45~55 Update PWR portion
49 2009/12/30 37,43 Change LAN IC P/N
16 2009/12/16 5 Delete JXDP support pin

in
a. RTL8105E change from SA00003PO00 to SA00003PO10
17 2009/12/16 43 Add M92 XTX (SA00002YX00) for BOM control
b. RTL8111E change from SA00003PT00 to SA00003PT10
18 2009/12/16 13~18 Modify circuit for co-lay M9X
50 2009/12/31 43 Change M92 XTX P/N from SA00002YX00 to SA00002YX30
a. Add BOM structure at RV133, RV33, LV33, CV308, CV309, CV310, LV34, CV311,
CV312, CV313, LV35, CV314, CV315, CV316, LV36, CV317, CV318, CV319, LV30, 51 2010/01/04 29 Change R281 from 22_0402 to 33_0402 per EMI request

i-
CV302, CV303, CV304, LV31, CV305, CV306, CV307, LV28, RV41, RV42, RV45, RV46, 52 2010/01/04 41 Remove BOM structure from R377 and C443, Change C443 from 22P_0402 to
RV56, RV54, RV132, CV206, RV59, CV320, CV321, RV57, RV58, RV48, RV49, RV50, 10P_0402 per EMI request
RV53, RV55
53 2010/01/04 39 Change LA2, LA3, LA4, LA5 from 0_0603 to FBMA-L11-160808-800LMT_0603
b. Add LV37 at +SPV10 and connect to +VGA_CORE (SM010015410) per EMI request
19 2009/12/16 14,18 Add BOM structure for GPU work around
is
B B
a. Add BOM structure at RV19, RV16, RV39, XV1, LV32, CV117, UV20, RV56
b. Delete BOM structure from RV23
20 2009/12/16 20 Change 2PCS@ to 4PCS@
kn

21 2009/12/16 40 Change CC2 from 0.1u to 100P (SE071101J80), and add BOM structure @
22 2009/12/16 8 Change C144 from SF000002O00 (390U, H5.9) to SF000002Z00 (330U, H4.5)
23 2009/12/17 43 Change JPOWER footprint to ACES_85201-0405N_4P (ZIF_上接點)
24 2009/12/17 35 Change JTPB footprint to P-TWO_161011-04021_4P-T (NO ZIF), and reverse pin
te

definition
25 2009/12/17 43 Change JLEDB footprint to ACES_85201-1605N_16P (ZIF_上接點)
26 2009/12/17 39 Change JUSBB footprint to ACES_85201-20051_20P (ZIF_上接點)
27 2009/12/17 13~22 Delete work around circuit of GPU
w.

a. Delete RV40, CV117, UV20, RV39, XV1, LV32, RV16, RV19

b. Delete Net ROMSCK_GPIO10, GPIO24_TRST#, GPIO26_TCK, GPIO27_TMS
c. Change +3VS of VGA to +3VS_DELAY
d. Add +3VS_DELAY circuit
ww

A A
28 2009/12/17 14 Change RV26 from 60.4ohm to 47.5ohm (SD00000G900)
29 2009/12/17 43 Delete H15
30 2009/12/21 45~55 Update PWR portion
31 2009/12/22 22 Swap pin of JLVDS to prevent burn issue Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title
a. +LCD_INV : Change pin from Pin35 to Pin40
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
b. BKOFF#_R : Change pin from Pin40 to Pin33 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 56 of 58
5 4 3 2 1
 5 4 3 2 1

PIR (Product Improve Record)

NALAA LA-6042P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.2 TO 0.3
NO DATE PAGE MODIFICATION LIST NO DATE PAGE MODIFICATION LIST
------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------
1 2010/01/28 8 Remove BOM structure from C122 and delete C148

m
D 2 2010/01/28 37 Co-lay UL3 16-Pin Transformer for 10/100 (SP050005V00) D

3 2010/01/28 38 Change UA1(CODEC) P/N from SA00003QR00 to SA00003QR10

co
4 2010/01/28 41 Add R37 10K pull-down resister at VR_ON to avoid leakage for CPU_CORE
5 2010/01/28 27 Change U12 P/N from SA007080B90 to SA007080100
6 2010/01/28 21 Change PJ6 from Jump to R_0603 resister R46 (SD013000080)
7 2010/01/28 18 Change RV57, RV58, CV320, CV321 BOM structure from MANHA@ to @

a.
8 2010/01/28 34 Change D18 P/N from SCA00000A00 to SC600001600 per ESD request
9 2010/01/28 22,35,39,43 Change D19, D57, D58, DA4, DA5 P/N from SCA00000G00 to SCA00001A00 per ESD
request
10 2010/01/28 39 Change LA2, LA3, LA4, LA5 footprint from R_0603 to KC_FBMA-L11-160808-800LMT_2P

si
11 2010/01/28 32 Add BOM structure @ at C2, C7, U54
12 2010/01/28 41 Change U19(EC) from SA00001J80 to SA00001J5A0 and Change EC strap pin from
R125 to R124
13 2010/02/01 39 Swap L and R pin definition

ne
14 2010/02/01 25 Reserve D20 and R126 on RTC charge circuit
15 2010/02/02 43 Change M92-XTX P/N from SA00002YX30(R1) to SA00002YX50(R3)
C C
16 2010/02/03 5 Add C414 at PECI for prevent noise issue
17 2010/02/03 34,39 Change U14, U15 from SA000033H00 to SA00002XX00

do
18 2010/02/03 8 Remove BOM structure from C117, C118, C119, C127, C128, C129, C150 and add C158
19 2010/02/03 45~55 Update Power portion
20 2010/02/04 34,39 Change U14, U15 footprint from RT9711CPB_SOT23-5 to RT9715BGS_SO8
21 2010/02/08 37 Change LL1 from SHI00004T00 to SHI0000AA00 for common design

in
22 2010/02/08 37 Change CL13 from SE000000I10 to SE093475K80 for common design
23 2010/02/08 23 Change C238, C239, C240, C241, C242, C243 from SE07122AC80 to SE07147AC80
per EMI request

i-
is
B B
kn
te
w.
ww

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 57 of 58
5 4 3 2 1
 5 4 3 2 1

PIR (Product Improve Record)

NALAA LA-6042P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.3 TO 1.0
NO DATE PAGE MODIFICATION LIST NO DATE PAGE MODIFICATION LIST
------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------
1 2010/02/09 25 Delete D20 and R126 on RTC charge circuit

m
D 2 2010/02/26 38,41 Add Net EC_MUTE# between U19.Pin83 and UA1.Pin4 D

3 2010/02/26 38,41 Add RA13 and RA29 at EC_MUTE#

co
4 2010/02/26 37 Change CL13 from SE093475K80 (0805) to SE107475K80 (0603)
5 2010/02/27 35,43 Change SW2, SW4 P/N from SN100000F00 to SN100002Y00 for cost down
6 2010/02/27 43 Add BOM structure @ at SW2 (Debug Button) due to PreMP
7 2010/03/01 38 Change EC_MUTE# pull-up from +5VALW to +5VS

a.
8 2010/03/01 5 Add BOM structure @ at C414
9 2010/03/05 14 Add test point T12 at UV1.AK23, T13 at UV1.AL24 for AMD request
10 2010/03/09 38 Delete RA13 and un-mount CA16 for S3 resume and cold boot noise issue

si
11 2010/03/12 8 Change C144 PN from SF000002Z00 to SF000002M00 for 2nd source list common
12 2010/03/12 6 Change U1 PN from SA00002XA00 to SA000035G00 for 2nd source list common
13 2010/03/15 41,43 Add R103, C218 at LID_SW#_R for prevent ESD damage
14 2010/03/16 38 Change CA12,RA12,CA18 connect from GND to AGND

ne
15 2010/03/17 40 Delete RC2,RC3,CC7,CC8 and add RC22,RC24,CC9,CC10 for EMI SD card issue
16 2010/03/22 22 Change C213 from SE070104Z80 to SE000000K80 for prevent noise coupling
C C
17 2010/03/22 45~55 Update Power schematics
18 2010/03/30 34 Add BOM structure @ at D18 (EMI test PASS can remove it)

do
in
i-
is
B B
kn
te
w.
ww

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/01 Deciphered Date 2010/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401849
Date: Tuesday, May 18, 2010 Sheet 58 of 58
5 4 3 2 1