Date: 19/09/2020

EXPERIMENT NO. 4

AIM: To design and simulate NAND gate using pseudo NMOS logic using SymicaDE tool.
TOOLS USED: SymicaDE
THEORY: This technique uses single pMOS transistor with grounded gate. The logical inputs
are applied to nMOS logic circuit. The static power dissipation is significant. Since the voltage
swing on the output and overall functionality depends on ratio of the nMOS and pMOS
transistor sizes, this circuit is called ratioed circuit. To get VOL as small as possible, the pMOS
device should be sized much smaller than the nMOS device but it causes a negative impact on
the propagation delay for changing the load since the current provided by the pMOS device is
limited. A major disadvantage of pseudo nMOS is the static power that is dissipated when the
output is low through the direct current path that exists between VDD and GND.

figure 4.1: pseudo-NMOS NAND Circuit

A B A NAND B

0 0 1

0 1 1

1 0 1

1 1 0

Table 4.1: NAND truth table

CIRCUIT DIAGRAM:

figure 4.2: pseudo NMOS NAND circuit has been successfully designed using SymicaDE tool.

Parameters Values
CMOS PTM 130nm
Technology
NMOS: W/L 400nm/180nm
PMOS: W/L 400nm/180nm
VDD 1.8V
Input signal V1=1.8V, V2=0, Time Period=100ns,
(Pulse) Pulse Width=50ns
A
Input signal V1=1.8V, V2=0, Time Period=200ns,
(Pulse) Pulse Width=100ns
B

Table 4.2: Specifications of pseudo-NMOS NAND

OBSERVATIONS:
Simulated Delay Time w.r.t A: 5.63849e-009
Simulated Delay Time w.r.t B: 5.41627e-009
 figure 4.3: Output of pseudo-NMOS NAND gate
COMPARISION TABLE:

S.NO PROPERTY NAND Gate using CMOS NAND Gate using

logic Pseudo NMOS logic
1. Delay ~3ns ~5ns
2. Swing 0V-1.8V 0.45V-1.8V
3. Number of transistors 4 3
Table 4.3: Comparison between pseudo-NMOS NAND and CMOS NAND

RESULT:
• Pseudo NMOS NAND circuits has been successfully designed using SymicaDE tool.
• Delay time is also calculated for it.