Carrier Based Single-state PWM Technique In multilevel Inverter
Nguyen Van Nho1, Quach Thanh Hai2
HochiminhCity University Of Technology
Department of Electrical Engineering
268 LyThuongKiet, District 10, Hochiminh City
Email: nvnho@hcmut.edu.vn
Abstract— In the paper, a novel analysis of carrier based PWM
methods for multilevel inverters is presented. The space vector
PWM and carrier based PWM correlations are investigated in a
nominal two-level switching diagram. The obtained results will
be applied to design various carrier PWM techniques. In this
paper, a carrier based single-state PWM technique, which
reduces number of switchings and optimizes active voltage
errors will be presented. This technique can be advantageous in
high level inverters. The carrier base PWM approach shows a
flexible offset control. The proposed method is mathematically
formulated and demonstrated by simulation and experimental
results.
I. INTRODUCTION
Nowadays, for increasing use in practice and fast developing
of high power devices and related control techniques,
multilevel inverters have become more attractive to
researchers and industrial companies. Two common inverter
topologies are NPC and cascaded multilevel inverters (Fig.1
and 2). In recent days, for reducing hardware construction
cost, it has been shown a try to develop prospective hybrid
multilevel inverters. There are basically three PWM schemes
for controlling multilevel inverters as: Carrier based PWM,
space vector PWM and selective harmonics elimination
PWM methods.
Fig. 1: a) 4-leg 5-level NPC inverter; b) c) and d) Analysis of inverter
voltages
Hong Hee Lee3
University Of Ulsan
Department of Electrical Engineering
680-749 San 29, Muger 2-dong, Ulsan, Korea
Email: hhlee@mail.ulsan.ac.kr
Figure 2: 3-phase Cascaded multilevel inverter
The comprehensive correlation between carrier based PWM
and SVPWM have been derived in the recent work [1],[2].
Compared to the space vector PWM methods, the carrier
based PWM methods can be advantageously utilised in: 1)
controlling common mode voltage, 2) controlling of
complicated inverter topologies as 4-leg, 5-leg-,... multilevel
inverters, 3) compensation of unbalanced dc sources. It will
be shown that the carrier PWM technique can become a
possible solution for some approximate PWM methods,
which use one or two switching states in a switching state
sequence and produce reference voltages with certain
voltage error. The drawbacks as nonlinear control
characteristics and existence of low-order harmonics of
output voltages will be compensated by reduced number of
switchings in each sampling time period. A common
characteristic of carrier based approximate PWM methods is
that the offset function can be properly designed to control
the PWM performance. Single state space vector PWM
method has been described in some recent paper [3], one of
its drawback is the limitation of output voltage range. The
methods of selecting the voltage vector in Direct torque
control and hysteresis current loop control for AC motor
drive systems are some typical and well-known applications
of single state PWM technique. In the paper, the carrier
based single state PWM will be proposed for minimum
voltage error. The only controllable parameter of this method
is the offset voltage, which does not influence on the active where n( x ) = Int (v xref ); x = a, b, c . (7)
voltage but able to set approximately common mode voltage G T
and balance switching losses. In the paper, it will be shown Each components of vector L = [ La , Lb , Lc ] presents
that any PWM scheme of multilevel inverter can be centered possibly a lower level of phase leg voltage in a switching
in a nominal two-level switching state diagram. This makes state sequence.
the PWM study to become more advantageous and Nominal switching time diagram: To investigate
comfortable. The proposed method is explained for NPC commutation process in a triangle period, a vertical shift of
inverters, its proper modifying can be also applied to cascade G T
topologies. coordinates by the vector L = [ La , Lb , Lc ] can be
implemented as shown in Fig.4. Three-phase active PD
II. CIRCUIT DESCRIPTION AND NOMINAL carrier bands are overlapped. The diagram is redrawn in a
SWITCHING DIAGRAM IN MULTILEVEL INVERTER FOR nominal two-level switching time diagram as shown in Fig.5.
BALANCE DC VOLTAGE SOURCES In this nominal diagram, the commutation instants occur
Assumption: each dc voltage cell is constant and equal to a depending on the relative voltage level termed nominal
unit. Define reference leg voltages between output and modulating signals ξ x , x = a, b, c defined as:
dc-neutral point “0”, consisting of active voltages
ξ x = v xref − L( x ) ; 0 ≤ ξ x ≤ 1 ; (8).
v x12 , x = a, b, c and reference common mode
Or
v0 ref (Fig.4) as: G G G
ξ = v ref − L
v xref = v x12 + v0ref . (1) Nominal switching states sequence: The nominal two-level
Or in the vector form as: switching diagram in Fig.5 shown that switching time
G G G digram in multilevel inverters can be explained using that of
v ref = v12 + v 0ref I two-level inverter. Therefore, in nominal switching diagram,
Active voltages, which exist at the three phase load voltages let’s define nominal switching states as :
can be determined from the amplitude and phase angle of
voltage vector as follows:
v a12 = v ref cosθ
vb12 = v ref cos(θ − 2π 3) ; (2)

vc12 = v ref cos(θ − 4π 3)

Define Max and Min as maximum and minimum values
from three phase active voltages as:

Max = Max(v a12 , vb12 , v c12 ) (3)

Min = Min(v a12 , vb12 , vc12 )
Figure 3: a) reference vector in vector triangle, b) Switching time diagrams
in multicarrier PWM.
Reference common mode voltage can be proposed of any
G
value, varying within the limits of v0 Max and v0 Min : s1 = [0,0,0]T
v0 Max = (n − 1) − Max G
s 2 = [ s 2 a , s 2b , s 2 c ]T
(4) . (9)
v0 Min = − Min G
s 3 = [ s3a , s 3b , s3c ]T
G
[
where v ref = v aref , vbref , vcref ]
T
and G
s 4 = [1,1,1]T
G G G
v12 = [v a12 , vb12 , vc12 ]T . (5) The first and last states as s1 ; s 4 remind two active zero
Active Low/or High level: each reference leg voltage v xref is redundant states in switching state sequence of two-level
G G
inverter. For the remaining two states as s 2 ; s3 , the vector
produced by subsequent alternating between the two lower
and higher active levels as L( x ) and H ( x ) , for which the components can be determined from relative positions of
nominal modulating signals ξ x .
following conditions will be satisfied as:
Define maximum, medium and minimum values of the
 n( x ) if 0 ≤ v xref < (n − 1) three phase nominal modulating signals as:
L( x ) = 
n( x ) − 1 if v xref = (n − 1) . (6)
H ( x ) = L( x ) + 1
ξ Max = Max(ξ a , ξ b , ξ c ) III. PROPOSED SINGLE STATE PWM METHOD
In single-state PWM technique, there is no commutation in a
ξ Mid = Mid (ξ a , ξ b , ξ c ) (10) G
sampling period. The reference vector v ref will be modified
ξ Min = Min(ξ a , ξ b , ξ c ) G G G G
G G and attain one from 4 relevant vectors S1 , S 2 , S 3 and S 4 ,
The components of vectors s 2 ; s3 can be derived as follows:
defined as (Fig.5b):
1 if ξ x ≥ ξ Max G' G
s2 x =  v ref = S j ; j ∈ {1,2,3,4} (16)
0 else
1 if ξ x ≥ ξ Mid
s3 x =  (11)
0 else
Switching state sequence in multilevel inverter
G G G G
S1 , S 2 , S 3 , S 4 : can be easily deduced from active low
G
voltage level L and nominal switching states as
G G G
Sj = L + sj (12)
Figure 5: a) Reference vector in single-state switching and function Kmax in
a triangle, and b) Principle of single-state PWM method.
Switching time duties: Reference voltage vector can be
described as: Define function K Max as the largest from three time duties
G G G G G
v ref = K 1 S1 + K 2 S 2 + K 3 S 3 + K 4 S 4 (13) of K 14 , K 2 and K 3 :
The switching time duties as K 1 , K 2 , K 3 , K 4 can be K Max = Max( K 14 , K 2 , K 3 ) (17)
determined easily from nominal switching diagram as:
The value of K Max in a triangle area is described in Fig.5a.
K 1 = 1 − ξ Max ; G
In sub-area, where the reference vector Vref is located and
K 2 = ξ Max − ξ Mid ; K3 = ξMid − ξMin ; K 4 = ξ Min
the condition K j = K Max , j ∈ {14,2,3} is satisfied , the
K 14 = 1 − ξ Max + ξ Min G
G'
K1 + K 2 + K 3 + K 4 = 1 (14) active error will be minimized if v ref = S j . Particularly,
G G
if K Max = K14 , both vectors S1 and S 4 have the same
Conventional PWM techniques attain zero active voltage G
error. For improving output quality, the offset can be active error e12 and minimizing the offset error e0 can be
regulated within the range of (v0Min,v0MAX). An extra G'
adjustment of the offset within the range defined in (15) can considered as condition for selecting the vector v ref . For
be implemented in various modified PWM methods. G
example, the vector S1 is select if
G G G G
− K 4 ≤ v0 add = e0 = ξ 0add ≤ K1 (15) Offset (S1 − v ref ) < Offset ( S 4 − v ref ) . (18)

K 2 + 2K 3 + 3K 4 (K + 2K 3 + 3K 4 )
Or <1− 2
3 3
Table 1: Algorithm for single-state PWM method

Conditions Selected vectors

G' G
K 14 > K 2 ; K 14 > K 3 v ref = S1
K 2 + 2K 3 + 3K 4 < 1.5
G' G
K 2 > K 3 ; K 2 > K 14 v ref = S2
G' G
K 3 > K 2 ; K 3 > K14 v ref = S3
G' G
Figure 4: a) Switching time diagram deduced in a) new defined coordinates K 14 > K 2 ; K 14 > K 3 v ref = S4
and b) Nominal switching time diagram.
K 2 + 2K 3 + 3K 4 > 1.5
Table 2: Relation between active errors and corresponding selected vectors

Active voltage error e12

G'
v ref
G
2 S1
K 22 + K 32 + K 2 K 3
3
G
2 2 S2
K14 + K 32 + K 14 K 3
3
G
2 2 S3
K14 + K 22 + K14 K 2
3
G
2 S4
K 22 + K 32 + K 2 K 3
3

The corresponding active errors are deduced in Table 2

and drawn in Fig.6.

If reference vector is located at the center of triangle, i.e.

K 14 = K 2 = K 3= 1 / 3 , active error can achieve a
maximum value of
e12 Max = 2 (3 3 ) . (19)

The influence of offset control is demonstrated by

corresponding reference modulating signals for 5-level
inverter in Fig.7. There have been calculated reference
modulating signals for cases of minimum common mode
(Fig.7a, c and e) and medium common mode (Fig.7b, d and
f). From the study, single state PWM with minimum
common mode offset presents advantageous compared to that
of medium common mode for reduced number of extra
commutations in a large modulation index range.
IV. OVERMODULATION IN SINGLE- STATE PWM
METHODS
Because of producing output voltage with nonzero error, the
single-state PWM method has a non-linear control
characteristic and generates low-order harmonic voltages
for the whole modulation range. Compared to conventional
PWM methods, overmodulation in single-state PWM method
losses its original meaning. However, overmodulation can be
supposed to be an approach to extend the reference
fundamental voltage V(1) mref to a maximum value in
VS
six-step mode, i.e., attaining a value of 2 .That is, the
π
overmodulation happens if the reference fundamental voltage
V(1) mref exceeds the value of Vs / 3 .
Figure 6: 5-level inverter. Active errors a c1,c2,c3 and “error”
in single-state PWM for using corresponding vectors
G G G G
V1 , V2 , V3 and V proposed .
The active voltages in single-state carrier overmodulation can
be deduced from the principle control between two-limit
trajectories [1], for which the active modulating signals
corresponding modulating index of m, m A ≤ m ≤ m B can
be deduced from the active signals of the corresponding limit
modulation indexes of m A , m B as:
v x12, m = (1 − η )v x12, A + ηv x12, B
Where η = ( m − m A ) /( m B − m A ) .
Compared to limit deduced in [3], the carrier based
single-state PWM approach can help to get a maximum
modulation index up to that of six-step method. Three limit
active modulating signals corresponding to modulation
indexes of 1,1.055 and 1.1 are proposed (Fig.8). In Fig. 8d,
reference modulating signal is deduced for mref =1.03.
V. SIMULATION AND EXPERIMENTAL RESULTS
Diagrams of the phase leg voltage and line-line voltage in
five-level inverter for several modulation indexes in under-
and over-modulation have been calculated and drawn in
Fig.9,10 and 11. The voltage quality can be more precisely
evaluated through the following diagrams of Fourier
analysis of low harmonic components and THD factor as
shown in Fig.12 and Fig.13. For comparison, corresponding
diagrams for 7-level inverter are also included in Fig.14 and
16. The single-state PWM method can be advantageously
operated at medium and high modulation index, where
harmonic amplitude can be reduced to about 5% to index of
0.45 for 7 level inverter, while this happens around index of
0.8 for 5-level inverter.

Control characteristics: The diagrams of nonlinear control

characteristics of five- and seven-level inverters are
calculated and drawn in Fig.15 and Fig.16. A better linearity
characteristic is obviously obtained for higher level inverters.

Experimental results: A harware set - Five-level cascaded

inverter has been built to validate the theoretical analysis.
The hardware parameters are as following: IGBT
IRG450UD, three-phase load R=20 Ω ; each dc source
Vdc=35.6Vdc; the measuring osciloscope TDS2012 and
Control kit eZdsp TMS320F2812. The diagrams of leg
voltage, line-line voltage and its FFT analysis for modulation
indexes of 0.4, 0.85 and 1.05 are measured and shown in
Fig.17,18 and 19. These diagrams are similar to the
simulated waveforms in Fig.9-11. Figure 8: a),b) and c) Diagrams of A-phase active voltage and leg voltage
for limit modulation indexes of 1,1.055 and 1.1 with minimum common
mode and d) derivation of reference modulating signals for m=1.03.

Figure 7: 5-level inverter: Diagrams of leg-pole voltage for single-state

PWM method with minimum CM offset for a) mref = 0.5 , c)
Figure 9: Five-level inverter. Simulation results. Diagrams of leg voltage and
mref = 0.9 , and with medium CM offset for and for b) line-line voltage for mref=0.4.

mref = 0.5 , d) mref = 0.9 and e) f) overmodulation.

 Figure 12: Single-state PWM for 5-level inverter. Harmonic voltage
diagrams

Figure 10: Five-level inverter. Simulation results. Diagrams of leg voltage

and line-line voltage for mref=0.85.

Figure 13: 5-level inverter. Diagram of voltage THD factor

Figure 14: 7-level inverter. Single state PWM method: Fourier

analysis diagram of harmonic voltage components .

Figure 11 : Five-level inverter. Simulation results. Diagrams of leg voltage

and line-line voltage for mref=1.05.
Figure 15: 5-level inverter. Diagrams of control characteristics of
fundamental voltages for entire modulation index range in single-state and
two-state PWM methods.

Figure 17: Five-level inverter. Experimental results. Diagrams of leg

voltage, line-line voltage and Fourier analysis of line-line voltage for
mref=0.4.

Figure 16: Single state PWM method: Control characteristics

for 7-level inverter

VI. CONCLUSIONS

In the paper, the carrier based single-state PWM method for

reducing the switching losses for multilevel inverter has
been proposed. It has been introduced a proper tranformation
of switching state diagram of multicarrier modulation into a
nominal switching time diagram. The proposed PWM
method can be extended to full voltage range to six-step
mode. The PWM performance as switching losses and its
distribution on switching devices and common mode voltage
can be improved by corresponding selection of common
mode voltage.

REFERENCES
[1] N.V.Nho, M.J.Youn,” Comprehensive study on Space
vector PWM and carrier based PWM correlation in multilevel
invertors ” , IEE Proceedings Electric Power Applications,
Vol.153, No.1, pp.149-158, Jan. 2006
[2] N.V.Nho,H.H.Lee,” Optimised Discontinuous PWM for
multilevel inverter with variable load power factor”, PESC
2006
[3] Jose Rodríguez, Luis Morán, Pablo Correa and Cesar
Silva,”A Vector Control Technique for Medium-Voltage
Multilevel Inverters’, IEEE TRANSACTIONS ON Figure 18: Five-level inverter. Experimental results. Diagrams of leg
INDUSTRIAL ELECTRONICS, VOL. 49, NO. 4, AUGUST voltage, line-line voltage and Fourier analysis of line-line voltage for
2002 mref=0.85.
Figure 19 : Five-level inverter. Experimental results. Diagrams of leg
voltage, line-line voltage and Fourier analysis of line-line voltage for
mref=1.05