SOFT-SWITCHED DC/DC CONVERTER WITH

PWM CONTROL

INDEX:
ABSTRACT
1. INTRODUCTION
2. TECHNIQUES USED
 PWM CONTROL
 SOFT SWITCHING
 COMPARISON OF ZVS AND ZCS
3. DEVICES USED
 POWER MOSFET
 POWER DIODE
4. PROPOSED CONVERTER
5. BASIC CONVERTER VARIATIONS
 CAPACITIVE FILTER
 INDUCTIVE FILTER
6. PRINCIPLE OF OPERATION
7. DC CHARACTERISTICS
8. ZVS TRANSITION
9. IMPLIMENTATION USING PSIM
10. EXPERIMENTATION RESULTS
11. CONCLUSION
 REFERENCES

ABSTRACT

An assymetrical pulse width modulation (PWM) control

scheme is used to control the coverter under constant switching
frequency operation. The modes of operation for both variations are
discussed. The d.c. characteristics which can be used in the design of
the converters, are also presented.

The aim of the present work is to incorporate constant

frequency operation in a basic soft switching half bridge converter
topology without additional components or complexity. This is
achieved by using assymetrical pwm control in this converter for
output regulation.Due to the inherent advantages of the proposed
convereter/control scheme, such as low MOSFET voltage stress, low
component current stress, and constant frequency operation, the
converters were found to be capable of achieving high efficiencies,
even under partial load conditions.
 INTRODUCTION:

High frequency soft-switched converters using the lossless

zero-voltage-switching (ZVS) technique have been recognized as
candidates for high-density dc/dc power converter applications.
These converters have the aim of high- frequency high efficiency
operation through reduction in power MOSFET switching loss.
However, in general, they suffer from one or more of the
following limitations:
1) Increased current levels;
2) Increased MOSFET voltage stress;
3) Wide switching fs frequency range;
4) Minimum-load requirement.
Some of the limitations can be overcome by using
half-bridge (HB) and full-bridge (FB)-based circuits with ZVS
action during transitions. It possesses considerable merits such
as constant frequency operation and low switch-voltage stress.
However, it utilizes four MOSFET’s, which make it unattractive for
economical low-power applications. Voltage is controlled by
varying switching frequency fs which is undesirable because the
frequency range can be very wide. Constant frequency operation
of the HB topology can be achieved through extra switches to
provide additional control means. However, in these cases, the
simplicity of the HB circuit with two power switches is
compromised.
Fig. 1. Basic HB soft-switched converter—without output rectifier/filter.

Fig. 2. Basic HB waveforms under PWM duty-cycle control.

The aim of the present work is to incorporate constant

frequency operation in a basic soft-switching half-bridge
converter topology without additional components or complexity.
This is achieved by using asymmetrical PWM control in this
converter for output regulation. Two main variations of the basic
topology will be presented in this paper [based on the type of
output filter (inductive or capacitive)]. Due to the inherent
advantages of the proposed converter/control scheme, such as
low MOSFET voltage stress, low-component current stress, and
constant frequency operation, the converters were found to be
capable of achieving high efficiencies, even under partial-load
conditions.
PWM CONTROL:

In dc-dc converters , the average output voltage must be

controlled to equal a desired level , though the input voltage
and the output load may fluctuate. Switch- mode dc-dc converter
with a given input voltage , the average output voltage is
controlled by controlling the switch on and off durations (ton and
toff ).to illustrate the switch mode conversion concept, consider a
basic dc-dc converter shown . the average value Vo of the output
voltage vo in fig depends on the ton and toff. One of the methods
for controlling the output voltage employs switching at a
constant frequency (hence a, constant switching time period
Ts= ton+toff) and adjusting the on duration of switch to control
the average output voltage. In this method, called pulse width
modulation (PWM) switching, the switch duty ratio D , which is
defined as the ratio of the on duration to the switching time
period , is varied.
The other control method is more general , where both the
switching frequency ( and hence the time period) and the on
duration of the switch are varied. This method is used only in dc-
dc converters utilizing force- commutated thyristors . variation
in the switching frequency makes it difficult to filter the ripple
components in the input and output waveforms of the
converters.
Switch mode dc-dc converters
 Pulse width modulator (a) Block diagram (b) comparator
signals

In the PWM switching at a constant switching frequency,

the switch control signal, which controls the state (on/off) of the switch,
is generated by comparing a signal – level control voltage Vcontrol with
a repetitive wave forms as shown above. The control voltage signal is
generally obtained by amplifying the error , or the difference between
the actual output voltage and its desired value.The frequency of the
repetitive waveform with a constant peak , which is shown to be a saw
tooth , establishes the switching frequency. This frequency is kept
constant in a PWM control and is chosen to be in few kilohertz to a few
hundred kilohertz. when the amplified error signal , which varies very
slowly with time relative to the switching frequency , is greater than
the saw tooth waveform , the switch control signal becomes high ,
causing the switch to turn on . otherwise, the switch is off. In terms of
Vcontrol and the peak of the saw tooth wave form Vst in above figure
the switch duty ratio can be expressed as

D = ton/Ts = Vcontrol/Vst
Asymmetric Duty Cycle:

I ) What is Asymmetric Duty Cycle?:

To understand the operation of these circuits, imagine a

standard PWM, transformer coupled, bridge-type converter (which is
known, perhaps, as a quasi square-wave converter). Initially, the
converter is operating at a 50% duty cycle with only enough dead time
to allow voltage commutation of the switches. With enough switch
current and proper timing, this circuit can switch losslessly with the
transformer leakage inductance or a separate commutating
inductance, providing an inductive kick to swing the switch voltages. If
the amplitude of this voltage “ring” is large enough, precise switch
turn-on timing can exploit it to effect a lossless switching transition.

Next, lower the duty cycle of this imaginary converter to

40%. Lossless switching is immediately lost since the switch voltages
will not be at the required zero volts when they are turned on.

To regain lossless switching, leave one of the legs at the

40% duty cycle while increasing the opposite leg to a 60% duty cycle.
Now, the switches are again able to exploit the inductive turn-off “ring”
to gain lossless switching. This unequal duty cycle operation gives
these circuits their name and allows the circuits to switch losslessly.
This unbalanced condition immediately poses serious operational
difficulties (primarily the volt-second balance of the power transformer
and the possibility of regulation), but these are solvable difficulties and
are addressed in the design equation section.

2) Advantage of Asymmetrical Circuit:

It is understandable at this point to ask what possible

reason there could be for going through such a seemingly awkward
and convoluted exercise to attain lossless switching. After all, lossless
switching can be achieved by any number of more straightforward
means. The answer is that these converters, with their strange duty
cycles, can also achieve low switch conduction losses (as low as PWM
circuits) long regarded as benchmark circuits with the lowest possible
conduction losses.

Comparisons

Any converter topology must compare favorably with the

standard converter circuits currently being employed if it is to warrant
any investigation beyond the level of simple curiosity. In addition, such
a comparison helps to define the converter’s possible role in power
conversion.

I ) Switch Mode Converter:

PWM switch mode converters have among the lowest

conduction losses of all the converter circuits. On the down side, PWM
converters are “hard switch” circuits that suffer from high switching
losses, which limit their usefulness at high frequencies.

2) Resonant Converter:

The undesirable switching losses of switch mode

converters lead designers to the resonant class of converters that
eliminate switching losses, opening the door to higher frequencies and
physically smaller converters. However, these converters pay a heavy
price in high conduction loss and large peak currents and voltages.

3) Resonant Pole Converter:

Resonant pole or phase shift converters also switch

losslessly, and their operation seems in many respects to mimic switch
mode converters. The one feature they do not mimic, however, is the
low conduction loss of switch mode converters. This fact is an
undesirable result of the freewheeling idle current required to flow in
the primary side circuit during the dead time between conduction
intervals.

4) Asymmetric Duty Cycle Converter:

The asymmetric duty cycle converters combine the best

features of these circuits. Their conduction losses are as low as switch
mode circuits. And they switch losslessly like resonant circuits. Timing
difficulties can limit their maximum frequency to something less than
that which is attainable by true resonant circuits, and the boundary
condition requirements for lossless switching are somewhat more
restrictive than for resonant pole converters. In many cases, however,
these drawbacks are acceptable because of the benefit of low
conduction loss and the elimination of switching loss.

SOFT - SWITCHING TECHNIQUES

With available devices and circuit technologies, PWM converters
have been designed to operate generally with a 30-50-kHz switching
frequency. In this frequency range, the equipment is deemed optimal
in weight, size, efficiency, reliability, and cost. In certain applications
where high-power density is of primary concern, the conversion
frequency has been chosen as high as several hundred kilohertz. With
the advent of power MOSFETs, device switching speeds of tens of
megahertz are now possible. Accompanying the higher switching
frequency are increased switching stresses and losses. Furthermore,
the presence of leakage inductances in the transformer and junction
capacitances in the semiconductor devices causes the power devices
to inductively turn-off and capacitively turn-on. As the semiconductor
device switches off an inductive load, voltage spikes induced by the
sharp di/dt across the leakage inductances produce increased voltage
stress and noise. On the other hand, when the switch turns on at a
high voltage level, the energy stored in the device's output
capacitance, 0.5CV2, is dissipated internally when the device is
switched on. Furthermore, turn-on at high voltage levels induces a
severe switching noise.

To improve switching behavior of semiconductor devices in

power processing circuits, two techniques were proposed. The first is
the zero-current-switching (ZCS) technique.B y incorporating an LC
resonant circuit, the current waveform of the switching device is forced
to oscillate in a quasi-sinusoidal manner, therefore, creating zero-
current-switching conditions during both turn-on and turn-off. By
simply replacing the power switch(es) in PWM converters with the
proposed resonant switch, family quasiresonant converters (QRCs) has
been derived.

This new family of circuits can be viewed as a hybrid of

PWM and resonant converters. QRCs utilize the principle of inductive or
capacitive energy storage and transfer in a manner similar to PWM
converters, and their circuit topologies also resemble those of PWM
converters. However, an LC tank circuit is always present near the
power switch and is used not only to shape the current and voltage
waveforms of the power switch but, also, to store and transfer energy
from the input to the output in a manner similar to the conventional
resonant converters. For off-line as well as dc-dc converters convise off
switching loss and switching stresses. Employing the zero-current
switching technique, several off-line converter topologies have been
successfully implemented achieving a power density of 25 W/in3 .
However, to operate the semiconductor switches above one
megahertz, the capacitive turn-on loss associated with the discharging
of energy stored in the parasitic junction capacitance of the MOSFET
becomes the primary limiting factor.

The second technique proposed is zero-voltage-switching

(ZVS) . By using an LC resonant network, the voltage waveform of the
switching device can be shaped into a quasi-sine wave, such that zero-
voltage conduction is created for the switch to turn on and turn off
without incurring any switching loss. This technique eliminates the
turn-on loss associated with the parasitic junction capacitances.
Practical quasi-resonant-converter circuits operating in frequencies
over 10 MHz have been implemented.

As the switching frequencies boosted into the megahertz

range, the abrupt switching approach used in the conventional PWM
converter encounters formidable difficulties. In particular, the
switching stresses and losses, which are suppressed by means of
scrubber circuits or ignored at lower frequencies, become intolerable
at high-frequency operations. To alleviate switching stresses and
losses, the concept of the resonant switch was introduced and
implemented either in the form of zero-current switching (ZCS) or zero-
voltage-switching (ZVS). By direct application of the resonant
switch(es) into PWM converters, a new family of quasi resonant
converters (QRCs) have been discovered. This new family of converters
with literally hundreds of topological variations can be viewed as
hybrids of PWM and conventional resonant converters.

They utilize the principle of inductive or capacitive energy

storage and transfer for power conversion in a fashion similar to PWM
converters. However, an LC tank circuit is always present in
conjunction with the power switch and is used not only to shape the
current and voltage waveforms but, also, to store and transfer energy
from input to output in a manner similar to the conventional resonant
converters. For this reason, the QRCs are regulated only with the use
of a frequency modulation (FM) technique. This family of QRCs can be
divided into two classes, one class is referred to as ZCS-QRCs
employing ZCS concept; the other referred to as ZVS-QRCs employ the
ZVS concept.

ZCS-QRCs and ZVS-QRCs again can be subdivided into two

categories: full-wave (FW) mode and half-wave (HW) mode, depending
upon whether the power switch is unidirectional or bidirectional. It has
been shown that the FW-QRCs are load insensitive. Therefore, the
switching frequency is maintained constant as the load varies QRCs,
are load sensitive. As the load varies, the switching frequency has to
be modulated over a wide range to maintain output-voltage regulation.
For off-line applications and for switching frequencies up to 1 MHz, the
ZCS technique is very effective since it eliminates the switching
stresses and turn-off losses. Employing the ZCS technique, a 1-MHz
100-W off-line converter was developed which achieved a power
density of 25 W/in3. This technique results in a switch current
waveform which is quasi-sinusoidal and a switch voltage waveform
which is quasi-square wave. The device’s voltage stress is minimum
but its conduction loss is higher than that of PWM converters. To
operate the semiconductor switches at a higher frequency, the

capacitive turn-on loss associated with ZCS must be avoided.

To minimize the capacitive turn-on loss, the ZVS

technique was proposed. This technique allows the power switches to
turn-on under zero-voltage condition and, therefore, eliminate the turn-
on loss associated with the parasitic junction capacitances. Since the
power switch is always turned on at zero-voltage, a simple capacitor
snubber (in many cases, Cds of the MOSFET) can be used to minimize
turn-off loss and, thus, achieve a zero-voltage turnoff condition.

The ZVS technique offers several distinct advantages:

• Elimination of switching losses and stresses while achieving high

efficiency by keeping the device‘s conduction loss minimal.
 • Elimination of dv/dt and di/dt noises due to device switching. The
dv/dt noise is often coupled into the drive circuit by means of the
Miller effect and is one of the primary limiting factors for
designing at very high frequencies.

• Reduction of EMI.

It is important to note that all the merits can be achieved

by utilizing the parasitic elements in the circuits such as the
transformer’s leakage inductance and semiconductor junction
capacitances.

Furthermore, the slow-recovery body diode of the MOSFET

can be used in the circuit due to the nature of zero-voltage switching.
Consequently, the converter circuits are remarkably simple. Since the
ZVS technique results in a quasi-square current waveform and quasi
sinusoidal voltage waveform, the conduction loss is minimized but the
peak voltage stress across the switch can be several times higher than
that of the PWM converter.

Consequently, the single-ended converter topologies are

not suited for off-line applications. The technique is particularly suited
for distributed, on-board, dc-dc converters where high power density is
most desired. Practical ZVS-QRCs have been implemented operating
in frequencies over 10 MHz.

Other important design aspects of high-frequency QRCs

have been addressed. A new quasi-resonant gate-drive for MOSFETs is
proposed. This simple drive scheme enables fast switching while
reducing the power consumption in the gate circuit by half compared
to conventional gate drives.

A new, multi-loop control, analogous to current mode

control for PWM converters, has also been developed for QRCs. The
new control provides a rugged system with excellent transient
response and noise immunity. The need for a VCO, which can be
difficult to implement at high frequencies, is eliminated.

WORKING OF SOFT SWITCHING:

. At turnoff in ZCS circuits, the drain-source voltage is

reduced to zero by external circuit means (such as the reversal of
current in a resonant circuit or the switching of current by an auxiliary
circuit). During the voltage reversal, the device is gated off so that
when voltage is reapplied the device is in the off state. Thus, ideally
there is no turnoff loss in the device. In practical implementations,
however, the rate
of reapplication of voltage (dv/dt ) must be limited to prevent
retriggering (GTOs) or latch-up (IGBTs), and reduce EMI.

In addition, the time during which reverse voltage is

applied must be sufficient to allow most of the device stored charges
to recombine. Otherwise, substantial device current will be present
during the reapplication of voltage resulting in high energy loss. It will
be noted that all thyristor forced commutated circuits popular during
the 1960s and 1970s (before the introduction of gate-controlled
devices) are of the ZCS. ZCS can also be achieved in circuits that
employ devices with inverse parallel diodes (rather than the series
diode). In this case, current is forced to flow in the inverse parallel
diode during which time the switching device is gated off.

Zero-voltage switching (ZVS) switching requires power

devices with gate turnoff capability. Low-loss turn off is achieved due
to a capacitance connected directly across the device. The capacitance
may be the parasitic drain source capacitance of a power MOSFET or a
discrete capacitance (which is the normal case for bipolar type devices
such as IGBTs and GTOs). The drain-source capacitance is not
discharged through the device at turn on—rather, at turn on, the drain-
source voltage is reduced to zero through external circuit means (such
as the reversal of voltage in a resonant circuit) as current, , reverses
and eventually flows through the inverse parallel diode. The device is
gated on during the diode conduction time. As the external circuit
forces a current reversal (positive ) the gate-controlled device picks up
the current in the forward direction. In this manner, very low turn on
loss is incurred. Note that, in ZVS, the capacitive energy is not lost but
is returned to the circuit through resonant action while in the ZCS case
the energy stored in the capacitance is lost. Thus, ZVS circuits are
normally the topologies of choice for very high switching frequencies
when FETs are used ( 500 kHz).

Either ZCS or ZVS techniques can be applied for higher

power applications at lower switching frequencies. The choice will
depend on switching frequency, size requirements, switching losses
(type of switching device used), and control complexity. Normally , ZVS
approaches are simpler to control than ZCS approaches in dc–dc
converters. However, recent work has suggested that ZCS techniques
result in lower switching losses for IGBT devices due to the growth
in turnoff switching loss as temperature increases. This is due to the
growth in the current turnoff “tail” that substantially increases at
elevated temperature. It is noted that most conventional PWM dc–dc
converters can be converted to a ZVS mode of operation with few
additional components.

Hard Switching Waveforms:-

• Comparison of Hard versus soft switching

EVICES USED:-

DIODES:
MOSFET :

1. Parasitic BJT. Held in cutoff by body-source short

2. Integral anti-parallel diode. Formed from parasitic BJT.

3. Extension of gate metallization over drain drift region. Field plate

and accumulation layer functions.

4. Division of source into many small areas connected electrically in

parallel. Maximizes gate width-to-channel length ratio in order to
increase gain.

5.Lightly doped drain drift region. Determines blocking voltage rating.

MOSFET :- CIRCUIT SYMBOLS

MOSFET CHARACTERISTICS :-

The transfer characteristics of power MOSFET can be classified in

three ways
1. Transfer characteristics
2. output characteristics
3. switching characteristics
TRANSFER CHARACTERISTICS :
This characteristics shows the variation of the drain
current Id as a function of gate source voltage VGS.

.
TRANSFER CHARACTERISTICS

OUTPUT CHARACTERISTICS :
This characteristics shows the variation of drain current ID as a
function of drain source voltage VDS. For low values of I D vs VDS the
characteristics almost linear, this indicates a constant value of on
resistance RDS = VDS/ID. Here A indicates fully on condition and B
indicates fully off state.

OUTPUT CHARACTERISTICS
SWITCHING CHARACTERISTICS:
The switching characteristics of a power MOSFET are influenced
to large extent by the internal capacitance of the device and internal
impedance of the gate drive circuit. At turn on, there is an initial delay
tdn is called turn on delay time. there is threshold voltage VGST. Here tdn
is called turn on delay time. There is further delay t r, called rise time,
during which gate voltages rises to VGSP, a voltage sufficient to drive
the MOSFET into on state. During tr, drain current rises from zero full
on current ID. Thus the total turn-on time is ton=tdn+tr. The turn on
time can be reduced by using low impedance gate drive source. As
MOSFET is a majority carrier device, turn off delay time, tdf, the time
during which input capacitance discharges from overdrive gate voltage
V1 to VGSP. The fall time, tf is the time during which input capacitance
discharges from VGSP to threshold voltage. During tf, drain current falls
from ID to zero. So when VGS Vs VGST, MOSFET turns off and completes
switching waveforms are shown.

TURN ON CHARACTERISTICS OF A POWER MOSFET

 TURN OFF CHARACTERISTICS OF POWER MOSFET

MOSFET:- INTERNAL CAPACITANCES

• These capacitances affect the MOSFET switching

• Gate-source capacitance Cgs approximately constant and
independent of applied voltages.

• Gate-drain capacitance Cgd varies with applied voltage.Variation due

to growth of depletion layer thickness until inversion layer is formed.

II. PROPOSED SOFT-SWITCHED CONVERTER WITH

PWM
CONTROL
The proposed converter without the output section is
similar to the HB topologies mentioned in Fig 1 given below
 Fig. 1. Basic HB soft-switched converter—without output rectifier/filter

capacitors Cf1 and Cf2 usually have the same capacitance value , and
they divide the supply voltage Vs such that
V1+V2=Vs.
Lm is the transformer magnetizing inductance while L is the primary-
side leakage inductance augmented, if necessary, by an external
inductor.C1 and C2 can be the device (such as MOSFET) parasitic
capacitance. The soft switching mechanism is used by using these
parasitic capacitances. Switches S1 and S2 are operated
asymmetrically as shown in Fig. 2. Neglecting the dead times to be
provided for soft transitions of the switches, the duty cycles of S1and
S2 will be D and (1-D), respectively. With this assumption, the voltages
V1 and V2 across Cf1 and Cf2 can be shown to be dependent on D as
follows:

V1=Vc1(avg) + Vab(avg) …………………………………………..…(1)

where
Vc1(avg)= Average voltage across S1= Vs(1-D) …….
(2)
 Vab(avg) Average voltage across L and transformer primary =0 .
(3)
Hence, V1 = Vs (1-D) …………………………………………(4)
V2 = Vs * D. …………………………………………(5)
The voltage Vab(Fig. 2) is applied to L and the transformer whose
output is rectified and filtered to feed the load. Thus, in general, the
Vab waveform and hence, output voltage can be controlled through
duty-cycle variation. The operation exhibits
a symmetry for the two ranges of D from 0% to 50% and from 50% to
100%. Full output control can be achieved with D varying within one of
these ranges.
The proposed converter-control combination
has several advantages including:
1) Low MOSFET voltage stress;

2) ZVS;

3) Low conduction losses;

4) Minimum component count;

5) Effective use of parasitic elements;

6) Simple and effective control;

7) High partial-load efficiency; and

8) Small output filtering circuit.

A negative aspect could be the relative sluggishness of

response due to the filter capacitances Cf1 and Cf2 whose voltages
now change with the control duty cycle. However, since fs would be
high, the relative loss in control bandwidth may not be significant. A
second disadvantage is the likelihood of transformer saturation at duty
cycles far from 50% due to increased dc magnetizing current. Overall,
however, the proposed converter and control are capable of achieving
high efficiencies and high power densities. Incidentally,it may be noted
that this control method is also applicable to a half-bridge converter
without the ZVS transition (i.e., to a hard-switched converter).
III. BASIC CONVERTER VARIATIONS

Fig. 3. Soft-switched topology using PWM control.

(a) Circuit A—CAPACITIVE FILTER

b) Circuit B—INDUTIVE FILTER

Two converter variations [Fig. 3(a) and (b)] will be discussed in

our project. In the converters in Fig. 3, switches S1 and S2 have been
replaced by bidirectional switches consisting of MOSFET’s Q1 and Q2
and their body diodes D1 and D2.Cf1 and Cf2 have been combined to
form one capacitor CB whose dc voltage Vc equals DVs under steady-
state operation. CB acts both as an energy source feeding the load
during Q2-ON interval and as a blocking capacitor for preventing
transformer saturation. Also, under steady-state operation, the dc
average value of the transformer magnetizing current (Im) is
automatically set such that the average charge into CB(Cf1and Cf2 in
Fig. 1) over a cycle equals zero.

In the capacitive-filter variation , the transformer is

current fed due to the presence of L and the absence of output
inductor. The secondary current is rectified and fed to a capacitor filter.
In this scheme, ideally, the output diode voltage rating is limited to
twice the output voltage only, which is smaller than that in the
inductive filter variation discussed below. Lower diode voltage rating
usually implies lower forward voltage drop with a consequent
reduction in conduction loss.

In the inductive-filter variation (Circuit B), an additional

output inductor L0 is used. Inductor L will be much less than L 0 value
reflected onto the primary side of the transformer. Hence, the
transformer is essentially voltage fed, and its secondary voltage is
rectified and fed to the L0C0 filter and load. In this circuit, L can be very
small compared to the requirement in Circuit A, and usually the
leakage inductance of the transformer is sufficient. Unlike in Circuit A,
where the primary and secondary currents are triangular in shape, the
currents in Circuit B are closer to rectangular wave shape resulting in
lower rms currents and device conduction losses.
IV. PRINCIPLE OF OPERATION
 The following explanation for both the converter variations’
operations will be based D on from 0% to 50%. The assumptions, which
have been made to highlight the basic operation of the circuit, are as
follows:

1) Transformer secondary-side leakage inductance neglected;

2) Forward drop and capacitance of the output diodes neglected;

3) CB is large enough so that Vc is almost constant (ripple

neglected) and equal to DVs .

4) Lm is large so that Im is almost constant;

5) In Circuit A, C0 is large so that V0 is constant;

6) In Circuit B, L0 is much larger than L . The current in L0 is

always continuous.

Capacitor Filter Variation (Circuit A)

 Depending on the operating conditions, the
circuit can be in Region-1 operation in which both the output diodes
conduct in one cycle or in Region-2 operation in which only one diode
conducts. Region-2 operation is likely to occur under light-load
conditions. The converter’s theoretical waveforms for Regions 1 and 2
are shown in Fig. 4(a) and (b), respectively. Here, Vgs1,Vgs2 are the
MOSFET gate-drive waveforms, Vds1,Vds2 are the MOSFET drain-to-
source

voltages of Q1 and Q2, respectively, and Ids1,Ids2 are the currents in

the switches ( S1 and S2 ). The converter goes through different
topological modes ( A1,A2,…A9) in a steady-state cycle. The
corresponding equivalent circuits of the converter in each of the
topological modes are given in Fig. 5. Since the voltages across CB and
C0 are both constant in a steady-state cycle, they are replaced by the
dc voltage sources Vc and V0, respectively. Table I shows the modes
that the circuit will go through in Regions 1 and 2 operation for the two
duty-cycle ranges. The circuit is initially assumed to be in mode A1.
The inductor current IL is then equal to Im, which is negative. It will be
shown later that after one cycle of operation, the current will return to
Im value.

1) Region-1 Operation—Circuit A:
 Fig. 4. Theoretical current and voltage waveforms for Circuit
A in (a) Region-1
Fig 5. Equivalent circuits for different topological modes (circuit A)

a) Mode A1 [Fig. 5(a)]—[S1 (D1, Q1), D3 ON; S2, D4OFF]:

From Fig. 5(a), it can be seen that VL(voltage across L) will be
equal to {Vs(1-D) – nV0 }. The inductor current IL is initially carried by
D1followed by Q1 within this mode. It will ramp up from Im level [see
Fig. 4(a)] until Q1 is turned off at the end of mode A1 . As can be seen,
 the current is IL is at (near) its peak Ia prior to switch turn off. This
helps the ZVS operation, which the circuit undergoes in mode A2 .

b) Mode A2 [Fig. 5(b)]—(D3 ON; S1, S2, D4 OFF):

This is a transition interval during which the voltage across S1

gradually builds up. Capacitors C1and C2 resonate with L. The current
IL , which was previously flowing into S1, will be diverted to C1 and C2 ,
charging C1 and discharging C2 . These capacitors together act as a
lossless snubber for S1, and, thus, soft switching is achieved for S1.
When C2 , which is initially at Vs , discharges to slightly below zero, D2
conducts and voltage Vds1 is clamped at Vs . The operating mode then
changes to A3. Thus, S2(D2) is switched on under ZVS condition. The
time interval from Q1 turn-off instant to the instant when D2 starts to
conduct (interval A2) is the minimum time required before Q2 can be
turned on.

c) Mode A3 [Fig. 5(c)]—[S2 (D2, Q2), D3 ON; S1, D4

OFF]:

The conduction of D2 marks the beginning of mode

A3 . The shaded area in the Vgs2 waveform in Fig. 4(a) shows the
conduction period D2 of within mode A3 . The current IL is driven down
by voltage (Vc+nV0) . The conduction of D2 will end when IL changes
polarity. MOSFET Q2 can be turned on any time within this shaded
region to provide a smooth transition from D2 to Q2 . The interval
between Q1 turn off to IL changing polarity (mode A2 + shaded-area
interval in Vgs2) in Fig. 4(a) is the maximum delay time before which
Q2 must be switched on. During light-load conditions, the Ia level could
be so small that C2 may not discharge completely to 0 V to end mode
A2 . In this case, the diode fails to conduct even after IL has already
changed polarity. This indicates failure of ZVS transition. Under such
conditions , Q2 must be forcibly turned on. The increase in the
switching loss may be tolerated because the overall loss is low at light
loads due to the reduction in the conduction losses.

In mode A3 , as IL decreases , the current in D3(ID3) also

ramps down in a corresponding manner. The mode ends when ID3
become zero (IL=Im) . If Vc (=DVs) is larger than nV0 , D4 will be
forward biased and will conduct. The circuit proceeds to mode A4 [Fig.
5(d)], and the overall operation is in Region 1. If Vc is smaller than
nV0 , then both the output diodes are off. The circuit proceeds to mode
A7 [Fig. 5(g)] . The
overall circuit operation in this case is in Region 2 (SectionIV-A2).

d) Modes A4, A5, and A6 [Fig. 5(d), (e), and (f)]:

These three modes of operation are similar to modes A1,A2

and A3, respectively. In mode A4 (S2(Q2),D4 ON;S1,D3 OFF), CB acts
as the dc source supplying to the load. The interval ends when Q2 is
switched off . In the following mode A5(D4 ON;S1,S2,D3 OFF), resonant
transition of the switch voltages occurs. Mode A5 ends when the
voltage Vds1 drops to slightly below zero and D1 starts to conduct.
Mode A6 (S1(D1),D4 ON;S3,D3 OFF) then occurs. During this mode, IL
ramps up, and , consequently, current ID4 in diode D4 decreases. As
can be noticed, soft switching has again been achieved for the
switches. When IL equals Im (ID4 = 0 ),D3 takes over conduction, and
the circuit proceeds back to mode A1. This completes one cycle of
operation in Region 1. Also note that the value of IL has returned to Im
as assumed at the start of mode A1 earlier.
 Also, the shaded area of the Vgs1 waveform in Fig. 4(a)
shows the conduction period of D1 in modes A6 and A1 together. Q1
can be turned on any time during this interval before IL reverses
polarity.

2) Region-2 Operation—Circuit A:

Fig. 4. Theoretical current and voltage waveforms for Circuit A

in (b) Region-2 operation.
 a) Mode A7 [Fig. 5(g)]—[S2 (Q2) ON; S1, D3, D4
OFF]:

As explained in Section IV-A1, the circuit proceeds to mode A7

following mode A3 if Vc<nV0 . The current IL, which equals Im at the
end of mode A3 now circulates through CB,Q2,L and the transformer
primary. Since Lm is much larger than L ,Vxy, is equal to –Vc .
Inductor current IL will remain constant (=Im) because the resonating
frequency between Lm and CB is considerably smaller than the
switching frequency. This mode will continue until Q2 is switched off.
The circuit then proceeds to mode A8 . It may be noted that for Region-
2 operation with D>50%, mode A7 will be replaced
by mode A9[ S1(Q1) ON;S2,D3,D4 OFF] (see Table I).

b) Mode A8 [Fig. 5(h)]—(S1, S2, D3, D4 OFF):

In this mode , capacitors C1/C2 will be linearly
discharged/charged by the magnetizing current Im . When Vds2 rises
to (Vc+nV0) , diode D3 will be forward biased and will conduct. The
circuit then proceeds to mode A2 again. Mode A2 thus occurs twice in
Region-2 operation.
c) Mode A2 [Fig. 5(b)]—(D3 ON; S1, S2, D4 OFF):

C2 will continue to charge, but not in a resonant manner (

L with C1 and C2) until the voltage Vds2 reaches Vs and D1 starts to
conduct. The circuit will then go back to mode A1 completing one cycle
of operation in Region 2. Please note that during
mode A2 ,IL still remains almost constant at Im because the transition
period is short.
V. DC CHARACTERISTICS
The converters dc characteristics can be obtained in a simple
manner by neglecting certain intervals. For Circuit A, these are the
transition modes A2 and A5 in Region 1 and A2 and A8 in Region 2. In
the following , Ion’ (=Io/n) and Vo’ (=Vo/n) are load-current and
voltage variables referred to the primary side through the transformer
ratio. Also, the subscript n refers to a normalized variable.

Circuit A
Since the transformer is current fed, the average output current
(I0) is taken as the desired output variable. The voltage normalizing
factor is Vs , and the normalizing impedance is Zb ( = 2Π fsL). In the
following, Ion' and Imn' refer to the normalized output current and
magnetizing current variables Ian and Icn are the normalized values of
the peak currents in Q1 and Q2, respectively.

1) Region-1 equations:

Ion' = [D(1-D) – (Von' )²] Π /2 .…………………………(6)

Imn = Von' (2D-1) Π /2 ……….………………………...(7)

Ian = [2D(1-D) + (1-2D) Von' – 2(Von' ) ² ] Π /2 …………

(8)

Icn = - [2D(1-D) - (1-2D) Von' – 2(Von' ) ² ] Π /2 ………

(9)

2) Region-2 equations:

Ion' = [ Π D²(1-D-Von')]/(D+Von')…………………
(10)
 Imn = - Ion'…………………………………………..(11)
Ian = Π D(1-D-Von')(D+2 Von' ) /(D+ Von') …….…
(12)
Icn = Imn ……………………………………………………..(13)
As noted earlier, the boundary between the two regions occurs when is
DVs equal to nV0 . Using this condition with (6) or (10), the boundary
equation can be obtained

Ion'=D(1-2D) .………………………………(14)

Equations (6)–(14) are valid for D < 0.5. Similar equations can be

obtained for D > 0.5 also. The plots of Ion ' and Imn , shown in Fig. 8 for
the full duty-cycle range from 0% to 100%, can be used as design aids.
The boundary between Regions 1 and 2 is also shown in Fig. 8. The
plots show the symmetrical nature of the converter characteristics

around D=0.5. It can be seen that as Von' increases, the duty-cycle

range for Region-1 operation will reduce. In fact, at a Von' of 0.5, there
is no Region-1 operation.

The magnetizing current helps to reduce the

rms current level in the circuit. It also assists in the ZVS mechanism at
the instant when Q2 is switched off by increasing Ic level. As can be
observed from Fig. 8 in Region-2 operation, Imn increases in the
negative direction as D increases from 0% (load increases). This
(negative) ncrease in Im occurs to balance the charge flow into
capacitor CB as the load increases.

The magnitude of Ic [Fig. 4(b): IL waveform] is thereby increased,

which is useful in discharging C1 and charging C2 during switch
transition. Even though the current level may not be sufficient to
discharge these capacitors fully, the energy loss (0.5CV ² ) due to hard
switching that would occur at these light loads will be reduced. Also,
while increasing Ic, the magnetizing current reduces the Ia level. This
helps in reducing the conduction loss in Q1, which is proportional to
the square of the rms current. However, a large dc magnetizing current
creates an offset in the core flux swing, and a bigger transformer core
would be needed due to this.

As D increases further (Fig. 8), the operation shifts

to Region 1. Here, Imn starts to decrease as D increases. Unlike
Region-2 operation, the blocking capacitor CB discharges to supply-
load current through D4 conduction. As D increases, the current that
flows out from CB to supply the load increases. Thus, the magnetizing
current that is needed to discharge CB in order to satisfy the equal
charge criterion for CB will be less as D become larger in Region 2. The
magnetizing current will eventually go to zero when D reaches 50%
(Ian=Icn). It may be noted that this behavior of the magnetizing
current (reducing with D in Region 2) again reduces the rms current
level and also assists in the ZVS mechanism.

The peak current Ian of Q1 and Icn of Q2 . Because these peaks

always occur before the turn off of the switches, they actually help in
ZVS, even at light loads. However, at full-load condition, these peaks
are large, and if the MOSFET cannot be switched fast enough,
substantial switching loss might occur. Thus, fast-gate turn off of
MOSFET’s is needed. Alternatively, bigger capacitors (C1 and C2 ) are
needed to prevent fast rise of the drain to source voltage of the
MOSFET’s. The Ian and Icn curves can be used to determine the
current ratings of MOSFET’s that are needed.
VI. ZVS TRANSITION

As was mentioned earlier, there is a minimum dead

time before a MOSFET can be turned on after the other one is turned
off. This minimum time depends on:
1) The value of before the switch is turned off;

2) The inductor’s value;

3) The value of the output capacitors C1 and C2; and

4) Input supply voltage.

The bigger the first two factors, the smaller the

minimum time will be whereas the bigger the next two factors, the
larger the minimum time. Increases in capacitor value and supply
voltage can also cause difficulty in achieving ZVS. When ZVS fails,
hard switching will have to be resorted to. Usually, for both Circuits
A and B, this situation occurs at low loads.

In practice, the switch transition cannot be made

too fast or too slow. If the transition is too slow, it will be comparable to
the switching period affecting the steady-state performance of the
circuit. Also, the approximate current (or voltage) transfer ratio plots
shown earlier will not accurately reflect the characteristics of the
converters. If the transition is too fast, the MOSFET may not be able to
switch correspondingly fast enough in order to have ZVS operation.

The maximum time before which the MOSFET

can be turned on depends on the instant when IL changes polarity.
Usually, except under light-load condition, this duration is quite large
compared to the ZVS transition period. However, it is better to turn the
MOSFET on as soon as the body diode starts to conduct because the
conduction loss in the body diode would be generally larger than the
loss in the MOSFET
working in the synchronous region (third quadrant operation). Thus,
ideally, a variable dead-time control based on the detection of the zero
crossing Vds of the of the MOSFET has to be implemented.
Alternatively, a suitable fixed dead time for the MOSFET turn on can be
introduced. This allows the circuit to have ZVS down to a certain load
percentage
only below which the ZVS operation is abandoned. Such an approach
with a fixed dead time simplifies the control circuitry of these
converters.
 PSIM

PSIM is a simulation package specially designed for power

electronics and motor control. With fast simulation and friendly user
interface, PSIM provides a powerful simulation environment for power
electronics, analog and digital control and motor drive system studies.

This covers both PSIM and its three add-on modules; motor drive
module, digital control module and SIM coupler module. The motor
drive module has built in machine models and mechanical load models
for drive system studies. The digital control module provides discrete
models such as zero order hold, z-domain transfer functional blocks,
quantization blocks, digital filters, for digital control analysis. The SIM
coupler module provides interface between PSIM and
MATLAB/SIMULINK for co-simulation.
CIRCUIT SIMULATION AND RESULTS:
Experimental waveforms at D = 40%
Experimental waveforms at D = 10%