EEE 102 Introduction to Digital Circuit Design

XILINX IDE TUTORIAL

September 2006

Objective

This tutorial will give you brief information on overall design flow. You will learn to
use
• design entry via a schematic editor,
• functional verification via an HDL Testbench utility (HDL Bencher),
• a simulation tool (Modelsim XE) and
• implementation via a Spartan2 (Xilinx) FPGA prototyping board from Digilent.

In this tutorial, we will implement the following function using schematic entry:

Step 1 - Starting ISE and Creating a New Project

To start the Xilinx ISE tools, click on the Start->Programs->Xilinx ISE 6-

>Project Navigator. This will bring up a screen similar to that of Figure 1.

Figure 1 - ISE Project Manager

To create a new project, click on the menu File->New Project. This will bring up
a small dialog box with information about the new project. In the "Project Name"
box, type intro, the name we will use for the introductory tutorial. Now, select an
appropriate location for all of the project files to be saved in the "Project Location"
box. Preferably use the location D:\labs.
Set “Device Family" property to Spartan2, (if you are using the Pegasus board)
"Device" property to xc2s50, “Package“ property to pq208 and “Speed Grade“
property to -6. The "Design Flow" should be set to "XST VHDL”.

Figure 2 - New Project Dialog Box

Step 2 - Add a New Schematic Source File

Now, the project has been created. Next step is to create our schematic design
file. Click on the menu Project->New Source. This will bring up a small dialog
box with several choices for design entry. Select the Schematic choice from the
left box and type intro in the "Source Name" box. Be sure that the file location is
in your project directory and that the "Add to Project" checkbox is selected.
Click on "Next" and then "Finish" to add the schematic source and start
schematic editor.

Figure 3 - New Source Dialog Box

 Figure 4 - Blank Schematic Capture

Step 3 - Schematic Design Entry

In order to implement the given combinational equation, we need to insert

various basic logic components (AND, OR, NOT (Invert) etc.). First of all, we will
add a 2-input AND gate for the A and B inputs. Click on the menu Add ->
Symbol. This will bring up the Symbol Dialog Box containing the symbol
categories and the individual components of each library. In the "Categories"
box, select the Logic category and then select and2 from the "Symbols". When
you move mouse over the blank region, you will see the alias of the and2 icon.
Click on the place you want to locate the and2 component (after your each click,
one more component will be placed).

Figure 5 - Symbols Dialog Box

 Figure 6 - Schematic Capture With and2 Symbol Placed

Repeat this procedure to place the or2 and inv symbols (also located in the
Logic category) on the screen as shown by Figure 7.

Figure 7 - Schematic Capture With Symbols Placed

I/O access for the FPGA can only be achieved by running the external nets (or
stimulus) through I/O buffers. Since all of the logic has been placed, but not
wired, the next step involves placing the I/O buffers onto the sheet. This is done
in the same manner as with the logic, only the category is IO. Select this
category and place the component ibuf (Input Buffer) in front of the input
terminals of the and2 and inv components. Select the obuf (Output Buffer)
component and place it at the output of the or2 component. This should look like
something similar to Figure 8.

Figure 8 - Schematic Capture With All Logic and Buffers Placed

After all of the components are placed, the components should be wired using
nets. To draw the nets, click on the menu Add->Wire. Left-click on the terminals
of components to be wired respectively (there appears a square marker when
you point the mouse on the terminal). If you did correctly, a blue wire should be
observed between two terminals of the components (Figure 9).

Figure 9 - ibuf Output and and2 Input Wired

Finish wiring and add extra wires to the input terminals of the ibuf components
and to the output terminal of the obuf component. Select the extra wire of ibuf
input terminal, and click on the menu Add->Net Name to assign the name of the
input net. Repeat this step for all ibuf inputs (A, B, C for this circuit) and obuf
output (D for this circuit) (Figure 10).

Figure 10 – Net Naming Process For The First ibuf

Figure 11- All Named Nets Placed

The last step in the design is to add the I/O markers. Click on the menu Add->I/O
Marker. From the “Add I/O Marker Options”, select the marker type (input for
A,B and C, output for D) and click on the corresponding named net. The
completed schematic should look similar to Figure 12.
 Figure 12- I/O Markers Placed (Complete Circuit Design)

You can check to be sure that your design does not have any errors by clicking
on the menu Tools->Check Schematic. If you have no errors reported, you
should see a popup window as shown in Figure 13. If there is an error, use the
information in this window as a guide to help solve the error.

Figure 13- Schematic Check Errors Window

Once you are done, save the changes to the schematic, close the Schematic
editor, and return to the Project Navigator.

Step 4 - Generating the Testbench Using HDL Bencher

HDL Bencher is used for both functional and timing simulation purposes. For this
tutorial, we are only going to perform a functional simulation, and our simulation
should cover all truth table for this example.

To start the HDL Bencher tool, add a new source of type "Testbench
Waveform" with the name intro_tb. When the "Associate with source" window
appears, select your schematic design file (intro) (it should be the only available
selection). Click on "Next" and then "Finish". An initial window called "Initialize
Timing" will appear (Figure 14). This is used to obtain the desired timing
scheme used for the Testbench. The default is ok so click "OK" and continue.

Figure 14- Initialize Timing Window

The HDL Bencher tool will then open and look similar to Figure 15.

Figure 15- HDL Bencher Window

In order to generate the Testbench for this circuit, we will have to apply stimulus
to the inputs and give the expected output value. The truth table for this circuit is
as follows:
 C B A D
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
Table 1- Truth Table for the Given Boolean Equation

By looking at the truth table, the easiest way to stimulate this circuit is to apply a
toggling waveform to each input with specific duration and length. In the case of
the input A, we need to repeat a toggling waveform four times with a length of
one. For input B, we need to repeat the sequence twice with a length of each
pulse width two. Finally, for input C, the sequence only happens once but the
length of each pulse is four. By applying this stimulus, and checking it against the
desired output, the circuit will be correctly tested.
At 0 ns, double-click on the “0” in the light-blue section of the input A. A button
named "Pattern" will occur next to the “0”. Clicking on this button will display
"Pattern Wizard". Select “Toggle” for "Choose Pattern", “4” for "Repeat
Pattern # times:" (number of times we need to repeat this pattern) and “1” for
“Toggle Every” (number of cycles to toggle). The "Pattern Wizard" should look
like Figure 16.

Figure 16- Pattern Wizard for Input A

Click "OK" to accept the pattern. The stimulus for input A should look like Figure
17.
 Figure 17- Stimulus Waveform for Input A

For input B, display the "Pattern Wizard". Repeat the pattern twice and set
"Toggle Every" to “2”. For input C, repeat once and set "Toggle Every" to “4”.
HDL Bencher should now look like Figure 18.

Figure 18- Stimulus Waveforms for All Inputs

In order to complete the testbench, we assign the correct output waveform. Click
on the first yellow box to toggle from unassigned to '1' (correct output value at
this time instance). HDL Bencher should now look like Figure 19.

Figure 19- Partial Output Waveform

Click on the yellow box at 450 ns and 750 ns.

 Figure 20- Partially Completed Testbench

Pay attention to the half red column next to letter C in the waveform editor. This
partial red column indicates that the input C is not fully covered or has not been
fully tested. Click on the "Coverage Statistics" button on the toolbar. ( )

Figure 21- Coverage Statistics

The statistics show that the inputs have not been fully toggled and we know that
the input C has a coverage problem. C goes from '0' to '1' but never come back
to '0' state, which is the problem. Assigning A, B and C to ‘0’ after 800 ns and
setting the output to ‘1’ solve the problem. Check the coverage statistics to
ensure that the coverage is full. The final testbench waveform is shown in Figure
22.

Figure 22- Final Testbench Waveform

Save the waveform by clicking on the menu File->Save Waveform. Exit HDL
Bencher and return to the Project Manager.
Step 5 - Functional Simulation of the Design

Select intro_tb.tbw (Testbench Waveform File) in the "Sources in Project" field

and then double-click on the Modelsim Simulator -> Simulate Behavioral
VHDL Model in the "Processes for Current Source" field. Modelsim will start
and it will run the Testbench simulation (Figure 23). If you click “Zoom Full”
button ( ), the whole simulation results will be seen in the window.

Figure 23- Testbench Simulation in ModelSim

Verify that the Testbench completed successfully. If there is an error during the
simulation process, check your original source file and Testbench file to correct.
If there is an error in the simulation results, that will be probably due to the
original source file.

Step 6 - Design Implementation

Implementing the design involves taking the netlist files from design entry and
creating an optimized structure for a specific FPGA in a specific configuration.
The steps of implementation are the following:

1) Entering design constraints - Primarily location (pin) constraints and

timing
constraints.
2) Translation - Merging several netlist files into one, top-level netlist.
3) Mapping -Taking the translated netlist and mapping it to the desired
FPGA using location (pin) constraints.
4) Place & Route - Actually placing physical parts on the FPGA according
the design and supplying routing resources to those parts.
5) Post-Route timing -Self explanatory.
The first step, and only one that is of any concern for this tutorial, is to enter the
desired location (pin) constraints needed to fit the design to the capabilities of the
Spartan2 board.

Before assigning pins you have to add an “Implementation Constraints File”.

from Project Menu-> New Source-> Implementation Constraints File. Name it
intro_ucf and click “Next” and go on the design. In the Project Manager select
the intro_ucf file in the "Sources In Project" field, double-click on User
Constraints -> Assign Package Pins in the "Processes for Current Design"
field. In the new window, you will use “Design Object List – I/O Pins” field. Write
the below texts to the white boxes of the corresponding input/output in the
“Location” column. (Care that a BANK text will occur at the bank column when
you enter the text and press enter key)

For xc2s50-pq208
A: P89
B: P88
C: P87
D: P46

Once this is completed, the tool should look like Figure 24.

Figure 24- Final Implementation Constraints

Close the Constraints Editor and return to the Project Manager.

To run the full implementation, select intro.sch in the “Sources in Project” field,
double-click on "Implement Design" in the "Processes for Current Source"
field. You should see a lot of messages getting written into "Console" window.
Ignore any warnings as the tool may report that certain ports have not been
connected; this happens with a top-level schematic design.
Step 7 - Download to the Board

Please refer to the document “Downloading” for information on generating and

downloading the design bitstream to the Spartan2 boards.

Conclusion
During this tutorial you learned the basics on the ISE tools including schematic
design entry, Testbench generation, functional simulation, implementation, and
downloading to the Spartan2 boards.