UNIT 9 DATA BUS CONTROL

The CPU is in the read operating mode. The R/W signal is

b. high and data is transferred to the CPU.
The purpose of a high CS signal is to
a. enable a memory or I/O device to communicate with the CPU.
The logic states of inputs A and B are shown. The output of AND
gate 1 (W) is
b. low.
When the outputs of the WRITE and READ gates are low, the
b. CS control signal is low.
Can the outputs of the WRITE and READ gates be high at the same time?
b. no
The truth table for the READ and WRITE circuit is shown. A low CS control signal
and a high
R/W control signal cause the outputs of the WRITE gate to be
c. low and the READ gate to be low.
To transfer data from the CPU to an I/O device, which tri-state buffer has to be
enabled?
b. WRITE tri-state buffer.
When the READ tri-state buffer is enabled with a high READ signal, the output of
the WRITE
tri-state buffer is
c. in a high impedance state.
What prevents a CPU from writing and reading data to an I/O device at the same t
ime?
b. One or both of the tri-state buffers are always in a high impedance state.
3. b
4. b
5. b
6. b
7. a
8. a
9. b
10. a
11. a
12. b
Does the WRITE tri-state buffer output LED indicate that the CPU is writing the
data bit to the
I/O device?
b. no
Does the READ tri-state buffer LED indicate that the CPU is reading the data bit
from the I/O
device?
b. no
16. a
18. a
19. b
21. b
22. a
1. b
2. d
3. c
4. d
5. a
Exercise 2 Dynamic Control of a Data Bus
When the CPU wants to communicate with a device, the CPU causes
a. a high CS signal to the device.
The logic state of what signal determines if the CPU reads or writes to a device
?
b. R/W signal
When the CPU is reading from a device via the data bus, the outputs of all other
devices
connected to the data bus are in a
c. high-Z logic state.
4. b
5. c
6. c
7. b
9. b
10. a
11. a
13. a
14. b
15. b
1. a
2. d
3. a
4. b
5. c
UNIT TEST
The direction of data flow during computer read and write operations is in refer
ence to the
c. CPU.
Data transfer between the CPU and a memory chip or an I/O device is controlled b
y the
c. CS and R/W signals.
When the CPU wants to transfer data with an I/O device, the CPU enables the
a. device with a CS signal.
The purpose of the R/W signal is to
b. control the direction of data flow between the CPU and a memory chip or I/O d
evice.
The data bus of a computer is
a. a bidirectional bus: data flows in either direction on the bus.
This timing diagram shows the relationship of the signal and data
a. during a write operation.
In this circuit, the inverter
d. ensures that both AND gates have complementary outputs when input A is logic
1.
In this circuit, AND gate output D is high when input A is
d. high and input B is low.
In this circuit, data is transferred from the DATA BUS to an I/O PORT when enabl
e signal C is
b. high and enable signal D is low.
In this circuit, data is transferred from the I/O PORT to the DATA BUS when enab
le signal C is
a. low and enable signal D is high.
4. a
7. a
9. a
4. a
7. a
9. c
4. a
7. a
9. d