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Intel 8085 contains 40 pins as shown in - pin 36, input pin. CPU, and consequently a synchronization channels.

uently a synchronization channels. Two signal wires and tw


figure which has - When signal on this pin is low, the μP is mechanism may needed. ground return wires are required in this
- 8 unidirectional address pins (A8 toA15) reset. 3. Data codes and formats in peripherals mode. A disadvantage of this mode is the
- 8 bidirectional multiplexed address/data RESET OUT: differ from the word format in the CPU additional cost of the second channel. It is
pins (AD0 toAD7) - pin 3, output pin. and memory. however possible to offer simultaneously
- 11 control output pins - This signal indicates that μP is being 4. The operating modes of peripherals are two way communication on a single
- 11 control input pins. reset. different from each other and each must channel using complex circuitry.
- Two power supply pins +5v and ground. - This signal can be used to reset other be controlled so as not to disturb the
- A8 – A15 (pin 21 – 28) output devices. operation of the other peripherals Channel
Transmitter Reciver
- Does the work of carrying the 8 MSB of X1, X2 : connected to the CPU.
the address data. AD0 – AD7: To resolve these differences
- [pins 12 – 19 ] I/O .
- Pin 1, 2 , i/p pin computes systems include special
- It carrys both data and address. - These are terminals to connect to an hardware components between the CPU
- It carries lower address bits as well as it external crystal oscillator which drives on and peripherals to supervise and
can be used as data bus as it can be used internal circuitary of the μP to produce a synchronize all inputs and outputs Reciver Transmitter
channel2
as data bus. suitable clock for the operation of μP. transfers. These components are called
- Carries data of 8 bit.ALE (Address latch CLK: interface units because they interface Fig,Full Duplex Mode
enable): - pin 37, output pin. between the processor bus and peripheral
- Pin 30, output pin - It is a clock output for user which can be devices. The two major types of I/O
- It goes high during first clock cycle of a used for other digital ICs interface are: RS 232C interface with DTE and DCE:
machine cycle. - Its frequency is same at which processor 1. Serial interface. The figure below
- When high, AD0 – AD7 is used as operates. 2. Parallel interface shows a interfacing with minimum lines
address bus. SID:
IO/M : - pin 5, input pin. Serial interface: A serial interface The signaling in RS-232C is not
- pin 34, o/p pin - It is a data line for serial i/p. exchanges data with the peripheral in compatible with the TTL logic level. For
- Distinguishes whether the address is fir - The SID signal can be used to i/p the serial mode, where data are transmitted TTL 0 v to 0.2V is considered a logic 0
memory or SID pin to the most significant bit of the one bit at a time along a simple and 3.4 v to 5v as logic 1. But RS-232C
I/O accumulator. communication link. Serial transmission is works in a negative logic -3 to -15v
- When high the operation is performed SOD: slow but inexpensive to implement as far considered as logic 1 and +3 to +15v as
between I/O and μP - Pin 4, o/p pin. as the number of wires is connected. logic 0. Because of this incompatibility of
- When low the operation is performed - It is a data line for serial o/p. The function of serial I/O interface the data lines with the TTL logic, voltage
between memory and μp. - It can be used to o/p the most significant is to deal with the data on the bus in the translators called line drivers and line
S0 , S1 : bit of the accumulator. parallel mode and to communicate with receivers are required to interface TTL
- Pin 29, 33, o/p pin VCC: the connected device in the serial mode. logic with RS-232C signals. The line
- These are status signals and indicates the - pin 40, input pin. If the bus has n data lines the serial i/o driver MC 1488 converts logic 1 into
type of operation performed. - +5v dc supply. interface accepts n bits of datas approx -9V and logic 0 into +9v. Before it
S0 S1 Vss : simultaneously form the bus . These n bits is received by the DCE it is again
Operation - Pin 20, input pin. are put to the I/O devices one bit at a time converted by the line receiver MC 1489
0 0 HALT - Ground. requiring n time slot for transmission. The into TTLCompatible logic. The minimum
0 1 READ reverse process takes place during interface required both a computer and a
1 1 WRITE reception of data form the device. peripheral device requires three lines; pin
1 1 FETCH (bring info. From the Addressing modes: Each instruction 2,3 and 7. These lines are defined in
Memory to μP) requires certain data in which it has to Parallel interface: Some I/O devices can relation to the DTE; the terminal
RD: operate. There are various technique to handle data at speeds that can not be transmits on pin 2 and receives as pin 3.
- Pin 32, o/p pin specify data for instructions. These supported with serial interfaces so On the other hand the DCE transmits on
- Controls READ operation. technique are called addressing mode. such a case a parallel interface must be pin 3 and receives on pin 1. Pin 7 is
- When it goes low, the selected memory 1. Direct addressing mode: In this mode of used, where n bits of the data are handled ground pin
or I/O device is read. addressing the address of the simultaneously by the bus an on the
WR: operand(data) is given in the instruction it links to the device. This achieves a faster
- Pin 31, o/p pin self. Eg. STA 2400H, IN 02H interchange of data but becomes
- A low indicates a write operation being 2. Immediate addressing mode: In this expensive due to the need of multiple
performed into the selected memory or I/P addressing mode the operand is specified wires. If any I/O devices particularly those
device. within the instruction itself . eg. AVI A, requiring high data transfer rate use this
READY: 06L , LXI H, 2500H arrangement.
- Pin 35, i/p pin 3. Register addressing mode: The operand Communication can be broadly
- It is used to sense whether a peripheral is are in general purpose register. The defined as an unilateral or bipolar transfer
ready to transfer data or not. upcode specifies the address of the of meaningful data between two points 8085 Microprocessor unit pin details:
- If READY is high, the peripheral is registers in addition to the operation to through a mediums. Communication can
ready. be performed. MOV A, B , MOV B, ADD be in
- It is low, the μp waits till it goes high. B, SUB C 1. Simplex mode
HOLD ( when high): 4. Register indirect addressing mode: In 2. Half duplex mode
- pin 39, i/p pin this mode of addressing the address of 3. Full duplex mode.
- It indicates the another device is operand is specify by the register pair as a The simplex mode: This mode allows the
requesting the use of buses. Having pointer for operand. Eg, LXI H, 2500H , transmission of data over a single channel
received a HOLD request the μP stops MOV A,M , ADD M in one direction only. The data can be
the use of the buses as soon as the current 5. Implied addressing mode: There are transmitted only from point A to point B
instruction is completed. The processor certain instruction which operate on the not formpoint B to point A as shown in in
regains the bus after the removal of the content of a accumulator such instruction figure below. Physically two wire are
HOLD singnal. do not require the address of operand. Eg, required for transmission of data. One is
HLDA: CMA, RLA, RAR, NOP, signal wire
- Pin 38, 0/p pin. and other is ground return wire
- A signal for HOLD ack. Transmitter Reciver
- It indicates that the HOLD request has
been received. I/O interface: Fig.Simplex Mode
- After the removal of a HOLD request the Input and output interfaces provide a The half duplex mode: This mode is also
HLDA goes low. method for transferring information known as two way alternate transmission.
INTR: between internal storage and external I/O This mode allows the transmission of data
- pin 10 , input pin devices. Peripherals connected to a over a single channel in both directions
- It is an interrupt request signal. computer need special communication but not simultaneously. In this mode too,
- When it goes high the program counter links for interfacing them with central just two wires are required, but additional
does not increment its content. The μP processing unit. The purpose of the circuitry is needed to determine and
suspects its normal sequence of instruction communication link is to resolve the establish the direction of flow of
at hand it goes to the CALL instruction. difference that exist between the information..
INTA: processor and each peripheral. The major A B
- pin 11, o/p differences are:
- The μP sends as interrupt ack after INTR 1. Peripherals are electromechanical and Transmitt Revicer
is received. electromagnetic devices and their manner er Channel
RST 5.5, RST 6.5, RST 7.5 & TRAP: of operation is different form the
- Pin 9,8 , 7 & 6, input pin operation of the CPU and memory, which Revicer Transmitter
- These are interrupt signals. are electronic devices. Therefore a
- When interrupt is recognized, the next conversion of signal value may be Fig. Half duplex mode
instruction is executed from a fixed required. The full duplex mode: This mode allows
location. 2. The data transfer rate of peripherals is the transmission of data in both directions
- RST 7.5,6.5,5.5 are ……..interrupt. usually slower than the transfer rate of the simultaneously but on two separate
RESET IN :
next instruction to be executed which is that the internal interrupt is initiated by
contained by the program counter (PC), some exceptional conditions caused by the INTR:
these all are pushed onto the stack. program itself rather than by an This interrupt is maskable. It can be
GPIB ( General purpose 5. The processor then loads the program external events. Internal interrupts are enabled by instruction EI and can be
instrumentation bus ) ~ IEE- counter with the entry location of the synchronous with the program, while disabled by instruction DI. The INTR
488 standard interrupt service routine that will respond external interrupts are asynchronous. If interrupt requires external hardware to
~ HPIB (Hewlette puckard interface bus) to this interrupt. Once the program counter the program is return, the internal interrupt transfer program sequence to specific
This is the most widely used industrial bus has been loaded, the control is transferred will occur in the same place each time. CALL locations. There are 8 numbers of
format. It was developed to facilitate to the interrupt handler program. External interrupts depends on external CALL-Locations for INTR interrupt. The
interface of computers with various 6. The fundamental requirement of the conditions that are independent of the hardware circuit generate RST codes for
instruments as – printers, tape recorders, interrupt service routine is that it should program being executed at the time. this purpose and places that on the data
digital voltmeters, frequency counters, begin by saving the contents bus externally. When the microprocessor
function generators etc. Some of the of all the registers on the stack( as state of Software interrupt: External and internal is executing a program, it
features of this bus are: the main program should be safe). interrupts are initiated from signal that checks the INTR line (when interrupt
1. Data transfer among the interconnected 7. The interrupt handler now proceeds to occur in the hardware of the cpu. A enable flip flop is enabled using EI
devices in digital format. process the interrupt. This will include an software interrupt is initiated by executing instruction) during the execution of each
2. Allows 8 bit parallel bi-directional examination of status information relating an instruction. Software interrupt is a instruction. If the line is high and the
communication. to the I/O operation or the other special call instruction that behaves interrupt is enabled, the microprocessor
3. Fifteen devices may be connected to event that caused an interrupt. It may also like an interrupt rather than a subroutine completes the currents instruction,
one continuous bus. involve sending additional commands or call. It can be used by the programmer to disabled the interrupt enable flip flop and
4. Total transmission path is limited to 20 acknowledgement to the I/O unit. initiate an interrupt procedure at any sends a INTA signal. The processor does
metres or two meters per device. 8. When interrupt processing is complete desired point in the program. The most not accept any interrupt requests until the
5. Data transfer rate on any single line is the saved register’s value ( of the main common use of software interrupt is interrupt flip flop is enabled again.
limited to 1M-byte/sec program) are retrieved from the stack and associated with a supervisor call The signal INTA is used to insert a Restart
6. The bus as 24 signals: eight restored to the register. instruction. This instruction provides (RST) instruction, ( it saves the memory
bidirectional data lines. 9. The final function is to restore the PSW means for switching from a CPU user address of the next instruction to the stack.
: eight control lines. and program counter values from the mode to the supervisor mode. Certain TRAP:
: eight ground lines. stack. As a result the next instruction to be operations in the computer may be It is a non maskable interrupt. It has the
This standard describes four types of executed will be from the previously assigned to the supervisor mode only, as highest priority among the interrupt
devices which may be interface to GPIB. interrupted main program for example, a complex input or output signal. It need not be enabled and it cannot
a. Listners: These devices can receive data transfer procedure. In 8085 the instruction be disabled. When this interrupt is
band control signals from other devices Types of interrupt: like RST0,RST1, RST2, RST3…..etc. triggered the program control is
connected to the bus but are not capable of There are three major types of interrupts causes a software interrupt transferred to the location 0024 H
generating data. e.g printers. thatcause a break in the normal execution without any external hardware or the
b. Talkers: These devices are only capable of a program. They can be classified as : Polled interrupt: Polled interrupt are interrupt enable instruction. TRAP is
of placing data on the bus and can not 1. External interrupts handled usingsoftware and are therefore generally used for such critical events
receive data. Only one talker can be active 2. Internal interrupts slower compared to vectored as power failure and emergency shut off.
at a given time but fourteen devices can 3. Software interrupts (hardware) interrupts. In this method there RST 7.5, 6.5, 5.5: These interrupts are
listen at a time. Example for talkers are: External interrupts: External interrupts are is one common branch address for all maskable and are enabled by software
scanners, tape readers, voltmeters etc. initiated via interrupts. The program that takes care using instructions EI and SIM ( set
the microprocessor’s interrupt pins by of interrupts begins at the branch address interrupt mask). The execution of the
external devices such I/O devices, timing and polls theinterrupts sources in instruction SIM enables/disables the
device, circuit monitoring the power sequence. The order in which they are interrupts according to the bit pattern of
supply etc. Causes of these interrupts may tested determines the priority of each the accumulator
be; I/O device requesting transfer of data, interrupt. The highest priority source is
I/O device finished transfer of data, tested first, and if its interrupt signal is on, SET Interrupt Mask (SIM) instruction:
Interrupt: elasped time of an event, or power failure. control branches to a service routine for - This is 1 byte instruction.
An interrupt is a signal that a peripheral Timeout interrupt may result from a this source. Other wise the next lower - Can be used for three different functions:
board sends to the central processor in program that is an endless loop and thus priority source is tested, and so on. Thus, i). One function is set mask for RST 7.5,
order to request attention. In response to exceeded its time allocation. Power failure the initial service routine for all interrupts 6.6 and 5.5 interrupts. This instruction
an interrupt, the processor stops what it is interrupt may have as its service routine a consists of a program that test the interrupt reads the content of the accumulator and
currently doing and executes a service program that transfers the complete state sources in sequence and branches to one enables or disables the interrupts
routine. When the execution of the of the CPU into a non-destructive memory of many possible service routines. Polled
service routine is terminated, the original in few milliseconds before power ceases. interrupts are very simple . But or large Instruction RIM:
process may resume its previous operation External interrupts can be further divided number of devices, the time required to - Read interrupt Mask.
The interrupt is initiated by an external into two types: poll each device may exceed the to service - 1 byte instruction.
device and is asynchronous, meaning that 1. Maskable interrupt. the device. In such case, the faster - Can be used for the followings.
it an be initiated at any time without 2. Non-maskable interrupt mechanism called chained interrupt is a. To read interrupt mask. This instruction
reference to system clock. However , the Maskable interrupt: A maskable used. loads the accumulator with 8-bits
response to an interrupt request is directed interrupt is one which cab be enabled or indicating the current status of the
or controlled by the microprocessor. disabled by executing instructions such as Chained interrupt: This is hardware interrupts.
Interrupts are primarily issued on: EI ( enable interrupts)and DI (Disable concept of handling the multiple b. To identify the pending interrupts. Bits
~ initiation of I/O operation. interrupt). If the microprocessor’s interrupts. In this technique, the devices D4, D5, and D6 identify the pending
~ completion of I/O operation. ‘interrupt enable flip flop’ is disabled, it are connected in a chain fashion as shown interrupts .
~ occurrence of hardware or software ignores a maskable interrupt. In 8085, the in figure below for setting up the priority c. To receive serial data. Bit D7 is used to
errors 1 byte instruction EI sets the interrupt system. receive serial data.
enable flip flop and enables the interrupt
process. Similarly the 1 byte instruction 8255 programmable peripheral
Process of interrupt operation: DI resets the interrupt enable flip flop and interface (PPI):
1. The I/O unit issues an interrupt signal to disables the interrupt process.No maskable A programmable peripheral interface is a
the processor. An interrupt signal from I/O interrupts are recognized by the processor multipart device. The part may be
is the request for exchange of data with when the interrupt is disabled. Interrupts of 8085: The 8085 has five programmed in a variety of ways as
the processor. Non maskable interrupt: This type of interrupts: required by the programmer. The device is
2. The processor finishes execution of the interrupt cannot be enabled or disabled by i. TRAP very useful for interfacing peripheral
current instruction before responding to instructions. This types has higher priority ii. RST 7.5 devices. It has 3 8- bit ports, namely port
the interrupt. over the maskable interrupt. This means iii. RST 6.5 A, port B and port C. The port C has been
3. The processor testes for an interrupt, that if both the makable and non maskable iv. RST 5.5 further divide into two of 4-bit ports, and
determines that there is one, and sends an interrupts are activated at the same time, v. INTR port C upper and port C lower. Thus a
acknowledgement signal to the device that then the processor will service the non- The four interrupts TRAP, RST 7.5, total of 4 ports are available, two 8-bit
issued the interrupt. After receiving this maskable interrupt first. In 8085 TRAP is 6.5,5.5 are automatically vectored ports and two 4-bit ports. Each part can be
acknowledgement, the device retains its an example of non maskable interrupt. (transferred) to specific locations on programmed either as an i/p port or an o/p
interrupts signal. without any external hardware. They do port.
4. The processor now begins to transfer Internal interrupt: Internal interrupt not require INTA signal or an input port; PA0 – PA7 - 8 pins of port A
the control to the routine which serves the arise form illegal or erroneous use of an the necessary hardware is already PB0 – PB7 - 8 pins of port B
interrupt request from the device. This instruction or data. Cause of this implemented inside the 8085. These PC0 – PC3 - 4 pins of port Clower
routine is called ‘Interrupt service routine’ interrupt may be: register overflow, interrupts and their call locations are: PC4 – PC7 - 4 pins of port Cupper
and it resides at a specified memory attempt to divide by zero, an invalid TRAP Call location
location. For this process, the CPU needs operation code, stack overflow etc. These TRAP 0024 H
to save information needed to reassume error conditions usually occur as a result RST 7.5 003 CH
the current program at the point of of premature termination of the instruction RST 6.5 0034 H
interrupt. The minimum information execution. These are even termed as RST 5.5 002C H.
required is i) the status of the processor, exceptions. The difference between The TRAP has the highest, followed by
which contained by the processor status internal and external interrupt is RST 7.5, 6.5, 5.5
word (PSW) and ii) the location of the and INTR. Figure below shows the
schematic diagram of Operating modes of 8255:
8085 interrupts.
8255 has 3 modes of operation which are Scan section: The scan section has scan consists of 40 pins with 5-10 MHZ clock bit registers and three 16 bit registers.
selected by s/w. counter and 4 scan lines (SL0 – SL3). signal. These registers can be classified as
Mode 0 - Simple input/output These 4 scan lines can be decoded using a 8088- introduced in 1980, 8/16 bit μp with a.General purpose register
Mode 1 – Strobed input/output 4- to – 16 decoder to generate 16 lines for memory addressing capability of 1 MB, b. Special purpose register.
Mode 2 – Bidirectional port. scanning. Display section: The display consists of 5-8 MHZ clock signal. a. General purpose register: The 8085
Mode 0: In this mode of operation, a port section has eight output lines divided into 80286- introduced in 1982, 16 bit μp with has 6 general purpose registers to store 8
can be operated as a simple o/p or i/p port. two groups A0 – A3 and B0 –B3. These memory addressing capacity of 16 MB, bit data during program execution. B,C, D
Each of the four ports of 8255 can lines can be used, either as a group of consists of 68 pin with 6-12.5 MHZ clock ,E, H, L are 8 bit registers and can be used
be programmed to be either an i/p or o/p eight lines or as two groups of four, in signal. singly or 16 bit register pairs. BC, DE,HL.
port. conjunction with the scan line, for a 80386 – introduce in 1985 , 32 bit μ p When used in register pairs , the high
Mode 1: Mode 1 is strobed input/output multiplexed display. The display can be with 4 GB memory addressing capability. order byte resides in the 1st register that is
mode of operation. The port A and port B blanked by using the BD line. This section Consists of 132 pins with 22 to 33 MHZ B when BC is as register pair and low
are designed to operate in this mod e includes 16 × 8 display RAM. clock signal. order byte in second( ie c when BC is
of operation. When port A and port B are 80486- introduced in 1989, 32 bit μp with used). The register pair Hl besides it's
programmed in mode 1, six pins of port c MPU Interface section: This section 4 GB memory addressing capacity, possible use as to independent registers
are used for their control. PC0,PC1 includes eight bidirectional data lines consists of 168 pin with 26-100 MHZ functions as a data pointer. It can hold
and PC2 are used for control of port B ( DB0 –DB7), one interrupt request (IRQ) clock signal. memory addresses that are referred to in a
which can be used as input or output port. line, and 6 lines for interfacing , including Pentium:- introduced in 1993, 32 bit up number of instructions which use register
If the port A is operated as an input I/P the buffer address line (A0) . When A0 is with 4 GB of memory addressing capacity indirect addressing.
or O/P port If the port A is operated as an high, signals are interpreted as control consists of 168 pins with 100 and 150 b. Special purpose register:
input port. PC3, PC4, and PC5 are used words or status; when A0 is low, signals MHZ. Accumulator: It is a 8 bit register used in
for its control. The remaining pins of are interpreted as data. The IRQ line goes Pentium pro, Pentium II , and Pentium III, arithmetic logic load and store operations
port C, i.e PC6 and PC7 can be used as high whenever data entries are stored in was developed each with 32 bit word as well in input output instructions
either input or output. When port A is the FIFO indicating the availability of length having 150-1000 MHZ clock Flag Register: It is 8 bit register in which
operated as an output port, pins PC3, PC6 data. signal. the bits carry significant information in
and PC7 are used for its control. The pins the form of flags.
PC4 and PC5 can be used either as input 8251A programmable communication Stored Program concept: The task of S- Sing Flag
or output. Interface:.(USART) entering and altering the programs for the Z- zero flag
Mode 2: Mode 2 is strobed bidirectional The 8251A is a programmable chip ENIAC (electronic numerical integrator AC- Auxiliary carry flag
mode of operation. In this mode port A designed for synchronous and and computer) was extremely tedious. The D- Parity flag
can be programmed to operate as a asynchronous serial data communication, programming concept could be faciliated CY- Carry flag
bidirectional port. The mode 2 operation is packed in a 28-pin DIP. Figure shows the if the program could represented in a form
only for port A. When port A is block diagram of 8251A. It includes 5 suitable for storing in memory along side
programmed in mode 2, the port B can be sections: Read/write control logic, the data. Than a computer could get it's
used in either mode 1 or mode 0. For Transmitter, Receiver, Data bus buffer, instruction by reading them form the Temporary register: It is 8 bit register
mode 2 operation PC3 to PC7 are used for and Modem control. memory and a program could be set or not accessible to the programmer while
the control of port A. altered by setting the values of a portion executing the instruction. The 8085
of memory . This approach is known places the date into temporary register for
8279 (Programmable keyboard/display stored program concept. a brief period. Program counter: The
interface): 8279 is a programmable program counter acts as a pointer to
keyboard interfacing device. It has been the next instruction to be executed and
designed for the purpose of 8-bit μP . It always contains 16 bit address of the
has two sections namely keyboard section memory location of the next instruction.
and display section. The function of the The program counter is updated by the
keyboard section is to interface the processor and points to the next
keyboard which is used as i/p device for Main memory is used to store both data instruction after the processor has fetched
the μP. The purpose of the display The control logic interfaces the chip with the instruction.
the MPU. The transmitter section converts and instruction ALU is capable for
section is to drive alphanumeric displays performing Arithmetic and logical Stack pointer: The stack is an area of
or indication lights. Some important a parallel word received from MPU into read write memory in which temporary
serial bits and transmit them over the TXD operation binary data. The program
features are: simultaneous - keyboard control unit(cpu) interprets the instruction information is stored in first in last out
display operations, scanned sensor mode, line to a peripheral. The receiver section basis. The stack pointer holds the address
receives serial bits from a peripheral, in memory and causes them to be execute.
scanned. Keyboard mode, 8 – character The input/output unit and helps inputting of last byte written on to the stack.
keyboard FIFO, 2 – key lock out or N – converts them into a parallel word and Instruction register and decoder: These
transfers back to the MPU. The modern data and getting results.The memory of
key roll over with contact debouched, Von-Neumann machine consists of are not accessible to the programmer after
single 16- character display, dual 8 or 16 control is used to establish data fetching an instruction from memory the
communication through modems over thousand storage location called words of
numerical display, programmable scan 40 binary digits(bits). Both data and processor load it in the instruction register.
timing and mode programmable from telephone lines. Read/ control logic and This instruction is decoded by the decoder
registers: This section includes R/W instruction are stored in it. The storage
Cpu. locations of control unit and ALU are and the sequence of events are established
control logic , six i/p signals, and 3 buffer for the execution of instruction.
registers: data register, control register and called registers. The various registers of
8279 block diagram: this model are MBR, MAR, IR, IBR, PC, Arithmetic and logic unit: The ALU
Keyboard section: This section has eight status registers. performs the computing function. It
AC.
lines ( RL0 –RL7)that can be connected to includes the accumulator, the temporary
8 columns of a keyboard, plus two Internal Architecture of 8085: register, arithmetic and logic circuits and
additional lines shift and CNTL/STB the flag register. The temporary register is
(control/strobe).The keys are used to store hold data during an
automatically debouched and the arithmetic/ logic operation. The result is
keyboard can operate in two modes; two- stored in the accumulator and the flags are
key lockout or N-key rollover. In set or cleared according to the result of
two-key lockout mode, if two keys are operation.
pressed almost simultaneously only the Timing and control unit: This unit
first key is recognized. In the N-key CS - Chip select: when signal goes low, synchronizes all the microprocessor
rollover mode, simultaneous keys are 8251A is selected by MPU for operations with the clock. The clock is
recognized and their codes are stored in communication. C / D - control/ data: symmetrical square wave signal that
the internal buffer. It can also be set up When this signal is high , control register drives the cpu. The control circuitary and
so that no key is recognized until only one or the status register is selected. When low all the operations are driven by the clock
key remains pressed. This section also data buffer is addressed. signals.
includes 8 × 8 FIFO RAM, that store Basic concept in memory interfacing:
keyboard entries and provides IRQ The primary function of memory
(interrupt request). Signal when FIFO is interfacing is that
not empty. two microprocessor should be able to read
from and write into a given register of a
Evolution of microprocessor: memory chip. To perform this operation
4004- introduced in 1971, first 4 bit up Intel 8085 is a 8 bit general purpose the micro processor should.
having memory addressing capability of 1 microprocessor capable of addressing upto 1. Be able to select the chip
KB 64kB of memory. It is a 40 pin ic package 2. Identify the register.
- Consist of 16 pin with clock signal of fabricated on a single LSI using an NMOS 3. Enable the appropriate buffer
750 HZ technology. It's clock speed is about 3 Let us consider a RAM chip (6.6) to be
8008- introduced in 1972, 8 bit μp , 40 pin MHZ and uses a single 5v DC supply. interfaced with 8085 μP. The interfacing
8080- introduced in 1973 , 8 bit μp. The internal structure of 8085 is shown in ckt is shown below.
8085- introduce in 1976, 8 bit μp having figure. It consists of three main section.
addressing capability of 64kb,cosists of 40 1. Register array.
pin with 3-6 MHZ clock signal. 2. Arithmetic and logic unit.
8086 – introduce in 1978, 16 bit μP 3. Timing and control unit.
having addressing capability of 1 MB , Register array: The 8085 has both 8 bit
and 16 bit registers. It has 8 addressable 8
the end of each data unit . In asynchronous
transmission the data message is sent one
word at a time.
- When no datas are sent over the time it is
maintained at an idle value; a logic 1.
- Start bit is a logic 0.
- The stop bit is a logical 1.
Both the transmitter and receiver are
given separate clocking signals. It is not
essential that they both be of exactly the
same frequency. The data is sent out of the
Fig. Interfacing R/W memory transmitter synchronous with its own
clock input and the data is similarly
interfacing 2732 EPROM received and assembled at the receiver.
Four interrupts TRAP, RST 7.5, 6.5, 5.5
are automatically vectored (transferred) to
specific locations on without any external
hardware. They do not require INTA
signal or an input port; the necessary
hardware is already implemented
inside the 8085. These interrupts and their When a character is to be transmitted, the
call locations are: transmitter first sends out a low bit. This
Call locations transition is perceived by the receiver and
TRAP 0024 H it gets ready to receive the data.
RST 7.5 003C H The transmitter then sends out the
RST 6.5 0034 H word bit by bit, one after the other,
RST 5.5 002CH synchronous with its clock.
The TRAP has the highest priority, The receiver assembles the data
followed by RST 7.5,6.5, 5.5 and INTR. one by one synchronous
Figure below shows the schematic with its clock.
diagram of 8085 Interrupts. The receiver must known beforehand
the transmission ‘Baud Rate’(bits per
Method of communication seconds) for proper assembling at its end.
Parallel data transfer: When a word of n After all the bit of a character are sent,
bits is to be transmitted in parallel each bit the transmitter sends out a stop bit which
is transmitted on a separate line along with is the idle value ( logic 1) to indicate the
a common ground line with respect to end of transmission.
which the status of each line is measured.
Thus, a channel comprises of (n+1) lines

Asynchronous communication is a start-


stop type of communication and is used
where the source of data may not be
providing a steady stream of new
characters. The data thus comes to the
receiver at unevenly spaced intervals
without reference to a master clock, hence
Here, the time required to transfer one the name Asynchronous.
word is equal to the time taken to transmit Asynchronous transmission:
a bit. Parallel data transmission is Synchronous communication is used for
impractical over long distances because of transferring large amount of data at a
prohibitive cost of installing a large stretch without frequent start or stops. In
number of lines. synchronous systems to , the line is
Serial data transfer: In serial data maintained at the idle value when no data
transfer, each bit of the word is sent in is being transmitted. The transmission
succession, one at a time over a single pair begins with a block header which is a
of wires. A parallel to serial converters is predetermined pattern of bits. The receiver
used to convert the incoming parallel data identifies the pattern and gets ready to
to serial form and then the data is sent receive the characters.
out with the lest significant bit Do first The transmitter sends the data
and most significant bit D7 coming last of character by character, bit by bit. After
all. If the bit rate is retained after the sending all the characters, the transmitter
parallel to serial conversion, the time sends another pattern of bits to indicate
taken to transmit a word in serial data the end of transmission
transmission will be n times more than
the time taken in parallel data
transmission. If the word in
the above example were to sent serially,
the data on the channel will appear as in
figure below.

There are tow types of serial transfers.


They are:
1. Asynchronous serial data transfer.
2. Synchronous data transfer.
Asynchronous transfer:
In this types of transmission, the
receiving device does not need to be
synchronized with the transmitting device.
The transmitting device can send one or
more data units when it is ready to send.
Each data unit must be formatted. In other
words, each data unit must contain ‘a
start bit’ and ‘stop bit(or bits)’ indicating
the beginning and
8086 Block Diagram generator to provide ready input to the This flag can be used to check for
8086. the signal is active high. transmission errors.
INTR-Interrupt Request : This is a ZF (zero flag). If this flag is set, the result
triggered input. This is sampled during the of the operation is 0.
last clock cycles of each instruction to DF(direction flag). Setting DF causes
determine the availability of the request. If string instructions to auto-decrement
any interrupt request is pending, the (count down); that is, to process strings
processor enters the interrupt from the high address to the low address, or
acknowledge cycle. This can be internally from right to left. Clearing DF causes string
masked by resulting the interrupt enable instructions to auto-increment (count up), or
flag. This signal is active high and process strings from left to right.
internally synchronized IF ( interrupt-enable flag) Setting IF
TEST : This input is examined by a allows the MPU to recognize external
‘WAIT’ instruction. If the TEST pin goes (maskable) interrupt requests. Clearing IF
low, execution will continue, else the disables these interrupts. IF has no effect on
processor remains in an idle state. The either nonmaskable external or internally
input is synchronized internally during generated interrupts.
each clock cycle on leading edge of clock. TF (trap flag) . Setting TF puts the
CLK- Clock Input : The clock input processor into single-step mode for
provides the basic timing for processor debugging. In this mode the MPU
operation and bus control activity. Its an automatically generates an internal interrupt
asymmetric square wave with 33% duty after each instruction, allowing a program
cycle. to be inspected as it executes instruction by
instruction.

Addressing Modes
8237A controller pin diagram
The different ways that a processor can
access data are referred to as its
addressing modes. It is the way by which
the location of the operand is determined.
How an operand is addressed in a program
depends on the types and location of the
data.
There are three general types of addressing
modes:
1.Register Addressing: In register
addressing the operand is placed in one of
the 16-bit or 8-bit general purpose register.
Eg. areMOV AX,CX ADD AL,BL
2.Indirect addressing mode: In indirect
pin details of 8086 microprocessor addressing mode the operand is specified in
 The Microprocessor 8086 is a 16-bit the instruction itself. For eg.
CPU available in different clock rates and MOV AL,35H MOV BX,031H
packaged in a 40 pin CERDIP or plastic 3.Direct addressing mode: In direct
package. addressing mode the operand’s off set is
 The 8086 operates in single processor given in the instruction as an 8-bit or 16-bit
or multiprocessor configuration to achieve displacement elements. For eg. ADD
high performance. The pins serve a AL[0301] ADD[0301],AX.
particular function in minimum mode 4.Register indirect addressing: the
(single processor mode ) and other Flag Register :A f l ag is a flip-flop which opernad’s off set is placed in any one of the
function in maximum mode configuration indicates some condition produced by the registers BX,BP,SI or DI as specified in the
(multiprocessor mode ). execution of an instruction or controls instruction. For eg. MOV AX,[BX] ADD
 The 8086 signals can be categorised in certain operations of the EU. The Flag AL,[SI]
three groups Register is a special register associated with 5.Based addressing : the operand off set is
1.The first are the signal having common the ALU. A 16-bit flag register in the EU the sum of an 8-bit or 16-bit displacement
functions in minimum as well as contains nine active flags. Fig.5 shows the and the content of basic register BX or BP.
maximum mode. location of the nine flags in the flag register. BX id used as a base register for data
2.The second are the signals which have segment,and BP is used as base register for
special functions for minimum mode stack segment. Eg MOV AL,[BX+05]
3.The third are the signals having special 6.Indexed addressing mode : the operand
functions for maximum mode. off set is the sum of the content of an index
 The following signal descriptions are register SI or DI.and 8-bit or 16-bit
common for both modes. displacement . For eg:- MOV AX,[SI+05]
 AD15-AD0 : These are the time
multiplexed memory I/O address and data
lines.
#.Address remains on the lines during T1
state, while the data is available on the
data bus during T2, T3, Tw and T4. These
lines are active high and float to a tristate
during interrupt acknowledge and local
bus hold acknowledge cycles Six flags are status flags- AF, CF, OF,
#.A19/S6,A18/S5,A17/S4,A16/S3 :
SF, PF and ZF. The remaining three
These are the time multiplexed address
flags are control flags -DF,IF, and TF
and status line.
AF (auxiliary flag). If this flag is set, there
BHE/S7 : The bus high enable is used to
has been a carry out or borrow of the 4
indicate the transfer of data over the
least significant bits. This flag is used
higher order ( D15-D8 ) data bus as shown
during decimal arithmetic instructions.
in table. It goes low for the data transfer
CF(carry flag). If this flag is set, there has
over D15-D8 and is used to derive chip
been a carry out or overflow of the most
selects of odd address memory bank or
significant bit. It is used by instructions that
peripherals.
add and subtract multi byte numbers.
RD – Read : This signal on low indicates
OF (overflow flag). If this flag is set, an
the peripheral that the processor is
arithmetic overflow has occurred; that is , a
performing memory or I/O read operation.
significant digit has been lost because the
RD is active low and shows the state for
size of the result exceeded the capacity of
T2, T3, Tw of any read cycle. The signal
its destination location.
remains tristated during the hold
SF (sign flag). Since negative binary
acknowledge.
numbers are represented in the 8086/8088
READY : This is the acknowledgement
in standard 2s complement notation. SF
from the slow device or memory that they
indicates the sign of the result ( 0 = positive,
have completed the data transfer. The
1 = negative).
signal made available by the devices is
PF (party flag). If this flag is set, the result
synchronized by the 8284A clock
has even parity, an even number of 1s.