Tutorial VHDL Ams

VHDL-AMS Introduction
Dolphin Integration
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www.dolphin-integration.com
Overview
VHDL-AMS History
From Event Driven to Continuous Behavior
Extended Semantic
Terminals, Natures, Quantities...
Tolerance Definitions
Handling of Discontinuities
Solvability
Initial Conditions
Model Execution
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Introduction to VHDL-AMS
History
VHDL (Very High Speed Integrated Circuit Hardware
Description Language) is a powerful language for the
description of event driven circuits
First standardization of VHDL in 1987 (IEEE 1076),
second standardization in 1993 (IEEE 1076-1993)
IEEE 1076.1-1999 is a standard extension of IEEE

1076 to support the description and the simulation of
analog and mixed-signal circuits and systems
IEEE 1076.1 together with IEEE 1076 is informally
known as VHDL-AMS (IEEE 1076.1-1999)
VHDL-AMS is a strict superset of IEEE 1076-1993
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Coverage
v v
t t
value discreet, time discreet value continuous, time discreet
v v
t t
value discreet, time continuous value continuous, time continuous
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1 1.
VHDL Model
Event Driven Behavior
LIBRARY IEEE;
2. USE IEEE.std_logic_1164.all;
3.
4. ENTITY andg IS AND

5. GENERIC (tpd_hl : TIME := 1 NS;
6. tpd_lh : TIME := 1 NS);
7. PORT (in1, in2 : STD_ULOGIC; in1
8. out1 : OUT STD_ULOGIC); out1
9. END andg; &
10.
11. ARCHITECTURE only OF andg IS in2

12. BEGIN
13. p1: PROCESS (in1, in2)
14. VARIABLE val : STD_LOGIC;
15. BEGIN
16. val := in1 AND in2; val = in1 & in2
17. CASE val IS
18. WHEN '0' =>
19. out1 <= '0' AFTER tpd_hl;
20. WHEN '1' =>
21. out1 <= '1' AFTER tpd_lh;
22. WHEN OTHERS =>
23. out1 <= val;
24. END CASE;
25. END PROCESS;
26. END only;
VHDL-Syntax
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1 VHDL Model
Event Driven Behavior
SMASH 5.3.3p1 - Transient c:\Users\Lars\Projects\Patent\2004ME~1\Dolphin\TUTORI~2\1\testb.nsx - Thu Nov 25 14:49:32 2004
10n 20n 30n 40n 50n 60n 70n 80n 90n

TESTBENCH.S1 VHDL'stdl
TESTBENCH.S2 VHDL'stdl
TESTBENCH.O VHDL'stdl
transition time transition time

from low to high from high to low
(tpd_lh) (tpd_hl)
The simulator calculates only

new values after events occur
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2 VHDL-AMS Model
Continuous Behavior
<smash_install_dir>\lib\vhdl\packages\electrical_systems_pkg.vhd
<smash_install_dir>\lib\vhdl\packages\fundamental_constants_pkg.vhd
1. LIBRARY IEEE;
USE IEEE.ELECTRICAL_SYSTEMS.all;
2.
USE IEEE.FUNDAMENTAL_CONSTANTS.all;
elec_p
3.
Parameter
4.
5. ENTITY Capacitor IS i
6. GENERIC (C := 1.0 : capacitance); v
7. -- GENERIC (A, d, EPS_R := 1.0 : REAL);
8. PORT (TERMINAL elec_p, elec_n: electrical);
9. END ENTITY Capacitor; Terminal elec_n
10.
connections
11. ARCHITECTURE simple OF Capacitor IS
12. QUANTITY v ACROSS i THROUGH elec_p TO elec_n;
13. -- CONSTANT C: capacitance := PHYS_EPS0 * EPS_R * A/d; C = ε0εr * A/d
14.
15. BEGIN
16. i == C * v'DOT; i = C * d/dt (v)
17. -- v == i'INTEG / C;
VHDL Syntax
18. END ARCHITECTURE simple; v = I(i)dt / C
VHDL-AMS Syntax
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2 1.
2.
>>> VHDL
LIBRARY IEEE;
Extended Model
Model Instantiation
net1
3. USE IEEE.ELECTRICAL_SYSTEMS.all;
4. USE work.all;
5.
Ω
R1=2kΩ
6. ENTITY testbench IS
∼
7. END testbench; V=5V
8. f=100kHz
9. ARCHITECTURE simple OF testbench IS net2
10. TERMINAL net1,net2 : electrical;
11.
C1=300pF
12. BEGIN
13. vsin1: ENTITY vsin(simple)
14. GENERIC MAP (ampl => 5.0,
15. freq => 100.0e3, Terminal
16. phi0 => 0.0) connections
17. PORT MAP (elec_p => net1, elec_n => ground);
18. R1: ENTITY resistor(simple)
19. GENERIC MAP (R => 2.0e3) Parameter
20. PORT MAP (elec_p => net1, elec_n => net2);
21. C1: ENTITY capacitor(simple)
22. GENERIC MAP (C => 300.0e-12)
23. PORT MAP (elec_p => net2, elec_n => ground); VHDL-Syntax
24. END simple; VHDL-AMS-Syntax
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2 Extended Model
Model Instantiation
SMASH 5.3.3p1 - Transient c:\Users\Lars\Projects\Patent\2004ME~1\Dolphin\TUTORI~2\2\testbench.nsx - Thu Nov 25 15:39:43 2004
1u 2u 3u 4u 5u 6u 7u 8u 9u
TB.VSIN1.V
TB.R1.V
TB.C1.V 5V
4V
3V
2V
1V
0V
-1V
-2V
-3V
-4V
The simulator has to calculate -5V
new values time continuously
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VHDL-AMS provides a new mechanism for analog
behavior specification and hybrid system modeling
o Continuous models are based on differential
algebraic equations (DAEs)

o DAEs solved by a dedicated simulation kernel: the
analog solver
o VHDL-AMS supports the handling of initial
conditions, piecewise-defined behavior, and

discontinuities
Optimization of the set of DAEs being solved and
how the analog solver computes its solution are
outside the scope of VHDL-AMS
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Quantities I
Quantities are the unknowns in the set of DAEs
Port Quantity
1. ENTITY example IS
2. PORT (
3. QUANTITY interface_q: REAL;
4. TERMINAL elec_p, elec_n: ELECTRICAL);
5. END ENTITY example;
6. Branch Quantities
7. ARCHITECTURE simple OF example IS
8. TERMINAL net1, net2, net3: ELECTRICAL;
9. QUANTITY v1, v2 ACROSS i1, i2, i3 THROUGH elec_p TO elec_n;
10. QUANTITY free_q: REAL; Free Quantity
11. QUANTITY v_intern ACROSS i_intern THROUGH net1 TO net2;
12. QUANTITY v ACROSS i THROUGH net3;
13. BEGIN
14. ...
15. END ARCHITECTURE simple;
16.
VHDL-Syntax
VHDL-AMS-Syntax
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Extended Semantics
Extended structural semantics
o Conservative semantics to model physical systems (e.g.
Kirchhoff’s law for electrical circuits)
o Non-conservative semantics for abstract models (signal-flow
descriptions)
o Mixed-signal interfaces
Mixed-signal semantics
o Unified model of time for a consistent synchronization of
mixed event-driven/continuous behavior
o Mixed-signal initialization and simulation cycle
o Mixed-signal descriptions of behavior
Frequency domain support
o Small-signal frequency and noise modeling and simulation
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3 Resonator
Small-Signal Domain
net1
Resonator
o Resonance frequency fr L1
o Quality factor Q
o Bandwidth B
net2
1 R fr 1 L
fr = B = Q = = C1
2π LC 2πL B R C
net3
1.
2.
ARCHITECTURE simple OF VSin IS
QUANTITY v ACROSS i THROUGH elec_p TO elec_n;
∼ Vsin1
3. QUANTITY Vac: voltage SPECTRUM 1.0, 0.0; R1

4.
5. BEGIN Spectrum Quantity

6.
7. v == ampl * sin(MATH_2_PI * freq * NOW + phi0) + Vac;

8.

VHDL-Syntax
VHDL-AMS-Syntax
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3 400u 800u
Resonator
Transient vs. Small-Signal
1.2m 1.6m 2m 2.4m 2.8m 3.2m 3.6m 4m 4.4m 4.8m

transient
TB.R1.V
TB.VSIN1.V 5V
4V
simulation
3V
2V
1V
0V
-1V
-2V
-3V
-4V
SMASH 5.3.3p1 - Small Signal c:\Users\Lars\Projects\Patent\2004ME~1\Dolphin\TUTORI~2\4\testbench.nsx - Thu Nov 25 15:10:10 2004
-5V
TB.C1.V 100 200 300 400 500 1K 2K 3K 7V4K 5K 6K 7K 10K 20K 30K 40K 50K
TB.L1.V DB(TB.C1.V) 6V 20dB
DB(TB.L1.V) 5V 10dB
4V
0dB
3V
2V -10dB
1V -20dB
0V
-30dB
-1V
-2V -40dB
-3V -50dB
Amplitude in decibel
-4V
-5V
-60dB
-6V -70dB
-80dB
P(TB.C1.V) 200Deg
P(TB.L1.V)
150Deg
Phase 100Deg
50Deg
0Deg
-50Deg
small signal -100Deg
simulation -150Deg
-200Deg
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Terminals and Natures
Terminal
o Serves as Interface or as local object
o Belongs to a nature
Nature
o Represents a physical discipline or energy domain
o Has two aspects related to physical effects
- Across: potentional like effects (e.g. voltage, velocity,
temperature, etc.)
- Through: flow like effects (e.g. current, force, heat flow rate,
etc.)
o Can be composite: array or record
o Up to now: No predefined natures in VHDL-AMS
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Nature Def. in Packages
1. SUBTYPE voltage IS real TOLERANCE "default_voltage";

2. SUBTYPE current IS real TOLERANCE "default_current";
3. NATURE electrical IS
4. voltage ACROSS
Nature definition
5. current THROUGH
6. electrical_ref REFERENCE;
7. NATURE electrical_vector IS Composite nature
8. ARRAY (NATURAL RANGE <>) OF electrical; definition
9. NATURE bus IS RECORD (array, record)
10. strobe: electrical;
11. data : electrical_vector(0 to 7);
12. END RECORD;
13. SUBNATURE high_voltage IS
Subnature
definition
14. electrical TOLERANCE
15. "high_voltage" ACROSS
16. "high_current" THROUGH;
17. ALIAS ground IS electrical_ref;
VHDL-Syntax
VHDL-AMS-Syntax
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Quantities II
Quantity
Expresses across values between or through values at
terminals as well as the notion of tolerance
Represents a continuous-time waveform
Unknown in the set of DAEs implied by the text of the model
Implicit Quantities
Q’Dot, Q’Integ, Q’Slew, Q’Delayed, S’Ramp, S’Slew...
Branch Quantities
Declared between two terminals
Gets its type from the nature of its plus and minus terminals
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4 Pulse Voltage Source
Implicit Quantities
Branch Declared between
Quantities two terminals Gets its type from the nature
of its plus and minus
terminals
1. ARCHITECTURE simple OF Vpulse IS (see Packages)
3. SIGNAL pulse : voltage:= low;
4. BEGIN
5. v == pulse'SLEW(rising_slope, falling_slope);
6. -- v == pulse'RAMP(rising_time, falling_time);
7.
8. pulse_proc : PROCESS BEGIN Implicit quantities

9. pulse <= low; resulting from the
10. WAIT FOR delay; attributes ‘SLEW and
11. LOOP
‘RAMP.
See example 2 for
12. pulse <= high;
implicit quantities
13. WAIT FOR (rise_time + high_width); resulting from ‘DOT and
14. pulse <= low; ‘INTEG
15. WAIT FOR (fall_time + low_width);
16. END LOOP;
17. END PROCESS;
18. VHDL-Syntax
19. END ARCHITECTURE simple; VHDL-AMS-Syntax
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4 Pulse Voltage Source
Implicit Quantities
10u 20u 30u 40u 50u 60u 70u 80u 90u

TB.VPULSE1.PULSE -5 5 -5 5 -5 5 -5 5 VHDL'real
TB.VPULSE1.PULSE
4
-2
-4
TB.VPULSE1.V
TB.R1.V 4V
TB.R2.V
2V
0V
-2V
-4V
Smooth ramp effect

resulting from ‘SLEW or
‘RAMP attribute
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Tolerances
Tolerance definitions
o Each quantity and each simultaneous statement belongs to
a tolerance group, indicated by a string expression
o Tolerances are used to specify how good the simulation
must be
o The language does not define the way how tolerance groups
should be handled by the simulator ⇒ Tool dependent
implementations
Supporting tolerances results in a faster and more
accurate simulation, especially if quantity values of
large different dimensions exist
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5 Tolerance Definitions
in Packages and Models
1. SUBTYPE voltage IS real TOLERANCE "Voltage";
2. SUBTYPE current IS real TOLERANCE "Current";
3. NATURE electrical IS
4. voltage ACROSS Tolerance definitions in
5. current THROUGH packages
6. electrical_ref REFERENCE;
Setting tolerances in the

capacitor.vhd simulator
1. ENTITY Capacitor IS
2. GENERIC (C: capacitance);
3. PORT (TERMINAL elec_p, elec_n: ELECTRICAL);
4. END ENTITY Capacitor;
5. ARCHITECTURE simple OF Capacitor IS

7. BEGIN Tolerance definitions in
8. i == C * v'DOT TOLERANCE "MyTol"; models
9. END ARCHITECTURE simple; VHDL-Syntax
VHDL-AMS-Syntax
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Handling Discontinuities
Break statement
o Announces a discontinuity in the solution of the DAEs
o Analog solver must re-initialize for next continuous interval
o Initial conditions may be specified on quantities
o Break on event on a signal or when some condition
becomes true
o A VHDL-AMS model that causes a discontinuity on a
quantity at some time T and does not execute a break
statement at T is erroneous!
- Except for discontinuities caused by S’Ramp, S’Slew and
Q’Slew
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6 Operational Amplifier
ENTITY OpAmp IS
vdd=15V
+
1.
net1
2. GENERIC (vdd : voltage := 15.0;
net2
vss : voltage := -15.0;
−
3.
4. gain : REAL := REAL'HIGH);

5.
6.
PORT (TERMINAL in_p, in_n: ELECTRICAL;
TERMINAL output: ELECTRICAL);
∼ V=20mV
f=100kHz
vss=-15V Ω
R1=1kΩ
7. END ENTITY OpAmp;

8.
9. ARCHITECTURE simple OF OpAmp IS

10. QUANTITY vin ACROSS in_p TO in_n;
11. QUANTITY vout ACROSS iout THROUGH output;
12. BEGIN
13. IF vin'ABOVE(vdd/gain) USE
Example: Clipping
14. vout == vdd; Use the ‘ABOVE attribute
15. ELSIF NOT vin'ABOVE(vss/gain) USE with a connecting
16. vout == vss; BREAK statement
17. ELSE instead of discontinuous
18. vout == vin*gain; functions to tell the
19. END USE; simulator about
20.
discontinuities!
21. BREAK ON vin'ABOVE(vdd/gain), vin'ABOVE(vss/gain);
VHDL-Syntax
VHDL-AMS-Syntax
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6 Operational Amplifier
BREAK announces a discontinuity
which results in a re-initialization of
without BREAK the analog solver at the exact time
where the BREAK occurred
SMASH 5.3.3p1 - Transient c:\Users\Lars\Projects\Patent\2004ME~1\Dolphin\TUTORI~2\6\testbench.nsx - Wed Nov 24 16:46:01 2004
10.9u 10.95u 11u 11.05u 11.1u 11.15u 11.2u 11.25u 11.3u 11.35u 11.4u 11.45u 11.5u 11.55u 11.6u 11.65u 11.7u 11.75u 11.8u
TB.OPAMP1.VOUT 15.4V
15.2V
15V
14.8V
14.6V
14.4V
14.2V
14V
with BREAK 13.8V

13.6V
13.4V
13.2V
13V
12.8V
12.6V
12.4V
12.2V
12V
11.8V
11.6V
11.4V
11.2V
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Solvability
A necessary condition for solvability is that there be
as many equations as unknowns in the model
In a VHDL-AMS design entity, the number of
equations must be equal to the number of
o through quantities plus
o free quantities plus
o interface quantities with mode out
Each (scalar) simultaneous statement creates one

equation
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DC Source
7 1. LIBRARY IEEE;
Solvability
VHDL-Syntax
3. ENTITY vdc IS voltage source VHDL-AMS-Syntax
4. GENERIC (ampl: voltage := 5.0);
6. END ENTITY vdc;
7. ARCHITECTURE simple OF vdc IS
9. BEGIN
10. v == ampl;
You need to define this additionally
THROUGH quantity even this is not
11. END ARCHITECTURE simple; explicit used in the model!
1. LIBRARY IEEE;
3. ENTITY idc IS current source
4. GENERIC (ampl: current := 1.0e-3);
6. END ENTITY idc;
7. ARCHITECTURE simple OF idc IS
8. QUANTITY i THROUGH elec_p TO elec_n;
9. BEGIN Here, the depended ACROSS quantity
10. i == -ampl; is not necessary but sometimes useful
11. END ARCHITECTURE simple; for display proposes.
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DC Source
7 Solvability
SMASH 5.3.3p1 - Transient C:\Users\Lars\Projects\patent\2004 Meeting\Dolphin\Tutorial_VHDL-AMS\7\testb_idc.nsx - Fri Nov 26 10:22:57 2004
10u 20u 30u 40u 50u 60u 70u 80u 90u

TB.DCSOURCE.V 5.2V
TB.R1.V
TB.R2.V 5V
4.8V
4.6V
4.4V
The internal voltage of the current source is
only visible, if a quantity for the voltage 4.2V
between elec_p and elec_n is defined 4V
3.8V
3.6V
3.4V
3.2V
3V
2.8V
2.6V
2.4V
2.2V
2V
1.8V
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Initial Conditions
An initial condition specifies the value of a quantity at the
beginning of a continuous interval
o Beginning of a time domain simulation
o After a discontinuity
Initial conditions can be specified with the break statement
Initial conditions replace implicit equations. An initial condition
for Q replaces:
o The equation Q’Dot == 0 while finding the quiescent point
o The equation Q == Q(T-) when reinitializing after a discontinuity
If an initial condition must be specified for a quantity Q

whose derivative Q’Dot does not appear in the model, the
user must specify which implicit equation to replace
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Pre-loaded Capacitor
8 1.
Initial Conditions
ENTITY Capacitor IS
2. GENERIC (C: capacitance);
4. END ENTITY Capacitor;
5. ARCHITECTURE ic_break OF Capacitor IS

7. BEGIN
Initial condition specified by a
8. BREAK v => 10.0;
BREAK statement
9. i == C * v'DOT;
10. END ARCHITECTURE ic_break;
11. ARCHITECTURE ic_domain OF Capacitor IS

13. BEGIN
14. IF domain = quiescent_domain USE
15. v == 10.0; Initial condition specified by
16. ELSE the evaluation of the predefined
17. i == C * v'DOT; signal DOMAIN
18. END USE;
19. END ARCHITECTURE ic_domain; VHDL-Syntax
VHDL-AMS-Syntax
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Pre-loaded Capacitor
8 Initial Conditions
SMASH 5.3.3p1 - Transient c:\Users\Lars\Projects\Patent\2004ME~1\Dolphin\TUTORI~2\8\testbench.nsx - Fri Nov 26 10:54:37 2004
1u 2u 3u 4u 5u 6u 7u 8u 9u
TB.R1.V
10V
Preloaded capacitor:
9V
Initial condition: v = 10V
8V
7V
6V
5V
4V
3V
2V
1V
0V
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Model execution
A VHDL model is the result of the elaboration of the
design hierarchy
o Digital part => set of processes + digital simulation kernel
o Analog part => set of equations + analog solver
Two phases
o Initialization: to compute the quiescent state of the model
o Simulation: time domain, small-signal frequency, or noise
Reduces to the VHDL 1076 initialization and
simulation cycle if the model does not include any
quantities
Only the analog solver is executed after initialization
if the model does not include any signals
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Summary
VHDL 1076.1 extends VHDL 1076 to the continuous
domain
No fundamental changes to VHDL 1076
Adds support for continuous and mixed continuous/discrete
behavior
VHDL 1076.1 is equally applicable to electrical and
non-electrical domains
Mixed discipline
Control systems
Two standards
VHDL 1076 for digital (event-driven) applications
VHDL 1076.1 for digital and mixed-signal applications
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This introduction to VHDL-AMS gave an

overview of the languages capabilities
A much deeper insight with many practical
examples gives our two-day training for
VHDL-AMS
Extended by an one-day training dedicated
to modeling mechanics in VHDL-AMS
For more information or suggestions, please
contact mems@dolphin-integration.com
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33

Tutorial VHDL Ams

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VHDL-AMS Introduction

IEEE 1076.1-1999 is a standard extension of IEEE

4. ENTITY andg IS AND

11. ARCHITECTURE only OF andg IS in2

10n 20n 30n 40n 50n 60n 70n 80n 90n

transition time transition time

The simulator calculates only

The simulator has to calculate -5V

new values time continuously

algebraic equations (DAEs)

conditions, piecewise-defined behavior, and

3. QUANTITY Vac: voltage SPECTRUM 1.0, 0.0; R1

5. BEGIN Spectrum Quantity

7. v == ampl * sin(MATH_2_PI * freq * NOW + phi0) + Vac;

9. END ARCHITECTURE simple;

1.2m 1.6m 2m 2.4m 2.8m 3.2m 3.6m 4m 4.4m 4.8m

small signal -100Deg

1. SUBTYPE voltage IS real TOLERANCE "default_voltage";

8. pulse_proc : PROCESS BEGIN Implicit quantities

10u 20u 30u 40u 50u 60u 70u 80u 90u

Smooth ramp effect

Setting tolerances in the

5. ARCHITECTURE simple OF Capacitor IS

4. gain : REAL := REAL'HIGH);

7. END ENTITY OpAmp;

9. ARCHITECTURE simple OF OpAmp IS

with BREAK 13.8V

o free quantities plus

o interface quantities with mode out

Each (scalar) simultaneous statement creates one

10u 20u 30u 40u 50u 60u 70u 80u 90u

between elec_p and elec_n is defined 4V

If an initial condition must be specified for a quantity Q

5. ARCHITECTURE ic_break OF Capacitor IS

11. ARCHITECTURE ic_domain OF Capacitor IS

This introduction to VHDL-AMS gave an

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