Fpga To PCB Training Module

FPGA to PCB
Training Module
Document Version 1.2, February 2008
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Module 3
Altium Designer Training FPGA to PCB
FPGA to PCB Training Module
1. From FPGA project to PCB project...................................................................... 32
1.1 Understanding the document stack............................................................. 32
1.2 Using the FPGA to PCB project wizard ....................................................... 34
1.3 Choosing the FPGA configuration............................................................... 34
1.4 Initial FPGA pin assignments...................................................................... 35
1.5 Choosing the target PCB project................................................................. 37
1.6 Configuring the FPGA component schematic sheet .................................... 37
1.7 Configuring the sheet symbol schematic sheet ........................................... 38
1.8 Exercise 1 – Running the FPGA to PCB project wizard............................... 39
1.9 Modifying the auto generated sheet .......................................................... 311
1.10 A word about special function FPGA pins ................................................. 311
1.11 Recreating the autogenerated sheet ......................................................... 312
2. Maintaining project synchronization ................................................................. 313
2.1 The FPGA workspace map....................................................................... 313
2.2 The synchronize dialog............................................................................. 314
2.3 Synchronizing matched signals................................................................. 316
2.4 Synchronizing unmatched signals............................................................. 317
3. Configuring FPGA I/O ......................................................................................... 320
3.1 Configuring I/O standards......................................................................... 320
3.2 Exercise 2 – Using the FPGA signal manager........................................... 321
4. Manually linking FPGA and PCB projects ......................................................... 323
4.1 Supported devices.................................................................................... 324
4.2 Creating the link ....................................................................................... 324
4.3 Linking an auto generated sheet to an existing PCB project ...................... 327
4.4 Exercise 3 – Manually linking a PCB and FPGA project ............................ 327
5. Pin swapping ...................................................................................................... 328
5.1 Pin swapping in the PCB document .......................................................... 328
5.2 Pin swapping in the FPGA project............................................................. 335
5.3 Pin swapping in both PCB and FPGA projects .......................................... 336
5.4 Exercise 4 – Pin swapping........................................................................ 336
6. Commissioning the design ................................................................................ 338
6.1 Exercise 5 – Migration stage 1.................................................................. 338
6.2 Exercise 6 – Migration stage 2.................................................................. 339
6.3 Exercise 7 – Calibration............................................................................ 339
6.4 Exercise 8 – Bootstrapping the FPGA....................................................... 340
6.5 Exercise 9 – Reverting to test mode ......................................................... 341
7. Review................................................................................................................. 342
i
Altium Designer Training Module FPGA to PCB
1. From FPGA project to PCB project
At some point in the life of all designs there comes a point where they must move from the laboratory
prototype to production. If a design has been successfully running on the Desktop NanoBoard, the
process of migrating from an FPGA based project to a PCB based project containing the FPGA
project is simplified through the use of the FPGA to PCB Project Wizard. This method
automatically links the two projects and maximizes synchronization functionality between them.
Project synchronization is important as it ensures that design changes made to either the PCB
document or FPGA project are propagated in a controlled fashion.
Over the remainder of the course we will look at moving a design from the test environment, to the
target PCB. To do this we will use a design that has already been completed for us, a Digital Spirit
Level. The FPGA portion of this design includes a softcore TSK51 processor which takes as its input
the output of an accelerometer and outputs a small bubble on an LCD mimicking a traditional spirit
level.
1.1 Understanding the document stack
Figure 1. Visualization of how the various project documents are stacked
Synchronization between PCB and FPGA projects is carried out and maintained by establishing a
link between the toplevel ports in the FPGA project – specified in the relevant constraint file – and
the corresponding pins on the FPGA component schematic. Linking is achieved using the signal
name. The name given to the port in the FPGA project must be the same as the net label assigned
to the corresponding pin on the schematic component in the PCB project. Figure 1 provides a
visualization of how the various documents in an FPGA/PCB project stack are linked together.
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FPGA_Top.SchDoc FPGA project
The top level FPGA schematic document
must contain ports at the point where
signals are connected to physical pins on
the FPGA device. The name of the ports is
important as they will be used in the
constraints file.
FPGA.Constraint FPGA project
The Constraint file defines the physical pin
number that ports defined in the top level
FPGA schematic will be connected to. This
is referred to as a port name to FPGA pin
number mapping. Port names declared in
the constraint file must match those
included in the top level FPGA schematic
document.
FPGA_Auto.SchDoc PCB project
The autogenerated schematic sheet is
created from information contained in the
FPGA constraint file. Essentially the
autosheet is a schematic representation of
the port to pin mappings made by the
constraint file. Port to pin connectivity on
the autosheet is accomplished through the
use of net labels – i.e. a net label is
attached to wires connected to the ports on
the sheet and a corresponding net label is
also attached to the device pin.
FPGA_Manual.SchDoc PCB project
An optional ‘manual’ sheet is generated as
part of the FPGA to PCB project wizard.
This manual sheet contains a sheet symbol
of the autosheet – the ports on the
autosheet are connected to corresponding
ports on the sheet symbol. Connecting to
this sheet symbol rather than directly to the
FPGA symbol introduces an important
abstraction layer. This layer facilitates easy
(automated) updates to the project if the
device or pin allocations should change as
the project develops.
TargetPCB.PCBDoc PCB project
The FPGA depicted in the autosheet and
abstracted on the ‘manual’ sheet will
eventuate into a physical device on the final
PCB. The physical pins of this device will
be connected to ports as described in the
autosheet.
Figure 2. The role of the various documents in the project stack
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1.2 Using the FPGA to PCB project wizard
With a schematic document in the FPGA project open as the active view in the main design window,
simply choose the Tools » FPGA To PCB Project Wizard entry from the menu. The wizard will
appear, as shown in Figure :
Figure 3. The FPGA To PCB project wizard.
1.3 Choosing the FPGA configuration
The second page of the wizard allows you to choose the configuration that will be used for targeting
the FPGA design to the PCB. The configuration uses a constraint file that defines the FPGA device
to be used and its associated pin mappings.
The configuration can either be an existing one that you have already defined as part of the FPGA
project, or a new one, generated by the wizard. In the case of the latter, the wizard will generate a
configuration and add to it a new constraint file. These will have default names (PCB
Configuration and PCB Constraints.Constraint respectively) and the constraint file will be
stored in the same location as the FPGA project file (*.PrjFPG), unless otherwise specified.
Figure 4. Wizardbased configuration generation.
The constraint file that is added to the configuration will contain a target device definition for the
FPGA project, according to the device you select in the Selected Device field. You can browse for a
device by clicking the … button, to the right of the field. This will open the Choose Physical Device
dialog, from where you can peruse from a number of devices available across a spectrum of FPGA
vendordevice families.
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Figure 5. Browsing for the required FPGA device.
1.4 Initial FPGA pin assignments
The second page of the FPGA to PCB Project wizard gives you the choice of what to do with
unconstrained ports – i.e. ports that have not been tied to a specific pin on the target device. The
decision as to how these pins are assigned is somewhat arbitrary and so there are a number of ways
of doing this:
1.4.1 Importing pin file from vendor place and route tools
Clearly for this option to be available the design must have previously been built for the current
device and a constraint file and configuration must already exist. For totally new designs this is the
preferred design path. It ensures that the vendor tools are given the most opportunity to optimize the
design without being unduly constrained and it ensures that the selected device is capable of
supporting the design. In this case, the pin assignments should be made prior to running the FPGA
to PCB project wizard. With a constraint file open in the main window, select Design » Import Pin
File from the menu to import the vendor pin file. The following dialog box will appear:
Figure 6. Selecting constraints to be imported from the vendor tools
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1.4.2 Assigning pins during the FPGA to PCB wizard
Probably the quickest and simplest way to allocate pins is whilst executing the FPGA to PCB project
wizard. Select the Assign Unconstrained Ports on the second page of the wizard. As the wizard
executes it will automatically allocate pin numbers to unallocated ports updating the constraint file
and auto generated sheet as it goes.
Figure 7. Assigning unconstrained ports as part of the FPGA to PCB project wizard
1.4.3 Assigning unconstrained signals from the FPGA signal manager
It is also possible to allocate unconstrained signals by selecting the Assign Unconstrained Signals
button in the FPGA Signal Manager dialog (Figure 8).
Figure 8. Using the FPGA signal manager to assign unconstrained signals
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Performing pin assignments via this method is probably less advisable as it does not give the user
the choice which constraint file (project or target) records the pin allocations. Furthermore, an
additional step is required after this one to resynchronize the net labels in the autogenerated sheet.
1.4.4 Assigning signals manually in the auto generated sheet
This is the most laborious method and generally not advisable. Using this method requires the
designer to manually enter the net names for all ports onto the autogenerated sheet. A second
synchronization step is also required to propagate the pin assignments into the constraints file.
1.5 Choosing the target PCB project
After choosing the FPGA configuration, the actual target PCB project must now be defined. Simply
accept the Wizard's generation of a new project (PCB Project1.PrjPCB), or browse to and select
an existing project. In the case of a new PCB project, the file will be stored in the same location as
the FPGA project.
1.6 Configuring the FPGA component schematic sheet
Whether the PCB project already exists or is being newly created, the relationship between the
FPGA project and its corresponding component in the PCB project has to be managed in some way.
This is achieved using a dedicated, autogenerated schematic sheet, referred to as the 'Main Sheet'
in the Wizard.
Figure 2. The autogenerated FPGA component schematic sheet.
This schematic sheet will be created with the component symbol placed for the FPGA device
targeted in the constraint file. The Wizard allows you to determine where and by what name, the
schematic is created. By default, the schematic will be named using the chosen designator for the
FPGA component (e.g. FPGA_U1_Auto.SchDoc) and will be stored in the same location as the
FPGA project. Each used pin on the component symbol is linked to a port entry in the constraint file
by signal (net label/port) name. The names for nets in the PCB project are therefore required to be
the same as those in the FPGA project. Once linked, any changes made to the source documents of
either PCB or FPGA project can be passed on, ensuring that the two projects remain synchronized.
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1.6.1 Configuring unallocated I/O
The Wizard also allows you to determine how any unused I/O pins on the component are handled.
You have the ability to control the treatment of various categories of pin types individually – Input
only pins, VREF pins, Special Function pins and all other unused pins.
For each category, the pins can be handled in one of the following ways:
Tie to single port Tie all unused pins in the category to a single port (which will also
appear on the parent sheet symbol (if applicable) on the sheet above)
Tie to individual ports Tie all unused pins in the category to their own, individual ports
(which will also appear on the parent sheet symbol (if applicable) on
the sheet above)
Tie to ports by IO Tie all unused VREF pins to a port on a bank by bank basis (which
bank (VREF only) will also appear on the parent sheet symbol (if applicable) on the
sheet above).
Add No ERC directive Add a No ERC directive to an unused pin, so that it is not included as
part of error checking when the design is compiled
Ignore Do nothing with an unused pin
Figure 3. Selecting how unused I/O is to be handled
Note: For VREF pins, when the Tie to single port or Tie to ports by IO bank options are selected,
you are given the additional option of whether or not to connect via Power Ports.

1.7 Configuring the sheet symbol schematic sheet
As part of the PCB project, you have the option of defining the 'owner' of the FPGA Component
sheet (holding the component symbol for the FPGA device). The final page of the Wizard allows you
to define the owner as a sheet symbol, which, if enabled, will be created on an additional schematic
sheet, the name and location of which you can freely choose. By default, the schematic will be
named using the chosen designator for the FPGA component on the previous page of the Wizard
(e.g. FPGA_U1_Manual.SchDoc) and will be stored in the same location as the FPGA project.
In summary, after all of the options in the Wizard have been set as required, the following will be
generated:
· A new PCB project (if specified)
· A new schematic sheet, added to the new or existing PCB project, which contains the schematic
representation of the FPGA component
· A new schematic sheet with parent sheet symbol (if specified). If an existing sheet is targeted,
the parent sheet symbol for the FPGA Component schematic will be added/updated as
necessary
· A new configuration (if specified), which will be added to the FPGA project file and which
contains a new constraint file
· The constraint file – either new for a new configuration or an existing one contained in a chosen
configuration – containing:
a part constraint
a PCB board constraint
a list of constraints for all ports on the toplevel source file of the FPGA project. Each of
these port constraints is matched (and therefore linked), by net name, to the equivalent pin
on the FPGA component in the PCB project's autogenerated schematic sheet.
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1.8 Exercise 1 – Running the FPGA to PCB project wizard
In this exercise we will utilize the design targeted to the Spartan2E device and we will run through
the FPGA to PCB Project Wizard.
1. Open the design SpiritLevel.PRJFPG in the folder \Module3\Exercise 1\
2. Open the configuration manager and make sure the NB1_6_XC2S300E6PQ208.Constraint is
included in the configuration. Click OK to close the configuration manager.
3. Open the FPGA schematic document – SL_FPGA_Complete.SchDoc.
4. Select Tools » FPGA to PCB Project Wizard.
5. At the Select the FPGA Configuration step, check the Use Existing Configuration option and
specify NB_Xilinx_Spartan2 configuration. Make sure Assign Unconstrained Ports is not
checked.
Figure 4. Use an existing configuration in the FPGA to PCB Project Wizard
6. At the Configure the PCB Project step, specify the PCB Project File Name as
SpiritLevel_2E.PrjPCB.
Figure 5. Specify the PCB project file name.
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7. At the Configure the Main Sheet step, specify the Main Sheet File Name as
Auto_2E.SchDoc and any further options as depicted in Figure 6. Click Next to continue.
Figure 6. Main sheet options.
8. At the Configure the Sheet Symbol Sheet step, check the Create Sheet Symbol box and
specify the Sheet Symbol File Name as SL_Top.SchDoc. Click Finish to complete the wizard.
Figure 7. Symbol sheet options.
9. Use File»Save As to save the two, newly autogenerated schematic sheets
10. Use File»Save Project As to save the newly created PCB project into this directory as well.
11. The basic schematic files have now been created and are ready for modification according to the
specific project requirements. At this point, however, the FPGA project may not appear visibly
linked to the PCB project. Rightclick on the PCB project in the projects panel and compile the
design. The design compiler will automatically change the project structure.
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Figure 8. Project Panel after compiling.
12. Observe the new structure of the created schematic sheets.
13. Save your work.
1.9 Modifying the auto generated sheet
Occasionally it may be necessary to perform modifications to the auto generated sheet. This will
cause the PCB project to lose synchronization with the FPGA project and the designs will need to be
resynchronized through the FPGA Workspace Map. Managing project synchronization is an
automated but not automatic process and project synchronization can only be performed in one
direction at one time – ie. design revisions can be propagated from the PCB to the FPGA or vice
versa but not both ways at the same time. Extreme caution should be exercised if both the PCB and
FPGA projects are being worked on in parallel.
Situations might also occur in which a design never totally synchronizes. This is commonly caused
when differences exist in the net naming between the PCB and FPGA schematics, or, when
additional components are connected to the FPGA for possible future expansion. The latter
scenario might include the addition of a connector at the board level that is not yet used in the FPGA,
and thus not represented in the FPGA design. If this occurs the PCB and FPGA designs will not
match and though this may cause the designs to appear out of sync, this will not affect the existing
functional portions of the design.
1.10 A word about special function FPGA pins
Special Function Pins are handled in a special way when creating the autogenerated sheet.
Extreme care must be observed to ensure their connectivity is maintained. As a rule of thumb it is
best to select the “Tie to individual ports” for Special Function Pins even if you don’t intend to use
them in the final design. If you need to use an I/O pin that has a special function net label attached
to it, just remove the special function net label and replace it with the net label for the net that you do
wish to be connected. Resynchronize the design as necessary.
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Selecting any other option other than the “Tie to individual ports” will cause special function net
labels to be ripped up or renamed. Beware!
1.11 Recreating the autogenerated sheet
The Synchronize dialog provides a button to Recreate Autogenerated Sheet. This feature should
be used under extreme care. If there are any PCB design changes that are yet to have been
propagated back to the FPGA project then they can be destroyed once the autogenerated sheet is
recreated.
Figure 9. Recreating the autogenerated sheet from the synchronize dialog.
Recall our previous warning about the nature of special function pins; selecting any other option
other than the Tie to individual ports will cause special function net labels to be ripped up or
renamed. Beware!
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2. Maintaining project synchronization
Maintaining synchronization between an FPGA project and its parent PCB project is greatly
improved through the internal synchronization mechanisms that operate within Altium Designer. It is
important, however, that users understand how this synchronization process works so that they don’t
inadvertently make design changes that will defeat project synchronization.
2.1 The FPGA workspace map
At any given time during the design process, the status of the linking between FPGA and PCB
projects can be readily checked by launching the FPGA Workspace Map dialog. Access to this
dialog is provided by choosing the command of the same name from the Projects menu, or by
pressing the button on the Projects panel.
In the example below the FPGA Workspace Map displays the relationships (links) between various
elements of FPGA and PCB projects and the status of these links – whether the two sides of a link
are synchronized and uptodate or whether some action is required to resynchronize them.
Figure 10. The FPGA workspace map dialog.
The various elements in the two project types are linked in a logical flow – from a soft core
microcontroller placed within an FPGA project, to a PCB design document within a linked PCB
project. Each of the links are summarized below:
2.1.1 FPGA project – soft processor
The Soft Processors region of the dialog is purely added for completeness and offers ataglance
information on the core microcontroller(s) that are being used in a particular FPGA project. The link,
as such, is therefore cosmetic. It will always be displayed as synchronized.
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2.1.2 Schematic document (PCB project) – FPGA project
This link reflects the synchronized status between the FPGA component in the PCB project and the
appropriate configuration in the FPGA project. When determining the status, the software is looking
for any netrelated changes.
2.1.3 PCB document – schematic document (PCB project)
This link reflects the synchronized status between the FPGA Component footprint on the PCB
document and the FPGA Component symbol on the schematic sheet, both within the PCB project.
2.1.4 Link status
A link can appear in one of two colors and hovering over a link will produce a textual description of its
status:
The green link signifies up to date (i.e. both sides are
synchronized). No action is required.
The red link signifies that the two sides of the link are not
fully synchronized (i.e. a design change has been made on
one side but has yet to be passed to the other). Clicking on
a schematicFPGA project link with this status will open the
Synchronize dialog, from where you can browse and
match any unmatched ports and pins.
Figure 11. Determining the link status
When two elements of the map are shown to be unsynchronized (i.e. the link between them is red),
clicking on the link or its associated icons will give access to a number of synchronization options.
The hint that appears when hovering over the link will, where possible, provide information on which
directions updates should be made in order to achieve synchronization.
Again, it may be possible for a design to never totally synchronize. Though this may occur, it is not a
sign of a failed design; it is merely the method with which the synchronizer evaluates differences
between the FPGA and PCB projects.
2.2 The synchronize dialog
If the FPGA Workspace Map determines that the project is not synchronized, a red link will be
displayed between the corresponding projects. Clicking on that link will reveal the Synchronize
dialog. This dialog provides an automated means for maintaining synchronization between FPGA
and PCB projects. It is important at this point that the reader understand that the process is
automated but not automatic and some care is required to ensure that recent design changes are not
overwritten.
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Figure 12. The synchronize dialog box
The Synchronize dialog has two primary regions. The upper region contains a list of PCB project
signal names that correspond with FPGA port names. These signals are referred to as the matched
signals. Information concerning the matched signals is further subdivided so that settings relating to
the Pin number and Electrical Type can easily be compared between the FPGA and PCB projects.
The lower region contains signals that can’t be matched based on their signal names – otherwise
known as unmatched signals. The Synchronize dialog has no option but to request user
intervention in knowing how to match and/or handle these signals.
Project synchronization can only be performed in one direction at one time – that is design revisions
can be propagated from the PCB to the FPGA or vice versa but not both ways at the same time.
Where it is necessary to work on both the FPGA and PCB projects in parallel, a stub project may
need to be created to manage synchronization between them. More information concerning stub
projects can be found in document AP0102 Linking an FPGA Project to a PCB Project.pdf.
2.2.1 Determining synchronization status
How the dialog is populated depends on the extent of net naming in the FPGA component
schematic. The following is a summary of the possibilities:
· A net label has been assigned to a pin with the same name as that used for the corresponding
port in the FPGA project. The pin number is different to that (if specified) in the associated
constraint file and/or the electrical type for the pin is different to that of the port. As the port and
pin have the same signal name, they will appear in the Matched Signals list. The entry will be
highlighted in red as the pin number and/or electrical type is different
· A net label has been assigned to a pin with the same name as that used for the corresponding
port in the FPGA project. The pin number is identical to that in the associated constraint file and
the electrical type for the pin is identical to that of the port. As the port and pin have the same
signal name, they will appear in the Matched Signals list. The entry will be highlighted in green
as the pin number and electrical type are also the same
· A net label has been assigned to a pin with a different name to any of the ports in the FPGA
project. An entry for the signal name will appear in the Unmatched PCB Signals list.
· All ports that have not been matched to pins with the same name will appear in the Unmatched
FPGA Signals list.
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2.3 Synchronizing matched signals
In the event that a matched signal has unsynchronized pin or electrical properties, the
unsynchronized items will appear red:
Figure 13. Synchronizing matched signals
The dialog above is highlighting the fact that the pin numbering for a number of signals is not
synchronized between the FPGA and PCB projects and that there are some unmatched PCB signals
between the two projects as well. The Synchronize dialog has matched the signal names between
the two projects and so the user has two options:
2.3.1 Update to PCB
The Update to PCB option will take the information listed in the FPGA columns and propagate it to
the PCB columns. In real terms, settings from the constraint file and FPGA schematic will be
propagated to the PCB Project (i.e. the autogenerated PCB Project file will be updated). This can
be seen in the ECO that is generated:
Figure 14. Running ECO to update the PCB Project documents
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2.3.2 Update to FPGA
The Update to FPGA option will take the value(s) listed in the PCB column and propagate it to the
PCB column. In real terms, settings taken from the PCB Project will be propagated to the constraint
file and / or the FPGA schematic. This can be seen in the ECO that is generated.
Figure 15. Running ECO to update the FPGA Project documents
It is important to remember that updates can only occur in one direction at a time. It is not possible,
for instance, for electrical type information to be propagated in one direction and pin numbering
information propagated in the opposite direction.
2.4 Synchronizing unmatched signals
As previously mentioned, PCB project signals that do not have a corresponding port in the FPGA
project cannot be matched and require further user intervention to be synchronized. Below we have
show a similar situation as before in that pin numbering and electrical type information does not
match between projects however in addition to this the ports have different names. The
Synchronize dialog has no option but to request the user change either the PCB or FPGA projects
manually. The Synchronize dialog assists in this process by allowing the user to create To Do
Items that can be exported to the To Do panel.
Figure 16. Synchronizing unmatched signals
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2.4.1 Add nets to PCB
The Add Nets to PCB button will remove the selected item from the Unmatched FPGA Signals box
and place a ToDo item that, once exported, will appear as follows:
Figure 17. Creating an 'Add Net' ToDo item
2.4.2 Remove ports
The Remove Ports button will remove the selected item from the Unmatched FPGA Signals box
and place a ToDo item that, once exported, will appear as follows:
Figure 18. Creating a 'Remove Port' ToDo item
2.4.3 Add ports to FPGA
The Add Ports to FPGA button will remove the selected item from the Unmatched PCB Signals
box and place a ToDo item that, once exported, will appear as follows:
Figure 19. Creating an 'Add Port' ToDo item
2.4.4 Remove nets
The Remove Nets button will remove the selected item from the Unmatched PCB Signals box and
place a ToDo item that, once exported, will appear as follows:
Figure 20. Creating a 'Remove Net' ToDo item
2.4.5 Rename PCB net to FPGA port
The button will remove both selected items from the Unmatched PCB Signals and
Unmatched PCB Signals boxes and place a ToDo item that, once exported, will appear as follows:
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Figure 21. Creating a 'Rename PCB Net' ToDo item
2.4.6 Rename FPGA port to PCB net
The button will remove both selected items from the Unmatched PCB Signals and
Unmatched PCB Signals boxes and place a ToDo item that, once exported, will appear as follows:
Figure 22. Creating a 'Rename FPGA Port' ToDo item
Once ToDo items have been exported, perform the updates manually, save the affected files and
check the FPGA Workspace Map dialog again to ensure synchronization has been reestablished.
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3. Configuring FPGA I/O
The FPGA Workspace Map dialog gives you the ability to check the state of the design across
linked FPGA and PCB projects and the means to propagate design changes between the two. The
following sections consider some of the more common design changes that might be made and that
require use of this dialog to detect such changes and ensure synchronization of the entire design.
In each case, it is assumed that the two, full design projects are local to the designer – stored on the
one machine and in the same directory structure.
3.1 Configuring I/O standards
FPGA devices generally support a range of I/O standards. These standards follow industry
specifications and often include options like LVTTL, LVCMOS and PCI to name a few. This enables
the FPGA to communicate directly with other devices requiring a certain standard. Often the
standards will also support further customization including the slew rate, current strength and
voltage.
Each device will have its own set of supported standards. Only supported standards can be selected
for the current device.
There is a complex set of interactions between different I/O standards in an FPGA. Some I/O
standards will be able to coexist while others are mutually exclusive. Often the requirements are
limited to I/O banks, such that all pins within an I/O bank on an FPGA must have compatible I/O
standards. This becomes particularly important with voltagereferenced standards such as GTL, as
an I/O bank will generally only be able to support one voltage reference value.
The interaction of selected I/O standards with one another is not modeled here and vendor
documentation should be referred to for more detailed information. As a general rule of thumb,
keeping pins using different I/O standards in separate I/O banks will ensure compatibility. Any errors
will be picked up when the vendor place & route tools process the design.
3.1.1 Selecting standards
I/O standards, slew rates and drive strengths for each pin of an FPGA device can be defined in the
FPGA Signal Manager dialog. This dialog is accessed by choosing the FPGA Signal Manager
entry under the Tools menu, from any schematic document within the PCB or FPGA project. When
accessed from a schematic in the PCB project, if more than one FPGA component is present a
dialog will appear beforehand listing the components from which to choose.
Figure 23. FPGA Signal Manager
Note: the list of available I/O standards is context sensitive only standards that are applicable for
that particular FPGA will be available.
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FPGA signals can be rapidly updated in groups by using the standard shift/ctrlselect technique and
right clicking one of the selected rows to access the popup menu. Additional columns can also be
enabled from this menu.
After defining the characteristics for the appropriate pins of the device as required, click OK to close
the dialog. The Engineering Change Order dialog will appear, with the settings you define listed as
a series of parameters to be added to the affected port constraint entries in the linked constraint file.
Figure 23. Updating the constraint file with signal manager changes
These changes are to signal characteristics only – not pinspecific changes. As such, they affect only
the relevant entries in the associated constraint file. The schematic representation of the FPGA
component is not affected and launching the FPGA Workspace Map dialog will show the link
between the schematic component and the FPGA project still green, highlighting the fact that the two
sides are fully synchronized.
The changes will be stored as constraints on the ports in the constraint file. Each required change
will be performed via an ECO and by executing the changes, the new I/O standards will be saved in
the constraint file. Any future synthesis/build process will then use these constraints for programming
the FPGA. (These constraints would also be used when performing a Signal Integrity analysis on the
PCB project).
3.2 Exercise 2 – Using the FPGA signal manager
1. With the Auto_2E.SCHDOC document open, select Tools » FPGA Signal Manager from the
menu.
2. Modify the following signals as described:
a. CLK_BRD: Slew Rate = FAST
b. JTAG_NEXUS_TCK: Slew Rate = FAST
c. JTAG_NEXUS_TDI: Slew Rate = FAST
d. JTAG_NEXUS_TDO: Slew Rate = FAST, Drive Strength = 24mA
e. JTAG_NEXUS_TMS: Slew Rate = FAST
f. LCD_DB[0..7]: Drive Strength = 24mA.
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Figure 234. Updated signals in signal manager
3. Select OK to implement the changes and open the Engineering Change Order dialog.
Figure 25. Committing changes made via the FPGA signal manager
4. Validate Changes and Execute Changes and then select Close.
5. Check the FPGA Workspace Map to ensure your project is still synchronised.
6. Save your work.
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4. Manually linking FPGA and PCB projects
In some circumstances the FPGA design will be developed in parallel with, but separate from, the
PCB design. In these situations it may be necessary to manually link the FPGA and PCB designs
together to ensure synchronization.
Figure 24. Manually linking FPGA and PCB projects that have been developed separately
In the event of an unlinked PCB and FPGA project, the FPGA Workspace Map may look something
like this:
Figure 25. FPGA workspace map with no link between the PCB and FPGA projects
Figure 25 shows that the schematic and PCB documents are correctly linked and synchronized,
however no link currently exists between the FPGA project and the PCB project. This is apparent by
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the lack of connecting lines between the SL1 Xilinx SpartanIIE PQ208 Rev 1.01.PRJPCB
and the FPGA projects and also by the comment No linked configuration below the
FPGA_51_Spirit_Level.PRJFPG icon.
4.1 Supported devices
In order for Altium Designer to establish a link between an FPGA project and a PCB project, the
FPGA component in use by each project must be recognized and supported. All devices present in
the vendor libraries are supported for linking.
The component placed on the schematic sheet has to be verified against the list of supported
devices in some way, before it is recognized and displayed in the FPGA Workspace Map dialog.
This is achieved using the Design Item ID field in the Component Properties dialog for the FPGA
component symbol on the PCB schematic. To be a recognized device, the entry in this field must be
identical to that in the Device field for the corresponding device in the Choose Physical Device
dialog. This is demonstrated in Figure 26:
Figure 26. Verification that device is supported.
4.2 Creating the link
Once the FPGA devices have been recognized as supported, it is possible to create the manual link
between the PCB and FPGA projects. This is done using the Structure Editor in the Projects panel
in much the same way as we previously linked an embedded project to an FPGA project.
The lower region of the Projects panel contains all the valid subprojects that are open in the
workspace. This includes FPGA, embedded and core projects. For FPGA projects, their defined
configurations will also be listed along with constraint files associated to each. Within this region of
the panel, constraint files can be moved from one configuration to another, simply by performing a
draganddrop. The constraint file will be disassociated from the source configuration and newly
associated to the target configuration. To copy a constraint file to another configuration, simply hold
down the CTRL key whilst performing the draganddrop.
To purely disassociate a constraint file from a configuration, simply drag the entry for the constraint
into free space within the lower region of the panel.
Doubleclicking on a configuration entry will launch the Configuration Manager dialog for the parent
FPGA project.
Linking of the two projects is achieved in one of the following ways:
· Dragging a configuration defined for the FPGA project from the lower region of the Projects
panel and dropping it onto the entry for the FPGA component in the PCB project
· Dragging the FPGA project – from either the upper or lower regions of the panel – and dropping
it onto the FPGA component entry in the PCB project
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· Rightclicking on the entry for the FPGA component in the PCB project and choosing the Set
Sub Project command from the popup menu that appears. This will open the Select Sub
Project dialog, from where you can browse to and open the desired FPGA subproject. This
method is particularly useful if the desired subproject is not currently open in the Projects panel.
Figure 27. Linking two projects via draganddrop in the structure editor
In each case, as you start to drag, the possible FPGA component entries (that reside on a schematic
sheet(s) within one or more PCB projects) that you can validly drop onto are highlighted in pale blue.
As the cursor passes onto a valid 'drop zone' it will change from a noentry symbol to a document
symbol as shown above.
If you choose to drag the entire FPGA project entry onto the target schematic FPGA component and
more than one valid configuration exists for that project – i.e. more than one configuration contains
an associated constraint file targeting the FPGA device – the Select Configuration dialog will
appear from where you can choose which specific configuration to use.
Figure 28. Selecting a configuration to be linked.
When the required configuration has been assigned, the parent FPGA project will become linked to
the PCB project and is shown in the structure hierarchy as a subdesign of the schematic FPGA
component.
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Figure 29. Structural view of a FPGA project linked to a PCB project.
To break the link between the two projects, simply click and drag the FPGA project entry into free
space within the panel (below the last entry).
Now that a configuration has been linked, the FPGA and PCB projects become linked and the FPGA
Workspace Map dialog will display a link between the schematic component in the PCB project and
the FPGA project.
Figure 30. FPGA workspace map showing the synchronization status of linked projects.
The projects are now linked, but they are yet to be synchronized.
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4.3 Linking an auto generated sheet to an existing PCB project
If you select the option to Create Sheet Symbol in the last stage of the FPGA to PCB Project
Wizard a sheet containing a sheet symbol of the FPGA project will be created. This can be used as
the basis for building a complete schematic to describe the target PCB hardware.
Alternatively, if you are working with a PCB project that already exists, you will probably already have
a sheet with many sheet symbols leading to various other subsheets. In this case you may simply
wish to connect an existing sheet symbol to the autogenerated sheet. This scenario would likely
occur where it has been decided to change the FPGA device on an existing PCB design. In this
case, you would open the Sheet Symbol dialog for the existing sheet symbol and manually edit the
Filename field to point to the autogenerated sheet.
Figure 31. Manually linking an auto generated sheet to a sheet symbol.
4.4 Exercise 3 – Manually linking a PCB and FPGA project
1. Open the SL Rev1.01.PrjPCB and the FPGA_U1\SpiritLevel.PRJFPG projects at the
same time.
2. Open the FPGA Workspace Map and verify that there is no link between the FPGA and PCB
projects.
3. Change to the Structure Editor and establish a link between the PCB and FPGA projects.
4. Reopen the FPGA Workspace Map and verify that a link now exists.
5. Click on the red link between the FPGA and PCB projects to resolve the unsynchronised signals.
6. Save your work.
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5. Pin swapping
5.1 Pin swapping in the PCB document
Many people may wonder why separate Auto and Manual schematic files are created in the FPGA
to PCB Project Wizard process. The Auto file creates the actual FPGA schematic symbol and links
the relevant pins to ports. The Manual file contains a sheet symbol that contains all of the ports
defined in the Auto file. The port linkage between the Auto and Manual files is a logical one rather
than physical. This abstraction makes it possible for the tool to perform pin swapping on the Auto
schematic without affecting connectivity on the Manual file.
The porttophysical pin assignments for an FPGA device are defined in a constraint file. You can
manually define the assignments, or let the place and route tools assign them and then import the
assignments back into the constraint file. However, once the FPGA is placed on the PCB, pin
assignments often need to be changed in order to optimize the PCB routing and then these changes
backannotated to the FPGA project, to keep the two projects synchronized.
5.1.1 Setup – Pin swapping methods
There are two ways that pin swaps can be represented at the schematic level. These are controlled
from the Options tab of the project options dialog box. In both cases, the actual wiring on the
schematic will not be altered; just its connectivity.
Figure 32. Setting pin and part swapping methods.
Adding / Removing NetLabels will move net labels on the swapped pins or nets to reflect the
changes that were made during pin swapping. In this case, the schematic symbol will be left
unchanged.
Changing Schematic Pins will allow Altium Designer to move the pins on schematic symbols
according to the pin swaps performed at the PCB level.
Where both options have been checked, Altium Designer will default to swapping net labels. If no
labels exist on the nets, it will swap pins on the schematic symbols.
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5.1.2 Setup – Swap groups
Before pins can be swapped with each other, it is important to first set up swap group IDs, as it may
not be desirable (or acceptable) for all pins to be swapped with one another. While all I/O pins within
an FPGA can theoretically be swapped to give a better layout for routing, conditions may dictate
otherwise. Firstly, some pins have additional special functions (clock pins, config pins and VREF pins
to name a few), and it may be preferable to reserve these for their special purpose. Secondly, setting
limitations here will allow any swapping process to obey the banking and I/O standards requirements
as described earlier. For this reason, it may be desirable for pins in a certain bank to only be
swappable with each other (or perhaps other banks with compatible I/O standards).
Swap groups may be defined at schematic or PCB level, as described below.
Setting swap groups in the schematic
To define swap groups in the schematic level, select the Tools » Configure Pin Swapping option.
The resulting dialog box will list all components in the design.
Figure 33. Setting up swap groups for various components.
Select the component you wish to define swap groups for and click on the Configure Component
button or simply doubleclick the component in the list to access the Configure Pin Swapping For
… dialog.
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Setting swap groups in the PCB
· Rightclick the component you wish to set up for pin swapping and select the Component
Actions >> Configure Pin / Part Swapping … .
· Select the Tools >> Pin / Part Swapping >> Configure option to access the Configure
Swapping Information In Components dialog box (see figure above). Select the
component you wish to define swap groups for and click on the Configure Component
button to access the Configure Pin Swapping For … dialog.
Figure 34. Specifying swap group IDs in the pin swap manager.
All pins with the same swap group ID can be freely swapped.
· Assign each I/O pin on the device to the required swap group. Either manually enter the label for
the group directly in the Swap Group ID field, or use the right click menu to assign swap groups
by various pin attributes.
5.1.3 Setup – Enabling components for pin / part swapping
Once swap groups have been defined, one more step is required before the actual pin swap. Altium
Designer will only swap pins for components which have been specifically marked as allowing pin
swapping. To do this for a given component, select it in PCB mode and view the component’s
properties. Then, under swapping options, make sure that Enable Pin Swaps has been enabled.
Do this for each component that requires pin swapping.
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Figure 35.Enabling pin swaps for a component.
5.1.4 Swapping
Having defined the Swap Group IDs as appropriate, the actual process of swapping pins can now be
performed. With the PCB document active, simply click on the Pin/ Part Swapping entry under the
Tools menu and choose a method to swap pins.
The Automatic Net/Pin Optimizer may be used on any or all components in a document and is not
limited to FPGA components. This pin swapper will attempt to find the optimal pin allocations for
routing, whilst obeying the pin swap Group IDs previously set up. It runs through a twostage
process: the first stage is a fast singlepass optimizer that will attempt to minimize crossovers and
connection lengths, while the second stage is an iterative optimizer which performs multiple passes.
The second stage is optional, as the time required for the iterative process increases significantly
when attempting to optimize multiple components.
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Figure 36. Rats nest prior to automated pin swapping
The two PCB snapshots depicted above and below show how the auto pin swapping tool can be
used to great effect to obtain an optimized set of pin allocations from which to route. In this case, all
I/O pins on the FPGA device have been assigned the same swap group ID.
Figure 37. Unraveled rats nest after automated pin swapping
The Interactive Pin/Net Swapping tool allows for finetuning and gives the power to make any
number of individual pin swaps – again, in accordance with the pin swap group IDs already
configured.
A sequence of swapping processes can be performed. For example, the automatic tool may be run
initially and then the interactive tool used afterwards to finetune a couple of out of place nets/pins.
If any FPGA components in the design are linked, due to the design being multichannel in nature,
(e.g. U1_X1, U1_X2), they must be optimized together. When using the interactive pin swapping
tool, swapping can not be carried out on the linked component and a dialog will appear alerting you
to this fact. For example, if U1_X2 is linked to U1_X1, both components must be optimized together,
but manual pin swapping can only be carried out on U1_X1.
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A pin swap operation achieves two things. Firstly it copies the important properties from the new pin
– this will be the electrical type of the pin as well as any parameters on that pin. Secondly it will
add/rename/remove an attached net label for that pin as appropriate. Note that this second step can
only occur if the FPGA component schematic sheet has been autogenerated using the FPGA To
PCB Project Wizard or has been created using a similar design style.
After updating the PCB, the changes need to be propagated to the rest of the project. To update the
PCB schematics, go to Design >> Update …. Once updated, you can then use the FPGA
Workspace Map to propagate the new changes into the FPGA project. You will notice that the
schematicFPGA project link appears out of date.
Figure 38. Resynchronizing the PCB/FPGA project link after pin swapping
Clicking on this link will bring up the Synchronize dialog, with the affected (swapped) pins
highlighted in red, as shown below.
Figure 39. Managing synchronizations between PCB and FPGA projects
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Click on the Update To FPGA button to push the changes to the FPGA project, or more specifically,
the appropriate FPGA constraint file. The update will consist of a number of parameter change ECOs
(appearing as a series of change parameter value modifications in the Engineering Change Order
dialog).
Figure 40. Confirm ECOs
Despite having passed the design changes through from the PCB project to the FPGA project, the
FPGA Workspace Map dialog will not show the designs as being fully synchronized. This is
because FPGA signals have been renamed with different net names in the PCB project. Also, the
PCB design contains additional connections not represented at the FPGA level (for alternate FPGA
implementations). This does not mean that functionally the two designs will not work but rather that
in its current implementation, these two designs have some differences not related to the
functionality.
Figure 41. Fully synchronized PCB/FPGA project
Important: After pin swapping has been carried out on the PCB, the changes pushed through to the
FPGA project and the projects resynchronized, the vendor place & route tools must be run again
(Build stage in the Devices view). This is because the pin swap information has been updated in the
constraint file only and now needs to be physically applied to the FPGA device. Running the place &
route tools again will ensure the new pin assignments are used in an updated FPGA programming
file.
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5.2 Pin swapping in the FPGA project
Pin swaps initiated from the FPGA project are likely to be required when a design no longer fits
within the FPGA device. The design may fit however, if existing pin constraints are relaxed and the
vendor tools are permitted to assign various pin numbers.
The constraint file can be edited to remove the pin number constraints as required.
After this process is completed and the design successfully fits again, the new vendor report file will
need to be imported.
With the appropriate constraint file open as the active document, select Import Pin File from the
Design menu. The newly created vendor report file will appear as an entry in the corresponding sub
menu. Importing this file will update the constraints as necessary.
The changes made to the constraint file now need to be pushed back to the PCB project. This
process is the reverse of that discussed in the previous section, with all changes again propagated
from within the FPGA Workspace Map dialog.
Entering the FPGA Workspace Map dialog will show the schematicFPGA project link out of date.
Clicking on this link will bring up the Synchronize dialog, with the affected pins highlighted in red, as
shown in below:
Figure 42. Managing synchronizations between PCB and FPGA projects
Click on the Update To PCB button to push the changes to the PCB project. This will perform a
series of pin swap operations (using ECOs) on the schematic document.
Performing these changes will then make the PCBschematic link out of date (if PCB components
exist at this stage). Clicking the relevant link will update the PCB document by changing the nets of
the newly swapped pins (again using ECOs, see below). Further changes may still be required to the
PCB document if these pins/nets contained any routing.
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Figure 43.Confirm ECOs
5.3 Pin swapping in both PCB and FPGA projects
It may be that pin changes have been made in both the PCB project and FPGA project without a
synchronize occurring. If this is the case, entering the FPGA Workspace Map dialog will show the
schematicFPGA project link out of date (Red).
Clicking on the link will open the Synchronize dialog, with all differences highlighted in red. It is not
possible to pass the relevant changes in their respective directions (PCB to FPGA and FPGA to
PCB) simultaneously. The sequence for passing the changes as required and resynchronizing the
link is summarized as follows:
· First choose the initial direction in which to pass changes, by clicking on either the Update To
PCB or Update To FPGA buttons
· In the Engineering Change Order dialog that appears, all changes will be geared to the chosen
direction. Enable only those modifications that are required for that direction.
· Execute the changes
· When the Synchronize dialog reappears, click on the Update button that was not initially
pressed, in order to pass changes in the second of the two directions
· Execute the changes in the subsequent Engineering Change Order dialog that appears
The Synchronize dialog will reappear, showing no differences in the Matched Signals list
(appearing totally green). In the FPGA Workspace Map dialog, the link will have returned to its fully
synchronized status (Green).
5.4 Exercise 4 – Pin swapping
This exercise continues on from work done in the previous exercise.
1. Open SL Rev1.01 NoRoutes.PcbDoc.
2. Check the Adding / Removing Net Labels option in the options tab of the project options dialog
box. Leave the Changing Schematic Pins option unchecked. Click OK to close the project
options dialog.
3. Select Tools » Pin/Part Swapping » Configure…
4. Select the FPGA component, and Configure Component
5. Ensure Show I/O Pins Only is selected from the dropdown list on the bottom left of the dialog
box.
6. Create a unique Swap Group ID for each of the following signals:
a. I\N\I\T\
b. DIN
7. All other IO pins can be placed into a single swap group called ‘general_IO’.
3 36
Figure 44. Specify swap group IDs for all of the IO
8. Select OK.
9. Zoom in to view the FPGA device in the centre of the PCB.
10. Double click on the FPGA device. When the Component U1 dialog appears, change the
Rotation to 180 degrees and click OK.
11. Use the automatic pin swapping to rearrange the pins.
12. Wait for a moment for the system to perform the pin swapping.
13. Go to the Design menu, and select Update Schematics to bring the changes across to the PCB
schematics.
14. Open the FPGA Workspace Map, and resolve any unsynchronised signals. The PCB should be
the master document at this stage so select Update to FPGA when performing any changes.
15. Save your work.
3 37
6. Commissioning the design
One of the advantages of having a hardware platform such as the Desktop NanoBoard at your
disposal during development is that you can perform a staged migration of the design onto a custom
target PCB. Even if components for the target have not yet arrived, initial commissioning can begin
by coupling the target to the NanoBoard and using NanoBoard resources as a substitute for the
missing components.
6.1 Exercise 5 – Migration stage 1
In this exercise, we consider the scenario where one or more of the target resources are yet to be
placed. In this case we may choose to run the main application from the target board but use
peripherals available on the NanoBoard to test our application. For this exercise to function correctly
we will need to load designs on to both the NanoBoard and Target platforms.
1. Locate the ..\Module 3\Exercise 5\ directory and load
SL Rev1.01.PrjPCB as well as FPGA_NB\SpiritLevel_NB.PRJFPG
2. Observe the contents of the schematic document SL_FPGA_NB.SchDoc. Notice how the
NEXUS JTAG Connector needs to be present and the TDI / TDO loop made to ensure that the
JTAG soft chain is not broken within the NanoBoard device.
3. Switch off the Desktop NanoBoard and target board power.
4. Using a 10pin ribbon cable, connect HDR1 on the target board to USER BOARD A on the
NanoBoard.
5. Using a 20pin ribbon cable, connect HDR2 on the target board to USER HEADER A on the
NanoBoard.
6. Ensure the Xaxis jumper is removed from the target board.
7. Ensure all DIP Switches on the target board are set to the ON position.
8. Place the CONFIG jumper on the target board.
9. Switch on the NanoBoard and target board.
10. Open the Devices view and verify the existence of two FPGA devices (and one configuration
device) in the Hard Chain. The first device will always be the NanoBoard device.
11. Build and download the SpiritLevel_NB / NB_Base configuration to the NanoBoard device.
12. Build and download the SpiritLevel / Tgt_Spartan2 configuration to the target board
device.
13. Observe the status of the Processor in the soft chain. If, after downloading both projects, this
device is listed as Missing, it is likely the soft chain is broken somewhere. Verify that a loop
between JTAG_NEXUS_TDI and JTAG_NEXUS_TDO exists on the SL_FPGA_NB.SchDoc.
Rebuild the project if necessary.
14. Set the NanoBoard clock frequency to 6 MHz and ensure that DIP Switch 8 on the NanoBoard is
ON. Observe the display on the target board. Assert one or two of the NanoBoard’s lower DIP
Switches and see what change occurs in the Target’s LCD. If the target board LEDs are not
flashing then this indicates it is not receiving a signal from the NanoBoard. Ensure all outputs
from the Digital IOB on the target board are 0 and check the wiring between the NanoBoard and
the target board. Also ensure the respective projects have loaded correctly.
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Figure 45. Devices view with all devices correctly connected and programmed.
Figure 46. Devices view after all devices have been programmed but with broken soft chain
6.2 Exercise 6 – Migration stage 2
In this final stage, we will remove the NanoBoard from the loop and run the design completely from
the target board. This exercise will follow on directly from the previous one.
1. Close the SpiritLevel_NB.PRJFPG project.
2. Ensure that both the Desktop NanoBoard and target board are switched off.
3. Remove the daughter board from the NanoBoard.
4. Disconnect the 20pin ribbon cable but leave the 10pin cable connected.
5. Ensure the X axis jumper is in place on the target board.
6. Ensure the CONFIG jumper is in place on the target board.
7. Apply power to both the NanoBoard and target board.
8. Build and download the SpiritLevel / Tgt_Spartan2 configuration to the target board
device.
9. Once the design is loaded, try tilting the target board and observe the LCD.
10. Note the existence of a number of downloadable instruments present in the target device. Note
that they are fully functional on the target device and don’t require the presence of the
NanoBoard.
6.3 Exercise 7 – Calibration
Some of the target boards will not display a zero reading when placed on a level surface. In this
exercise we will show how to calibrate this error out. This exercise flows on from the previous
exercise and uses the same source files.
1. Ensure that the project from the previous exercise has been loaded and is operational.
2. Open TimeTSK51.C and locate lines 93 and 94. Try a nonzero number (between 1 and 255) to
apply a calibration factor. Remember to use the ‘Compile and Download’ button to quickly rebuild
and run the software.
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Figure 47. Applying a calibration factor by hard coding it into the source code
3. Iteratively try to find the best calibration factor to produce a zero reading on a flat, level surface.
4. Save your work.
6.4 Exercise 8 – Bootstrapping the FPGA
An FPGA design is not much good if every time the board is powered up it needs to be connected to
some programming device to configure the FPGA. The spirit level application was designed to
operate as a standalone system and so it needs some means for storing the FPGA configuration
when power is removed. For this purpose, a serial configuration device has been installed on the
target board. On power up, the FPGA device observes that it is connected to the configuration
device and automatically configures itself from the device. In this final exercise we will program the
configuration device and make the spirit level a truly selfcontained embedded system. This exercise
flows on from the previous one. Any calibration factors incorporated into the source code will be
included in the device configuration.
1. Ensure that the project from the previous exercise has been loaded and is operational.
2. If the Make PROM File step in the Build flow is currently greyed out, enable this step by clicking
on its options icon and specify the appropriate configuration PROM device.
Figure 48. Specifying the configuration PROM device
3. Select the mcs option under the Format drop down.
4. Rebuild the entire project to ensure that your calibration values are included in the build and the
configuration PROM file gets created.
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Rightclick on the configuration device in the hard chain and select Choose File and Download…
from the popup menu.
Figure 49. Downloading a PROM to the configuration device.
5. Locate the MCS bitfile. You will find it under
\ProjectOutputs\Tgt_Spartan2\spiritlevel.mcs. Once you select it, downloading
will begin immediately.
6. The programming process may take several seconds as the device has to first be erased before
it can be programmed. When asked if you wish to verify programming select Yes. Be sure not
to remove power from the device until programming is complete. You will be notified of
successful programming with the following information dialog.
Figure 50. PROM file programming confirmation
7. Remove power from the target board.
8. Disconnect the 10pin USER BOARD ribbon cable from the target board.
9. Remove the CONFIG jumper from the target board but make sure the Xaxis jumper remains
connected.
10. Reapply power to the target board and verify that the application correctly loads and runs itself.
11. Switch off the NanoBoard and the target board and reconnect the 10pin USER BOARD ribbon
cable between the target board and the NanoBoard.
12. Reapply power to the target board and NanoBoard and observe in the Devices view that the
downloadable instruments are still accessible.
6.5 Exercise 9 – Reverting to test mode
1. To ensure the target boards are left in a state ready for the next users, it will be necessary to
reprogram the PROM with the Test Mode configuration file. You will find this file as
\Exercise9\ConfigTest.mcs. Use the steps outlined in the previous exercise to program
this test file back into the PROM.
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7. Review
3 42

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