UNIT 4 MCQ

1. In 8051 an external interrupt 1 vector address is of ________ and causes of

interrupt if ____.
a) 001BH, a high to low transition on pin INT1
b) 001BH, a low to high transition on pin INT1
c) 0013H, a high to low transition on pin INT1
d) 0013H, a low to high transition on pin INT1
Answer: C

2. Serial port vector address is of _______. And causes an interrupt when ________.
a) 0013H, either TI or RI flag is set
b) 0023H, either TI or RI flag is reset
c) 0013H, either TI or RI flag is reset
d) 0023H, either TI or RI flag is set
Answer: D

3. In serial communication modes, mode 1 the Baud rate =

a) BR=2SMOD/32 * (Timer 0 over flow rate)
b) BR=2SMOD/16 * (Timer 1 over flow rate)
c) BR=2SMOD/16 * (Timer 0 over flow rate)
d) BR=2SMOD/32 * (Timer 1 over flow rate)
Answer: D

4. Interrupt service routine and called routine have following features

a. Both save PC on stack and have identical instruction for return
b. Both save PC on stack and have different instruction for return
c. Both save PC as well as other registers on stack
d. ACALL instruction can be used to call both type of routines
Answer: B

5. In 8051
a. IT0 is in TCON and defines interrupt type (edge or level triggered)
b. IT0 is in IE and defines interrupt type.
c. IT0 is in TCON and defines the flag for edge triggered interrupt
d. IT0 is in IE and defines flag for edge triggered interrupt
Answer : A
6. On microcontroller reset, interrupt priority and vector addresses are in same order
a. True
b. False
C. Cannot be determined
Answer: A

7. Consider an ISR
0023 CLR TI
0025 MOV SBUF, @R0
0027 RETI
Bytes transmitted by this program if run continuously will be
a. Equal to 2 if R0 has initial value as 2
b. Data stored in R0
c. Data pointed by value stored in in R0
d. No transmission
Answer: C

8. How does the processor respond to an occurrence of the interrupt?

a. By Interrupt Service Subroutine
b. By Interrupt Status Subroutine
c. By Interrupt Structure Subroutine
d. By Interrupt System Subroutine
Answer: A

9. Which register specify the storage / loading of vector address during the interrupt
generation?
a. Stack Pointer
b. Program Counter
c. Data Pointer
d. All of the above
Answer: B

10. Match the following :

A. ISR 1. Program executed after interrupt occurence
B. IE 2. Allows the termination of ISR
C. RETI 3. Interrupts Initialization
D. INTO 4. Occurrence of high to low transition level
a. A-1, B-2, C-3, D-4
b. A-3, B-2, C-4, D-1
c. A-1, B-3, C-2, D-4
d. A-4, B-3, C-2, D-1
Answer: C

11. What kind of triggering configuration of external interrupt intimate the signal to
stay low until the generation of subsequent interrupt?
a. Edge - Triggering
b. Level Triggering
c. Both a & b
d. None of the above
ANSWER: b

12. Which among the below mentioned reasons is / are responsible for the
generation of Serial Port Interrupt ?
A. Overflow of timer/counter 1
B. High to low transition on pin INT1
C. High to low transition on pin INT0
D. Setting of either TI or RI flag

a. A & B
b. Only B
c. C& D
d. Only D
ANSWER: d

13. The timer generates an interrupt, if the count value reaches to

a) 00FFH
b) FF00H
c) 0FFFH
d) FFFFH
Answer: d

Explanation: the timer is an up-counter and generates an interrupt when the count
has reached FFFFH.
14. The interrupt that has lowest priority amongst the following is
a. TF0
b. RI
c. INT0
d. INT1
Answer: B

15. The interrupts, INT0(active low) and INT1(active low) are processed internally by
flags
a) IE0 and IE1
b) IE0 and IF1
c) IF0 and IE1
d) IF0 and IF1
Answer: a

16. The flags IE0 and IE1, are automatically cleared after the control is transferred to
respective vector, if the interrupt is
a) level-sensitive
b) edge-sensitive
c) in serial port
d) in parallel port
Answer: b

17. Which of the following is used in case of external interrupt programming

a) 4 LSBs of TCON register
b) Interrupt enable
c) priority register
d) all of the mentioned
Answer: D

18. EA bit is used to

a) enable or disable external interrupts
b) enable or disable internal interrupts
c) enable or disable all the interrupts
d) none of the mentioned
Answer: C
19. The number of priority levels that each interrupt of 8051 have is
a) 1
b) 2
c) 3
d) 4
Answer: b

20. All the interrupts at level 1 are polled in the second clock cycle of the
a) forth T state
b) fifth T state
c) third T state
d) none
Answer: b
Explanation: All the interrupts at level 1 are polled or sensed in the second clock
cycle of the fifth T state or 9th clock cycle out of 12 clock cycles. Then all the
interrupts at level 0 are also polled in the same cycle.

21. If two interrupts, of higher priority and lower priority occur simultaneously, then
the service provided is for
a) interrupt of lower priority
b) interrupt of higher priority
c) both the interrupts
d) none of the mentioned
Answer: b

22. When any interrupt is enabled, then where does the pointer moves immediately
after this interrupt has occurred?
a) to the next instruction which is to be executed
b) to the first instruction of ISR
c) to the first location of the memory called the interrupt vector table
d) to the end of the program
Answer: c
Explanation: When any interrupt is enabled, then it goes to the vector table where
the address of the ISR is placed.

23. What are the contents of the IE register, when the interrupt of the memory
location 0x00 is caused?
a) 0xFFH
b) 0x00H
c) 0x10H
d) 0xF0H
Answer: b
Explanation: When interrupt of 0x00 is caused (the reset interrupt) then all the other
interrupts will be disabled or the contents of the IE register becomes null.

24. Which bit of the IE register is used to enable TxD/RxD interrupt?

a) IE.D5
b) IE.D2
c) IE.D3
d) IE.D4
Answer: d

25. Why normally LJMP instructions are the topmost lines of the ISR?
a) so as to jump to some other location where there is a wider space of memory
available to write the codes
b) so as to avoid overwriting of other interrupt instructions
c) both of the mentioned
d) none of the mentioned
Answer: c
Explanation: There is a small space of memory present in the vector table between
two different interrupts so in order to avoid overwriting of other interrupts we
normally jump to other locations where a wide range of space is available

26. What is the disadvantage of a level triggered pulse?

a) a constant pulse is to be maintained for a greater span of time
b) difficult to analyse its effects
c) it is difficult to produce
d) another interrupt may be caused, if the signal is still low before the completion of
the last instruction
Answer: d
Explanation: In a level triggered pulse, if the signal does not becomes high before the
last instruction of the ISR, then the same interrupt will be caused again, so
monitoring of pulse is required for a level triggered pulse.

27. What is the correct order of priority that is set after a controller gets reset?
a) TxD/RxD > T1 > T0 > EX1 > EX0
b) TxD/RxD < T1 < T0 < EX1 < EX0 c) EX0 > T0 > EX1 > T1 > TxD/RxD
d) EX0 < T0 < EX1 < T1 < TxD/RxD
Answer: c
Explanation: EX0 > T0 > EX1 > T1 > TxD/RxD. This is the correct order of priority that
is set after a controller gets reset.

28. The service to an interrupt will be delayed if it appears during the execution of
a) RETI instruction
b) instruction that writes to IE register
c) instruction that writes to IP register
d) all of the mentioned
Answer: d
Explanation: The service to an interrupt will be delayed if it appears during the
execution of RETI instruction or the instruction that writes to IE/IP registers.

29. While CPU is executing a program, an interrupt exists then it

a) follows the next instruction in the program
b) jumps to instruction in other registers
c) breaks the normal sequence of execution of instructions
d) stops executing the program
Answer: c
Explanation: An interrupt function is to break the sequence of operation.

30. While executing main program, if two or more interrupts occur, then the
sequence of appearance of interrupts is called
a) multi-interrupt
b) nested interrupt
c) interrupt within interrupt
d) both b and c
Answer: d
Explanation: If an interrupt occurs while executing a program, and the processor is
executing the interrupt, if one more interrupt occurs again, then it is called nested
interrupt.

31. NMI stands for

a) nonmaskable interrupt
b) nonmultiple interrupt
c) nonmovable interrupt
d) none
Answer: a

32. If any interrupt request given to an input pin cannot be disabled by any means
then the input pin is called
a) maskable interrupt
b) nonmaskable interrupt
c) maskable interrupt and nonmaskable interrupt
d) none
Answer: b
Explanation: A nonmaskable interrupt input pin is one which means that any
interrupt request at NMI (nonmaskable interrupt) input cannot be masked or
disabled by any means. RESET interrupt is an example of non maskable interrupt.

33. Which devices are specifically being used for converting serial to parallel and
from parallel to serial respectively?
a) timers
b) counters
c) shift registers
d) serial communication
Answer: c
Explanation: Some registers like parallel in serial out and serial in parallel out are
used to convert serial data into parallel and vice versa respectively

34. What is the difference between UART and USART communication?

a) they are the names of the same particular thing, just the difference of A and S is
there in it
b) one uses asynchronous means of communication and the other uses synchronous
means of communication
c) one uses asynchronous means of communication and the other uses asynchronous
and synchronous means of communication
d) one uses angular means of the communication and the other uses linear means of
communication
Answer: c
Explanation: UART stands for Universal Asynchronous receiver-transmitter and
USART stands for Universal Synchronous and Asynchronous receiver-transmitter
35. Which of the following best describes the use of framing in asynchronous means
of communication?
a) it binds the data properly
b) it tells us about the start and stop of the data to be transmitted or received
c) it is used for error checking
d) it is used for flow control
Answer: b
Explanation: In data framing in asynchronous means of communication, the data is
packed between the start and the stop bit. This is done so as to tell the other
computer about the start and the end of the data.

36. Which of the following signal control the flow of data?

a) RTS
b) DTR
c) both of the mentioned
d) none of the mentioned
Answer: a
Explanation: RTS is a request to send control signal which is a control for the flow of
data. On the other hand DTR is a Data Terminal Ready control signal which tells
about the current status of the DTE

37. Which of the following is the logic level understood by the micro-
controller/micro-processor?
a) TTL logic level
b) RS232 logic level
c) RS485
d) none of the mentioned
Answer: a
Explanation: TTL logic or the transistor transistor logic level is the logic that is
understood by the micro-controllers/microprocessors

38. What is null modem connection?

a) no data transmission
b) no MAX232
c) the RxD of one is the TxD for the other
d) no serial communication
Answer: c
Explanation: In null modem connection the RxD of one is the TxD for the other
39. With what frequency UART operates( where f denoted the crystal frequency )?
a) f/12
b) f/32
c) f/144
d) f/384

Answer: d
Explanation: UART frequency is the crystal frequency f/12 divided by 32, that comes
out to be f/384.

40. What should be done if we want to double the baud rate?

a) change a bit of the TMOD register
b) change a bit of the PCON register
c) change a bit of the SCON register
d) change a bit of the SBUF register
Answer: b
Explanation: PCON register consists of SMOD bit as its D7 bit, so if we set this bit
then the baud rate gets doubled

41. The serial communication is used for

a) short distance communication
b) long distance communication
c) short and long distance communication
d) communication for a certain range of distance
Answer: b
Explanation: Serial communication is more popular for communication over longer
distances as it requires less number of conductors.

42. If the microcontroller is expected to communicate in multiprocessor system, then

the required condition is
a) SM0 is set
b) SM1 is set
c) SM2 is set
d) REN is set
Answer: c
Explanation: The bit, SM2 is set if the microcontroller is expected to communicate in
multiprocessor system.
43. Which two bits are important with respect to data reception of byte in mode 1
serial communication?
a. RI & TI
b. REN & RB8
c. RI & REN
d. TI & RB8
ANSWER: c. RI & REN

44. Which pin in the shift register mode (Mode 0) of serial communication allow the
data transmission as well as reception?
a. TXD
b. RXD
c. RB8
d. REN
ANSWER: b. RXD

45. Which factor/s is/are supposed to have the equal values at both phases of
transmission and reception levels with an intimation of error-free serial
communication?
a. Baud Rate
b. Number of data bits & stop bits
c. Status of Parity bits
d. All of the above
ANSWER: d. All of the above

46. Which of the following is disadvantage of polling method

a. wastage of program execution time
b. priority cannot be assigned to interrupts
c. masking of an interrupt is not possible
d. all of the above
Answer: D

47. If INT1 interrupt is to be configured as edge triggered interrupt, then which of the
following bits should be set
a. TCON.4
b. TCON.3
c. TCON.2
d. TCON.0
Answer: C
Explanation: INT1 interrupt related pin is IT1 in TCON register. It is at position
TCON.2.

48. Following instruction is used

MOV IP, # 04 H. Which interrupt will have highest priority
a. INT0
b. INT1
c. T0
d. T1
Answer: B
Explanation: 04 H = 00000100 in binary. Which means that INT1 priority bit is set and
hence that interrupt will have highest priority. The priority will be as follows:
INT1>INT0>T0>T1>Serial

49. If IP register is loaded with value 00011010 B, then which interrupt will have
second lowest priority.
a. Serial
b. INT1
c. INT0
d. T0
Answer: C
Explanation: From the data loaded in IP register it can be observed that, high priority
is assigned for T0, T1 and serial interrupts. These 3 will have high priority but
according to their default priority, serial will be lowest in these 3. Hence the priority
table will be as follows
T0 > T1 > Serial > INT0 > INT1

50. A Timer 0 interrupt service routine is currently in execution and an INT0 interrupt
is activated, IP register contains 00 H.
a. Timer 0 interrupt service routine continues to execute
b. Timer 0 ISR is halted and INT0 ISR is served first
c. Program stops both ISRs and returns to main program
d. None of the above
Answer: B
Explanation: Since IP contains 00 H, interrupt priority is as per default state of
microcontroller. INT0 has higher priority than T0 hence INT0 will be executed first
and then T0 will continue from where it was halted.
51. Following features can be attributed to serial communication
a. Slower data transfer
b. Less no of hardware lines required
c. Long distance communication is possible
d. All of the above
Answer: D

52. Which serial communication type is used for character data transfer
a. Synchronous
b. Asynchronous
c. Both
d. None of above
Answer: B

53. Bit state after stop bit is called as

a. Void
b. Absence
c. Space
d. None of above
Answer: C
Explanation: Bit status after stop bit is called as space and bit status before start bit is
called as mark.

54. MAX 232 IC is used to

a. match TTL logic levels with RS232 logic levels
b. Match RS 232 levels with RS 485 levels
c. Match TTL levels with RS 485 levels
d. None of the above
Answer: A

55. For RS232, binary level 1 is represented by

a. -3 V to -25 V
b. +3 V to +25 V
c. 0 to 5 V
d. 0 to -5 V
Answer: A
56. MAX 232 pin consists of total ______ capacitors
a. 2
b. 3
c. 4
d. 5
Answer: 4

57. Which of the following signals is input for MODEM

a. DTR
b. RTS
c. CTS
d. DCD
Answer: A
Explanation: DTR is sent by PC to modem, hence it is input for modem and output for
PC.

58. ________ is a connection between two terminals such that, data may travel in
both directions, but only one way communication is allowed at a time.
a. Full duplex
b. Simplex
c. Half duplex
d. all of above
Answer: C

59. Which mode of data transfer is used for rate <= 20 k bits / second
a. Synchronous
b. asynchronous
c. bulk
d. byte
Answer: B
Explanation: 20k bps = 20000 bps. With the help of SCON and PCON (SMOD bit)
register 8051 can be programmed up to 19200 bps only.

60. Which timer in which mode is used to generate baud rate for serial data transfer
a. Timer 1 mode 2
b. Timer 0 mode 1
c. Timer 0 mode 2
d. Timer 1 mode 1
Answer: A

61. What value should be loaded in TH1 register to generate a baud rate of 9600 with
default settings.
a. -12
b. -3
c. -6
d. -24
Answer: B
Explanation: In order to answer this or any other related question to value setting for
baud rate, following table should be referred.
Value in TH1 Value in TH1 (Hex) Baud rate for Baud rate for
(decimal) SMOD bit = 0 (from SMOD bit = 1 (from
PCON reg.) PCON reg.)
-3 FD H 9600 19200
-6 FA H 4800 9600
-12 F4 H 2400 4800
-24 E8 H 1200 2400

62. By setting PCON.7 = 1, baud rate value _______ as compared to default

a. increases 4 times
b. increases 6 times
c. increases 2 times
d. increases 3 times
Answer: B
Explanation: Refer above table. For setting of -3 in TH1 , if SMOD = 0, baud rate is
9600 and for SMOD = 1, baud rate is doubled and becomes19200.

63. Whenever INT1 interrupt occurs, the microcontroller branches to address

a. 0003 H
b. 000B H
c. 0013 H
d. 001B H
Answer: C
Explanation: Whenever any interrupt occurs, microcontroller jumps to IVT (interrupt
vector table) first. Every interrupt has a specific IVT address as given in following
table.
Interrupt Name IVT address
Reset 0000 H
 INT0 0003 H
T0 (TF0) 000B H
INT1 0013 H
T1 (TF1) 001B H
Serial 0023 H

64. Which of these is not a standard package for RS232 protocol

a. DB 25
b. DB 13
c. DB 9
d. All of above
Answer: DB 13

65. Baud means

a. Bits transmitted in one second
b. Bits transmitted in one minute
c. Bytes transmitted in one second
d. Bytes transmitted in one minute
Answer: A
Explanation: Baud = bps (bits per second)

66. If data is transmitted with 9600 baud, then the transmission rate is
a. 1.04 ms
b. 10.4 ms
c. 0.104 ms
d. 0.0104 ms
Answer: Transmission rate = 1/baud. Hence, 1/9600 = 1.04 * 10-4 = 0.104 ms

67. 9th bit of data is transmitted in mode 2 and 3 of serial communication using
a. TB8 bit of SCON
b. TI bit of SCON
c. SMO bit of SCON
d. SM1 bit of SCON
Answer: A

68. PS bit in ______ register must be set to give the serial data interrupt highest
priority
a. IE
b. SCON
c. IP
d. PCON
Answer: C

69. DB 25 is
a. 25 pin connector
b. 20 pin connector
c. 9 pin connector
d. 22 pin connector
Answer: A

70. Asynchronous transmission begins with

a. Stop bit
b. Start bit
c. Parity bit
d. Sync bit
Answer: B