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Towards cloud energy metering system with 32 bit FPGA device architecture

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DOI: 10.4314/jcsia.v26i2.12

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 https://dx.doi.org/10.4314/jcsia.v26i2.12

THE JOURNAL OF COMPUTER

SCIENCE AND ITS APPLICATIONS
Vol. 26, No. 2 December 2019

TOWARDS CLOUD ENERGY METERING SYSTEM

WITH 32 BIT FPGA DEVICE ARCHITECTURE

K. C. Okafor,1 A. A. Obayi2 and O. U. Oparaku3

1
Dept. of Mechatronics Engineering, Federal University of Technology Owerri, Nigeria
2
Dept. of Computer Science, University of Nigeria, Nsukka
3
Dept. of Electronic Engineering, University of Nigeria, Nsukka
1
kennedy.okafor@futo.edu.ng, 2adaora.obayi@unn.edu.ng,3 ogbonna.oparaku@unn.edu.ng

ABSTRACT

Cloud based Advanced Metering Infrastructure (CAMI) is the next digital future for energy
management (EM). Various efforts on EM capabilities are mainly skewed towards embedded device
architectures that support non-concurrent execution. This paper presents cloud energy metering system
(CEMS) using high speed 32 bit field programmable gate array (FPGA) device. The architectural
framework for energy tracking and profile measurement in CEMS is presented. This aims at accurate
metering with demand side management (DSM). An application context that supports an EM
architecture is highlighted. The contextual CEMS features energy monitoring in distributed energy
utilities such as solar generators, wind and energy storage sources. Process integration with Cloud
based Internet for real-time energy reading is achieved through the FPGA synthesis to provide end-to-
end energy analytics. CEM prototype (Xilinx FPGA) running on a wireless open-access research
platform supports management of large historical data-sets from the current data up to the last granular
interval, hourly, daily, monthly and yearly dataset captures. The system provides the low latency
datasets in both tabular and graphical forms for end-user visualization of energy consumption patterns.
In the experimental setup, three case scenarios demonstrate how the metering system executes fast
edge computing profiling, thereby providing data-visualization services to end-users. The results show
the Avg. Latency time for CAMI household 1, 2 and 3 respectively. In case 1, the average latencies for
actual and measured (proposed CAMI) are 75% and 25% respectively. In case 2 and case 3, this gave
66.67% and 33.33% respectively. Clearly, the proposed CAMI offers lower latency for all scenarios of
energy consumption metering usage.

Keywords: Advanced Metering, Energy management, Cyber-physical systems, Cloud Computing,

IoT, Fog.

1.0 INTRODUCTION metering and billing systems [3][4]. Smart-

Cloud based metering technology with
FPGA’s is a disruptive technology that have
recently gained attention in today’s energy
industry. Indeed, smart metering designs
with FPGA devices [1] and digital inclusive
technology such as the Internet cloud [2] are
needed to provide new efficiency in energy
AMI have changed the way metering is done
by allowing customers participation in
making demand side management [5].
In the world of cloud driven AMI found in
modern Smart Grids [6], [7], smart meters
combine highly intelligent electronic/digital
components with full duplex two-way
 Towards Cloud Energy Metering System With 32 Bit FPGA Device Architecture
K. C. Okafor, A. A. Obayi and O. U. Oparaku
communication to achieve seamlessness. The
essence is to create efficient monitoring and
management of energy usage data. The
features of these meters include energy usage
monitoring for billing, power and theft
detection, anti-tampering feature, load
connect/disconnect detection, firmware up-
gradations, demand side management,
(DSM), and analytics, among others [8]. A
functional SM can give unbiased split up
consumer energy usage at short intervals.
The benefit is that it automates the billing
system with very low cost overhead. In most
SMs, there are two essential components viz:
metering and communication modules [8].
These components have specific controller
units relating seamlessly during its operation.
Also, these meters have load enable/disable
switch, I/O control interfaces, with
embedded power storage subsystems, among
others.
With the global energy crisis, these features
can enhance energy efficiency, reduce
wastages and control usage pattern by
consumers. This is very useful in the
generation; distribution and transmission of
electrical energy where the traditional
electrical grids are revised with smart
metering elements. The major difference
between the recent smart metering systems
and the legacy metering models is that the
SM enforces active participation of
consumers in energy conservation through
real time feedback communication on their
exact energy consumption profiles [5].
Till date, most metering system in Nigeria
does not support full duplex communication
for real time energy feedback. Low
latency/high speed processing capabilities is
yet to be fully implemented and deployed.
This research presents Cloud based CEMS
which depends on high speed processor such
as FPGA. In this paper, various works on
FPGA based processors and their various
categories are reviewed to provide clear
understanding of its application in CEMS.
The main feature of the proposed CEMS is
122
the low latency FPGA application specific
circuit (ASIC) system on chip (SOC).
In the proposed system, the core is designed
to have little power drain while having
characteristics like low delay real-time clock,
signal conditional converter and other RF
interfaces. These forms part of the ongoing
research on CEMS/AMI concept. The system
has efficient latency and replaces the legacy
alternative.
[9] gave essential benefits of AMI for energy
driven society. These include:
i. It offers low latency energy data-stream
updates.
ii. It gives cumulative data-sets from
various home units’ sources while
performing data analytics at the cloud
backend.
iii. It gives secured data protection for user
location, and other energy billing data-
sets.
iv. It manages bandwidth sensitive
workloads during its full duplex
communication.
v. It provides trajectory data-mining using
location and context-aware service
provisioning. This reason is that by
staying closer to edge user location
devices, more I/O streams (information
data) can be acquired from user source
device and location.
The benefits of the proposed CEMS include
reduction in data collection costs, improved
reading precision, efficient and more
organized billing process, significant
increase in its operational efficiency through
the provision of real time metering activities.
Essentially, the work presents the developed
CEMs implementation architecture for the
distributed energy resources like solar, wind,
etc as highlighted in [4]. The design strategy
for achieving analog to digital conversion
module in a 32 bit FPGA driven smart
meters is considered. In this case, the
metering filters in FPGA ADC is
The Journal of Computer Science and its Applications Vol. 26, No. 2, December 2019

programmed with VHDL to deliver a architecture whose power calculation theory

System-On-a-Programmable Chip (SOPC) was verified with IEEE 1459-2010 Standard.
based model. In future, a smart Sigma delta HDL was used to synthesize the design.
ADC will be introduced as an IP core in the Their approach satisfied windowing
Altera FPGA component library while specifications established for power quality
leveraging it as a platform in the proposed measurement methods [14].
AMI.
In terms of FPGA processor architectures,
2.0 RELATED WORKS various works have been carried out to
address speed performance issues. For
In this Section, related works on smart
instance [15] presented an FPGA 32
metering systems relying on FPGA
bit extended arithmetic logic unit (ALU)
technology are discussed. The work [8],
architecture simulated in Xilinx Vivado 14.4
presented an implementation of FPGA sigma
tool and implemented on 28nm zynq 7000
delta architecture for the analog to digital
FPGA board. [16] presented a 32-bit MIPs
conversion module in smart meters. [10]
FPGA-Based pipelined microprocessor with
presented a transceiver architecture that
Very high speed hardware descriptive
depicts resource estimations for ASIC and
language (VHDL), [17]. The system executes
FPGA adapted to an AMI. The work
instructions in single cycle, and also
developed an integrated multi-rate and multi-
improves performance with pipelining
regional frequency shift keying (MR-FSK)
techniques. Xilinx FPGA was used as the
transceiver compliant with IEEE 802.15.4g
implementation platform and was verified
standard for smart metering utility networks.
using Xilinx assembly programs. [18]
[11] presented a typical power measurement
presented the implementation of a 32-bit
device whose computational units are
MIPS (Microprocessor without Interlocked
embedded in an FPGA device. This was
Pipeline Stage) processor based on QR
developed for analyzing 4-wire three-phase
decomposition (QRD) using Givens rotation
systems based on IEEE 1459-2010 standard,
algorithm. Their design has modified
considering under sinusoidal, non-sinusoidal,
hardware that reduces the latency of QRD
balanced and/or unbalanced condition. The
processes. It was realized with Xilinx 14.7
system was built on a synthesized
ISE simulator while its code was done in
programmable logic device (PLD) using
Verilog HDL language and implemented on
hardware description language (HDL)
Virtex - 7 FPGA kit. Other similar works on
alongside with digital signal processing
32 bit FPGA designs have been studied and
schemes.
presented in [19], [20], [21], [22], [23], [24]
[12] demonstrated a prototype [25], [26], [27] and [28].
implementation of an MR-OFDM baseband
With the FPGA device board [29], the design
modem (with FPGA compliant
can be used create, implement, and test CEM
IEEE802.15.4g standard) adapted to smart
AMI design using programmable logic.
metering utility networks. The work used
Figure 1 shows the I/O ports in DE2 -115
VHDL while prototyping with Altera's
highlighting the board layout with
device 5CGXFCC5C6F27C7N having
indications on the location and connections
maximum seed of 65.16MHz. The modem
of various components.
parameters that were analyzed for the energy
meter include active power, reactive power,
3.0 FPGA DEVICE ARCHITECTURES
current, voltage and frequency. [13]
presented an electric power measurement Clearly, the FPGA device architecture is
implementation in a three-phase power perceived to have strong potential for
system by using an FPGA device optimal design of AMIs. This is further
123
 Towards Cloud Energy Metering System With 32 Bit FPGA Device Architecture
K. C. Okafor, A. A. Obayi and O. U. Oparaku

buttressed in [30] where the authors
identified the merits of using FPGA-ASIC.
These were summarized as follows:
 Using FPGAs offers re-programmability
for bugs’ correction.
 FPGA development allows shorter time
to market and reduces unnecessary costs.
 High level integration in FPGAs reduces
power consumption/dissipation.
Reduces component counts significantly.
Hence, using FPGA with an isolated CPU
chip often yield cost savings, miniaturized
system, and reliability.

Figure 1: ALTERA FPGA Development Board (DE2-115 T-Pad) [31].

Table 1 show the features of commercial FPGAs which could be used in any CEMs.

Table 1: Soft Processor Cores for FPGAs [32],[33]

Features Nios II 5.0 Micro-Blaze 4.0
FPGA Gate Count 26,000-72,000 30,000-60,000
FPGA Frequency 50-200MHz 50-200MHz
FPGA Datapath Width 32bits 32bits
FPGA Pipeline Stages 1-6 3
FPGA Register File 32 general purpose with 6 special 32 general purpose &
Purpose 32 special Purpose
FPGA Instruction Word 32bits 32bits
FPGA Instruction Cache Optional Optional
FPGA Hardware Multiply & Optional Optional
Divide

In this work, to achieve CEMS considering programmable-chip (SoPC) design. This

low latency FPGA design, this will require a
leverage on electronic digital automation
process (EDA) as found in [34], [35], [36],
and [37]. Figure 2 shows the proposed CAD
EDA process framework for CEMS-on-a
comprises the legacy design process used in
FPGA-device architectures. It supports the
inclusion of the processor core configuration
and software design tools.

124
The Journal of Computer Science and its Applications
Figure 2: Proposed CEMS CAD tool flow for 32 bit FPGA SoPC design
The established CEMS uses high
performance FPGA (Xilinx) variant referred
to as application specific integrated circuit
(ASIC) circuit. This is explored to achieve
efficient performance in the cloud domain.
The choice of the processor for the system
implementation is influenced by cost and
availability in the market. This work also
aims at developing an integrated framework
for soft core processor used in embedded
CEMS, (Xilinx FPGA).
4.0 CEMS DESCRIPTION
In this Section, a high speed 3 phase power
micro-grid solar utility described by [5],
serves as the application context for
125
Vol. 26, No. 2, December 2019
deployment as depicted in Figure 3.
Depending on the consumption rate of end
user n+1, the AMI collects data locally and
transmits into the cloud. As highlighted in
the work, this transmission occurs as often as
1sec or as infrequently as daily, according to
the usage of power. The collector retrieves
the data, process it or simply pass it on for
processing upstream in the cloud. The energy
data is transmitted to the utility central
collection point for processing and use by
business applications. Since the communica-
tions path is two way, signals or commands
can be sent directly to the meters, customer
premise or distribution device.
 Towards Cloud Energy Metering System With 32 Bit FPGA Device Architecture
K. C. Okafor, A. A. Obayi and O. U. Oparaku

Figure 3: Proposed Cloud Energy Management Infrastructure

5.0 SMART METER ARCHITECTURE modular and scalable in its architecture. In

Figure 4 is currently being developed for the
32 bit FPGA low latency Silicon-on-Chip
(SOC) architecture. It shows the CEMS with
TCP/IP interface. This is the core of the
CEMS. The low latency FPGA device runs
on a 32 bit microprocessor with a digital
signal processor (DSP) for handling signal
processing functions especially for power
quality measurement features. This is an
efficient feature since the multi-core
processor SOC runs on low latency shared
peripheral and memory interface bus. This
method of interconnection of resources in a
CEMS SOC makes the system design to be
the implementation phase, the CEMS SOC
will satisfy the requirements previously
highlighted in Figure 3 and 4. The CEMS
support core energy measurement and
calculation functions. Specialized co-
processor with additional peripherals for data
exchange and communication is used in this
regard. The hardware architecture supports
sufficient flash and internal memory. This
executes the real time operating system
which can support most of the commercially
available or open source protocol stacks for
Wi-Fi, Modem (2G/3G), TCP/IP, Zigbee,
Bluetooth Peripherals, Wimax, etc.

Figure 4: FPGA CEMS Architecture

126
The Journal of Computer Science and its Applications
6. SYSTEM IMPLEMENTATION
The initial model of the FPGA CEM has in
its implementation on the peripheral interface
controller (PIC). However, the CEMS
leveraging low latency Xilinx FPGA ASIC
processor as depicted in Figure 5. As
discussed by [38], two basic sensors (voltage
and current) are employed for energy
computation in Figure 5. But acquiring data
in real time from CEM meter (32 bit FPGA
Figure 5: An FPGA powered CEMS with Consumer loads
As discussed in an earlier work [5], the
energy metering and reporting features in the
FPGA based CEMS include:
 kW, kWh, kVARh, voltage, current,
power factor, frequency.
 kWh & kVARh (delivered, received,
sum, net - Instantaneous).
 Configurable demand reset date and load
profile logging interval.
 Internet connectivity via dynamically
assigned IP address or static IP address.
 Data transfer via TCP/IP RF protocol.
 CEMS sending load profile, demand and
consumption summary details.
 Low latency timing synchronization.
 Log-in to web server is authenticated.
 Data encapsulation format - XML.
 Programmable alpha-numeric meter ID
and meter serial number.
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Vol. 26, No. 2, December 2019
core) into the data-center server provides
significant benefits for Figure 3. Real-time
data provides a greater understanding of the
dynamic response characteristics of energy
usage. Acquiring real-time data enables
proactive management. Most importantly,
the system’s ability to send frequent reports
has no impact on communication costs,
unlike the telephone-modem based meters.
 Programmable demand (kW) threshold.
Meter sends email when exceeded.
 Programmable daily reporting of peak
demand, consumption and previous
month’s energy usage.
 Programmable reporting of load profile
data at end of interval or at fixed
intervals, (total kWh, last interval's kW,
voltage, current, power factor values by
phase and frequency).
 Client report data to be sent every 1 to 15
minutes or daily.
Figure 6 shows the implementation of the
CEMS with its application program interface
(API) called enterprise energy tracking
analytic cloud portal (EETACP) application.
These are built with C and JAVA languages
respectively.
 Towards Cloud Energy Metering System With 32 Bit FPGA Device Architecture
K. C. Okafor, A. A. Obayi and O. U. Oparaku

measure the energy consumption of complex

household processing tasks. Evidently, the
metering system synchronizes with the cloud
architecture whose computing resources are
leveraged to store captured datasets. Hence,
the metering system executes fast edge
computing profiling, thereby providing data-
visualization services to end-users.

Figure 7, 8 and 9 shows the Avg. Latency

time for CAMI household 1, 2 and 3
respectively. In case 1 (shown in Figure 7),
the average latencies for actual and measured
are 75% and 25% respectively.
Figure 6: CEMS Prototype test-bed environ-
ment. In case 2 and case 3, this gave 66.67% and
33.33% respectively. Clearly, the proposed
Service oriented programming approach CAMI offers lower latency for all scenarios
(SOPA) was employed in API design. Also, of energy consumption metering usage. This
the EETACP application was realized so as has been validated for over 3 case scenarios
to capture energy data from the CEMS and in this work.
store it in MySQL database server every
second based on 24 hour scale of daily
energy supply. At the hardware layer, the
CEMS was achieved using embedded digital
hardware implementation (HDEI) for Cloud
interfacing. The economic relevance of
system lies on its low cost, high performance,
security and flexibility characteristics.
Interested readers can study more about the
base-system in [4].

7. 0 EVALUATION/RESULTS
IMPLEMENTATION Figure 7. Avg. Latency time for CAMI
household 1
In the experimental setup of the CEMS,
energy consumption considering low latency
processing was investigated. This focused on
the average power consumption during four
weeks’ timeframe. A three case scenario for
household loads are metered using Figure 6.
Figure 7 shows the energy consumption
according to CAMI computing operation
discussed previously. The experiment was
conducted focusing on the energy
consumption required for all sorts of
household devices. To achieve this, various
load demands were metered while using a Figure 8. Avg. Latency time for CAMI
trans-coded resolution of 250p and 1080p to household 2
128
The Journal of Computer Science and its Applications
Figure 9. Avg. Latency time for CAMI
household 3.
Consequently, a low latency FPGA based
metering system provides satisfactory
response to energy data-stream updates. It
provides aggregate data-sets from diverse
home units while allowing data analytics at
the cloud. It can manage bandwidth sensitive
workloads during its full duplex
communication. Besides, trajectory data-
mining using location and context-aware
service provisioning is feasible.
8.0 RECOMMENDATIONS
Some few recommendations for full Cloud
based FPGA metering in any digitally
inclusive society will include:
i. Establishing strong regulatory reforms
with appropriate legal enforcements to
eradicate inefficiencies and minimize
corruption in the energy value chain.
ii. Encouraging energy Internet of Things
(e-IoT) computing service providers for
energy automation.
iii. Investing in network infrastructure for
6G/4G-LTE. The attention should be on
providing high-speed networks for
ubiquitous energy services.
iv. Training experts and end-users on the
existing IoT-edge smart metering
technologies.
v. Supporting disruptive energy
ecosystems by introducing software
defined networks (SDN) and network
129
Vol. 26, No. 2, December 2019
function virtualization (NFV). These
will reduce computational workload
across heterogeneously interconnected
devices on the metering cloud.
vi. Deployment of AMI data-centre servers
must be done in such a way as to deliver
maximum quality of service at all
layers.
vii. Training of young African digital
workforce with supports from the
industry, government and international
organizations. There is an urgent need
for training, re-training and capacity
building efforts while encouraging
policy initiatives that will facilitate
energy innovation. This should go
beyond the conventional academic
research and innovation while
expanding a vibrant ecosystem for
disruptive energy technologies, via
support of smart grid tech innovation
hubs.
9.0 CONCLUSION/FUTURE WORK
In this paper, Cloud Energy Metering System
using 32 bit FPGA device architecture is
presented. The system supports bi-directional
data communication for cost efficient AMI
system. Low latency FPGA ASIC
implementation was employed during the
design phase. The functionalities of CEMS
have been highlighted while enumerating the
benefits. This edge model is expected to
eliminate all forms of energy frauds and as
well as the corruption in the existing
metering model. The next generation AMI
will be highly dependent high performance
processing and security layers. Hence, the
next research direction will focus on:
 Investigating on AMI reliability
constraints at the Edge, Fog, and cloud,
using previous dynamic modelling efforts
in [39], [40] & [41].
 Carrying performance evaluation on both
FPGAs and embedded controllers in the
context of data acquisition latency
effects.
 Towards Cloud Energy Metering System With 32 Bit FPGA Device Architecture
K. C. Okafor, A. A. Obayi and O. U. Oparaku
10. ACKNOWLEDGEMENT
This research was carried out as an extended
work on SGEMS/EETACP project
commissioned by the Department of
Electronic Engineering, University of
Nigeria Nsukka. Many thanks to Mr. Jim
Ovia who supported this research via Nigeria
Computer Society. TETFund (FUT/DVC
(Acad.)/GEN 92/II/90) also deserves our
appreciation for partly sponsoring this work.
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