Lab Test-1

CS G553 Reconfigurable
Computing

8 Marks
Max time 2 Hrs
• Instructions
– Submit the answer only once
– Test bench is compulsory for the simulation
wherever required
– Use ModelSim student version for the simulation.
– Upload a single zip file with file name “ID_LT.ZIP”.
For example if your ID is 2020H1230153G, the file
name should be “2020H1230153G_LT.ZIP”. The zip
file should include two Verilog files (*.v) and a
screenshot of the simulation window
corresponding to the test bench in the Verilog
files.
1. Design an 8:3 priority encoder, Simulate it
using Verilog HDL (use Behavioural Modelling).
[3 Marks]
2. Design a system such that it generates a
sequence of 1101011 and also gives an output
‘1’ when it detects a pattern 1101 in the
generated sequence. The sequence detector
may be overlapping or non-overlapping,
mention your choice as a comment in the first
line of the Verilog code [5 Marks]
Write test bench