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I t d ti to
Introduction t Cortex-M
C t MC Core
COMPEL/STM Seminar
November 2010
Seminar Agenda
Overview of ST Microcontroller Portfolio
Introduction to Cortex-M Core
STM32 General Purpose Lines
Product-Line Overview (F100/F101/F103)
Walk through the main peripherals
ST Standard Peripheral Library
Live demonstration of the STM32 Value Discovery Kit
STM32 Low
Low-Power
Power Line
Product-Line Overview (L15x)
Low-Power modes and consumption
Specific Peripherals
STM32 Connectivity Line
Product-Line Overview (F105/7 & next)
Ethernet & USB Host Peripherals
Third Party Stacks
Audio Support
pp
STM32 Wireless
Product-Line Overview (W108)
RF Performances
Wireless Stacks (Zigbee, RF4CE, proprietary)
STM32 Tools
Third Party Compiler & IDE
Boards and Debuger
ST Libraries
2
Cortex-M processors
Forget traditional 8/16/32-bit classifications
Seamless architecture across all applications
pp
Every product optimised for ultra low power and ease of use
Cortex-M3 core
Harvard architecture
3-stage pipeline w. branch speculation
Thumb®-2 2 and traditional Thumb
ALU w. H/W divide and single cycle multiply
Cortex-M3 Processor
Cortex-M3 core
Configurable interrupt controller
Bus matrix
Advanced debug components
Optional MPU & ETM (Not available in STM32F10x)
Cortex-M3 Processor Overview (1/2)
ARM v7M Architecture
Thumb-2 Instruction Set Architecture
Mix of 16 and 32 bit instructions for very high code density
Harvard architecture
Separate I & D buses allow parallel instruction fetching & data storage
Integrated Nested Vectored Interrupt Controller (NVIC) for low latency
interrupt processing
Vector Table is addresses, not instructions
Designed to be fully programmed in C
Even reset, interrupts and exceptions
Integrated Bus Matrix
Bus Arbiter
Bit Banding – Atomic Bit Manipulation
W ite B
Write Buffer
ffe
Memory Interface (I&D) Plus System Interface & Private Peripheral Bus
Integrated System Timer (SysTick) for Real Time OS or other scheduled tasks
Cortex-M3 Processor Overview (2/2)
3-Stage Pipeline
Fetch,
Fetch Decode & Execute
Single Cycle Multiply
*UMULL, SMULL,UMLAL, and SMLAL are interruptible and can also complete early
d
depending
di on source values
l
Hardware Division
UDIV & SDIV (Unsigned or Signed divide)
Instruction takes between 2 & 12 cycles depending on dividend and devisor
Closer the dividend and division the faster the instruction completes
Instruction is interruptible (abandoned/restarted)
Cortex-M3 & ARM7: Comparison
ARM7TDMI-S Cortex-M3
Architecture v4T v7M
ISA Support ARM (32
(32-bit)
bit) & Thumb (16
(16-bit)
bit) Thumb-2
Thumb 2 (Merged 32/16
32/16-bit)
bit)
DATA
0 0
♦ data transfer (core/dma),
0
♦ peripheral control
1 1 1 1
CST
♦ peripheral control 1
1 1 1 00
1 1 0 1 1
0001 1 001 0 1 1 11 0 1
0
11 0 00 100 00 0 0
DMA 011 0 1 0 11 0
0 DMA 1 0
1 1
01
1 0 1 0 0
PERIPH 0 PERIPH
0 RAM FLASH 0 RAM FLASH
00
PERIPH 1 PERIPH 1
1 CORTEX-M3
DMIPS ARM966 (ARM)
ARM7TDMI (ARM)
Outstanding efficiency of 1.25 DMIPS/MHz and 1.2 CPI
ARM7TDMI (THUMB)
fCPU
THUMB2 instruction set provide 32bit performance with 16bit code density
Bit banding allows optimized code and give highest density use of SRAM
Unaligned data access supported to improve data constant and RAM utilization
long (32) long (32)
char (8)
Structure
u u char (8) long (32) …
long (32) management … long char (8) char (8) char (8)
32bit machine char (8) char (8) char (8) example int (16) long (32) …
which does Data
int (16) … long int (16)c
not support aligned long (32) char (8) int (16) long …
int (16)c char (8) … long (32)
unaligned data int (16)
long (32)
Unused (wasted) space Free space for the rest of the application
15
Debug Capabilities
Serial Wire Debugging for optimized device pin-out
More pins
M i available
il bl
JTAG SWD
for the application
Serial Wire Vi
S i l Wi Viewer for
f targeted
t t d low
l bandwidth
b d idth data
d t trace
t
♦ Using serial wire interface or dedicated bus CKout+D[3..0] for better bandwidth
♦ Triggered by embedded break and watch points
ETM capability
bilit for
f better
b tt reall time
ti debugging
d b i
♦ Instruction trace only
♦ External signal triggering capability
♦ Can be used in parallel with data watchpoint
Debugging features still kept whilst the core entered low power mode
17
Privilege, Modes and Stacks
Privileged/Non-privileged operation
Same as ARM7 Supervisor/User
18
Execution Modes
Cortex-M3 has 2 execution modes and 2 privilege levels:
Privileged User
Handler mode
An exception is being processed Handler Mode
Always privileged execution
Thread mode
No
N exception
ti iis b
being
i processed
d Thread Mode Thread Mode
19
Stacks
Cortex-M3 supports two stacks
Main Stack (initialised after reset by hardware)
Process Stack
Exceptions use main stack
Thread mode uses either the main or process stack
Firmware
Firm are selectable
The intended usage model is
OS and
dEExceptions
ti use main
i stack
t k
Threads (user processes) use the process stack
Intended
I d d to prevent user process ffrom modifying
dif i the
h main
i stack
k
Can be configured to use just one stack (reset default)
20
Exception/Interrupt Handling
Very low latency interrupt processing
Exceptions processed in Privileged operation
Interruptible LDM/STM for low interrupt latency
Automatic processor state save and restore
Provides low latency ISR entry and exit
Allows handler to be written entirely in ‘C’
23
Interrupt Response- Tail Chaining
IRQ1
Highest
IRQ2
42 CYCLES
Tail-chaining
ARM7 Cortex-M3
• 26 cycles from IRQ1 to ISR1 entered • 12 cycles from IRQ1 to ISR1 entered
•Up to 42 cycles if LSM • 12 cycles if LSM
•42 cycles from ISR1 exit to ISR2 entry •6 cycles from ISR1 exit to ISR2 entry
•16 cycles to return from ISR2 •12 cycles to return from ISR2
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Interrupt Response – Preemption
IRQ1
Highest
IRQ2
42 CYCLES
26
Interrupt Response – Late Arriving
IRQ1
Q
Highest
IRQ2
ARM7 Cortex-M3
27
Interrupt Prioritization
Each interrupt source has an 4-bit interrupt priority value
The 4 bits are divided into pre-empting priority levels and non-pre-empting
“sub-priority”
sub priority levels
The software programmable PRIGROUP register field of the NVIC chooses how
many of the 4-bits are used for “group-priority” and how many are used for “sub-
priority”
S b
Sub-priority
i it levels
l l only
l hhave an effect
ff t if the
th pre-empting
ti priority
i it llevels
l are th
the
same
Group priority is the pre-empting priority
Lower numbers are higher priority
Hardware interrupt number is lowest level of prioritization
IRQ3 is higher priority than IRQ4 if the priority registers are programmed the same
Preempting Priority
PRIGROUP Binary Point Sub-Priority
(Group Priority)
(3 Bits) (group.sub)
Bits Levels Bits Levels
011 4.0 gggg 4 16 0 0
100 3.1 gggs
ggg 3 8 1 2
101 2.2 ggss 2 4 2 4
110 1.3 gsss 1 2 3 8
111 0.4 ssss 0 0 4 16
0
16 groups all with pre-
PRIGOUP = 011 „gggg“ emption
p over lower ggroups
p
15
0
0 4 groups with each 4
3 sub-groups. Pre-
PRIGOUP = 101 „ggss“ 0 emption only across
3
groups
3
0
16 sub-groups without
PRIGOUP = 111 „ssss“ pre-emption over lower
15
sub-groups
Cortex-M3 Exception Types
y
Type of
No. Exception Type Priority Descriptions
Priority
1 Reset -3 (Highest) fixed Reset
Table size (in words) is = number of IRQ inputs + 0x14 Bus Fault
16 0x18 Usage Fault
37
Power Management
“8bit Microcontroller like” power mode management
SLEEP NOW
♦ “Wait
“W i ffor I
Interrupt”
” instructions
i i to enter low
l power mode
d
Æ No more dedicated control register settings sequence
♦ “Wait for Event” instructions to enter low power mode
Æ No need of Interruptp to wake-upp from sleep
p
Æ Rapid resume from sleep
SLEEP on EXIT
♦ Sleep request done in interrupt routine
♦ Low
L power moded entered
t d on interrupt
i t t return
t
Æ Very fast wakeup time without context saving (6 cycles)
DEEP SLEEP
♦ Long
o g duration
du a o sleep
s eep
Æ From product side: PLL can be stopped or shuts down the power to digital
parts of the system
Æ Enables low power consumption
In STM32F10x the SysTick clock can be: CPU clock or CPU clock/8
(provided externally by the Reset Clock Control )
39
Thank You !
50