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STM32 Seminar Introduction t C t M Core I t d ti to cortex-m. ARM v7M architecture Mix of 16 and 32 bit instructions for very high code density Harvard architecture Separate I and D buses allow parallel instruction fetching and data storage. Integrated Nested Vectored Interrupt Controller (NVIC) for low latency interrupt processing Vector Table is addresses, not instructions Designed to be fully programmed in C Even reset, interrupts and exceptions.
STM32 Seminar Introduction t C t M Core I t d ti to cortex-m. ARM v7M architecture Mix of 16 and 32 bit instructions for very high code density Harvard architecture Separate I and D buses al…