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9, SEPTEMBER 2009
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TORRES AND RINCÓN-MORA: BATTERY-CHARGING CMOS SYSTEM PROTOTYPE 1939
(1)
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1940 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 56, NO. 9, SEPTEMBER 2009
(8)
- (6)
and equating this to the invested energy required to precharge
where energy-transfer losses account for lower values. ( or ), as derived in (2), yields a
precharge time of
III. PROPOSED ENERGY-HARVESTING SYSTEM
(9)
A. Topology
Since inductors are quasi-lossless devices, to maximize en- which is independent of , assuming quasi-lossless energy
ergy gain, an inductor-based precharger that transfers energy transfers. Consequently, even as changes (Li Ion spans
from the battery to variable capacitor , as seen in Fig. 3, is 2.7–4.2 V across its state of charge), a constant
implemented. Inductor L is first energized by imposing battery transfers sufficient energy to . In practice,
voltage across it with switches and . Inductor cur- is set slightly higher to offset the energy losses associated with
rent consequently increases linearly until sufficient energy is the transfer.
stored, at which point switches and open and and Precharge ends as soon as capacitor voltage equals
close and channel the stored energy to . This precharge or surpasses battery voltage , when all switches turn OFF.
step occurs at maximum capacitance, just before the onset of Excess energy in the inductor returns to the battery through the
the harvesting phase. harvesting diode by charging a diode voltage above
Once is precharged, as capacitance decreases, battery and subsequently transferring the remainder through the now
clamps capacitor voltage via either a syn- forward-biased diode. It is best to minimize this extra energy
chronous switch or an asynchronous diode and the resulting to reduce the losses associated with transferring energy through
harvesting current charges the battery. Note that, while a syn- the system.
chronous switch may dissipate lower Ohmic losses (because the
voltage across its terminals is low), the energy used in the addi- B. Circuitry
tional circuitry required to synchronize it (i.e., prevent reverse The proposed energy-harvesting power-train circuit, which
current flow) offsets some, if not all, of those gains. A diode, on is comprised of the harvesting diode and precharge CMOS
the other hand, naturally conducts current only in one direction switches , and transmission gate ,
(towards the battery) so it only dissipates Ohmic losses, which, as illustrated in Fig. 4, was fabricated with the 1.5 m CMOS
given the current levels, are substantially low to begin with. As process technology available from AMI Semiconductor
a result, considering the power, risk, and complexity associated foundry. The control electronics were kept off chip for experi-
with the synchronous switch, the asynchronous diode offers a mental flexibility and ease of reach.
more appealing proposition. The system energizes inductor L when transistors and
The precharge control block illustrated in Fig. 3 senses are ON, and subsequently channels the stored energy to
when to precharge (at maximum capacitance) and variable capacitor when and transmission gate
applies the proper gate-drive signal configuration for a pre- conduct, after and are OFF. Comple-
determined inductor-energizing time . To mentary switches realize switch because
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TORRES AND RINCÓN-MORA: BATTERY-CHARGING CMOS SYSTEM PROTOTYPE 1941
Fig. 4. Complete energy-harvesting and battery-charging system prototype implementation (dimensions in m).
alone lacks gate drive to conduct enough current when the ca-
pacitor is initially discharged. Individual on-chip buffers drive
each power switch, except for , which shares its driving
signal with . The harvesting diode connecting the capac-
itor to the battery is a diode-connected NPN transistor—AMI’s
1.5 m CMOS technology offers vertical n-type BJTs.
To detect the state of , and thus determine when to
precharge it, an off-chip control circuit is used. Comparator
detects the first condition required to start the
precharge process, which is to ascertain when falls
below . The propagation delay of this comparator should
be sufficiently short to ensure the precharge phase stops before
charges above its target value , which could other-
wise incur additional losses in the system. Slope detecting com- Fig. 5. Energizing timer-circuit schematic (dimensions in m).
parator detects whether or not the second condition
is met, that rises (when starts to decrease from
its maximum value of ), by comparing with its de-energize L via , when it goes high (all switches
previous state , a delayed version of itself. That are OFF during dead time). The combined propagation delay
way, if increases (or decreases), is lower of gates , and NOR determines this dead time.
(or higher) and therefore asserts an enabling (or dis- The de-energizing switches remain ON until the first condition
abling) signal. A 5 M and 4.7 nF RC circuit implements a is no longer true, when is again greater than , at
delay of approximately 20 ms and buffer isolates which point the logic disables the timer and shuts off all MOS
and decouples from the RC circuit. The comparators in- switches.
clude some hysteresis to desensitize the circuit to glitches and The energizing time of the inductor is set with the timer
any other extraneous noise present. circuit shown in Fig. 5. Once reset and enabled by the logic
When the aforementioned conditions are met, on-chip logic block (i.e., is turned off), the circuit triggers a
controls the precharge switching sequence, including dead time cut-off signal when comparator senses that linearly
between oppositely phased digital signals to avoid transient increasing ramp voltage surpasses preset reference
shoot-through (short-circuit) power losses in the precharger voltage , the latter of which effectively sets the
switches. Logic gate AND enables a timer with signal total energizing time for the inductor. Charging on-chip capac-
and starts the energizing process of inductor L via signal itor with a constant current-source reference produces
, while is low. . The current source is realized by forcing reference
After the timer reaches its preset value, it flags the logic to voltage across resistance R via the negative
stop energizing L with signal , which forces feedback loop comprised of op-amp and transistor
to drop and, after a dead-time delay, prompts the circuit to . This reference current is subsequently mirrored and
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1942 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 56, NO. 9, SEPTEMBER 2009
B. Precharge
amplified by a factor of five (i.e., ) before channeling it
to The precharger was then tested by allowing the system to (1)
detect the conditions necessary for a precharge cycle, (2) initiate
(10) the sequence, and (3) charge variable capacitor to battery
voltage . To this end, was set at its maximum
linearly charging with a slope of capacitance point and turned. Fig. 8 shows how both conditions
for precharge are detected. First, during the reset phase, before
(11) precharge, is high because is less than or
equal to . As soon as begins to increase, which
and defining to indicates that (under charge-constrained conditions)
starts to decrease from its maximum value of
(12) switches to a high state because exceeds its delayed
version , which means the precharge sequence
initiates.
In practice, parasitic capacitors in parallel to slow the
Fig. 9(a) shows control signals and when
rising ramp rate so should be lower.
subjected to this test, the former of which instructs the system
to energize inductor L and the latter to release its stored energy
IV. EXPERIMENTAL RESULTS AND EVALUATION
to . As L is energized, (3 V) is impressed across
The power switches, gate drivers, digital logic, diode, and L [inductor voltage is shown in Fig. 9(b)], forcing an in-
part of the timer were fabricated on 1.4 mm 1.8 mm of the ductor current of 17.61 mA (on average) and resulting in an av-
2.2 mm 2.2 mm die shown in Fig. 6 using AMI’s 1.5 m erage invested energy per cycle of 1.66 nJ. This energy level
CMOS process. A 3 V supply emulated a moderately charged is greater than what is required by because it includes
Li Ion ( , whose full range normally spans 2.7–4.2 V. transfer losses that must be surmounted, as analyzed and derived
The off-chip surface-mount 4 mm 4 mm 2 mm inductor in [45]. When de-energizing L, is reversed by connecting L
package used had an inductance of roughly 10.72 H with an to , gradually releasing energy to and consequently
equivalent series resistance (ESR) of 240 m . Manually turning increasing its voltage .
a trimmer capacitor with a maximum–minimum capacitance While ’s drain capacitance is completely drained at the
range of approximately 250–60 pF, including parasitic capac- end of precharge, just after all switches turn off, remnant (ex-
itances present (measured), emulated the harvesting device cess) energy in L and ’s charged drain capacitance shifts
under vibration conditions. Although continually turning the back and forth (i.e., resonates) between L and both drain capaci-
manual capacitor to charge a battery would have been ideal, tances. LC oscillations therefore result until parasitic resistances
the process was impractical because of its nonperiodic nature present eventually dampen them completely. This excess energy
and the human element of fatigue; however, the objective of the represents an over-investment on the part of the precharge cir-
setup was to test the viability of the harvesting scheme on a per cuit. For context, consider that 10 pF of parasitic capacitance
cycle basis, not its steady-state behavior, which is the subject produces the oscillations measured when 45 pJ of excess energy
of further research. is available at 3 V, which means excess energy constitutes only
a small fraction of the average invested energy of 1.66 nJ/cycle.
A. Harvest With Direct Precharge
To prove harvesting is possible by constraining voltage, the C. System Test: Precharge and Harvest
capacitor is manually precharged and decreased. Momentarily
shorting the variable capacitor to the supply after setting it to After determining the precharger was functional, full system-
its maximum capacitance, manually precharges (i.e., prepares) level experiments were performed, verifying precharge and har-
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TORRES AND RINCÓN-MORA: BATTERY-CHARGING CMOS SYSTEM PROTOTYPE 1943
vest automatically cycled with variations in , as designed range, such as a person tapping heels at 1 Hz and a car engine
and shown experimentally in Fig. 10. The average energy per vibrating at 200 Hz [20], the proposed system, when subjected
cycle directed to the battery over 126 different sets of measure- to vibrations of 200 Hz, could gain 1.6 J every second, that is,
ments was 9.7 nJ/cycle (Fig. 10(a) is a sample run), giving a net 1.6 W of average power. (3) Manually turning the trimming
energy gain (by subtracting the investment from the har- capacitor is considerably slower than 200 Hz, demanding an
vest) of approximately 8 nJ/cycle. Fig. 10(b) illustrates the re- impractically large delay that dissipates more
sults of continually turning the trim capacitor for six consecutive energy than in actual applications. So, for instance, 12.5 pF and
cycles, harvesting a total of 63 nJ over the span of the six cycles 20 M would yield a delay nearing 250 s (i.e., 5 % of the
shown (not subtracting the corresponding investment energy). total 200 Hz cycle) and require only about 112.5 pJ/cycle. (4)
Gate drivers and controller circuit must be optimized for low
V. DISCUSSION energy.
A few comments on the results are worth mentioning at this Gate-Drive and Controller Losses: Since parts of the
point. (1) Because there is no manual (i.e., artificial) delay precharger could not be optimized for low energy because their
between the precharge phase and capacitor decreasing, physical parameters (such as transistor aspect ratios and circuit
more average energy per cycle is harvested than under the direct configuration) were preset, they were powered from a separate
(i.e., manual) precharge method. (2) Average power in these supply so that unreasonable power requirements would
measurements depends on the vibration frequency (cycles per not otherwise mislead the experimental results obtained. Un-
second ) of the system and the mechanical design of the derstanding the impact these requirements have on the energy
variable capacitor . Considering many harvested, however, is nonetheless important. To this end,
applications exhibit accelerations in the 1–500 Hz frequency multiplying the gate-oxide capacitance per unit area
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1944 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 56, NO. 9, SEPTEMBER 2009
Fig. 8. Detection of precharge conditions: (a) variable capacitor voltage V increases (its delayed version V is lower) and (b) the state detector
outputs V and V .
of the process (e.g., 1.12 fF/ m ) by the total gate area of the OFF for 4.9998 ms of 5 ms). Biasing comparator and
power switches (Fig. 4) indicates gate-drive losses from a 3 V amplifier with 25 A each from a 3 V supply only
supply are approximately 401.3 pJ/cycle. Similarly, three- and draws 30 pJ/cycle when operating for 200 ns of the 5 ms period.
four-stage gate drivers require roughly 266 pJ/cycle to drive The 2.4 mA that flows into the timer circuit (Fig. 5) would dis-
all power transistors. Collectively, gate-drive and driver losses sipate about 1.44 nJ/cycle when limited to 200 ns of the 5 ms
sum to 667.3 pJ/cycle, which means the projected net energy period. More importantly, however, further reducing its energy
gain of the harvester reduces from 8 to 7.33 nJ/cycle. is possible by decreasing to, say, 5 pF and its charging
Reducing the controller’s quiescent energy to pJ levels per current to 200 A, reducing 2.4 mA and 1.44 nJ/cycle
cycle is possible by resizing and biasing transistors to operate to 240 A and 144 pJ/cycle. In the end, when considering all
in subthreshold (given high-speed circuits are not necessary to measured and projected power losses, the proposed converter’s
process low vibration frequencies) and leveraging and duty-cy- net energy gain can be 6.9 nJ/cycle at 200 Hz.
cling already-existing circuit blocks (i.e., operate components Battery: The battery’s ESR also dissipates conduction power
only for short spurts and duel them for other functions). Com- during precharge. Just to cite an example, a commercially avail-
parators and (Fig. 4), for one, can be able Li-Ion polymer battery (from PowerStream PGE014461)
biased with 5 nA each, dissipating about 150 pJ/cycle at 200 Hz offers 200 mAh of capacity with an ESR of 180 m , which is
cycles. Precharge, for another, occurs only within a small frac- on the same order as the inductor’s ESR and therefore its im-
tion of the entire cycle (e.g., 200 ns of the 5 ms period, assuming pact on efficiency is, for all practical purposes, negligible. The
a vibration frequency of 200 Hz) so the components used to con- only other possible loss associated with the battery can be the
trol it can be disabled during the remainder of the period (e.g., electronics used to monitor the Li Ion’s state of charge during
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TORRES AND RINCÓN-MORA: BATTERY-CHARGING CMOS SYSTEM PROTOTYPE 1945
Fig. 9. Precharge waveforms: (a) inductor energizing and de-energizing control signals V and V with corresponding variable capacitor voltage
V and (b) inductor voltage V .
the charging process. Fortunately, most of the circuit can be dis- vibrations [19], [20]. The precharger and control circuitry
abled, except for a slow and relatively inaccurate voltage de- could viably boost this voltage up to the maximum allowed
tector whose purpose is to engage the rest of the circuit when process voltage, regardless of battery conditions, except doing
the Li Ion voltage is near 4 V. In other words, efficiency remains so increases complexity and controller losses.
unchanged and decreases only when the battery is near its fully Summary: The purpose of this paper (and contribution) is
charged state, at which point the system’s need for energy is less to show experimentally that the proposed prototyped circuit is
acute. able to draw energy from a variable voltage-constrained capac-
Voltage-Constrained Harvesters: Unlike in charge-con- itor. Although the controller and switches were not optimized
strained schemes, voltage-constraining harvesting capacitor in their present form for power efficiency because function-
protects the circuit from voltages that exceed the ality was more important, projections show that a net energy
breakdown limits of standard CMOS technologies [37], [38]. gain (after considering all losses) is possible. Note an impor-
Additionally, voltage-constraining with the already-ex- tant feature (and contribution) of the proposed solution is also
isting battery that is to be charged enhances integration because its ability to automatically detect when to precharge the capac-
no additional source is required. One drawback is that the itor without having to sense or measure capacitance or accu-
energy harvested is proportional to the battery’s voltage, which rately synchronize the system to capacitor variations. Finally,
means less energy is harvested at lower battery voltages. What as mentioned earlier in the paper, given the innate nature of the
is more, preferably, the constraining voltage should vary to harvester, the presented prototype also doubles as a vibration
match the harvesting electrostatic force with other mechanical sensor, increasing the functional efficiency and the packing den-
damping forces to achieve optimum energy conversion from sity of the final solution.
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1946 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 56, NO. 9, SEPTEMBER 2009
Fig. 10. System-level measurements showing variable capacitor C voltage V , harvesting current I , and extrapolated energy profile E
during (a) one complete and (b) six maximum–minimum–maximum C cycles.
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TORRES AND RINCÓN-MORA: BATTERY-CHARGING CMOS SYSTEM PROTOTYPE 1947
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1948 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 56, NO. 9, SEPTEMBER 2009
Erick O. Torres (S’05) was born and raised in San Gabriel A. Rincón-Mora (S’91–M’97–SM’01)
Juan, Puerto Rico. He received the B.S. degree from received the B.S., M.S., and Ph.D. degrees in elec-
the University of Central Florida, Orlando, FL, the trical engineering.
M.S.E.E. degree from the Georgia Institute of Tech- He worked for Texas Instruments in 1994–2003,
nology, Atlanta, GA, in 2003 and 2006, respectively, was appointed Adjunct Professor for Georgia Tech,
and also where currently he is working toward the Atlanta, GA, in 1999–2001, and became a full-time
Ph.D. degree, all in electrical engineering. faculty member in 2001. He has authored or coau-
During a six-month co-op assignment in 2006, thored five books and one book chapter, 26 patents,
he worked as a circuit design engineer with Texas over 100 scientific publications, and 26 commercial
Instrument’s Mixed-Signal Automotive group de- power management chip designs.
signing several analog circuit blocks for various Dr. Rincón-Mora is an Associate Editor for the
integrated power control unit projects. Currently, he is a Research Assistant IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS since
at the Georgia Tech Analog, Power, & Energy IC Design Lab, Georgia Insti- 2007; Circuit Design Vice Chair for IEEE’s 2008 7th International Caribbean
tute of Technology. He has been awarded several fellowships, including the Conference on Devices, Circuits and Systems (ICCDCS); Chairman of At-
Goizueta Foundation Fellowship, Georgia Tech President’s Fellowship, and lanta’s joint IEEE Solid-State Circuits Society (SSCS) and Circuits and Systems
Texas Instrument’s Analog Fellowship. His recent research interests include Society (CASS) since 2005; member of IEEE CAS-S Analog Signal Processing
low-energy analog and power IC design for energy harvesters in microscale (ASP) Technical Committee since 2003; Steering Committee Member for IEEE
self-sustaining systems. Midwest Symposium of Circuits and Systems (MWSCAS) since 2006; Tech-
nical Program Chair for IEEE 2007 Joint MWSCAS-NEWCAS in Montreal;
Technical Program Co-Chair for IEEE’s 2006 MWSCAS in Puerto Rico; Vice
Chairman of Atlanta’s IEEE SSCS-CASS in 2004; and Selection Committee
Review Panelist for the National Science Foundation (NSF) for 2003–2007. He
is a Life Member of the Society of Hispanic Professional Engineers (SHPE),
and a Professional Member of IET, U.K. He is also a member of Eta Kappa
Nu, Phi Kappa Phi, and a Life Member of Tau Beta Pi.
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