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750 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 8, NO. 6, NOVEMBER 2009
attention in the literature. Electrically, JFETs behave similarly of scalings available for MESFETs, depending on the figure-
to corresponding MOSFETs, and they also benefit from lower of-merit of interest [11], also applies to JFETs. In addition to
input capacitance and lower noise. Because of these proper- gate currents, the properties scaled and compared next include
ties, some applications have favored JFETs over MOSFETs, for the drain current, transconductance, and subthreshold current,
example, as the low-noise front ends for charge sensing ampli- estimated under the gradual channel approximation, as well as
fiers. For ICs, complementary enhancement mode silicon JFETs the gate capacitance and band-to-band tunneling. Discussions
have been investigated because of their inherently greater resis- of the principal 2-D and short-channel effects, which are largely
tance to radiation damage [9], [10]. The scaling behaviors of the similar for JFETs and MOSFETs, are given with the numerical
closely related MESFET have been studied and reported [11], as simulation results of Section III.
have complementary enhancement mode silicon MESFET tech-
nologies [12]. However, the Schottky-contact gates have much A. JFET Scaling
larger saturation current densities than p-n junction gates, and
Fig. 1 depicts the n-channel bulk JFET scaling model. All
an upper limit on channel doping to avoid gate tunneling cur-
dimensions scale by κ > 1, including the gate length L/κ and
rents prevents these devices from scaling to smaller dimensions.
width W/κ. An oxide defines the bottom of the channel, which
For JFETs, a simple, one-sided diode model can give an initial
has a metallurgical thickness of a/κ, and h/κ is the depletion
gate current density estimate. Considering a 30-nm-thick n-type
thickness into the channel. To reduce 2-D and short-channel
neutral layer doped to 5 × 1018 cm−3 at a forward bias of 0.7 V
effects, the channel will be conservatively constrained to L =
yields a current density of the order of 1 A/cm2 . This suggests
2a [14]. For numerical comparisons, the reference design has
that, at the sub-one-volt supplies planned for the near future,
a gate length of L = 50 nm, channel doping of Nd = 1.6 ×
JFET gate current densities may compete with MOSFET gate
1018 cm−3 , and gate doping of Na = 1.6 × 1019 cm−3 , which
current densities.
has a threshold voltage of approximately Vt = 250 mV. These
Section II presents a scaling analysis of enhancement mode
parameters were chosen, in part, to enable scaling to a viable
JFETs for complementary logic. A comparison to the scaling be-
10 nm gate length device with minor modifications, as discussed
havior of MOSFETs shows that the gate leakage crossover point
in Section IV.
lies somewhere between gate lengths of 20–35 nm, depending
For scaling, threshold will be defined here to occur
on the supply voltages and gate insulator. The numerical simula-
when the depletion edge coincides with the channel bottom,
tions reported in Section III examine the behavior of a simple 25
with the drain–source potential Vds = 0. Taking the gate–
nm gate length design and find electrical properties that validate
channel junction to be one-sided, this happens at h = a =
the scaling analysis and compare favorably with reported MOS-
2s (Vbi − Vg )/qNd , where Vg is the gate potential, s the
FETs. Section IV discusses the implications and opportunities
semiconductor permittivity, and q the elementary charge. The
for JFET engineering, including many of the modifications de-
built-in potential Vbi will be larger than the nonscaled applied
veloped for MOSFETs that should be applicable to JFETs, and
potentials for the enhancement mode devices under consider-
the prospects for scaling JFETs to 10 nm and below. The final
ation, and Vbi will vary only logarithmically with doping—
section summarizes the findings and conclusions of this paper.
or even more slowly for degenerately doped material. Conse-
quently, the channel doping will need to scale as ∼κ2 to ac-
II. SCALING ANALYSIS commodate the scaling of a and h. With these assumptions and
scalings, the threshold voltage
The scaling analysis presented here correlates the JFET gate
current with the gate length. This allows for comparison with qa2 Nd
corresponding MOSFET gate currents, as well as with other Vt = Vbi − (1)
2s
properties, under scaling. A good deal of MESFET scaling
analysis applies to JFETs [11]. However, the literature does will also change slowly with scaling. Designing a particular Vt
not appear to include MESFET analyses suitable for examin- entails changing both the channel thickness and doping.
ing a JFET–MOSFET gate leakage crossover point. The simple The forward gate current density depends on the doping and
JFET scaling discussed later varies the structural dimensions thus the gate length. A 1-D ideal diode model illustrates this,
and dopings under an approximate constant voltage regime. A giving a gate current density of
constant voltage scheme applies to these enhancement mode
1 Dn Dp
devices because forward diode currents limit supply voltages Jg = qn2i + (eV g /V t h − 1) (2)
κ N a Wp N d Wn
on the high end, and at the low end, OFF-state drain currents,
Ioff , limit the minimum practical values of the threshold volt- where ni is the intrinsic carrier concentration, Dn and Dp
age Vt . The voltages used in a given setting will depend on the the minority carrier diffusivities, Wn and Wp the neutral layer
figures-of-merit needed for that application. This conservative widths, and V the thermal potential. Consequently, in this model,
scaling scheme has the largest, and most problematic, dopant and neglecting that diffusivity decreases with doping, the for-
and field increases. A constant voltage scaling for the MOSFET ward gate current scales as Ig ∼ 1/κ3 . Such a 1-D model should
is also used for comparison. Other scaling regimes are possible overestimate the gate current density along the channel because
for both transistors. For example, a two-parameter generalized not all of the gate–channel interface sees the full gate volt-
scaling is common for MOSFETs [13], and the wider variety age, analogous with current crowding seen at the base–emitter
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JACKSON et al.: JUNCTION FIELD EFFECT TRANSISTORS FOR NANOELECTRONICS 751
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752 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 8, NO. 6, NOVEMBER 2009
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JACKSON et al.: JUNCTION FIELD EFFECT TRANSISTORS FOR NANOELECTRONICS 753
Fig. 4. Simulated forward drain characteristics for a 25 nm JFET. The gate Fig. 5. Simulated gate current versus gate voltage for a 25 nm JFET at V d s =
potential increases in steps of 0.1 V from 0 to 0.8 V. At V g = V d s = 0.7 V, 0.0 and 0.7 V. For V d s = 0.7 V, model runs with and without band-to-band
gm = 690 mS/mm, and gd s = 84 mS/mm. tunneling turned on show the relative contribution from tunneling.
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754 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 8, NO. 6, NOVEMBER 2009
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JACKSON et al.: JUNCTION FIELD EFFECT TRANSISTORS FOR NANOELECTRONICS 755
lateral doping gradient between the gate and drain can reduce to decrease gate leakage. For example, Fig. 2 includes gate cur-
the maximum electric field, and consequently, the tunneling, al- rent density estimates for enhancement mode GaAs JFETs using
lowing a shorter setback, and the setbacks can be asymmetric, a 1-D diode model. The curves in Fig. 2 use constant values for
with a smaller source–gate setback. the product of minority carrier diffusivity and effective intrin-
The basic enhancement mode JFET can benefit from tech- sic concentration, with nie D of 1013 cm−4 /s for electrons and
nologies developed to scale MOSFET performance without 2 × 1015 cm−4 /s for holes, because for GaAs at very high dop-
changing the gate length [32]. The raised gate can serve as ing levels, bandgap narrowing is counterbalanced by a widening
an ion implantation mask for a halo implant to reduce short- due to degeneracy effects [41]. At a given forward bias, these
channel effects. Uniaxial strain can improve mobility [33], [34]. calculations give several orders of magnitude decease in gate
Fabricating a p-channel transistor on (1 1 0) silicon can decrease current density compared to silicon devices. This suggests that
the effective mass, and thus, increase the hole current. The JFET GaAs-based JFETs could be the preferred devices for low-power
also lends itself to using higher mobility silicon germanium al- applications, which otherwise impose a minimum gate length of
loys in the channel, though material with smaller bandgaps can approximately 35 nm for silicon MOSFETs [1]. Additionally,
greatly increase the band-to-band tunneling leakage. the larger bandgap of GaAs would greatly reduce leakage from
Band-to-band tunneling in the reverse-biased gate–drain junc- band-to-band tunneling. The mobility of the channel can be
tion presents a design challenge in scaling the 25 nm device to increased by defining the channel bottom with a heterobarrier
10 nm. This problem is directly analogous, and of a similar mag- and using “modulation” or “remote” doping. Using a smaller
nitude, to the well-studied drain-to-body tunneling problem in bandgap gate could significantly reduce gate injection into the
MOSFETs [1]. For the JFET, the constant potential scaling of JFET channel, though a larger bandgap in the gate depletion
Section II indicates that the channel thickness should decrease field would still be desirable to avoid band-to-band tunneling.
from 12.5 nm to 5 nm, and the channel doping should increase to Further modifications can include using high-mobility quantum
Nd = 4.0 × 1019 cm−3 . Using the 1-D, one-sided abrupt junc- wells to define the channel, which have been shown to lead to
tion model plotted in Fig. 2, with a 0.7 V reverse bias, band-to- large transconductances [42].
band tunneling would be of the order of 100 kA/cm2 . If, instead,
a linearly graded junction model is used, then the estimate is C. Nanowire JFETs and the 10 nm Barrier
of the order of 1 kA/cm2 [21]. The tunneling measurements
Double gate and wraparound gate geometries have been in-
from Solomon et al. include data from two p+ n junctions with
vestigated for MOSFETs to control short-channel effects [32],
n dopings of Nd = 2.21 × 1019 and 9.05 × 1019 cm−3 (wafer
[43]. JFETs lend themselves to similar modifications, which
PN-BF2 Q5 and Q8) that gave tunneling currents of 3 A/cm2 and
may be necessary for scaling below the 10 nm barrier. A cylin-
70 A/cm−2 , respectively. Those data show both that the tunnel-
drical geometry has the best scaling properties for controlling
ing estimates for the JFET are conservative and that the tun-
short-channel effects [44]. Nanowires grown with a catalyst nat-
neling leakage at 10 nm may well be manageable. Generally,
urally have this geometry. They allow much greater composition
a too large leakage could in part be reduced by using a less
modulation than planar structures because the strain constraint
conservative L/a ≈ 1.5, enabled by a halo implant to control
is relaxed, and thus a greater range of electronic structure en-
short-channel effects, and allowing for a lower channel doping.
gineering [45]–[48]. Well-defined heterostructures in both the
Further reducing the doping gradient at the metallurgical junc-
radial and axial direction have been reported [48], [49]. Radial
tion also helps. For example, in the idealized limit of an undoped
heterostructures can, in principle, be used to engineer the gate
10 nm layer between the gate and channel dopings, giving an
leakage, and axial heterostructures to control the source–drain
electric field of approximately 1.7 MV/cm, the tunneling current
tunneling. Epitaxial III–V nanowires have been grown directly
would be on the order of 1 A/cm2 [1]. This dopant gradient could
on silicon [50]. Nanowire MOSFETs have been made both in
be approximated by having the peak of the channel doping occur
silicon and III–V semiconductors [51]–[54]. Schottky contacts
at the bottom of the channel, by not fully scaling the gate–drain
for the source and drain can be utilized to reduce the source
setback, and by having the gate–channel metallurgical junction
to drain leakage current, with nickel disilicide contacts to sili-
occur slightly up in the gate.
con nanowire reported [55]. However, practical nanowire JFETs
present great challenges in growth and doping control.
B. Compound Semiconductors and Heterostructures
Changing the JFET semiconductor from silicon to a III–V V. CONCLUSION
compound semiconductor can improve some device properties This paper has examined the implications of a gate leakage
and allow for a wider range of heterostructures for device en- crossover point from MOSFETs to JFETs under scaling. A sim-
gineering. The semiconductors used for JFETs include Si, SiC, ple scaling analysis suggests that a practical crossover point
GaAs, InP, GaP, and InGaAs/InP [35]–[38]. Enhancement mode lies in the vicinity of 25 nm, depending on the supply voltage
GaAs JFETs have been studied for ICs [39]. A similar semicon- and the MOSFET gate insulator being considered. Otherwise,
ductor change for MOSFETs entails developing suitable di- the analysis indicates that while the JFET drain current can be
electrics, greatly complicated by the ubiquitous interface states somewhat smaller than a similar MOSFET, the gate capacitance
at the III–V semiconductor–oxide interface [40]. The perfor- is also smaller, and other properties scale similarly to those of
mance benefits can include larger mobilities and larger bandgaps MOSFETs. Numerical simulations of a 25 nm JFET showed
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756 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 8, NO. 6, NOVEMBER 2009
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