1.

BASICS OF DIGITAL ELCTRONICS

1.0 INTRODUCTION
Number system is basis for counting various items. On hearing the world number all of us
immediately think of the familiar decimal number system with its 10 digits…. 0,1,2,3,4,5,6,7,8,9. Modern
computers communicate and operate with binary numbers which use only the digits 0 and 1.
Number systems are useful in digital computer technology. The knowledge of these systems is very
essential in designing the digital system and to perform reliable and economic arithmetic operations.
Number system is developed based on the number of symbols used. There are mainly two types
1. Non-positional number system
2. Positional number system.
Roman number is an example non positional number system. This is quite difficult to use as it has no
symbols for ‘zero’. The most widely used number system is positional number system. In this system the
position of the digit indicates the significance to be an attached to the digit. Positional number system has
RADIX or BASE.

1.1 NUMBER SYSTEMS

In general, in any number system there ins an ordered set of symbols known as digits with rules
define for performing arithmetic operations like addition, subtraction etc. A collection of these digits makes
a number which in general has two parts- Integer and Fraction, separated by a radix point (.)
DECIMAL NUMBER SYSTEM:
The most popularly known number system is Decimal number system. It has an ordered set of ten
symbols -0,1,2,3,4,5,6,7,8 and 9, known as digits. These symbols are used to specify any decimal number.
The Radix or base of this number system is 10. Any number is a collection of these digits. For ex, 1987.78
signifies a number with integer part equal to 1987 and a fractional part equal to 0.78.Integer part an
fractional part are separated by a radix point (.) or decimal point.
The digits in a number are placed side by side and each position in the number is assigned a weight.
This says that, the position of a digit with reference to the decimal point determines its value i.e.,
weight/value. The sum of all digits is multiplied by their weights gives to total number being represented.
The left most digit, which has the greatest weight is called ‘Most Significant Digit’(MSB) and the right
most digit, which has the least weight is called ‘Least Significant Digit’(LSB).

For example, 5678.9, can be represented as

i.e., 5000+600+70+8+0.9= 5678.9

The decimal number 5678.9 can be written as 5678.910where the 10 subscript indicates the radix or base.
There are some other number systems which are widely used in digital systems like microprocessors,
logic circuits, computers etc. They are Binary, Octal and Hexa-decimal number systems.
BINARY NUMBER SYSTEM:
The number system with base or radix 2 is known as binary number system. Binary system uses
only two symbols 0 and 1 to represent any number. he two symbols 0 and 1 are known as Binary Digits or
bits. It is also a positional system, that is every position is assigned a specific weight. However in binary
system weight is expressed as power of 2 as shown in fig. Ex: 110010.1012. The right most bit is known as
Least Significant Bit (LSB) and the left most bit is known as Most Significant Bit (MSB). In binary
number, a group of 4 bits is known as a ‘Nibble’ and a group of eight bits is known as ‘Byte’
OCTAL NUMBER SYSTEM:
The number system with base or Radix 8 is known as ‘Octal Number system’. The octal number
system uses 8 symbols 0,1,2,3,4,5,6 and 7 to represent numbers. Similar to decimal and binary number
system it is also a positional system and has two parts- Integer and Fractional part separated by a radix
(Octal) point (.). Every position is assigned a specific weight and is expressed as power of 8 as shown in fig.
For Ex : (6345.675)8 is an octal number.

HEXADECIMAL NUMBER SYSTEM:

The hexadecimal number system is very popular in computer uses. The base of Hexa decimal
number system is 16 which requires 16 distinct symbols to represent the numbers. These are
0,1,2,3,4,5,6,7,8,9, and alphabets A,B,C,D,E and F, where A=10, B=11, C=12, D=13, E=14, F=15. Since
numeric digits and alphabets both are used to represent the digits in this system, this is known as an
alphanumeric system. Ex: (A34.567)16 or (A34.567)H

1.2 COMPARISION OF NUMBER SYSTEMS

Radix specifies the number of digits used for corresponding number system. For Decimal number
system, Radix is 10, for Binary number system, Radix is =2 for Octal number system, the Radix is 8 and for
Hexadecimal number system, the Radix or base is 16.
The following table gives Decimals numbers 0 through 15 with their Binary, Octal and Hexadecimal
equivalents.
DECIMAL BINARY OCTAL HEXADECIMAL
0 0000 0 0
1 0001 1 1
2 0010 2 2
3 0011 3 3
4 0100 4 4
5 0101 5 5
6 0110 6 6
7 0111 7 7
8 1000 10 8
9 1001 11 9
10 1010 12 A
11 1011 13 B
12 1100 14 C
13 1101 15 D
14 1110 16 E
15 1111 17 F

1.3.1 CONVERSIONS - DECIMAL TO ANY RADIX NUMBER SYSTEM

A decimal number can be converted to any radix number by using Double-Dabble method.. Any
number consists of Integer part and Fractional part. Separate conversion steps (two steps) are followed for
integer and fractional part of the decimal number system.
 The first step is to convert integer part of decimal number to any base number system.
 The second step is to convert fractional part of decimal number to any base number system.
 The conversion of integer step is accomplished by the successive division method and the conversion
of fractional part is accomplished by successive multiplication method.
Steps for successive division method for converting integer part:
1. The given integer is divided by radix, leaves a remainder.
2. Divide the quotient obtained from the step 1 and leave a remainder.
3. Repeat the step 2 until the quotient is less than the radix number.
4. Collect the remainders from bottom to top, to get equivalent number system.
Steps for successive multiplication method for converting fractional part:
1. Multiply the decimal fraction by the radix to producing the product. From the product integer part is
whether 0 or 1. This part is separated.
2. Multiply the fractional part of the product in step 1 producing the next partial product. From the
product separate the integer part.
3. Repeat step 2 until the necessary steps.
4. Collect the all integers from top to bottom, to get the equivalent number system.

DECIMAL TO BINARY NUMBER CONVERSION:

Example: Convert (25.3125)10 into binary form.

Therefore (25.3125)10 = (11001.0101)2

DECIMAL TO OCTAL NUMBER CONVERSION

Example: Convert (143.513)10 into octal form.

Therefore (143.513)10 = (217.40651)8

DECIMAL TO HEXADECIMAL NUMBER CONVERSION

Example: Convert (10767.565)10 into hexadecimal form.

Therefore (10767.565)10 = (2A0F.90A3D70)16

1.3.2 CONVERSION - ANY RADIX NUMBER SYSTEM TO DECIMAL NUMBER
Conversion of any radix number system, to decimal number system is performed by multiplying each bit
by its positional weight (power of radix depending on the digit position) and adding the products together.
The following steps are used to convert any radix number to decimal number.
1. Write the positional weight for each bit.
2. Multiply the positional weight with the bits and write the products together.
3. Sum all the products obtained from step 2 which gives the equivalent decimal number.

BINARY TO DECIMAL NUMBER CONVERSION

Example : Convert binary number (1101.1)2 to its decimal equivalent.

Therefore (1101.1)2 = (13.5)10

OCTAL TO DECIMAL NUMBER CONVERSION

Example: Convert (567.56)8 into decimal form.

= 5 x 82 + 6 x 81 + 7 x 80 + 5 x 8-1 + 6 x 8-2
= 5 x 64+ 6 x 8 + 7 + 0.625 + 0.09375
= 320 + 48 + 7 + 0.625 + 0.09375
= (375.71875)10
Therefore (565.56)8 = (375.71875)10

HEXADECIMAL TO DECIMAL NUMBER CONVERSION

Example: Convert (56.56)16 into decimal form.

=5 x 161 + 6 x 160 + 5 x 16-1 + 6 x 16-2

=80 + 6 + 0.3125 + 0.0234375
= (86.3359375)10
Therefore (56.56)16 = (86.3359375)10
1.4 BINARY TO OCTAL & HEXA DECIMAL NUMBER & VICE VERSA
A binary number can be converted into octal number and Hexadecimal number. Similarly an Octal
number can be converted into binary and Hexadecimal number can be converted in to binary. Finally an
Octal number can be converted in to Hexadecimal and vice versa.

BINARY TO OCTAL NUMBER SYSTEM

Binary numbers can be converted into equivalent Octal numbers by making groups of three bits (23 = 8)
 For integer part: The grouping will be started from right to left i.e., LSB to MSB and replace each
group of three bits by its equivalent octal digit.
If the last group contains less than 3 bits, padding the zeros in front of the binary bit to make 3
bit group and write the equivalent octal number
 For fractional part: The grouping of three bits is started from binary point to the right.
If the last group has less than 3 bits, padding the zeros at the end to make it 3 bit group.
Example : Convert the binary number (111101100.1101)2 to Octal form.
BINARY- TO - HEXADECIMAL NUMBER SYSTEM
Binary numbers can be converted into equivalent Hexadecimal numbers by making groups of four bits
(24 = 16) since the base of the binary number is 2 and hexadecimal is 16.
 For integer part: The grouping of four bits will be started from right to left i.e., LSB to MSB and
replace each group of four bits by its equivalent Hexadecimal digit.
If the last group contains less than 4 bits, padding the zeros in front of the binary bit to make 4
bit group and write the equivalent Hexadecimal number
 For fractional part: The grouping of 4 bits is started from binary point to the right. If the last group
has less than 4 bits, padding the zeros at the end to make it 4 bit group.

Example :Convert the binary number (111101100.1101)2 to its Hexadecimal form.

OCTAL –TO- BINARY CONVERSION

Octal numbers can be converted into equivalent binary numbers by replacing each octal digit by its 3-bit
equivalent binary.
Example : Convert (756.4)8 into an equivalent binary number

Therefore (756.4)8 = (111101110.1)2

HEXA DECIMAL –TO- BINARY CONVERSION

Hexadecimal numbers can be converted into equivalent binary numbers by replacing each hexa decimal
digit by its 4-bit equivalent binary.

Example : Convert (756A.F4)16 into an equivalent binary number

Therefore (756A.F4)8 = (111010101101010.111101)2

OCTAL- TO-HEXADECIMAL CONVERSION
 The conversion of octal number into hexadecimal number can be done by converting it to binary and
then to hexadecimal. The following steps are involved for converting octal to hexadecimal number:
1. Convert the given octal number into its binary equivalent by writing 3 bit groups for each octal digit.
2. Regroup the bits into 4 bit groups
3. Replace each 4 bit group by its equivalent Hexadecimal digit.
Example : Convert (247.36)8 to equivalent Hexadecimal number.
Step 1 : Octal to Binary : (247 . 36 )8 = 010 100 111 . 011 110
= (10100111.01111)2
Step 2 : Regroup the bits into 4 bit groups (10100111.01111)2
= 1010 0111 . 0111 1000
Step 3 : Binary to Hexadecimal = ( A 7 . 7 8) 16
Therefore (247.36)8 = ( A 7 . 7 8) 16

HEXADECIMAL – TO- OCTAL

The conversion of hexadecimal number to octal number can be done by converting it into binary and
then to octal. The following steps are involved to convert hexadecimal number into octal number.
1. Convert given hexadecimal number into its binary equivalent by writing 4 bit groups for each
hexadecimal digit.
2. Regroup the bits in 3 bit group
3. Replace each 4 bit group by octal digit.
Example : Convert (A72E.BF)16 to equivalent Octal number.
Step 1 : Hexadecimal to Binary : (A72E.DF)16 = 1010 0111 0010 1110 . 1101 1111
= (1010011100101110.11011111)2
Step 2 : Regroup the bits into 3 bit groups (1010011100101110.11011111)2
= 001 010 011 100 101 110.110 111 110
Step 3 : Binary to Hexadecimal = 1 2 3 4 5 6 . 6 7 6
Therefore (A72E.DF)16 = ( 123456.676) 8

1.5 BINARY ARITHMETIC OPERATIONS

The familiar decimal arithmetic operations such as addition, subtraction, multiplication and division
can be performed on binary numbers. In fact, binary arithmetic operations are simpler than decimal
arithmetic because any binary number is a collection of only two digits 0 and 1.
BINARY ADDITION
The rules for binary addition are given in the following table. A is called Augend and B is called
addend. When A and B are 0 the sum is 0 and carry is 0 and the result is 0. When A and B are 0 and 1 the
sum is 1 and carry is 0 and the result is 1. When A and B are 1 and 0 the sum is 1 and carry is 0 and the
result is1.When A and B are 1 the sum is 0 and carry is 1 and the result is 10.

Example : Add the following binary numbers

BINARY SUBTRACTION
 The binary subtraction is performed in a manner similar to decimal subtraction. The rules for binary
subtraction are given in table. A is called Minuend and B is called Subtrahend. When A is greater than or
equal to B, Borrow = 0. When A is less than B, then Borrow =1.
0-0=0 1-1=0 1-0=1 0-1=1, with a borrow of 1

BINARY MULTIPLICATION
Binary multiplication is similar to decimal multiplication. In binary, each partial product is either zero
(multiply by 0) or exactly the same as the multiplicand (multiply by 1). The rules for multiplication are
given in table. A is called multiplicand and B is called Multiplier. In a digital circuit , the multiplication
operation is performed by repeated addition of all partial products to obtain the final product.
Example: Multiply (1011)2 by (1101)2

BINARY DIVISION
Binary division is carried out in the same manner as the decimal division.
Ex.1: Divide (11010)2 by (101)2 2. Divide (100010010)2 by (1101)2 3. Divide (100010010)2 by (1101)2

1.6 REPRESENTATION OF SIGNED NUMBERS

(USING 1’2 & 2’S COMPLEMENT METHOD)
The representation of negative numbers is also equally important. There are two ways of representing
signed numbers.
1. Signed magnitude form
2. Complement form.
SIGNED MAGNITUDE FORM: In general, plus sign is used to represent positive number and minus
sign is used to represent a negative number. However, because of hardware limitations, in computers, both
positive and negative numbers are represented with only binary digits.
In sign magnitude form an additional bit called ‘sign bit’ is placed in front of number. The sign bit is “0”
for positive numbers and it is “1” for negative numbers. Thus numbers are represented in the signed
magnitude format. Signed magnitude format for 8-bit signed number is
COMPLEMENT FORM: There are two types of complements for each radix system. They are - Radix
complement and Diminished Radix complement. The first is referred to as the r’s complement and the
second as the (r-1)’s complement.
For example, in binary system r=2 then, 2’s complement and 1’s complement are used.
In decimal number system r=10 then, 10’s complement and 9’s complement are used.
1’S COMPLEMENT REPRESENTATION
The 1’s complement of a binary number is the number that is obtained by changing all ones with
zeros and zeros with ones.
2’S COMPLEMENT REPRESENTATION
2’s (1’s) complement system is used for representing negative numbers. The 2’s complement is the
binary number that is obtained by adding 1 to the 1’s complement of the given number.
2’s complement= 1’s complement + 1.
Example: Find 1’s and 2’s complement of 10101.

Characteristics of 2’s complement numbers

1. There is one unique zero. The 2’s complement of ‘0’ is ‘0’.
2. The left most bit cannot be used to express a quantity. It is a sign bit. If it is a 1, the number is negative
and if it is 0, the number is positive.
3. For an n-bit word, which includes sign bit, there are (2n-1 -1) positive numbers and (2n-1) negative numbers
and one 0 for a total of 2n unique states.
Table : Signed binary numbers

1.7 2’S COMPLEMENT SUBTRACTION

Most digital computers do subtraction by the 2’s complement method. The advantage of performing
subtraction by the complement method is reduction in the hardware. Instead of having separate digital
circuits for addition and subtraction, only adding circuits are needed. That is, subtraction is also performed
by the adder only. Instead of subtracting one number from other, the complement of subtrahend is added to
the minuend.
The 2’s complement subtraction can be performed using the following steps:
Step 1: The number of bits in A (Minuend) & B (Subtrahend) must be same. If not, make it equal by
padding the 0’s at appropriate places.
Step 2: Find the 2’s complement of Subtrahend (B)
Step 3: Add the 2’s complement of Subtrahend to Minuend (A)
Step 4: If there is a carry ‘1’, then the result is positive and is in true form. In this case discard(ignore) the
carry.
If there is no carry (0), then the result is negative and is in 2’s complement form. In this case toget
the result take the 2’s complement of the result and put ‘-‘ sign.

Example : Subtract 101011 from 11101 using 2’s complement method.

1.8 BINARY CODES

Computers and other digital circuits process data in the binary format. Various binary codes are used
to represent data which may be numeric, alphabets or special characters. Binary codes are classified into
different types.

a) Numeric and alphanumeric codes:

Numeric codes are codes which represent numeric information. i.e. only numbers as a series of 0s and 1s.
8421 code, Excess-3 code, Gray code are numeric codes. Numeric codes used to represent decimal digits
are called Binary Coded Decimal (BCD) codes. 8421,2421,5211 are BCD codes.
Alphanumeric codes are codes used to represent alphanumeric information - characters, alphabets and
numerals. EBCDIC code and ASCII code are alphanumeric codes.
b)Weighted and non-weighted codes:
The BCD codes may be weighted codes or non-weighted codes. The weighted codes are those which
obey the position-weighted principle. Each position of the number represents a specific weight. For each
group of four bits, the sum of the weights of those positions where the binary digit is 1 is equal to the
decimal digit which the group represents. 8421,2421,84-2-1 are weighted codes. 8421 and 2421 are
called positively weighted codes and 84-2-1 and 74-2-1 are called negatively weighted codes
Non-weighted codes are codes which are not assigned with any weight to each digit position, i.e., each
digit position within the number is not assigned fixed value. Excess-3(XS-3) code and Gray code are non-
weighted codes.
c) Reflective codes:
A code is reflective when the code is self complementing. In other words, when the code for 9 is the
complement the code for 0, 8 for 1, 7 for 2, 6 for 3 and 5 for 4.
    Ex: 2421BCD, 5421BCD and Excess-3 code are reflective codes.
d) Sequential codes:
In sequential codes, each succeeding code is one binary number greater than its preceding code. This
property helps in manipulation of data.
    Ex: 8421 BCD and Excess-3 are sequential codes.
e) Error defecting and correcting codes:
Codes which allow error detection and correction are called error detecting and correcting codes.
Ex: Hamming code is the mostly commonly used error detecting and correcting code.

DIFFERENCES BETWEEN WEIGHTED AND UN-WEIGHTED CODEs

S.NO WEIGHTEDCODES NON-WEIGHTED CODES
1 Every bit in a code is assigned a specific Specific weights are not assigned to the bits.
weight.

2 BCD, 2421, 5211 are examples. Excess-3, Gray code are the examples.

3 Uses: I/O operations in digital circuits, data Uses: arithmetic operations in digital computers,
manipulation during arithmetic operations, digital calculators, shift position encoders etc…
digital voltmeters, calculators etc..

1.9 BCD (8421), EXCESS-3 & GRAY CODES

BCD CODES:
Binary Coded Decimal (BCD) is a numeric code in which each digit(0 to 9) of a decimal number is
represented by a separate group of four bits. The most common BCD code is 8421 BCD, in which each
decimal digit is represented by a 4 bit binary number. It is called 8421 because the weights associated with 4
bits are 8421 from left to right. This means that bit-3 has weight 8, bit-2 has weight 4, bit-1 has weight 2 and
bit 0 has weight 1. The 8421 BCD code is so widely used that it is common practice to refer it simply as
BCD. The table shows 4-bit 8421 BCD code is used to represent a single decimal digit.

EXCESS-3 CODE:
 Excess-3 code is modified form of BCD number. The excess-3 code can be derived from the natural
BCD by adding 3 to each coded number. For example decimal 12 can be represented in BCD as
0001 0010. Now adding 3 to each digit, the Excess-3 code is 0100 0101(12 in decimal).
 It not weighted code.
 Its self-complimenting code, means 1's complement of the coded number yields 9's complement of
the number itself.
 It was mainly used in IBM mainframe computers. Used in digital system for performing subtraction
operations.
 Table shows an Excess-3 codes to represent single decimal digit.

GRAY CODE:
 Differs from leading and following number by a single bit. i.e any two adjacent numbers differs by
only one bit. Hence it is one type of unit distance code.
 Gray code for 2 is 0011 and for 3 is 0010.
 No weights are assigned to the bit positions.
 Extensively used in shaft encoders.
 It is an example for Reflecting code and Cyclic code.
BINARY – TO - GRAY CODE CONVERSION
To convert the binary number into the Gray code, the process is as follows.
The most significant bit (MSB) in Gray is taken directly from the MSB in binary. The rest of the
Gray bits comes from a XOR operation between the precedent binary bit(b(i-1)) and the current binary bit
(b(i)). It is shown in fig.
Example : Conversion from ‘11101’ binary to its equivalent in Gray code.

Therefore (11101)2 = (10011)Gray

GRAY – TO - BINARY CONVERSION

The following process has to be adopted to convert a number given in the Gray code into equivalent
binary number.
The most significant bit (MSB) in binary is taken directly from the MSB in Gray. The rest of the
binary bits comes from a xor operation between the precedent binary bit (b(i-1)) and the current Gray bit
(g(i)). In the case shown in the figure above:
Example : Conversion from ‘10011’ Gray to its binary equivalent.

Therefore (10011)Gray = (11101)2

1.10 USE OF ALPHANUMERIC CODES

 Earlier computers were used only for the purpose of calculations i.e. they were only used as a calculating
device. But now computers are not just used for numeric representations, they are also used to represent
information such as names, addresses, item descriptions etc.
 Such information is represented using letters and symbols. Computer is a digital system and can only
deal with l's and 0’s. So to deal with letters and symbols they use alphanumeric codes.
 Alphanumeric codes, also called character codes, are binary codes used to represent alphanumeric data.
The codes write alphanumeric data, including letters of the alphabet, numbers, mathematical symbols
and punctuation marks, in a form that is understandable and process able by a computer. These codes,
are used to interface input-output devices such as keyboards, monitors, printers etc. with computer.
 The most commonly used alphanumeric codes are: ASCII, EBCDIC codes.
ASCII (American standard code for information interchange):
 The American Standard-Code for Information Interchange (ASCII) pronounced "as-kee" is a 7-bit
code based on the ordering of the English alphabets.

 The ASCII codes are used to represent alphanumeric data in computer input/output.

 Since it is a seven-bit code, it can almost represent 128 characters. These include 95 printable
characters including 26 upper-case letters (A to Z), 26 lowercase letters (a to z), 10 numerals (0 to 9)
 and 33 special characters such as mathematical symbols, space character etc. The below table lists
the 7 bit ASCII code containing the 95 printable characters.
 Ex: ASCII code for B is 1000010 (42)16

EBCDIC ( Extended Binary Coded Decimal Interchange Code):

 The Extended Binary Coded Decimal Interchange Code (EBCDIC) pronounced as "ebi-si
disk" is another frequently used code by computers for transferring alphanumeric data.
 It is 8-bit code in which the numerals (0-9) are represented by the 8421 BCD code preceded
by 1111. Since it is a 8-bit code, it can almost represent 2 8 or 256 different characters which
include both lowercase and uppercase letters in addition to various other symbols and
commands.
 EBCDIC was designed by IBM, so it is basically used by several IBM models. This code, do
not use a straight binary sequence for representing characters, as was in the case of ASCII
code.
 Since it is a 8-bit code, so it can be easily grouped into groups of 4 so as to represent in arm
of hexadecimal digits. By using the hexadecimal number system notation, the amount of
digits used to represent various characters and special characters using EBCDIC code is
reduced in volume of one is to four.
 Thus 8-bit binary code could be reduced to 2 hexadecimal digits which are easier to decode.
The table lists the EBCDIC code for certain characters.
  Read the above table as you read the graph. Suppose you want to search for EBCDIC code
for letter 'A’. To that case, the value of X 3 X2 Xl X0 bits is 0001 and value X7 X6 X5 X4 bits is
1100.
Ex: EBCDIC code for letter 'A’ is 11000001(A). & EBCDIC code for 'B' is 11000010(B).

.
1.11 IMPORTANCE OF PARITY BIT
 The simplest technique for detecting errors is that of adding an extra bit, known as the parity bit, to each
word being transmitted.
 The parity bit is an extra bit included in a binary message to make the number of 1’s either odd or even.
 The message, including the parity bit is transmitted and then checked at the receiving end for errors.
 An error is detected if the checked parity does not match with the transmitted one.
 The circuit that generates the parity bit in the transmitter called a parity generator and the circuit that
checks the parity in the receiver is called a parity checker.

 There are two types of parity- Odd parity and Even parity. For odd parity, the parity bit is set to a 0 or
a 1 at the transmitter such that the total number of 1 bits in the word including the parity bit is an odd
number. For even parity, the parity bit is set to a 0 or 1 at the transmitter such that the total number of 1
 bits in the word including the parity bit is an even number. Table shows the parity bits to be added to
transmit decimal digits 0 to 9 in the 8421 code.
 When the digital data is received, a parity checking circuit generates an error signal if the total number
of 1’s is even in an odd parity system or odd in an even parity system. This parity check can always
detect a single bit error but cannot detect two or more errors within the same word.
1.12 DIFFERENT POSTULATES IN BOOLEAN ALGEBRA
The postulates of a mathematical system form the basic assumption from which it is possible to
deduce theorems, laws and properties of the system. Boolean algebra is formulated by a defined set of
elements, together with two binary operators ‘+’ and “.”. The postulates of Boolean algebra are shown in
table.

LAWS AND THEOREMS OF BOOLEAN ALGEBRA

1.13 LOGIC GATES
Logic gates are the basic building blocks of a digital system. The electronic gate is a circuit that is
able to operate on a number of binary inputs in order to perform a particular logical function. There are just
three types of basic gates—AND, OR, NOT.
The interconnection of gates to perform a variety of logical operations using logic gates is called
logic design. The operation of a logic gate can be easily understood with the help of “Truth table”.
Truth table is a table that shows all the input-output possibilities of a logic circuit i.e., the truth table
indicates the outputs for different possibilities of the inputs.
AND GATE
 The AND gate performs logical multiplication. The logic expression is X = A.B
 The AND gate may have two or more inputs and a single output. The output of AND gates is logic 1,
only when each one of its inputs is at logic 1 state.
 The output of AND gates is logic 0, if any one of its inputs is at logic 0 state.
 Therefore the AND gate may be defined as a device whose output is 1, if and only if all its inputs
are 1. Hence the AND gate is also called as An-All-Or-Nothing gate.
 The logic symbol and the truth table of two input AND gate are shown in figure.
OR GATE
 The OR performs logical addition. The logic expression is X = A + B
 OR gate may have two or more inputs but only one output.
 The output of OR gate is logic 1, if one of its inputs is at logic 1.
 The output of OR gate is logic 0, when all the inputs are 0.
 Therefore, an OR gate may, be defined as a device whose output is 1, even if one of its input is 1.
Hence OR gate is also called as Any-Or-All Gate.
 The logic symbol and truth table of a two-input OR gate are shown in figure.

NOT GATE
 A NOT gate is also called an Inverter. i.e., it performs complement operation. X = A’
 It has only one input and only one output.
 It is a device whose output is always the complement of its input. The output of a NOT gate is ‘1’
when its input is logic ‘0’. The output of a NOT gate is ‘0’ when its input is logic ‘1’.
 The logic symbol and the truth table of an inverter is shown in figure.

1.14 UNIVERSAL LOGIC GATES

Any logic function or expression can be realized by using only NAND gates or only NOR gates.
Hence NAND and NOR gates are called Universal gates.
 NAND and NOR gates can perform all the three basic logic functions (AND,OR, NOT). Therefore,
AOI logic can be converted to NAND logic or NOR logic.
NAND GATE
 The NOT-AND operation is known as NAND operation. The NAND gate is equivalent to an AND
gate followed by a NOT gate.
 The expression for the output of the NAND gate can be written as .
 The output of NAND is logic 0 , only when all the inputs are 1.For any other combination of inputs,
the output is logic 1 level i.e., any one input is 0, the output is 1.
 The logic symbol and the truth table of two input NAND gate are shown in figure.

NOR GATE
 The NOT=OR operation is known as NOR operation. The NOR gate is equivalent to an OR gate
followed by a NOT gate.
 The expression for the output of the NOR gate can be written as .
 The output of NOR gate is logic 1 , only when all the inputs are at logic 0 level. For any other
combination of inputs, the output is a logic 0 level i.e., if any one input is ‘1’, the output is logic ‘0’.
  The logic symbol and the truth table of two input NOR gate are shown in figure.

1.15 EXCLUSIVE-OR (XOR) GATE

 The Exclusive-OR gate is a two input, one output logic circuit.
 The output of XOR gate is logic 1, when one and only one of its two inputs are at logic 1 state.
 When both the inputs are logic 0, or when both the inputs are logic 1, the output is logic 0.
 Since an X-OR gate produce an output 1 only when the inputs are not equal, it is called an “anti
coincidence gate (or) inequality detector”.
 The logic symbol and truth table of a two-input X-OR gate are shown in figure.
 If the input variables are represented by A and B, the output variable by X, the expression for the
output is written as

1.16 DE-MORGAN’S THEOREMS

De-Morgan’s theorem represents two of the most powerful laws in Boolean algebra.
Theorem 1: This law states that the complement of a sum of variables is equal to the product of the
individual complements.

That means the complement of two or more variables OR together is the same as the AND of the
complements of each of the individual variables.
Schematically, each side of this law can be represented as: NOR GATE = BUBBLED AND GATE

Theorem 2: This law states that the compliment of the product of variables is equal to the sum of their
individual compliments.

That means the compliment of two or more variables AND together, is equal to the sum of compliments of
each of the individual variables.
Schematically, each side of this law can be represented as NAND GATE = BUBBLED OR GAE
1.17 DEMORGAN’S THEOREMS – PROOF
Theorem 1: This law states that the complement of a sum of variables is equal to the product of the
individual complements. This is illustrated in the truth table.

Theorem 2: This law states that the compliment of the product of variables is equal to the sum of their
individual compliments. This is illustrated in the truth table

1.18 REALIZATION OF AND, OR, NOT USING NAND, NOR GATES

The NAND and NOR gates are known as universal gates, since any logic function can
be realized using NAND or NOR gates.
AND, OR,NOT gates using NAND gates:
NOT gate: An inverter can be made form a NAND by connecting all the inputs together and creating a
single common output as shown in fig.
AND gate : An AND gate can be generated using only NAND gates. It is generated by
simply inverting output of NAND gate as shown in fig.
OR gate: OR gate can be generated using only NAND gates as shown in fig.. The Boolean
expression for OR gate is
AND, OR,NOT gates using NOR gates:
NOT gate: An inverter can be made form a NOR gate by connecting all the inputs together and creating a
single common output as shown in fig.
OR gate : An OR gate can be generated using only NOR gates. It is generated by simply
inverting output of NOR gate as shown in fig.
AND gate: AND gate can be generated using only NOR gates as shown in fig.. The
Boolean expression for AND gate is
1.19 Simplification of Boolean Expressions Using De-Morgan’s Theorem’s :
Example 1 : Simplify the logic expression

Example 2 :Simplify the logic expression

Example 3 :Simplify the logic expression

1.20 STANDARD REPRESENTATIONS FOR LOGICAL FUNCTIONS

(SSOP & SPOS FORMS)
Logic functions are expressed in terms of logic variables. The values assumed by the logic functions
as well as logic variables are in The binary form.
In a Boolean function the variables are appeared either in complemented or un complemented form.
Each occurrence of a variable either in complemented or un complemented form is called a literal.
Any logic expressions can be expressed in the following two forms.
1. Sum Of Products (SOP) form 2. Product Of Sums(POS) form
SUM OF PRODUCTS FORM(SOP):
The Sum Of Products (SOP) expression consist of two or more product (AND) terms that are ORed
together. A product term is defined as either a literal or a product of literals. Each product term consists of
one or more literals appearing in either complemented or un complemented form.

Ex : .
PRODUCT OF SUMS FORM(POS):
The Product Of Sums or POS expression consist of two or more sum (OR) terms that are ANDed
together. A sum term is defined as either a literal or a sum of literals. Each sum term consists of one or
more literals appearing in either complemented or un complemented form.
Ex :

CANONICAL FORM – STANDARD SOP & STANDARD POS

The canonical forms are the special cases of SOP and POS forms. These are also known as
 Standard Sum Of Product (SSOP) form
 Standard Product Of Sums (SPOS) form

SSOP : If each product term in SOP form contains all the literals then the SOP form is knows as Standard
or canonical SOP form. Each individual term in Standard SOP or Canonical SOP form is called “min
term”. Therefore standard SOP form is also called min term canonical form.
Example of Standard Sum Of Product (SSOP) expression is

where “Σ” denotes sum of product.

SPOS: If each sum term in POS form contains all the literals (either in complemented or un-complemented
form), then the POS form is knows as Standard POS or Canonical POS form. Each sum term in the
standard POS form is called a “max term”. Therefore standard POS form is also called max term
canonical form.
Example of Standard Product Of Sum expression is

Where “π” denotes product of sum.

The following table gives the Min terms(mi) and Max terms(Mi) for a three variable/literal logic
function. In general for an n-variable logic function there are 2n (if n= 3, 2n = 8) min terms and 2n max terms.

1.21 WRITING BOOLEAN EXPRESSIONS FROM THE GIVEN TRUTH TABLE

 Logic expressions can be represented in truth table form. It is possible to write logic expression in
standard SOP or POS form corresponding to a given truth table.
Standard SOP form:
 The logic expression corresponding to a given truth table can be written in SSOP form by writing
one product term for each input combination that produces an output of 1.
 These product terms are ORed together to create Standard Sum of Products.
 These product terms are expressed by writing complement of variable (A’ =0)when it appears as an
input 0 and the variable itself (A=1)when it appears as an input 1.
 Consider for example the following Truth Table1.
 The product term corresponding to input combination 010, 011and 110 are ORed together. Then the
Standard sum of products form is

Standard POS form:

 The logic expression corresponding to a given truth table can also be written in SPOS form by
writing one sum term for each input combination that produces an output of “ 0”.
 These sum terms are ANDed together to create Standard Products Of Sums.
 These sum terms are expressed by writing complement of variable (A =0) when it appears as an
input “1” and the variable itself (A’=1) when it appears as an input 0.
 Consider for example the following Truth table 2.
 The sum term corresponding to input combination 010, 101and 110 are ANDed together. Then the
Standard Products of Sum form is
Drawing the logic circuit for a given logic function

1.22 KARNAUGH MAP(K-map):

The simplification of Boolean function is very important as it saves the hardware required and hence the
cost for design of specific Boolean function. Boolean expressions can be simplified by two methods.
1. Boolean algebra
2. Karnaugh map (K-map) method.
 K-map is graphical chart which contains boxes called cells. K-map method is a systematic method of
simplifying the Boolean expressions.
 Each cell represents one of 2n possible products that can be formed from ‘n’ variables. A two variable map
contains 22 = 4 cells, a three variable map contains 2 3 = 8 cells & a four variable map contains 2 4 = 16
cells as shown in fig.
 Product terms or Sum terms are assigned to the cells of K-map as shown in fig.
 Gray code is used to label the rows and columns of K-map as shown in fig.
Plotting a K-map: A given logic function can be represented on the K-map. Fig. show the K-map plotted
for a 2-variable logic function. The terms which are having output “1” have the corresponding cells marked
with 1s. the other cells are marked with 0s.
Similarly an n-variable logic function can be represented on an n-variable K-map.

GROUPING CELLS FOR SIMPLIFICATION

 Grouping technique is used simplify the Boolean function using K-map.
 Grouping is nothing but combining terms in adjacent cells. Two cells are said to be adjacent if they
conform the single change rule. i.e. there is only one variable difference between coordinates of two
cells. For example the cells for min terms ABC(7) and A’BC(3)
are adjacent.
GROUPING TWO ADJACENT CELLS (PAIR) :
 A pair is a group of two adjacent cells in a K-map. It cancels one variable in a k-map simplification.
The variable which is in complemented and un complemented form is eliminated. For example by
grouping ABC(7) and A’BC(3), A is in complemented and un complemented form, so A variable is
eliminated and the resultant product terms is BC.
 Fig shows adjacent cells (pair)
Examples of Pairs in a three variable K-map

GROUPING FOUR ADJACENT CELLS (QUAD) :

 A Quad is a group of Four adjacent cells in a K-map.
 It cancels two variables in K-map simplification. The variables which are in complemented and un
complemented form are eliminated and the variable which is common to all the cells is remain in the
product term.
 Fig shows grouping of four adjacent cells (Quad)

GROUPING EIGHT ADJACENT CELLS (OCTET) :

 Octet is a group of eight adjacent cells in a K-map.
 It cancels three variables in K-map simplification. The variables which are in complemented and un
complemented form are eliminated and the variable which is common to all the cells is remain in the
product term.
 Fig shows grouping of eight adjacent cells (Octet)
Simplifying Boolean expression Using K- Map: (SOP FORM)
 Construct the k-map for the given expression and group the 1’s in the cells.
 Each group of 1’s create a product term composed of all variables that appear in only one form either un
complemented or complemented with in the group. Variables that appear in both un complemented and
complemented form are eliminated.
 The final simplified expression is formed by summing the product terms of all the groups.

Example 1:
Using k-map simplify the following expressions to their minimum SOP form and realize using basic gates.
Y = Σm(1,3,4,6)

Example 2:

Example 3:

Simplifying Boolean expression Using K-Map: (POS FORM)

 Construct the k-map for the given expression and group the 0’s in the cells.
 Each group of 0’s create a SUM term composed of all variables that appear in only one form either un
complemented or complemented with in the group. Variables that appear in both un complemented and
complemented form are eliminated.
 The final simplified expression is formed by making Product of SUM terms of all the groups.
Example 4: Simplification of POS expression

Example 5: Simplification of POS expression

Example 6: Simplification of SOP expression

Example 7: Simplify the following expression

Assignment questions
Short answer questions
1. Convert the following
a) (38.15) 10 = (?)2 b)(101010.1011)2 =( ? )10 c) (1110011)2 = (?)16 d) (67)10 = (?)8 f)( 110010)2 = (?)H

2. Perform the following binary operations

a) 1001 + 1110 b) 1111 – 110 c) 10111 * 11 d)1100 /100

3. Perform binary subtraction using 2’s complement method.

10110101 – 10001101

4. Explain the operation of AND, OR, NOT and XOR gates using truth table.

5. Explain the operation of NAND, NOR, gates using truth table.

6. State & prove De-Morgan’s theorems.

7. Explain the use of Alphanumeric codes a) ASCII b) EBCDIC

8.Compare Weighted and Un-weighted codes.

9. Convert the (10110101)2 into Gray & Excess-3 codes

Essay questions
1..Realize AND, OR, NOT gates using NAND & NOR gates.

2. Simplify the following Boolean expression using Boolean algebra and K-map
a) Y= Σm(,2,3,5,6,7) b) Y= Σm(,2,3,5,6,7) c) Y= Σm(0,1,2,3,8,9,10,11)
 2. LOGIC FAMILIES
2.0 INTRODUCTION
In Digital Designs, primary aim is to create an Integrated Circuit (IC). Different circuit
configurations and production technologies are used during the production of digital integrated circuits.
Each of these approaches is called as specific Logic Families.
Now the idea of having different approaches or different logic families is that each ICs of same
family when fabricated will have identical electrical characteristics. The characteristics which are bound to
be identical are supply voltage range, speed of response, dissipation of power, input and output logic levels,
current sinking capability, current sourcing capability, noise margin, fan-out etc.
Digital ICs are the ones which make up the whole system. And if all the ICs are of same logic family
then they are compatible to each other and the intended logic functions are performed and the goal is
achieved. But in case ICs belonging to different logic families are used in a digital system then to ensure
compatibility interfacing techniques must be used. So, the knowledge of different logic families and use the
best combination of ICs during the design of a digital system is needed.
LEVEL (OR) SCALE OF INTEGRATION
Depending on the number of devices integrated on a substrate, the following are different levels of
Integration
Name of the group No of Transistors No of Gates Applications
Small Scale Integration Less than 100 UP TO 12 Used for educational purposes and
(SSI) interface complex digital devices.
Ex: 7400, 7412, 7432
Medium Scale Integration 100 - 1000 12-100 Used in multiplexers, de multiplexers,
(MSI) registers and counters etc.
Ex: 7490, 74121(MMV)
Large Scale Integration 1000 - 10000 100 - 1000 Used in small memory chips and
(LSI) Programmable Logic devices.
Ex: ROM & RAM ICs.
Very Large Scale More than 10000 1000 - Used in large computer memories,
Integration (VLSI) 10000 microprocessor, microcontrollers and
Digital Signal Processors.
Ex: 8085, 80386 etc.
Any integration beyond the capacity of VLSI are termed as Ultra Large Scale Integration (ULSI).
The Pentium III manufactured by INTEL belongs to this category and has more than one million (10 6)
components.

2.1CLASSIFICATION OF DIGITAL LOGIC FAMILIES

Logic families are classified into two categories. They are
1. Bipolar logic families
2. Uni polar logic families
Bipolar logic families :The main elements of a bipolar IC are diodes and transistors. In this classification
they are further divided into two types based on BJT operating mode. They are  :
1. Saturated mode
2. Non-saturated mode
In saturated logic, the transistors are driven to saturation mode, the saturated bipolar logic families are:
1. Resistor-Transistor Logic(RTL)
2. Diode Transistor Logic (DTL)
3. Direct Coupled Transistor Logic (DCTL)
4. High Transistor Logic (HTL)
5. Transistor Transistor Logic (TTL)
6. Integrated Injection Logic(IIL)
The non saturated bipolar logic families are :
1.Schottky TTL
2.Emitter coupled logic (ECL)
Resistor Transistor Logic :In RTL (Resistor Transistor Logic), all the logic are implemented using
resistors and transistors.
Advantages: 1. Less number of Transistors
Disadvantages: 1. High Power Dissipation
2. Low Fan In
Diode Transistor Logic: In DTL (Diode transistor logic), all the logic is implemented using diodes and
transistors.
Disadvantages: 1. Propagation Delay is Larger
Direct-Coupled Transistor Logic (DCTL): It is similar to (RTL) but the input transistor bases are
connected directly to the collector outputs without any base resistors.
Advantages:1. DCTL gates have fewer components
2. More economical 3. Simpler to fabricate onto integrated circuits.
Disadvantages:1. DCTL has much smaller signal levels.
2. More susceptibility to ground noise
High Threshold Logic (HTL): It is a variant of Diode–transistor logic which is used in such environments
where noise is very high.
Advantages: 1.Increased Noise Margin
2. Spike Control
3. High Noise Threshold Value
Disadvantages: 1. Slow speed .
2.High power drawn
Integrated injection logic (IIL, I2L, or I2L) : It is a class of digital circuits built with multiple collector
bipolar junction transistors (BJT). When introduced it had speed comparable to TTL yet was almost as low
power as CMOS, making it ideal for use in VLSI (and larger) integrated circuits
It is sometimes also known as merged transistor logic as it incorporates the advantages of both
MOS technology (High Density Package) and BJT technology (High speed). Use of resistors, capacitors and
inductors are completely avoided in this logic.
Advantages: 1. I2L has high noise immunity because it operates by current instead of voltage.
2. High speed 3. High Package Density
Transistor-Transistor Logic: In Transistor-Transistor logic (TTL), logic gates are built only around
transistors.TTL Logic has different sub-families-
Standard TTL, High Speed TTL Low Power TTL , Schottky TTL, Low Power Schottky TTL,
Advanced Schottky TTL, Advanced Low Power Schottky TTL, Fast Schottky
Emitter Coupled Logic :The main specialty of ECL is that it is operating in Active Region than the
Saturation Region. That is the reason for its high speed operation. The Emitters of the Transistors Q1 and Q2
are coupled together.
Advantage: High speed operation
Disadvantage: 1. Large Silicon Area 2. Large Power Consumption
Schottky TTL: It offers a speed that is about twice that offered by the high power TTL for the same power
consumption.
Uni polar logic families : MOS devices are Uni polar devices and only MOSFETs are employed in these
MOS logic circuits. The MOS logic families are 1.PMOS 2.NMOS 3.CMOS
 MOSFETs has beconme very popular for logic circuits due to highdensity of fabrication and low
power dissipation.
 When MOS devices are used in logic circuits, there can be circuits in which either only p-channel or
only n- channel devices are used. Such circuits are referred to as
 PMOS Logic
 NMOS Logic respectively.
 It is also possible to fabricate enhancement mode p-channel and n-channel MOS devices on the same
chip. Such devices are referred to as complementary MOSFETs and the logic based on these devises
is known as CMOS logic.
 The power dissipation is extremely small for CMOS and hence CMOS logic has become very
popular.
 Most of the MOS digital ICs are fabricated entirely using MOSFETs and no other components such
as resistors.
 Since the fabrication of resistors require large chip area, therefore, the ICs consisting of only
MOSFETs require much smaller chip area. This makes possible high density of fabrication, i.e.,
higher number of components per unit chip area.
Therefore, MOS logic made large scale and very large scale integration possible. A number of
microprocessors, memories and peripheral devices are available in MOS.

2.2.CHARACTERISTICS OF DIGITAL ICS

The various characteristics of Digital ICs are
1. Fan out : Fan out specifies the number of similar gates that can be driven by a gate. High Fan out is
advantageous because it reduces the need for additional drivers o drive more gates.
2. Power dissipation: This is the amount of power dissipated (consumed) in an IC. It is determined by the
current Icc, that it draws from the Vcc supply, and is given by Vcc x Icc. This power is specified in
milliwatts.
3. Propagation Delay :The speed of a digital circuit is specified in terms of propagation delay. Propagation
delay is the average transition delay time for the signal to propagate from input to output when the signals
change in value. It is expressed in ns.
4. Noise Margin: It is the maximum noise voltage added to an input signal of a digital circuit that does not
cause an undesirable change in the circuit output. It is expressed in volts.
5. Fan In : Fan in of a logic circuit is the number of inputs connected to the gate without any degradation in
the voltage level.
6. Operating temperature: All the gates or semiconductor devices are temperature sensitive in nature. The
temperature in which the performance of the IC is effective is called as operating temperature. Operating
temperature of the IC vary from 00 C to 700C for consumer and industrial applications and -550C to +
1250C for military purposes.
7.Speed- Power Product ( Figure of Merit) : It is specified by the manufacturer as a measure of the
performance of a logic circuit based on the product of propagation delay time and the power dissipation at
a specified frequency. It is also known as Figure of Merit.
Figure of Merit = Propagation delay time (ns) x Power dissipation (mW).
So it is specified in pico joules (ns x mw = PJ). A low value of speed power product is desirable.
8.Input /Output voltage level: The currents and voltages levels are specified for each logic state which are
very useful in the design of digital systems. For example 0V represents Logic 0 (Low) and 5V represents
Logic 1 (High).

2.3LOGIC LEVELS & VOLTAGE REQUIREMENTS OF TTL AND CMOS ICS

The two states of a gate are usually represented by some measurement of an electrical property: Voltage
is the most common, but current is used in some logic families. A threshold is designed for each logic
family. When below that threshold, the wire is "low", when above "high."
Most digital logic gates and digital logic systems use “Positive logic”, (Active high logic) in which a
logic level “0” or “LOW” is represented by a zero voltage, 0v or ground and a logic level “1” or “HIGH” is
represented by a higher voltage such as +5 volts.
 There also exists a complementary “Negative Logic”, (Active Low logic) system in which the values
and the rules of a logic “0” and a logic “1” are reversed. In this a logic level “1” or “HIGH” is represented
by a zero voltage, 0v or ground and a logic level “0” or “LOW” is represented by a higher voltage such as
+5 volts.
The following currents and voltages are specified which are very useful in the design of digital systems.
Voltage parameters:
 VCC: The voltage applied to the power pin(s).In most cases Vcc is the voltage the IC needs to operate at
 High-level input voltage, VIH : This is the minimum input voltage which is recognized by the gate as
logic 1 or High.
 Low-level input voltage, VIL: This is the maximum input voltage which is recognized by the gate as logic
0 or Low.
 High-level output voltage, VOH: This is the minimum voltage available at the output corresponding to
logic 1 or High.
 Low-level output voltage, VOL: This is the maximum voltage available at the output corresponding to
logic 0 or Low.
 Threshold Voltage ,VT : The voltage applied to a device which is "transition-Operated", which cause the
device to switch.
Example : For certain logic gates, the input voltage may change from 0V to 0.8 V without changing the
output level. Then the voltage 0.8V is defined as maximum low level input voltage(V IL). Similarly if the
logic 1 may change from +2V to +5V without changing the output level, then the +2V is known as
minimum high level input voltage (VIH).
Similarly in logic gates, the output voltage from 0V to 0.4 V is considered as low output.
Then the voltage 0.4V is defined as maximum low level Output voltage(V OL). Similarly the voltage from
+2.4V to +5V is considered as logic 1, then +2.4 V is known as minimum high level Output voltage (VOH).

Fig: Noise margin

Current parameters:
 High-level input current, IIH : This is the minimum current which must be supplied by a driving source
corresponding to 1 level voltage.
 Low-level input current, IIL: This is the maximum current which must be supplied by a driving source
corresponding to 0 level voltage.
 High-level output current, IOH: This is the minimum current which the gate can sink in 1 level.
 Low-level output current, IOL: This is the maximum current which the gate can sink in 0 level.
 High-level supply current, ICC (1): This is the supply current when the output of the gate is at logic 1.
 Low-level supply current, ICC (0): This is the supply current when the output of the gate is at logic (0).
Voltage requirements of TTL and CMOS ICs:
In digital logic design only two voltage levels or states are allowed and these states are generally referred
to as Logic “1” and Logic “0”, High and Low, or True and False.
 VOHmin : The minimum output voltage in HIGH state (logic '1'). V OHmin is 2.4 V for TTL and 4.9 V for
CMOS.
 VOLmax : The maximum output voltage in LOW state (logic '0'). VOLmax is 0.4 V for TTL and 0.1 V for
CMOS.
 VIHmin : The minimum input voltage guaranteed to be recognized as logic 1. V IHmin is 2 V for TTL and 3.5
V for CMOS.
 VILmax : The maximum input voltage guaranteed to be recognized as logic 0. V ILmax is 0.8 V for TTL and
1.5 V for CMOS
The following table shows the difference between the logic levels of traditional TTL and CMOS logic gates.

Device type Logic 0 Logic 1

TTL 0 to 0.8 V 2.0 to 5V (Vcc)
CMOS 0 to 1.5V 3.5 to 5V (VDD)

2.4 PROPAGATION DELAY & NOISE MARGIN

PROPAGATION DELAY: It is defined as the time required for the output of a digital circuit to change it
state after changing one or more of its inputs. The speed of a digital circuit is specified in terms of the
propagation delay time.
The delay times are measured between the 50 percent voltage levels of input and output waveforms.
There are two delay times:
tpHL: when the output goes from the HIGH state to the LOW state and
tpLH: corresponding to the output making a transition from the LOW state to the HIGH state.
The propagation delay time of the logic gate is taken as the average of these two delay times. It is shown in
fig.

NOISE MARGIN : Noise margin is a parameter closely related to the input-output voltage characteristics.
This parameter allows us to determine the allowable noise voltage on the input of a gate so that the output
will not be affected.
Stray electric and magnetic fields may induce unwanted voltages known as noise on the connecting
wires between logic circuits. This may cause the voltage at the input to a logic circuit to drop below V IH or
rise above VIL and may produce undesired operation.
The circuit’s ability to tolerate noise signals is referred to as Noise Immunity, a quantitative
measure of which is called Noise Margin. It is shown in fig.
The specification most commonly used to specify noise margin (or noise immunity) is in terms of
two parameters. 1. LOW noise margin NML 2. HIGH noised margin NMH.
NML – Noise Margin Low is defined as the difference in magnitude between the maximum LOW
output voltage of the driving gate and the maximum input LOW voltage recognized by the driven gate.
 NML (NOISE MARGIN low level) = NML = VIL – VOL
NMH - Noise Margin High is defined as is difference in magnitude between the minimum HIGH
output voltage of the driving gate and the minimum input HIGH voltage recognized by the receiving gate.
NMH (NOISE MARGIN high level ) = NMH = VOH – VIH
The noise margin defined above is dc noise margin. The ac noise margin is defined as the ability of a
logic circuit to tolerate a large noise amplitude if the noise is of very short duration. The ac noise margin is
greater than d.c noise margin.
Example : For a 4011B IC
VOH = 4.95V and VOL = 0.05V
VIH = 3.5V and VIL = 1.5V
Then NMH = VOH – VIH = 4.95 – 3.5 = 1.45 V
NML = VIL – VOL = 1.5 – 0.05 = 1.45 V
FAN-IN & FAN-OUT CAPACITY OF A DIGITAL IC.
Fan-In : Number of inputs connected to a gate is called the Fan-in of the gate. For example for a 2 input
gate, Fan-in is 2. For 4 input gate Fan-in is 4.
Gates with large Fan-in are bigger and slower. Fan in is always fixed for a gate. i.e., the no. of inputs

Fan Out : It is defined as the maximum number of logic gates that can be driven by a gate or number of
gates connected at the output of a gate
It is also knows as loading factor. Fan Out for TTL logic is around 10, that is connect more than 10
gates can be connected to an output of a TTL gate.
In CMOS it is up to 1000s of gate. A single gate is capable of driving thousands of gates but with each
gate added, its propagation delay is going to increase.
Fan out is determined by the internal design of the gate. Different logic families like TTL, CMOS,
ECL,SCHOTTKY has different fan-out for the same gate..
The Fan out depends on
 the electric current sourcing capability of the output when the output is HIGH of the logic gate
 the electric current sinking capability of the output when it is LOW.
 And it also depends on the requirements of the inputs which are to be connected with the output
of the logic gate.
Hence it depends on IOH or IOL and the Fan-out is minimum of two ratios.
Fan-Out =min(IOH/IIH,IOL/IIL)

POWER DISSIPATION
Every IC requires a certain amount of electric power to operate. This power is supplied by one or
more supply voltages connected to the power pin(s) on the chip.
The amount of power that an IC dissipates is determined by the average supply current I CC that it draws
from the VCC supply. It is the product of ICC and VCC
For many ICs, the value of ICC for a LOW gate output is higher than for a HIGH output. Therefore the
current drawn on the supply depends on the logic states of the circuits on the chip.
 Fig. Currents ICCH and ICCL
For example, in fig ICCH is the current drawn from VCC by the OR gate chip when all the gate outputs
are HIGH. Similarly, ICCL is the current drawn from VCC by the OR gate chip when all the gate outputs are
LOW. The average ICC is then determined based on 50% duty cycle operation of the gate (LOW half of
the time and HIGH half of the time.

This can be used to calculate the average power dissipation as

FIGURE OF MERIT (OR) SPEED-POWER PRODUCT

For any digital IC, it is desirable to have shorter propagation delays (High speed) and lower values of
power dissipation. Speed (propagation delay) and power consumption are the two most important
performance parameters of a digital IC. A simple means for measuring and comparing the overall
performance of an IC family is the speed-power product (the smaller, the better). It is also called Figure of
Merit.
The speed power product is computed as the product of propagation delay and average power
dissipation. Smaller the product, the better the overall performance.
Figure of Merit = Propagation delay time (ns) x Power dissipation (mW).
So, the speed power product has the units of Joules.
Example: An IC has an average propagation delay of 10 ns and an average power dissipation of 5 mW.
Then the speed-power product = (10 ns) x (5 mW) = 50 pico Joules (pJ)

2.5 OPEN COLLECTOR TTL NAND GATE

In this type of gates totem pole output stage is removed. Only transistor Q4 is present and its
collector is left open as shown in fig. Normally, an external resistor must be connected at collector. This
resistor is called as active Pull-up resistor.
The collector point of Q4 is brought out as output as shown in fig. Therefore it is called as open
collector output. For proper operation it is necessary to connect an external resistance R3 between V CC and
open collector output as shown in fig.
 Fig. Open collector TTL NAND gate Fig. Open collector TTL NAND gate with active Pull-up
Operation:
1. When any one of the inputs (or) all inputs A & B are Low, the corresponding base emitter junction of Q1
is forward biased. So Q2 remains OFF. Hence no current flows through R4. Therefore Q4 is OFF and its
collector voltage is equal to VCC i.e., Y= ‘1’.
2. When all the inputs are High, all the two base collector junctions of Q1 are reverse biased. The collector
base junction of Q1 is forward biased i.e., Q1 is Off. So Q2 will be turned ON. Sufficient voltage is
developed across R4. Base current is applied to Q4 and Q4 goes in to saturation i.e., ON. So the output
voltage is equal to VCE(sat) of Q4 thus Y=’0’.

2.6 TTL NAND GATE WITH TOTEM POLE OUTPUT

TTL is most widely used bipolar digital IC family because of its versatility and high speed
capability. TTL logic uses only transistor to perform the basic logic operation. TTL is a saturated type of
logic circuit. It uses transistor operating in saturation mode.
A two input standard TTL NAND gate has s a multiple emitter transistor for the inputs A and B. In this
the output stage consists of two active elements, Q3 and Q4. The operation of Q3 and Q4 are
complementary, that is, when one transistor is ON the other is OFF. This configuration with Q3 stacked on
top of Q4 is referred to as a totem-pole output. The transistor Q3 acts as emitter follower. A totem pole
output is used to reduce the output impedance and improve the fan out capability.
Operation:
1. If A or B is low, the base-emitter junction of Q1 is forward biased and its base-collector junction is
reverse biased. Then there is a current from V CC through R1 to the base emitter junction of Q1 and into
the Low input, which provides a path to the ground for the current. Hence there is no current into the
base of Q2 and making it into cut-off. The collector of Q2 is High and turns Q3 into saturation. Since Q3
acts as a emitter follower, but providing a low impedance path from V CC to the output, making the output
into High. At the same time, the emitter of Q2 is at ground potential, keeping Q4 OFF.
Therefore output voltage is High i.e., Y=1.
2. When A and B are High, the two input base emitter junctions of Q1 are reverse biased and its base
collector junction is forward biased. This permits current through R1 and the base collector junction of
Q1 into the base of Q2, thus driving Q2 into saturation(ON). As a result Q4 is turned ON by Q2, and
producing Low output which is near ground potential. At the same time, the collector of Q2 is
sufficiently at Low voltage level to keep Q3 OFF.
Therefore output voltage is Low i.e., Y=0.
So,when Q3 is On, the output I High and Q4 is ON the output is Low.
Without diode D1 in the circuit, Q3 conduct slightly when the output is low. To prevent this diode D1
is inserted. Its voltage drop keeps the base emitter diode of Q3 reverse biased. In this way, only Q4 conducts
when the output is low. Thus the diode D1 ensures that the transistors Q3 and Q4 conduct simultaneously.

Fig. TTL NAND gate

2.7 CMOS NAND GATE

The complementary Metal Oxide Semiconductor Field Effect Transistor (CMOS) logic uses both P
and N channel MOSFETs and hence known as CMOS. These have an extremely small dc power
dissipation, enhanced noise immunity, high fan out capacity and better compatibility with other logic
circuits. They are thus used in low power logic circuits as well as in memories.
A positive voltage of +VDD at the gate input of the NMOS FET will drive it into saturation(On),
whereas such a positive voltage at its gate will keep the PMOS FET OFF. A zero voltage input to the
NMOS will turn it OFF, while such a voltage will turn ON the PMOS.
The circuit of 2 input CMOS NAND gate is shown in fig. The transistors Q1 and Q2 are p-channel
MOSFETS and are connected in parallel with each other. Q3 and Q4 are n-channel MOSFETs and are
connected in series with each other.
With high inputs, the p-channel MOSFETs are sent into OFF condition and the n-channel MOSFETs
in to ON condition. Hence, when both the inputs A and B are high, Q1 and Q2 are in OFF state and Q3 and
Q4 in ON state. Input A is connected to gates of Q1 and Q3. Input B is connected to the gates of Q2 and
Q4.

Fig. CMOS NAND GATE

Operation:
1. When A=0 and B=0, both p-MOSFETs i.e., Q1 and Q2 will be ON and both the N-MOSFETs Q3 and
Q4 will be OFF. Therefore Y=VCC = 1.
2. When A=0 and B=1, the output is High. For A =0 the transistor Q1 is ON and Q2 is OFF. For B=0 the
transistor Q3 is OFF and Q4 is ON. Therefore Y=VCC = 1.
3. When A=1 and B=0, the output is High. For A =1 the transistor Q1 is OFF and Q2 is ON. For B=0 the
transistor Q3 is ON and Q4 is OFF. Therefore Y=VCC = 1.
4. When A=1 and B=1, both p-MOSFETs i.e., Q1 and Q2 will be OFF and both the N-MOSFETs Q3 and
Q4 will be ON. Therefore Y=0V = 0
The operation of CMOS NAND gate is shown in truth table.

2.8 COMPARISON OF TTL, CMOS & ECL LOGIC FAMILIES

S.NO PARAMETER TTL ECL CMOS
1. Basic gate NAND OR-NOR NOR –NAND
2. Fan out 10 25 20 to 50
3. Power dissipation in mW per gate 10 40-55 0.0025
4. Noise immunity Very Good Poor Very Good
5. Propagation delay in ns per gate 10 0.75 5-70
6. Speed power product (pJ) 100 100 --
7. Clock rate (MHz) for FFs 35 >60 10
8. Available functions Very High High High
2.19 IC NUMBERS OF DIGITAL IC LOGIC GATES.
S.NO
IC NUMBER(TTL) DESCRIPTION OF IC
.
1 7400 Quad 2 Input NAND gate
2 7401 Quad 2 Input NAND gate (open collector)
3 7402 Quad 2 Input NOR gate
4 7403 Quad 2 Input NOR gate (open collector)
5 7404 Hex Inverters
6 7405 Hex Inverters (open collector)
7 7408 Quad 2 Input AND gate
8 7409 Quad 2 Input AND gate (open collector)
9 7410 Triple 3 input NAND gate
10 7411 Triple 3 input AND gate
11 7420 Dual 4 input NAND gate
12 7421 Dual 4 input AND gate
13 7430 8 input NAND gate
14 7432 Quad 2 Input OR gate
15 7486 Quad 2 Input EX- OR gate
16 7432 Quad 2 Input OR gate
SNO. CMOS ICS DESCRIPTION
1. 74 C00 Quad 2 input NAND gate
2. 74 HC 00 Quad 2 input NAND gate

Assignment questions:

1. List the important characteristics of digital ICs.

2. Define Voltage levels of Digital ICs
3. Explain Propagation delay, Noise margin, Fan in, Fan out and Speed Power product.
4. Compare TTL,CMOS and ECL logic families.
5. Give the IC numbers of different ICs.
6 .Draw & explain the operation of TTL Nand gate with Totem pole output
7. Draw & explain the operation of CMOS Nand.
 3. COMBINATIONAL LOGIC CIRCUITS
3.0 INTRODUCTION
Logic circuits for digital systems may be divided into two broad categories- Combinational Circuits
and Sequential Circuits. In combinational circuits, the outputs at any instant of time depend upon the inputs
present at that instant of time. That is there is no memory in these circuits. In sequential circuits outputs are
dependent on both their present inputs and their previous output state giving them some form of Memory.
Adders, Sub-tractors, multiplexers, de-multiplexers and comparators are examples of Combinational logic
circuits.

3.1COMBINATIONAL LOGIC CIRCUITS

 Combinational Logic Circuits are made up from basic logic AND, OR and NOT gates that are
“combined” or connected together to produce more complicated switching circuits. i.e., logic gates are
the building blocks of combinational logic circuits. An example of a combinational circuit is a Decoder,
Multiplexer, Comparator etc..
 In combinational circuits, the outputs at any instant of time depend upon the inputs present at that instant
of time. That is combinational logic circuits have no feedback and no memory

 A CLC has ‘n’ inputs and ‘m’ outputs. For n inputs there are 2 n possible combinations of binary values.
For each input combination there is one output. ‘m’ Boolean functions are used to define each output
variable.
 Operation can be described by the truth table.
 It does not have clock signal and its action does not depend on clock transition.
 Combinational logic circuits can be very simple and any combinational circuit can be implemented with
only NAND and NOR gates as these are classed as “universal” gates.

3.2 HALF ADDER & ITS FUNCTION USING TRUTH TABLE
Half adder is a combinational  arithmetic circuit that adds two binary digits and produces a sum bit
(S) and carry bit (C) as the output.
If  A and B are the input bits, then Sum bit (S) is the X-OR of A and B  and the Carry bit (C) will be
the AND of A and B. From this it is clear that a half adder circuit can be easily constructed using one X-OR
gate and one AND gate.
The schematic symbol and logic circuit of a half adder are shown in the figure below.
OPERATION : The output logic expressions can be derived for the Sum and Carry outputs as a function of
inputs. It is shown in truth table.
 When A=0 & B=0, the Sum is 0 and Carry is 0.
 When A=0 & B=1, the Sum is 1 and Carry is 0.
 When A=1 & B=0, the Sum is 1 and Carry is 0.
 When A=1 & B=1 the Sum is 0 and Carry is 1.
The Sum(S) is 1 only if the input variables are not equal. Therefore the Sum can be expressed as XOR of
input variables.

Similarly the Carry is 1 only when both A and B are 1s. therefore Carry output can be expressed as AND of
input variables.
Carry = A.B

The Sum(S) is 1 only if the input variables are not equal. Therefore the Sum can be expressed as XOR of
input variables.

Similarly the Carry is 1 only when both A and B are 1s. therefore Carry output can be expressed as AND of
input variables.
Carry = A.B
So, a half adder can be constructed using and XOR gate and an AND gate as shown in fig.

3.3 HALF-ADDER USING I) NAND GATES ONLY AND II) NOR GATES ONLY
Realization of Half adder using NAND gates : A Half adder can be realized using only NAND gates as
shown in fig.
Note: Required number of NAND Gates to implement Half Adder = 5
Realization of Half adder using NOR gates : A Half adder can be realized using only NOR gates as
shown in fig.

Note: Required number of NOR Gates to implement Half Adder = 5

3.4 FULL ADDER CIRCUIT AND ITS TRUTH TABLE

A full adder is a combinational logic circuit that performs the addition of three input bits. It consists
of three inputs and two outputs. The logic symbol for full adder is shown in fig.

Fig. Logic symbol

OPERATION: The operation of full adder can be explained with the help truth table. In the truth table A,B
and Cin are the three inputs and SUM & Carry are the outputs. A and B corresponds to the bits to be added
and C is the carry from the previous position.
The output logic expressions for the full adder are

K-map simplification for SUM and Carry are given below.

Full Adder Logic circuit : Using the Logic expressions for SUM and Carry the full adder can be
constructed using basic gates as shown in fig.(a). The logic expressions can be simplified using Boolean
laws or K-maps and then the simplified logic circuit can be constructed and is shown in fig (b)
3.5 FULL-ADDER USING TWO HALF-ADDERS & AN OR GATE
A Full adder can be realized using two Half adders and an OR gate. The block schematic is shown in fig.

Fig. Block schematic of Full adder using two Half adders and OR gate
PROOF:

The above expressions suggest that Full Adder can be constructed using two Half adders and an OR gate.

Fig. Logic diagram of Full adder using Two half adders and OR gate

3.6 4 BIT PARALLEL ADDER USING FULL ADDERS

A parallel binary adder is a digital circuit that adds two n- bit binary and produces the sum of two
binary numbers in parallel.
 Addition between two Multi-bit Binary Numbers A(A 3 A2 A1 A0) and B(B3 B2 B1 B0) is done by
adding the bits successively, starting from the Least Significant Bit (LSB), i.e. P0 + Q0. Any Carry bit from
previous bits is added to the sum of the next consecutive bits.
A single full adder performs the addition of two one bit numbers and an input carry. For performing
the addition of binary numbers with more than one bit, more than one full adder is required depends on the
number bits. Thus a parallel adder is used for adding all bits of the two numbers simultaneously.

Fig. Logic diagram of 4- bit parallel adder

By connecting a number of full adders in parallel, n-bit parallel adder is constructed. From the below figure,
it is to be noted that there is no carry at the least significant position, hence use either a half adder or made
the carry input of full adder to zero at this position.
The figure below shows a parallel 4 bit binary adder which has three full adders and one half-adder.
The two binary numbers to be added are A 3A2A1A0 and B3B2B1B0 which are applied to the corresponding
inputs of full adders. This parallel adder produces their sum as C4S3S2S1S0 where C4 is the final carry.
In the 4 bit adder, first block is a half-adder that has two inputs as A 0 & B0 and produces their sum S0
and a carry bit C1. Next block should be full adder as there are three inputs applied to it. Hence this full
adder produces their sum S1 and a carry C2. This will be followed by other two full adders and thus the final
sum is C4S3S2S1S0.

3.7 2’S COMPLIMENT PARALLEL ADDER/ SUBTRACTOR

The operations of both addition and subtraction can be performed by a one common binary adder.
Such binary circuit can be designed by adding an Ex-OR gate with each full adder as shown in below figure.
The figure below shows the 4 bit parallel binary adder/sub tractor which has two 4 bit inputs as A 3 A2 A1 A0
and B3 B2 B1 B0.
The mode input control line M is connected with carry input of the least significant bit of the full adder. This
control line decides the type of operation, whether addition or subtraction.

Fig. 2’s complement Parallel adder/sub tractor

When M= 1, the circuit is a sub tractor and when M=0, the circuit becomes adder. The Ex-OR gate
consists of two inputs to which one is connected to the B and other to input M. When M = 0, B Ex-OR of 0
produce B. Then full adders add the B with A with carry input zero and hence an addition operation is
performed.
When M = 1, B Ex-OR of 1 produce B complement and also carry input is 1. Hence the
complemented B inputs are added to A and 1 is added through the input carry, nothing but a 2’s complement
operation. Therefore, the subtraction operation is performed.
In 2’s complement adder/sub tractor the final carry has no significance and is not used. Therefore S0
to S2 are sum bits and S3 is the sign bit.
In this way the circuit can be used as an adder as well as sub tractor. This simplifies the overall
hardware required to implement the arithmetic circuit.

3.8 SERIAL ADDER

A serial adder is a binary adder that can add the bits serially (one bit at a time). Serial adder is a
sequential circuit, consisting of a flip-flop and a single full adder.
At each clock cycle, it is taking the result of the previous bit addition result carry stored in the flip-
flop, calculating the sum result and storing the carry to the flip flop for the next calculation. In this manner,
the input data have to be fed serially, synchronized by the clock, and the result is read serially as well.
The numbers to be added are applied at the inputs a and b bit by bit and added along with previous
carry which is available in memory element (flip flop). At first two LSBs (0 & B0) are applied at the inputs
of the adder. It produces sum (S0) and Carry (C0).
The carry is taken and feed back in such a way that it adds to the next bits (A1 & B1) of the given
number and gives sum and carry.
This process is repeated until all the bits are added.
Example : Let us consider two 4 bit binary numbers A (1010) and B (0111). First two LSBs A0(0) and
B0(1) are applied at the inputs of Full adder. Then the sum S0 is 1 and Carry C0 is 0. The sum is sent to t
shift register and the carry is stored in Delay flip flop.
The carry is delayed and adds along with A1 (1) and B1 (1) and produces the sum S1(0) and Carry
C1(1). Similarly all the bits are added.
Serial adder is used where circuit minimization is more important than speed.

.
Fig. Serial Adder

3.9 COMPARISION BETWEEN SERIAL ADDER & PARALLEL ADDER

SERIAL ADDER
1. The bits are added serially (bit by bit)
2. Only one Full adder is required to add
n-bits
3. Delay flip flop is used to delay
feedback of present carry output as
input to next bit addition.
4. It is an example of Sequential logic
circuits
5. It is slower
PARALLEL ADDER
All the bits can be added simultaneously
N full adders are required to add ‘n’ bits
Delay flip flop is not present
It is an example of Combinational logic
circuits
It is faster
 6. It is economical It is costly
7. Circuit is simple Circuit is complex.
8. It has memory element No memory elements.

3.12 WORKING OF MULTIPLEXER

In electronics, a multiplexer (or Mux) is a combinational circuit that selects one of several analog
or digital input signals and forwards the selected input into a single line. A multiplexer of 2 n inputs has n
select lines, which are used to select which input line to send to the output.
A multiplexer is also called a data selector. Multiplexers can also be used to implement Boolean
functions of multiple variables.
An electronic multiplexer can be considered as a multiple-input, single-output switch. The schematic
symbol for a multiplexer is an isosceles trapezoid with the longer parallel side containing the input pins and
the short parallel side containing the output pin. The schematic of a 2-to-1 multiplexer and an equivalent
switch are shown in fig. The wire connects the desired input to the output
A Multiplexer is a combinational circuit which receives binary inputs from one of the 2 n input lines
and it directs these inputs to a single output. The selection of a particular input data line to the output is
decided by a set of selection inputs Sn to S0. A 2n – to – 1. Multiplexer has 2n input lines I0 to In , one output
line and n selection input lines Sn to S0. Bit combination of Selection inputs decide that which input is
directed to output. The Multiplexer or MUX is also called a data selector, because it selects one of the many
input data lines and steers the binary information to the output. A 2n – to – 1 Multiplexer is shown below.
BLOCK DIAGRAM, TRUTH TABLE AND CIRCUIT DIAGRAM

4X1 MULTIPLEXER OR 4-TO-1 MULTIPLEXER

A 4 to– 1 or 4X1 Multiplexer is combinational logic circuit with four inputs from I 0 to I4, two
selection inputs S1 and S0 and one output line Y. As there are two selection inputs therefore, they can have
only four possible combinations which are 00, 01, 10 and 11. When selection inputs are 00 the input line
I0 is selected and it is directed to output. Similarly other inputs are directed one by one to the output Y for
their combination of selection inputs. The Block Diagram of a 4 – to – 1 Multiplexer is shown below.
 The output equation of the 4X1 Multiplexer is given below.
Y = I0S’1S’0 + I1S’1S0 + I2S1S’0 + I3S1S0
The Truth Table of 4X1 multiplexer is given. When S 1 and S0 are equal to 1 and 0 the input I 1 is
joined to output. Similarly for other values of S1and S0 the remaining inputs are directed to output.
The circuit diagram of the 4 – to – 1 Multiplexer is shown here. The implementation of this circuit is
done by the help of AND Gate, OR Gate and NOT Gate. NOT Gates are used to get the complement values
of selection inputs as shown in the picture. There are four AND Gate which give four different outputs for
different values of selection inputs. The output of each AND Gate is directed as  input to OR Gate where OR
Gate gives the final output of the Multiplexer.
When both the selection lines S1 and S0 are both 0, the first AND gate is enabled and all other AND
gates are disabled. The output of first AND gate is 0, if A is 0 and 1 if A is 1. Thus Y is same as A.
In the similar manner the other combinations of the truth table can be verified.

3.13 IC NUMBERS OF TTL & CMOS MULTIPLEXER ICS

 S.No IC No. Function Output State
.
1 74150 16:1 mux. Output is inverted input
2 74151 8:1 mux. Complementary Outputs
3 74152 8:1 mux. Output is Inverted input
4 74153 Dual 4:1 mux. Output same as input
5 74157 Quad 2:1 mux. Output same as input given
6 74158 Quad 2:1 mux. Output is inverted input
7 74352 Dual 4:1 mux. Output is inverted input

3.14 APPLICATIONS OF MULTIPLEXERS

Multiplexers are used in many digital systems. Some of them are
1. Data selection and Data Routing
2. Logic function generator
3. Parallel to serial conversion
4. Operation Sequence generator.
5. Seven segment display multiplexer
6. Digital counter with multiplexed displays.
7. Waveform generation.
8. Telephone/ communication systems
9. Data acquisition systems

3.15 DEMULTIPLEXER

A de multiplexer is a combinational circuit which is having one  input, 2n outputs and n select lines.
The de multiplexer passes the binary data present on the input to any of the outputs depending  upon the
select lines. The output line in which data is passed is decided by the select line. 
De multiplexer means one to many. A de multiplexer is a circuit with one input and many output. By
applying control signal, any input can be transferred to the output. Few types of de multiplexer are 1-to 2, 1-
to-4, 1-to-8 and 1-to 16 de multiplexer.
Following figure illustrate the general idea of a de multiplexer with 1 input signal, m control signals,
and n (2m) output signals
WORKING OF 1 X 4 DE MULTIPLEXER CIRCUIT
The 1 to 4 de multiplexer has 1 input, 2 control bits, and 4 outputs. The four outputs are Y0,Y1,Y2
and Y3. The input bit is labeled as Data D. This data bit is transmitted to the data bit of the output lines. This
depends on the value of S1 and S0, the control inputs or select inputs.
De multiplexer is also called as data distributor or serial to parallel converter.

The logic symbol and truth table of 1 X 4 de multiplexer is given. From the truth table it is clear that
data input appears at output Y0 when S1=0 and S0=0 and at Y1 when S1=0 and S0=1. Similarly the data
input appears at output Y2 when S1=1 and S0=0 and at Y 3 when S1=1 and S0=1. Also from the truth table
the expressions for outputs can be written as follows.

Now using these expressions, a 1 to 4 de multiplexer can be implemented using four 3-input AND
gates and two NOT gates as shown in fig.

Fig. Logic circuit of 1 x 4 de multiplexer

When S1S0 = 00, the upper AND gate is enabled while other AND gates are disabled. Therefore,
only data bit D is transmitted to the output, giving Y0 = Data. If D is low, Y1 is low. If D is high,Y0 is high.
The value of Y0 depends upon the value of D. All other outputs are in low state.
When S1S0 = 01, the upper second AND gate is enabled while other AND gates are disabled.
Therefore, only data bit D is transmitted to the output, giving Y1 = Data. If D is low, Y1 is low. If D is
high,Y1 is high. The value of Y1 depends upon the value of D. All other outputs are in low state.
If the control input is changed to S1S0 = 10, all the gates are disabled except the third AND gate
from the top. Then, D is transmitted only to the Y2 output, and Y2 = Data.
 If the control input is changed to S1S0 = 11, all the gates are disabled except the fourth AND gate.
Then, D is transmitted only to the Y3 output, and Y3 = Data.
A decoder with data line becomes a de multiplexer
3.16 IC NUMBERS OF TTL & CMOS DE-MULTIPLEXER ICS
The 7400 series has several ICs that contain de multiplexer(s):
S.No IC No. IC No. Function Output State
. (7400) (4000)
1 74138 1:8 de mux. Output is inverted input
2 74139 Dual 1:4 de Output is inverted input
mux.
3 74154 1:16 de mux. Output is same as input
4 74155 Dual 1:4 de Output is inverted input
mux.
5 74156 Dual 1:4 de Output is open collector
mux.
6 74159 CD4514/15 1:16 de mux. Output is open collector and same as input

3.17 APPLICATIONS OF DE-MULTIPLEXER

De multiplexers are used to connect a single source to multiple destinations. These applications include
the following:
1. Communication System
2. Serial to Parallel Converter
3. Data distribution systems.
4. Security monitoring systems
5. In synchronous data transmission systems.
6. In Arithmetic and Logic Units.
7. Security monitoring systems.
8. Used as clocked de-multiplexer synchronous data systems in the receivers.
9. Digital system based displays

3.18 DECODERS
Decoder is a combinational circuit that essentially performs a reverse encoder function. The basic
function of decoder is to detect the presence of a specified combination of bits on its input and to indicate that
presence by a specified output level. In general a decodes has ‘n’ input lines to handle ‘n’ bits and 2 n output
lines. Only one of the output is high at a time. It accepts the input bits and delivers a logic 1 at any one of 2 n
outputs.
The logic symbol of a decoder is shown in fig.
Ex: 1. 3 to 8 line (Binary to Octal) decoder
2. 4 to 10 line (BCD to Decimal) decoder
3. 4 to 16 line (Binary to Hexadecimal)decoder

2 X 4 DECODER
 A 2 X 4 decoder has 2 inputs and (22) 4 outputs. In decoder only one output is high for one
combination of input and all other outputs are low. Table summarizes the operation of 2 to 4 line decoder.

The logic symbol and logic circuit are shown in fig.

When the inputs A and B are 0 then the output of Y0 AND gate is high because all inputs of Y0 gate
is high. The outputs of all other gates are low. Therefore Y0 = 1
When the inputs A=0 and B=1 the output of Y1 AND gate is high. Therefore Y1 = 1.
When the inputs A=1 and B=0 the output of Y2 AND gate is high . Therefore Y2 = 1
When the inputs A=1 and B=1 the output of Y3 AND gate is high.. Therefore Y3 = 1
Thus in decoder only one of the outputs is high for one combination of inputs and other outputs are low. It
is also called 1 of 4 decoder.

3 X 8 OR BINARY TO OCTAL DECODER

A 3X 8 decoder has 3 inputs and (2 3) 8 outputs. In decoder only one output is high for one
combination of input and all other outputs are low. TRUTH Table summarizes the operation of 3 to 8line
decoder. It is also known as Binary to Octal decoder.

The logic symbol and Logic circuit of Octal to binary decoder is shown below.
 . There are 3 inputs A B C and 8 decimal outputs Y0 to Y7.When A = 0,B=0,C=0, Y0 AND gate has all
high inputs. Therefore Y0 is high. And the remaining all AND gates have at least one low input as a result all
these AND gates have Low outputs.
Similarly when ABC = 111, the Y7 output is high. In general the subscript of high output equals the
Octal l equivalent of binary combination. From the above table each of these decoding functions is implemented
with AND gates.
The Boolean expressions for the outputs of decoder are given above.

3.19 APPLICATIONS OF DECODERS

Decoders have number of applications in digital technology.
1. They are used to convert binary data to other form 9code converters).
a. Binary to Octal converter
b. BCD to Decimal converter
c. Hexadecimal to Binary converter
d. BCD to Gray code converter.
2. Used to route the input data to a specified output line Ex: addressing a specified memory
location.
3. Used for data distribution. i.e., de multiplexing
4. Also used as building blocks in implementing logic functions.

3.20 BCD TO DECIMAL / 4X10 LINE DECODER

The 4 to 10 line decoder is also known as BCD-to-decimal decoder. This converts each BCD code word
(8421 code) in to the possible digit indications. The logic symbol and truth table of decoding functions of BCD-
to-decimal decoder is shown below.
 INPUTS OUTPUTS
A B C D Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 1 0 0 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 0 0 0 1 0 0
0 0 1 1 0 0 0 0 0 0 1 0 0 0
0 1 0 0 0 0 0 0 0 1 0 0 0 0
0 1 0 1 0 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 0 1 0 0 0 0 0 0
0 1 1 1 0 0 1 0 0 0 0 0 0 0
1 0 0 0 0 1 0 0 0 0 0 0 0 0
1 0 0 1 1 0 0 0 0 0 0 0 0 0
. There are four inputs A B C D and ten decimal outputs Y0 to Y9 on right side of logic symbol. When
A = 0,B=0,C=0 and D=0 Y0 AND gate has all high inputs. Therefore Y0 is high. And the remaining all AND
gates have at least one low input as a result all these AND gates have Low outputs.
Similarly when ABCD = 1001,the Y9 output is high. In general the subscript of high output equals the
decimal equivalent of binary combination. From the above table each of these decoding functions is implemented
with AND gates.
From the truth table Boolean expressions can be written for the outputs of decoder and are are given
below.

ENCODERS
 An encoder is a combinational logic circuit that accepts an active level on one of its inputs representing a
digit (such as decimal or octal digit) and converts it to a coded output(such as binary or BCD). Encoders also
used to encoder various symbols and alphabetic characters.
Encoder has number of input lines, but only one of the inputs is activated at a given time and
produces an N-bit output code that depends on the activated input.. The encoder allows 2 power N inputs
and generates N-number of outputs. For example, in 4-2 encoder, has 4 inputs and it produces only 2
outputs. The logic symbol of encoder is shown in fig.

4 TO 2 LINE OR 4 X 2 ENCODER
The encoder circuit is used to convert one form of data in to binary form. The input may be in
decimal , octal or hexadecimal and the output is in binary. The logic symbol, circuit and truth table of 4 X
encoder are given below.

Consider each input of encoder corresponds to each decimal digit and the output is a 2- bit binary code.
From the table we can determine the relationship between each 2-bit binary code and the decimal digits.
For instance, the MSB of 2-bit binary code, Y1 is a 1 for decimal digits 2 OR 3. Then the OR
expression for bit Y1 in terms of the decimal digits can be written as
Y1 = 2 +3
Similarly the OR expression for bit Y0 in terms of the decimal digits can be written as
Y0 = 1 + 3
The above logic expression can be implemented to obtain the logic circuitry required for encoding each
decimal digit to a 2-bit binary code. Note that the 0 digit input is not needed because the 2-bit binary code
outputs are all low, when there are no high inputs
Operation: When one of the decimal digit input is at high, the appropriate levels occurs on the 2 output lines.
When push button 0 is pressed, Y1 and Y0 OR gates have low outputs. Therefore output word is
Y1Y0 = 00 which is the binary code for decimal 0.
When push button 1 is pressed, Y1 and Y0 OR gates have low and high outputs. Therefore output word is
Y1Y0 = 01 which is the binary code for decimal 1.
When push button 2 is pressed, Y1 and Y0 OR gates have High and Low outputs. Therefore output word is
Y1Y0 = 10 which is the binary code for decimal 2.
When push button 3 is pressed, both Y1 and Y0 OR gates have High outputs. Therefore output word is
Y1Y0 = 11 which is the binary code for decimal 3.
Similarly any encoder can be constructed
3.21 DECIMAL TO BCD ENCODER / 10 TO 4 LINE ENCODER
This encoder consists of 10 input lines and 4 output lines. Each input line corresponds to the each
decimal digit and 4 outputs correspond to the BCD code.
This encoder accepts the decimal data as an input and encodes it to the BCD output which is
available on the output lines. The figure below shows the basic logic symbol of decimal to BCD encoder
along with its truth table.
The truth table represents the BCD code for each decimal digit. From the truth table the relationship
between the BCD bit and decimal digit can be determined.

From the above table, the expressions for BCD outputs are
1. Y3 is 1 for decimal digit 8 or 9.
2. Y2 is 1 for decimal digit 4 or 5 or 6 or 7.
3. Y1 is 1 for decimal digit 2 or 3 or 6 or 7.
4. Y0 is 1 for decimal digit 1 or 3 or 5 or 7 or 9.
From the above expressions, the decimal to BCD encoder
OR gates as shown in below figure
Therefore Y3 = 8 + 9
Therefore Y2 =4 + 5 + 6 + 7
Therefore Y1 = 2 + 3 + 6 + 7
Therefore Y0 = 1 + 3 +5 + 7 + 9
logic circuit can be implemented by using set of
 Fig. Logic circuit of Decimal to BCD encoder
Operation: Push button switches are used to select one of the inputs. When the switch is pressed the
corresponding input line is high and the appropriate output occurs on BCD output lines.
When push button 0 is pressed, all the OR gates have low outputs. Therefore output word is
Y3Y2Y1Y0 = 0000 which is the binary code for decimal 0.
When push button 1 is pressed, Y3,Y2, Y1 gates have low output and Y0 OR gate has high outputs.
Therefore output word is Y3Y2Y1Y0 = 0001 which is the binary code for decimal 1.
Similarly for all the decimal inputs selected the encoder gives the corresponding BCD output.
3.22 STATE THE NEED FOR TRI-STATE BUFFER /SWITCH
1. The output of a digital circuits has two states of output – Low or High. In complex digital circuits
like micro computer or microprocessor a number of gate outputs may be required to be connected
to a common line which is referred to as a bus. When a number of gate outputs are connected to a
bus, loading is increased and speed of operation will be decreased.
2. To avoid the problem of loading and speed of operation a special circuit with three states-Low,
High and High impedance(Float) states is needed. This circuit is knows as Tri-state buffer.
3. In many digital systems tri-state buffers are used to interface the buses and devices. When many
devices are interfaced to a common bus , tri state buffers are used to disconnect all devices except
the one which is communication at that time.
4. By replacing open collector outputs with tri-state buffers, the switching time needed to change the
output state is reduced.

3.23 TYPES OF TRI-STATE BUFFERS & IC NUMBERS

There are two types of tri-state buffers.
1. Active High (Normally open) tri-state buffer
2. Active Low (Normally closed) tri-state buffer
Active High (Normally open) tri-state buffer: In this normally the buffer is open when the enable is 0 and
closed when the Enable is 1. So the input(Low or High) is transferred to the output when enable is 1. The
symbol and truth table of Active High Enable buffer is given in fig. Ex : 74126 is quad tri-state active high
enable buffer.
Active Low (Normally closed) tri-state buffer: In this normally the buffer is closed when the enable is 0
and open when the Enable is 1. So the input(Low or High) is transferred to the output when enable is 0 or
disable. The symbol and truth table of Active Low Enable buffer is given in fig. Ex : 74125 is quad tri-
state active Low enable buffer.

OPERATION OF TRISTATE BUFFER

Below figure shows the circuit diagram of the tri-state buffer. The data to be transferred is given at D in
and the output is taken at the emitter of transistor T3 (Dout).
The enable input is used to close or open the switch. When the enable is low (logic 0), the transistor T1
will be in cutoff condition. This sends the transistor T2 in to saturation pulling the base voltage to T 3 to
ground. This opens the base to emitter junction of transistor T3. As a result Dout floats or no data is
transferred.
When the enable is high (logic 1), the transistor T1 will be in saturation. Thus the collector voltage
decreases and sends the transistor T2 in to off condition. The transistor T3 now acts as an emitter follower.
Therefore, its output is High or Low depending upon the input Din. Therefore this circuit now acts as a
closed switch.

3.24 USE OF TRI-STATE BUFFER IN DIGITAL CIRCUITS

 1. Totem pole outputs for TTL or active pull up/pull down outputs for CMOS can not be connected
together because of very large current drain from power supply and then damage the ICs. So tri-state
logics are used in digital circuits.
2. Open-collector outputs can be connected together with a common collector (drain) - resistor
connected externally. This causes problem of loading and speed of operation.
3. The TSL has ability to multiplex many functions economically.
4. Tri state Logic also take the advantage of high speed operation of active pull up/pull down output
arrangement , while allowing outputs to be connected together to share a common bus.
So tri-state logic is used in digital circuits.

3.25 DIGITAL COMPARATORS

A magnitude digital comparator is a combinational circuit that compares two digital or binary
numbers (consider A and B) and determines their relative magnitudes in order to find out whether one
number is equal, less than or greater than the other digital number.
Three binary variables are used to indicate the outcome of the comparison as A>B, A<B, or A=B.
The below figure shows the block diagram of a n-bit comparator which compares the two numbers of n-bit
length and generates their relation between themselves.

These comparators can compare 2-bit, 4-bit and 8-bit numbers depending on the application requirement.
These are available in TTL as well as CMOS logic family ICs and some of these ICs include IC 7485 (4-bit
comparator), IC 4585 (4-bit comparator in CMOS family) and IC 74AS885 (8-bit comparator).

1-BIT SINGLE BIT MAGNITUDE COMPARATOR

A comparator used to compare two bits, i.e., two numbers each of single bit is called a single bit
comparator. It consists of two inputs for allowing two single bit numbers and three outputs to generate less
than, equal and greater than comparison outputs.
The figure below shows the block diagram of a 1-bit or single bit magnitude comparator. This
comparator compares the two bits and produces one of the 3 outputs as (A<B), (A=B) and (A>B).
 The truth table for the single bit comparator is given below. When A0 B0 = 00 & 11, both inputs are
equal, therefore A=B output will be high. When A0 B0 = 01, B is more than A and hence AB is active.
From the truth table logical expressions for each output can be expressed as

By using these Boolean expressions a logic circuit can be implemented for this comparator using two
AND gates, one NOT gate and one Ex-NOR gate as shown in below figure. AND gates are used to find
whether a binary digit is less than greater than another bit whereas Ex-NOR gate is used to find whether two
binary numbers are equal or not.
In the figure, one AND gate has inputs of A0 (B0) ̅ and another has inputs (A0) ̅ B0. Therefore, one
AND gate output is 1 if A0 > B0 (i.e., A0 =1 and B0 =0) and is zero if A0 < B0 (i.e., A0 =0 and B0 =1).
Similarly, other AND gate output is one if A0 < B0 (i.e., A0 =0 and B0 =1) and is zero if A0 > B0 (i.e., A0
=1and B0 =0).
The Ex-NOR gate has inputs A0 B0, hence the output of the Ex-NOR gate will be 1 if A0 = B0 and
the output will be 0 if A0 is not equal to B0.

2-BIT COMPARATOR

A 2-bit comparator compares two binary numbers, each of two bits and produces their relation such
as one number is equal or greater than or less than the other. The figure below shows the block diagram of a
two-bit comparator which has four inputs and three outputs.
The first number A is designated as A = A1A0 and the second number is designated as B = B1B0.
This comparator produces three outputs as A>B, A=B and A<B.
 The truth table of this comparator is shown below which depicting various input and output states.

The k-map simplification for the above truth table is as follows.

From the above k-map simplification, each output can be expressed as

By using above obtained Boolean equation for each output, the logic diagram can be implemented by
using four NOT gates, seven AND gates, two OR gates and two Ex-NOR gates.
The figure below shows the logic diagram of a 2-bit comparator using basic logic gates.
 Fig. Logic circuit of a 2-bit comparator

2-BIT COMPARATOR ( METHOD 2)

The logic for 2-bit magnitude comparator is given below. Let the two numbers to be compared are A
(A1A0) and B (B1B0).
1. A will be greater than B when any one of the following conditions is satisfied.
a. If A1 > B1 i.e., A1 =1 and B1 = 0 irrespective of other bits
b. If A1 = B1 and A0 >B0 i.e., A0 = 1 and B0 =0
2. A will be less than B when any one of the following conditions is satisfied.
a. If A1 <> B1 i.e., A1 =0 and B1 = 1 irrespective of other bits
b. If A1 = B1 and A0 <B0 i.e., A0 = 0 and B0 =1
3. A will be equal to B when the following conditions is satisfied.
If A1 = B1 and A0 = B0
To represent these conditions in the form of truth table, it requires 16 combination and hence a function
table is given below.

In the function table ‘X’ indicates don’t care condition. From the function table, the expression for
A>B, A=B and A <B can be written and shown in table. Then the logic circuit can be constructed using
various logic gates as shown in fig.
 Fig. Logic circuit of a 2-bit comparator

APPLICATIONS OF ENCODERS
Encoders are used to convert data from any form to binary form. They are used as
1. Decimal to binary (BCD) converters
2. Octal to Binary converters
3. Hexadecimal to binary converters.
4. Used to drive seven segment displays
5. Key board encoders.

Assignment questions
1. List the applications of encoders, decoders, multiplexers and de mux.
2. State the need for tri-state buffer.
3. Explain the working of 4 x 1 mux
4. Explain the working of 1 x 4 de mux
5. Explain the working of encoders and decoders
6. Explain the working of Comparator.
 4. SEQUENTIAL LOGIC CIRCUITS

4.0UNDERSTAND THE WORKING OF SEQUENTIAL LOGIC CIRCUITS.

A combinational circuit does not have memory as its output is determined only by the present input
but the output state of a “sequential logic circuit” is a function of the following three states, the “present
input”, the “past input” and/or the “past output”. The previous inputs and outputs are saved in memories.
 Simple sequential logic circuits can be constructed from standard Bi-stable circuits such as: Flip-
flops, Latches and Counters. 
The memory elements used in sequential logic circuits are Flip Flops
Comparison between Combinational and Sequential Logic circuits

S.No. Combinational Circuit Sequential Circuit

1. It contains no memory elements It contains memory elements
2. The present value of it’s outputs are The present value of outputs are
determined solely by the present values of determined by the present value of inputs
it’s inputs and past state outputs.
3. It’s behavior is described by the set of It’s behavior is described by the set of
output functions next-state(memory) functions and the set
of output functions
4. Easy to design Harder to design.
5. Basic building blocks are logic gates Basic building blocks are Flip flops.
6. Ex : Adders, Multiplexers, De Ex: Registers and Counters
multiplexers, comparators etc.,

4.1. Explain the concept of Sequential logic circuits.

Sequential logic circuits are those in which present value of output depends on the present value of
input as well as previous value of output. The block diagram of SLC is shown in fig.

Fig. Sequential Logic Circuit

The features of SLC are
1. It has one or more inputs and one or more outputs.
2. The output is determined by the present values of inputs as well as past values of outputs.
3. It has a memory
4. One or more feed back paths from output to input.
5. SLC operation can be described by the truth table and timing diagram
6. Basic building blocks of SLC are Flip flops.
EX: Counters and Shift registers.
Types of Sequential Logic Circuits
 There are two types of sequential circuits, 
i) Synchronous Sequential Circuits
ii) Asynchronous Sequential Circuits
Synchronous Sequential Logic Circuits (SSLC):The sequential circuits which are controlled by clock are
called SSLC. These circuits will be active only when the clock signal is present. Ex : Flip flop
Asynchronous Sequential Logic Circuits (ASLC): The sequential circuits which are not controlled by
clock are called ASLC. Ex : Latch (Un clocked flip flop).
Comparison between SSLC and ASLC
Synchronous Sequential Logic Circuits Asynchronous Sequential Logic Circuits
1. SSLCs depend on external clock pulses for state 1. ASLCs does not depend on external clock
transitions. pulses for state transitions.
2. In this memory elements are clocked Flip flops. 2. The memory elements are Un clocked Flip
3. These are slower. flops.
4. Easy to design 3. These are faster.
5. High cost. 4. Difficult to design
6. More hardware is required. 5. Low cost.
6. Less hardware is required
Flip Flop: Flip flop is a sequential circuit which generally samples its inputs and changes its outputs only
at particular instants of time and not continuously. Flip flop is said to be edge sensitive or edge triggered
rather than being level triggered like latches.
 Flip Flop is a one bit storage element.
 Flip Flop has two stable states. Those are Set(1) and Reset(0) modes.

4.2. NAND AND NOR LATCHES WITH TRUTH TABLES.

Latch is an asynchronous bi stable device which can reside in any one of two stable states – Set, Reset.
Latches can be constructed using NOR gates or NAND gates.
NOR Latch:
The circuit of the S-R Latch using NOR Gates and its truth table is shown below. It has two NOR gates.
The two inputs of a latch are R (Reset) and S (Set). The two outputs of a latch are Q and Q’. The output of
each gate is connected to the input of other gate. This produces feedback arrangement or cross coupling.

The truth table explains the operation of NOR latch.

1. When R=0 and S=0 then Q and Q’ remains unchanged.
This state is also called No change state.
2. When R=0and S=1 then Q=1, Q’=0
This state is known as the SET state.
3. When R=1and S=0 then Q=0, Q’=1
This state is known as the RESET state.
In 2 & 3 cases the outputs are compliments of each other and the value of Q follows the value of S.
4. When R=1 and S=1 then Q & Q’ = 0 (Invalid / Forbidden)
This is an invalid state because the values of both Q and Q’ are 0. They are supposed to be compliments
of each other. Normally, this state must be avoided.
NAND Latch:
The following figure shows the circuit of a RS latch using two cross coupled NAND gates. It has two
inputs R and S and 2 outputs Q and Q’. The output of each gate is connected to the input of the other gate,
which gives the feedback arrangement. The operation of NAND latch can be explained using Truth table.

It has four states. They are

1. When R=0 and S=0 then Q=1, & Q’ =1 (Invalid / Forbidden)
If both the values of S and R,are switched to 0 it is an invalid state because the values of both Q and Q’
are 1. They are supposed to be compliments of each other. Normally, this state must be avoided.
2. When R=0 and S=1then Q=1, Q’=0
This state is called the SET state.
3. When R=1 and S=0 then Q=0, Q’=1
This state is known as the RESET state.
In the 2 & 3 states the outputs are just compliments of each other and the value of Q follows S.
4. When R=1 and S=1 then Q & Q’= No change
If both the values of S and R are switched to 1, then the outputs are in the last state . This is called Hold
state or No change State.

4.3. STATE THE NECESSITY OF CLOCK

Clock:
 It is a square wave signal with 50% duty cycle.
 It is used to control all the flip-flops.
Timing Diagram of a Clock:
The behavior of a clock can be easily described using a timing diagram. A timing diagram
has time on the horizontal axis (x-axis) and the voltage on the vertical axis (y-axis). For simplicity, use 0
and 1, instead of voltages. Here's an example

The period is related to the frequency, f. In fact, they are inversely related f = 1/T. The frequency
means how many times the waveform repeats per second. The unit of measurement for frequency
is Hz (pronounced Hertz), and is for the time as f-1 (inverse seconds).
  The higher the frequency, the shorter the period of one cycle.
Necessity of Clock:
Clock is necessary in digital systems
1. To Co-ordinate / Control the Flip-flops. i.e., to change the Flip flop output from one state to
another state
2. To Synchronize different functional systems.
Therefore in flip flops the output of the flip flop will change in accordance with inputs only when the clock
is applied.
Triggering : Preventing the flip flop output from changing its state until the clock pulse arrived is known as
Triggering or Clocking.
Triggering of a clock depends upon the following parameters.
i) Clock Edges ii) Clock Levels
Clock Edges: A clock also has "edges". Those are
 Positive Edge (Rising Edge)
 Negative Edge (Falling Edge)
Positive Edge (Rising Edge): These are the times that the clock transitions from 0 to 1 (this is called
a positive edge).
Negative Edge (Falling Edge) :These are the times that the clock transitions from 1 to 0 (this is called
a negative edge).

Clock Levels: Clock is having two types of levels. Those are

 High Level
 Low Level
High Level: The Clock is having logic 1 state that is called High level.
Low Level: The Clock is having logic 0 state that is called Low level.

4.4. DIFFERENCE BETWEEN LEVEL CLOCKING AND EDGE TRIGGERING

Triggering: Triggering : Preventing the flip flop output from changing its state until the clock pulse arrived
is known as Triggering or Clocking.
This means making a circuit active. Making a circuit active means allowing the circuit to take input
and give output.. When the circuit is not triggered, it will not change the data stored inside the flip-flop nor
will it change the output Q or Q' even the inputs are changed. The triggering is given in form of a clock
pulse or gating signal.
Types of Triggering:
Triggering of the clock depends upon two things. Those are
1. Level Triggering: In level triggering the circuit will become active when the gating or clock pulse is on
a Low OR High level. The types of level triggering are
 Negative level triggering in which the circuit is active when the clock signal is low.
 Positive level triggering in which the circuit is active when the clock signal is high.
The symbols of flip flops with Low and high level triggering are shown in fig.
2. Edge Triggering: In edge triggering the circuit becomes active at negative or positive edge of the clock
signal.
 In Positive edge triggered, It will take input at exactly the time in which the clock signal goes from
Low to High.
 In Negative edge triggering. It will take input at exactly the time in which the clock signal goes from
high to low.

Logic symbols of edge triggering are shown below.

4.5. SR FLIP FLOP USING NAND GATES

The SR flip-flop, also known as a SR clocked Latch, can be considered as one of the most basic
sequential logic circuit. This simple flip-flop is basically a one-bit memory bi-stable device that has two
inputs, one which will “SET” the device (meaning the output = “1”), and is labeled S and another which will
“RESET” the device (meaning the output = “0”), labeled R. Then the SR description stands for “Set-Reset”.
A basic NAND gate SR flip-flop circuit provides feedback from both of its outputs back to its
opposing inputs and is commonly used in memory circuits to store a single data bit. Then the SR flip-flop
actually has three inputs, Set, Reset and its current output Q relating to it’s current state or history. The term
“Flip-flop” relates to the actual operation of the device, as it can be “flipped” into one logic Set state or
“flopped” back into the opposing logic Reset state.

Truth table : Timing diagram

Operation:

S.No Condition Operation

.

1 S=R=0 If S = R = 0 then output of NAND gates 3 and 4 are forced to become 1.

No change Hence R' and S' both will be equal to 1. Since S' and R' are the input of the
basic S-R latch using NAND gates, there will be no change in the state of
outputs.

2 S = 0, R = 1, Since S = 0, output of NAND-3 i.e. R' = 1 and E = 1 the output of NAND-4

Clk = 1 i.e. S' = 0.Hence Qn+1 = 0 and Qn+1 bar = 1. This is RESET condition.

3 S = 1, R = 0, Output of NAND-3 i.e. R' = 0 and output of NAND-4 i.e. S' = 1.Hence
Clk = 1 output of S-R NAND latch is Qn+1 = 1 and Qn+1 bar = 0.
This is the SET condition.

4 S = 1, R = 1, As S = 1, R = 1 and Clk = 1, the output of NAND gates 3 and 4 both are 0

Clk = 1 i.e. S' = R' = 0. This is the Forbidden condition.

4.6. NEED FOR PRESET & CLEAR INPUTS .

The inputs given to RS,JK,D,T flip-flops are called synchronous inputs. Because the data on
these inputs are transferred to the flip-flops output only on the triggering edge of the clock.
 The inputs that effect the state of the flip-flop is independent of the clock are known as
Asynchronous inputs
 Some IC F/Fs also have asynchronous inputs. These are normally labeled as preset(PRE) and
clear(CLR). An active low level of the preset input will SET the F/F and an active low level of
the clear input will RESET it.
NEED : When power is first applied flip-flops come up in random states. To get some computers started, an
operator has to push a master reset button. This clears all the flip-flop. Some time it is necessary to preset the
flip-flop a computer run. To get this two more inputs known as preset and clear are given to any flip-flop.
 Fig 1: Shows SR flip-flop with preset and clear inputs. At low PRESET, the Q becomes 1 and a low
CLEAR reset Q to 0.
 When PRESET and CLEAR are both low, then the outputs of Flip flop is in Forbidden state. Therefore
PRESET and CLEAR should never be low.
 PRESET and CLEAR both are high during the normal operation of flip-flop. It is shown in truth table
 A low PRESET and high CLEAR sets the flip-flop and high PRESET and low CLEAR reset the flip-
flop.

The PRESET and CLEAR inputs override the other inputs, because they have top priority. For
example when PRESET low, the Q goes high and stays there irrespective of changes in S , R and CLK. The
flip-flop will returns to normal operation only when PRESET goes high. Similarly for CLEAR function.
These inputs affect the flip-flop independent of the clock. Thus PRESET and CLEARinputs are called as
asynchronous inputs. Where as S and R inputs are called Synchronous inputs.
Difference between synchronous and asynchronous inputs:
S. No Synchronous input Asynchronous inputs
1 The S-R, D and J-K inputs are called The asynchronous inputs are PRESET(PR)
synchronous inputs. and CLEAR (CLR)
2 The data on the synchronous input are The asynchronous inputs activate the flip-
transferred to the output of a flip-flop only on flop independently of the clock
the triggered edge of the clock pulse
3 These inputs will not affect the synchronous These inputs override the effect of the
inputs synchronous inputs
4 Low priority inputs High priority inputs. These are active Low
inputs

4.7. LEVEL CLOCKED JK FLIP FLOP

The JK flip-flop is refinement of the RS flip-flop. The indeterminate state (R= S= 1) of RS flip-flop
is determined in JK flip-flop. In this condition (J =K= 1), the complement of previous output is results as
present output known as toggle. For this case Qn+1 = Qn’ (bar).
The below figure shows a JK flip-flop.
 When J and K low, for high/low level of CLK both the input gates are disabled and the circuit is
inactive.
 When J is low and K is high, the upper gate is disabled. So means R’ = 1. So there is no way to set
the flip-flop. The only possibility is reset. When Q is high, the lower gate passes a next trigger as
soon as the high/low level CLK arrives. This forces Q to become low. Therefore J =0 and K = 1
means that a clock resets the flip-flop.
  When J is high and K is low, the lower gate is disabled means S’ = 1. So there is no way to reset the
flip-flop. The only possibility is set. When Q is low, Q’ is high, therefore, the upper gate passes a
trigger on the high level clock . This drives Q in to the high state. That is J = 1 and K = 0 means that
the next high level clock set the flip-flop.
 When J and K are both high, it is possible to set or reset the flip-flop, depending on the current of the
output. If Q is high, the lower gate passes a reset trigger on the next high/low level CLK . On the
other hand, when Q is low, the upper gate passes a set trigger on to the next high/low level clock .
Either way, Q changes to the complement of the last state. Therefore J = 1 and K = 1 means that the
flip-flop will toggle on the next high/low level Clk. Toggle more than once is called Race condition.
This is occurred in J=K=1

Fig. JK Flip-Flop circuit

.
The above Table summarizes the operation. The circuit is inactive when CLK is low, high level.
Likewise the circuit is inactive when J and K both are low. Output changes for only high/low level of the
CLK. The output is either set, reset, race around.
Truth table Timing diagram

JK FLIP-FLOP SYMBOLS: In the following Figure (i): is the standard symbol for a positive edge
triggered JK flip-flop of any design. Fig 3(ii) is the symbol for a flip-flop with the preset an clear functions.
As usual, PR and CLR have active low states. Fig 3(iii) is another commercially available JK flip-flop. The
bubble on the clock input is the standard way to indicate negative edge triggering.
4.8. RACE AROUND CONDITION.
RACING IN JK FLIP-FLOP:
. For level clocking, with a high J, high K and CLK, the output will toggle. New outputs are then
feedback to the input gates. After two propagation times the output toggles again. And once more, new
outputs return to the input gates. In this way, the output can toggle repeatedly as long as the CLK is high.
That is, get oscillations during the positive half cycle of the clock. This is called Racing or Race around
condition. The JK flip-flop has to be edge triggered to avoid oscillations
“Toggling more than once during a clock cycle is called Racing.”
Methods avoid Race around condition in Level triggered JK flip-flop:
 To avoid this Race around condition the Master-Slave JK flip-flop is used.
 Edge triggered JK Flip-Flop is also used to avoid Race around condition.

4.9. MASTER SLAVE JK FLIP FLOP

A way of avoiding racing in JK flip-flop is by means of master slave JK flip-flop. A master slave
flip-flop is a combination of two clocked flip-flops. The first is called the master and the second is the slave.
Master is positively clocked and slave is negatively clocked. This implies that
1. While the clock is high, the master is active and the slave is inactive.
2. While the clock is low, the master is inactive and the slave is active.
The below Figure gives the JK master slave flip-flop. Let us assume low Q and high Q’. For an input
condition of high J, low K and high CLK, the master goes in to the set state, producing high S and low R.
Nothing happens to the Q and Q’ output because the slave is inactive
When the CLK goes low, however, the high S and low R forces the slave in to the set state,
producing a high Q and a low Q’. There are two distinct, steps in setting the final Q output. First, the master
is set while the CLK is high. Second the slave is set while the CLK is low. This action is called clocking and
triggering. One can clock the master during the positive half cycle of the CLK, and trigger the slave during
the negative half cycle of the CLK.
 The truth Table summarizes the action of JK master slave flip flop. It responds to clock pulse only..
For the input condition of low J and high K and high CLK forces S to go low and R to go high. Again no
change occur in Q and Q’ because slave is inactive. When CLK returns to low, the S and R forces slave to
reset, this forces Q to go low and Q’ to go high.
If the J and K inputs are high, the master toggle once while the CLK is high, the slave then toggles
once when the CLK goes to low. No matter what the master does, the slave copies. Therefore in master slave
JK flip-flop the toggling more than once for level clocking is eliminated.
In the below Figure (ii) shows the symbol for a JK master-slave flip-flop with preset and clear
function. Table Summarizes the operation of a JK master slave flip-flop. The flip-flop responds for clock
pulse instead of clock edge.
Operation:
1. If J=K=0, this input condition does not produce any change.
2. If J=1, K=0 the master flip-flop sets on positive CLK level. The High Q on the master drives the
input (J) of the slave Flip-flop. . Then slave flip-flop Sets at the arrival of the negative level of the
clock pulse. Once again, the slave flip-flop copies the action of the master Flip-flop.
3. If J=0,K=1 the master resets on the Positive level of the clock pulse. The high Q’ output of the
master drives the input (K) of the slave flip-flop. Then slave flip-flop resets at the arrival of the
negative level of the clock pulse. Once again, the slave flip-flop copies the action of the master Flip-
flop.
4. If J=K=1, the master flip-flop toggles on the positive clock level and the slave toggles on the
negative clock level.
4.10. LEVEL CLOCKED D & T FLIP FLOPS
(i) Level clocked D Flip-Flop:
Delay Flip Flop or D Flip Flop is the simple gated S-R latch with a inverter connected between S
and R inputs. It has only one input. The input data is appearing at the output after some time. Due to this
data delay between i/p and o/p, it is called delay flip flop. S and R will be the complements of each other
due to (NAND) inverter. Hence S = R = 0 or S = R = 1, these input condition will never appear. This
problem is avoided in D flip flop.

Operation:

Condition Operation

1 CLK = 0 Flip-Flop is disabled. Hence no change in output.

2 CLK = 1 If clk= 1 and D = 0 then S = 0 and R = 1. Hence

and D = 0 irrespective of the present state, the next state is
Qn+1 = 0 and Qn+1 bar = 1. This is the reset condition.

3 CLK= 1 If clk = 1 and D = 1, then S = 1 and R = 0. This will

 and D = 1 set the latch and Qn+1 = 1 and Qn+1 bar = 0 irrespective
of the present state.

(ii) Level clocked T Flip-Flop:

Toggle flip flop is basically a JK flip flop with J and K terminals permanently connected together. It
has only input denoted by T as shown in the Symbol Diagram. The symbol for positive Level triggered T
flip flop is shown in the Block Diagram.

Operation:

S.N. Condition Operation

1 CLK = 0 Flip-Flop is disabled. Hence no change in output.

2 CLK = 1,T = 0 The output Q and Q bar won't change

3 CLK = 1,T = 1 Output will toggle corresponding to every positive level of clock signal.

4.11. SYMBOLS OF THE FLIP FLOPS.

SR Flip-Flop D Flip-Flop JK Flip-Flop T Flip-Flop

Designing of all Flip-Flops by using Basic Flip-Flop (SR Flip-Flop):

4.12.EDGE TRIGGERED D & T FLIP FLOPS.

Edge triggered D flip-flop:
The below figure shows a RC circuit at the input of a D flip-flop. By deliberate design, RC time
constant is much smaller than the clock’s pulse width. Because of this the capacitor can charge fully when
CLK goes high. This exponential charging produces a narrow positive spikes across the resistor for leading
edge and narrow negative spikes for trailing edge of the CLK pulse. At the instant of leading edge of clock
i.e., for positive spike Q =D. If CLK is 0 or 1 or for trailing edge the output do not changes with D.

The truth table and timing diagram Illustrates the action. The output changes only on the rising edge
of the clock. In other words, the data is stored only on the positive going edge.
The truth table summarizes the operation of the positive edge triggered D flip-flop. The up and down
arrows represents the rising and falling edges of the clock. The first three entries indicates that there’s no
output change when the clock is low, high or on its negative edge. The last two entries indicates an output
change on the positive edge of the clock. In other words, input data D is stored only on the positive going
edge of the clock.

Edge triggered T flip-flop:

The circuit symbols of edge triggered T flip-flop is shown below and truth table in table. This flip-
flop toggles for leading edge of clock input only. The operation is shown in truth table.
4.13. APPLICATIONS OF FLIP FLOPS
All the flip flops are having the following applications
 Data storage :
 To Data Transfer
 Frequency Division
 Counter circuits
 Register circuits
 Memories
 Data synchronizers
 Bounce elimination switch
REGISTERS
A group of flip flops that can be used to store binary information is known as register. An ‘N’ bit
register has group of ‘N’ flip flops and is capable of storing any binary information containing ‘N’ bits.

Example: A register used to store 8 bit binary number must have 8 flip flops. Naturally the flip flops must
be connected together. Such that binary numbers can be entered (or) shifted into register.

4.14 NEED FOR REGISTERS

The two functional characteristics for registers are
1) Temporary storage
2) Shifting capability (shift left, shift right).
Temporary storage : Registers are often used to store binary information appearing at the output of an
encoding matrix. A register must be used to accept the input data from an alpha-numeric key board and then
present this data at the input of microprocessor chip. Similarly registers are used to accept output data from
the processor and present this data to the circuitry which drives the CRT.
Thus the register form a very important link between digital system and I/O channels.
Shifting capability : A binary register is also used to perform some arithmetic operations by shifting the
bits on the application off clock pulses. (complement, multiplication, division etc ).
The shifting capability permits the movement of data from one stage to another stage either in serial
or parallel form.

4.15 TYPES OF REGISTERS

The data can be entered into register in serial form or parallel form and can be retrieved in serial form
or parallel form. This leads to the construction of 4 basic register types
i) Serial In Serial Out (SISO) Shift Register
ii) Serial In Parallel Out (SIPO) Shift Register
iii) Parallel In Serial Out (PISO) Shift Register
iv) Parallel In Parallel Out (PIPO) Shift Register
1. SERIAL-IN SERIAL-OUT: It accepts the data serially i.e., one bit at a time, on a single line as shown in
the figure. It produces stored information on its output also in serial form. It is to be noted that valid data bit
comes out of the n-bit SISO register only after the application of n clock pulses. Further one requires
providing additional n clock pulses in order to retrieve the entire n-bit input word.

2. SERIAL- IN PARALLEL -OUT: It accepts data serially and data bits are taken out of register in
parallel form. Once the data is stored, the output of each state is available on its respective output line and all
bits are available simultaneously. It is to be noted that valid n-bit data word comes out of the n-bit SIPO
register just after the application of n clock pulses.

3. PARALLEL –IN SERIAL-OUT: In case of Parallel-In Serial-Out shift registers (Figure c), the data
loading happens in parallel fashion while the data retrieval is serial in nature. Here the entire input word
enters into the shift-register at a single clock cycle. From then on, for each clock cycle
1. Data within the register shifts either right or left by one bit
2. One bit exits the register.
 This means that the data bits of the input word are obtained at the PISO output bit-by-bit. This
indicates that in order to obtain the entire n-bit input word, one would have to wait for additional n clock
cycles.

4. PARALLEL –IN PARALLEL-OUT: It accepts data in parallel form and produces output in parallel
form. It allows simultaneous entry of all data bits and as well as all the bits appear as parallel output. In
parallel-in parallel-out shift registers (Figure d) both data loading as well as data retrieval processes are
parallel in nature. This means that the entire data word can be entered into the registers at a single clock
tick.

4.16. SHIFT LEFT AND SHIFT RIGHT REGISTERS

4 BIT SHIFT LEFT REGISTER:
The shift registers that shifts the data bit by bit to the left is known as ‘Shift Left Register. In this the bits are
moved from lower significant position to higher significant position. The following figure shows a Shift Left
Register using positive edge triggered D flip-flops.

Fig. 4 – bit Shift Left Register

The ‘Q’ output of each flip-flop is connected to the ‘D’ input of flip-flop at its left side. Each clock
pulse shifts the contents of register ‘1’ bit position to the left. The operation is explained with a binary word
1101 shifted into register. Initially all the flip-flops are cleared. Then Q= Q3Q2Q1Q0=0000.
Data entering begins with MSB bit of the given 4-bit word i.e.. 1101. This bit ‘1’ is entered into the
‘D1n’ input making D0=1 for the first flip-flop.
 When the first clock pulse is applied, the bit’1 is stored in the first flip-flop. The remaining flip-flops
have 0s then Q=0001
 During the 2nd clock pulse, the second MSB bit of “1101” i.e., ‘1’ is entered into first flip-flop. The ‘1’
that was in first flip-flop is shifted to 2nd flip-flop then Q=0011
 During the 3rd clock pulse, the third bit i.e., ‘0’ is entered into first flip-flop. The ‘1’ in 1 st flip-flop is
shifted to 2nd flip-flop. The ‘1’ in 2nd flip-flop is shifted to 3rd flip-flop. Then Q=0110.
 When the 4th clock pulse is applied, the 4th biti.e., ‘1’ is entered into first flip-flop. The ‘0’ is first flip-
flop is shifted to 2nd flip-flop. The ‘1’ in 2nd flip-flop is shifted into 3rd flip-flop. The ‘1’ in 3rd flip-flop is
shifted into 4th flip-flop. Then Q=1101
This completes the serial entry of data 1101 into Shift Left register.
Thus the bits have moved to left by one bit position. The Truth Table shows the data stored in each flip-
flop for each clock pulse. It can be seen that to transfer all the data bits, 4 clock pulses are required. The
below figure shows the corresponding timing diagram.

4 BIT SHIFT RIGHT REGISTER

The shift registers that shifts the data bit by bit to the right is known as ‘Shift Right Register’. In this the bits
are moved from higher significant position to lower significant positions. The following figure shows a shift
right register using positive edge triggered D flip-flops.
The ‘D’ flip-flop simply transfers data from input ‘D’ to the output ‘Q’ after a delay of ‘1’ clock
pulse. The ‘Q’ output of each flip-flop is connected to D-input of flip-flop at its right side. Each clock pulse
shifts the contents of register one bit position to right side. The data output is taken in serial form from the
output of right most flip-flop.
The operation can be explained by a 4 bit binary word 1101.Initially all the flip-flops are cleared.
Then Q=Q3Q2Q1Q0=0000.
The data entry begins with LSB (D0) bit of the given 4 bit word i.e.. 1101
 When the first clock pulse is applied, the LSB bit ‘1’ is stored in first flip-flop. Then Q=1000.
 When the second clock pulse is applied, the bit 1101 i.e.. ‘0’ is entered into 1st flip-flop. The bit ‘1’
which was in 1st flip-flop is shifted to 2nd flip-flop then Q=0100.
 When the 3rd clock pulse is applied, the 3rd bit 1101 i.e.. ‘1’ is entered into the 1st flip-flop. The bit ‘0’ is
1st flip-flop is shifted to 2nd flip-flop. The bit ‘1’ in 2nd flip-flop is shifted to 3rd flip-flop. Then Q=1010.
 When the 4th clock pulse is applied, the 4th bit 1101 i.e., ‘1’ is entered into the first flip-flop, then
Q=1101
This completes the serial entry of data 1101 into shift right register.
The truth table shows the data bit stored in each flip-flop for each clock pulse. In this case also, it can
be seen that to transfer all the data bits,4 clock pulses are required. The figure shows the corresponding
timing diagram for the shift right register.
4.17. 4-BIT BI-DIRECTIONAL SHIFT REGISTER
If a binary number is shifted left by one position then it is equivalent to multiplying the original
number by 2. Similarly if a binary number is shifted right by one position then it is equivalent to dividing
the original number by 2.Hence use the shift register to multiply and divide the given binary number. Such
a register is called bi-directional register. A four bit bi-directional shift register is shown in fig.
There are two serial inputs namely the serial right shift data input DR, and the serial left shift data input
DL along with a mode select input (M or Right/Left).

Fig. 4 – bit Bi-directional Shift Register

Operation :
1. With M = 1 : Shift right operation
If M = 1, then the AND gates 1, 3, 5 and 7 are enabled whereas the remaining AND gates 2, 4, 6 and
8 will be disabled.The data at DR is shifted to right bit by bit from FF-3 to FF-0 on the application of clock
pulses. Thus with M = 1 the serial shift right operation is performed.
2. With M = 0 − Shift left operation
When the mode control M is connected to 0 then the AND gates 2, 4, 6 and 8 are enabled while 1, 3,
5 and 7 are disabled.The data at DL is shifted left bit by bit from FF-0 to FF-3 on the application of clock
pulses. Thus with M = 0 the serial shift left operation is achieved.
Note : Draw the truth tables and timing diagrams of Shift left and shift right registers

4.18. PARALLEL IN PARALLEL OUT SHIFT REGISTER

In this type of register data inputs can be shifted either in or out of the register in parallel. In this
register, there is no interconnection between successive flip-flops since no serial shifting is required.
Therefore, when the parallel entry of the input data is accomplished, the respective bits will appear at the
parallel outputs.
The PIPO shift register is the simplest of the four configurations as it has only three connections, the
parallel input (PI) which determines what enters the flip-flop, the parallel output (PO) and the sequencing
clock signal (Clk).

A 4 bit parallel in parallel out shift register is shown in below figure. The process of loading data in
to register is known as the ‘Write Operation’ and the process of reading is known as ‘Read operation’.
This type of shift register also acts as a temporary storage device or as a time delay device similar to
the SISO configuration above. The data is presented in a parallel format to the parallel input pins P3 to P0 and
then transferred together directly to their respective output pinsQ 3 to Q0 by the same clock pulse. Then one
clock pulse loads and unloads the register. This arrangement for parallel loading and unloading is shown
below.

Fig. 4-bit Parallel In Parallel Out Register

4.19. UNIVERSAL SHIFT REGISTER (74194 )
74194 is a 4-bit bidirectional universal shift register IC. It has the shift left and shift right capability.
The data can be transferred either in serial or parallel mode. The register is fully synchronous with all
operations taking place in typically less than 20 ns making the device specially useful for implementing very
high speed CPU’s or for memory buffer registers. The logic diagram and the associated waveforms of the
74194 are given in below figure.
The shift register is capable of performing- Parallel loading , Lift shifting and Right shifting
The universal shift registers is reset when the master reset (MR’) input goes LOW. This over rides all
other input conditions and therefore forces the Q outputs to LOW. The synchronous operation of the device
is determined by the two mode select inputs S0 and S1. As shown in the table.
 The register uses 4 flip-flops to store and shift the 4-bit data. The 4 data inputs are (D0 to D3) D-type
inputs. The first and last stages provides D-type serial data inputs (D SR & DSL) to allow multi stage shift left
or shift right data transfers without interfacing with parallel load operation.
Mode select and data inputs in 74194 are edge-triggered, responding only to the LOW-to-HIGH
transition of the clock (CP). The mode select inputs of the 74194 are gated with the clock and should be
changed from HIGH to-LOW only while the clock input is HIGH.
Operation:
1. When S0 is high and S1 is low then shift right operation is done in synchronous with positive edge of
clock. In this mode the serial data is entered at shift right serial input DSR.
2. When S0 is low and S1 is high them shift left operation is done in synchronous with clock. Serial
data is entered at shift left serial input DSL.
3. When S0 and S1 inputs are at high parallel loading operation is done is synchronous with a positive
transition of clock. This is done by applying 4 parallel bits of data to the parallel inputs.(PA to PD).
4. When both S0 and S1 inputs are at low level then it is in inhibit clock operation. In this mode the
operation will inhibit the shifting of data in the shift register.
The truth table illustrates the operation of Universal shift register.
 H = HIGH voltage L = LOW voltage level
h = HIGH voltage level on setup time prior to the LOW-to HIGH clock transition
l = LOW voltage level on setup time prior to the LOW-to HIGH clock transition
X = Don’t care = LOW-to-HIGH clock transition

4.20. APPLICATIONS OF SHIFT REGISTERS

Registers are used in many applications.
 Temporary data storage : Shift registers are used in computers as memory elements. All the digital
systems need to store large amount of data, in an efficient manner. So storage elements like RAM
and other type of registers are used.
 Data manipulation : In many digital systems operations like division, multiplication are performed
by using registers. The data is transferred through serial shift registers and other type.
 Time Delay : Serial in serial out register are used to provide time delay from input to the output.
 Data conversion : Serial in parallel out registers are used for converting the data from serial form to
parallel form. So these are also called “Serial to parallel converters”. Parallel in serial out registers
are used for converting the data from parallel form to serial form. So these are also called “Parallel to
serial converters”.
 Keyboard encoders : It is a good example of application of shift register used as a ring counter in
conjunction with other devices.
 Ring counters : When the output of the last stage is connected back to the serial input it is known as
ring counter. The output of ring counter has sequential and non overlapping pulses. These are useful
for control state counters and stepper motor.
LOGIC CIRCUIT AND TIMING DIAGRAM OF UNIVERSAL SHIFT REGSTER.
 5. COUNTERS& SEMICONDUCTOR MEMORIES

5.0 INTRODUCTION
A group of flip flops connected together to perform counting operation is known as counter. A
counter is a sequential logic circuit used to count the number of clock cycles applied. The counter can be
used as an instrument for measuring time. the counters are mostly constructed using JK flip flops in toggle
mode or T-flip flops. There are basically two types of counters.
1. Asynchronous counters.
2. Synchronous counters.
In Asynchronous counters each flip-flop is triggered by the previous flip-flop output, and clock pulse
is applied to first flip-flop only. These are called as Serial or Ripple or Asynchronous counters. It has
speed limitation.
In Synchronous counter each flip-flop is triggered by clock at same time. This is done by connecting
the single clock pulse to each flip-flop of the counter. These are Parallel or synchronous counters.
Synchronous counters increase the speed of operation.
5.1 MODULUS OF A COUNTER
Modulus of the counter is defined as the total number of states that occur in the output of a counter.
The number of flip-flops needed for the counter depends on the maximum number it has to count.
If a counter consists of n- flip flops, then maximum possible number of states of a counter is 2 n (N).
Therefore the counter can count from 0 to 2n – 1. such counters are known as Modulus or Mod – N
counters.
For example binary counter has 4 flip flops, then maximum possible no of output states are 2 4 = 16.
Then the counter is Mod – 16 counter. a 3-bit binary counter is also called as Mod-8(2 3) counter.coumod-16
counter.

5.2 MOD – 16 (or) 4-BIT ASYNCHRONOUS COUNTER.

Mod-16 Counter is a Four bit asynchronous counter. It consists of 16 states from 0000 to 1111 and
uses four flip-flops. The logic circuit of Mod-16 counter is shown in fig.

Fig. Logic circuit of Mod – 16 counter.

The MOD-16 ripple counter has four JK Flip flops named as A, B, C and D, where A flip flop
output represents the Least Significant Bit (LSB) and D output represents the Most Significant Bit (MSB).
Here the flip flop A is triggered by the clock pulse. The next flip flops are triggered by the output of
previous flip flops. that is B is triggered by QA, C is triggered by the QB and D is triggered by the Qc.
Operation:
1. JK inputs of all the flip flops are tied together and connected to +5V. so the flip flops operate in toggle
condition. They are negative edge triggered. So, a flip flop toggles when there is negative change in the
previous flip flop output. Initially all the flip flops are at RESET. At this state the counter output is Q= Q D
QC QB QA= 0000.
2. When the negative going edge of the 1st pulse occurs, the output of the A Flip flop Q A toggles i.e., goes to
HIGH. It has no effect on the B, C and D Flip flops. Because to trigger them a negative transition pulse is
required. At this state output Q= 0001.
3. For the negative going edge of the 2 nd clock pulse occurs QA goes to LOW. This indicates the negative
edge triggering is applied as a clock to B F/F. Thus second flip-flop B output goes to HIGH. But no effect
on C F/F. at this output Q= 0010
4. For 3rd clock pulse the QA goes to HIGH, which is a positive transition pulse. So, Q B does not change and
there is no change in the output of QC and QD. At this time the output Q=0011.
5. When 4th clock pulse is applied, the QA goes to LOW, which is negative transition and is applied as a
clock to flip-flop B. Then the B toggles and output of B changes from HIGH to LOW, which is negative
transition and is applied as a clock to flip-flop C. Then C flip flop Toggles and the output of Q C goes from
LOW to HIGH. This is a positive transition and D flip flop does not toggle. At this state the output Q=0100.
6. When 5th clock pulse is applied, the output QA goes to HIGH. Which does not affect the output of flip-flop
B, C and D. At this state the output is Q=0101.
7. When applying 6th clock pulse, the output QA goes to LOW, which affect the output of B flip-flop. The Q B
changes from LOW to HIGH. Hence the output of counter at this time Q=0110.
8. When applying 7th clock pulse, the output QB goes to HIGH, which does not affect the output of B flip-
flop and the output of C Flip flop QC also at the previous state. Hence the output of counter Q= 0111.
9. When applying the 8th clock pulse the output goes to LOW, which causes the change at B Flop flop. The
output QB goes to LOW, this will cause the change at C Flip flop. The output Q C also goes to LOW from
HIGH. Then the D flip flop Toggles. At this state the output of counter Q= 1000.
similarly the counter will change its output for each incoming clock pulses. at the 15 th clock pulse Q
= 1111. when the 16th clock pulse is applied at the input, all flip flops toggles and changes all the outputs
from High to Low. therefore Q = 0000 and the cycle repeats back to its initial state.
This is shown in truth table and timing diagram. As shown in truth table, the counter output is the
binary equivalent of decimal count. which represents the no of clock pulses arrived.
The timing diagram of a counter shows that the counter is also a frequency divider. Each Flip flop
divides the clock frequency by 2. A Counter with n- flip flops divides the frequency by 2 n. Therefore Mod-
16 counter is also known as divided by 16 counter. These counters are also known as “Ripple” counters
because the carry moves through the flip flops like a ripple in a water.

Fig. Timing diagram of Mod -16 counter Fig. Truth Table

MOD – 8 COUNTER

Fig. Logic circuit

5.3 DECADE COUNTER (MOD-10 RIPPLE COUNTER)
Decade or decimal counter follows a sequence of 10 states and returns to 0(0000) after the count is 9.
A decade counter must have four flip-flops. This is a BCD counter because its ten state sequences is the
BCD code.
To obtain the truncated sequence it is necessary to force the counter to recycle before going through
all its normal states. The method of achieving the recycling after the count 1001 is to decode the count 1010
with a NAND gate and connecting the output of NAND gate to the CLR input of flip-flops.

Operation:
1. The operation of the decade counter is performed by the application of ten clock pulses. The clock is input
is applied to first flip-flop only. The next flip-flops are triggered by the outputs of previous flip-flops. The
output of counter is given by Q=QD, QC, QB, QA.
2. From the timing diagram, the output of Q A toggles between HIGH and LOW for every clock pulse. The
output of QB changes its state when QA goes to HIGH to LOW transition, the output of Q C changes its state
when QB goes to negative transition and also QD changes its state when QC goes to negative transition. In this
manner, the counting process will be continued from the count 0000 to 1001.
3.When the counter goes to 1010, the NAND gate output goes LOW and flip-flops are in clear condition.
Thus, when 10th clock pulse occurred output Q is 0000 instead of 1010. Because only Q B & QD are connected
to the NAND gate inputs. The two unique states are QB=1 and QD=1 are sufficient to decode the 1010.
The timing diagram and truth table are shown in fig.
 DRAWBACKS OF RIPPLE COUNTERS:
1. The propagation delay is the main disadvantage.
2. The speed of operation is low, because the flip-flops of these counters are not clocked simultaneously.
3. To obtain a truncated sequence it is necessary to force these counters to recycle before going through all
its normal states.
All these drawbacks are eliminated by Synchronous counters
5.4 4-BIT SYNCHRONOUS COUNTER
This counter is implemented with negative edge triggered flip-flops. The clock signal is given to all
the flip flops clock input i.e., all the flip-flops are connected to common clock input. (Synchronous)
This counter consists of 4 J K flip-flops, namely A, B, C and D. Where A flip-flop ii the LSB and D
flip-flop is the MSB of the counter. In synchronous binary counter, the flip-flop in the LSB position toggles
(complement) for every clock pulse. The other flip-flops are toggled (complemented) with a pulse provided
all the bits in lower order positions are equal to 1.

Operation:
The basic operation of the 4-bit synchronous counter can be illustrated from its timing diagram. The
output of counter is given by Q=QD, QC, QB and QA. Initially all the flip-flops are in reset condition and the
count Q=0000.
1. When the first clock pulse arrives the first flip-flop goes from LOW to HIGH. The output Q=0001.
In the timing diagram notice that QA changes to each clock pulse.
2. When the second clock pulse arrives, the first and second flip-flops toggles because of the HIGH
level at the both J & K inputs. Thus the first flip-flop goes to LOW and second flip-flop goes to
HIGH. Output of the counter Q=0010.
3. When the third clock pulse arrives the output of the counter Q=0011. Now both QA and QB are 1.
Hence the output of first AND gate is high. The output of this AND gate is connected to J and K
inputs of FF-C. therefore FF c toggles during the next clock pulse.
 4. When fourth clock pulse arrives, the first and second flip-flops toggles and go to LOW. the third flip
flop also toggles and Qc becomes 1. Then the output Q=0100. Similarly the fifth, sixth and
seventh clock pulses occurs, then the counter counts from 0101 to 0111 respectively.
5. Whenever QA, QB, QC are at HIGH, the fourth flip-flop changes its state during the eight clock
pulse. the fourth flip flop toggles only twice in the sequence. This condition is detected by the AND
gate. So, that when the clock pulse occurs, the fourth flip-flop will change the state.
6. Whenever the clock pulse occurs periodically from eight clock pulse to fifteenth clock pulse, then the
counter counts from 1000 to 1111.
7.When sixteenth clock pulse occurs all the four flip-flops change from 1 to 0 and the output becomes
Q=0000.

Fig. Timing diagram of Synchronous counter Fig. Truth Table

5.5 DISTINGUISH BETWEEN ASYNCHRONOUS & SYNCHRONOUS

COUNTERS
Asynchronous counters
1.The first flip flop is clocked by external clock and
the successive flip flops are clocked by the output of
previous flip flop
2.Flip flops are not clocked simultaneously
3. Speed of this counter depends on frequency of
the clock and propagation delay of each flip flop
4. Circuit is Simple and straight forward in
operation.
5.Hardware requirement is minimum
6.Settling time is more. It is equal to sum of
propagation delays of all the Flip flops.
7. Speed is less
8. The maximum frequency depends on modulus.
9. Also called as Serial or Ripple counters
10. Cost is less
Synchronous counters
1. External clock is given to all the flip flops
(Synchronous)
2.Flip flops are clocked simultaneously
3.Speed of this counter depends only on frequency of the
clock.
4. Circuit is not simple and straightforward in operation
5.Hardware requirement is more
6.Settling time is less. It is equal to the propagation delay
of a single the Flip flop.
7.Speed is more
8.Maximum frequency does not depend on modulus.
9. Also called as Parallel counters.
10. Cost is more

5.6 AYNCHRONOUS 3-BIT UP/DOWN COUNTER

The counter which is capable of progressing in either direction through a certain counting sequence
is known as up/down counter. This counter is also known as `bidirectional counter`. The counter can count
either in the upwards or downwards.
A basic 3-bit up/down counter is given below. In this counter, the flip-flop in the lower-order portion
is complimented with every clock pulse.
Operation: A control input Up/Down determines the basic operation of the counter. When the control input
is HIGH, then the counter works as Up counter and when it is LOW, then the counter works as down
counter.
The counter works as Up counter if the outputs of Flip flops are connected to the clock inputs of the
succeeding flip flops.
The counter works as Down counter if the complemented outputs of Flip flops are connected to the
clock inputs of the succeeding flip flops.
The truth table explain the operation of up down counter.

TRUTH TABLE:

UP COUNTER: (Up/Down =1)

When the control input Up/Down is high, the upper AND gates are enabled and lower AND gates
are disabled. Hence Q0 is connected to the clock input of FF-1 and Q1 is connected to the clock input of FF-
2.
These conditions are same as those of normal UP counter. Thus the counter works as Up counter.
DOWN COUNTER:(Up/Down =0)
When the control input Up/Down is Low, the upper AND gates are disabled and lower AND gates
are enabled. Hence complemented output of Q 0 is connected to the clock input of FF-1 and complemented
output of Q1 is connected to the clock input of FF-2.
These conditions will produce a Down counter.
Thus a single counter can work as Up/Down counter based on the control signal value.
Timing diagram:
 The 3-Bit counter advances upward in sequence (0,1,2,3,4,5,6,7) or downwards in reverse sequence
(7,6,5,4,3,2,1,0). Generally most bidirectional counters can be made to change their count direction either up
or down at any point within their counting sequence. This is achieved by using an additional input pin which
determines the direction of the count, either Up or Down and the timing diagram gives an example of the
counters operation as this Up/Down input changes state.

5.7 IC NUMBERS
FLIP FLOPS :

TTL IC NO FUNCTION CMOS IC NO FUNCTION

7473 Dual JK Flip Flop 74HC74 ,74AC74 CMOS D Flip Flop
7474 Dual D Flip Flop 74HC273,74AC273 CMOS D Flip Flop
7475 Quad Bi-stable Latch 4013,40174 CMOS D Flip Flop
7476 Dual JK Flip Flop 74HC76 JK Flip Flop
74107 Dual JK Flip Flop 74AC109 JK Flip Flop
74109 Dual JK Flip Flop 4027 JK Flip Flop
74173 Quad D Flip Flop 4042,4079 CMOS Latches
74174 Hex D Flip Flop 74HC75, 74HC373 CMOS Latches

REGISTERS
TTL CMOS REGISTER FUNCTION
7491 4031 8-Bit Serial In Serial Out register
74164 4014 8-Bit Serial In Parallel Out register
74165 ------ 8-Bit Parallel In Serial Out register
74195 4035 4-Bit Parallel In Parallel Out register
74194 4034 4-Bit bidirectional universal shift register

COUNTERS
TTL IC FUNCTION CMOS FUNCTION
7490 Decade counter 4510 Up/down counter
7492 Divided by 12 counter 4518 Dual 4-bit decade
7493 4-bit (Mod-16) Ripple counter counter
74160 - 74163 4-bit synchronous counter 4520 Dual 4-bit Binary counter
74168,74169 4-bit Synchronous Up/Down counter

5.8 RING COUNTER

Timing signals that control the sequence of operators are essential in digital computer systems. The
counter which is used for their basic operation is known as ring counter. A ring counter is a Circular Shift
Register with only one flip-flop being set at any particular time and all other flip-flops are cleared.
4-bit ring counter: In the logic diagram, the outputs Q and Q’ of each flip-flop are connected to the next
flip-flop and the Q output of the fourth flip-flop is connected to the first flip-flop. The clock input is applied
simultaneously to all flip-flops.
Fig. 4 Bit Ring counter
Operation:
 Initially, a logic 1 is preset into the first flip-flop and the rest of the flip-flops are cleared. To achieve
this, a “CLEAR” signal is firstly applied to all the flip-flops together in order to “RESET” their outputs
to a logic “0” level and then a “PRESET” pulse is applied to the input of the first flip-flop ( FFA )
before the clock pulses are applied. This then places a single logic “1” value into the circuit of the ring
counter.
 Then the output of the counter is given by Q=QD.QC.QB.QA ie., Q=0001
 The single bit logic 1 is shifted with every clock pulse and circulates back from the fourth flip-flop to the
first flip-flop.
 The truth table summarizes the operation of Ring counter. As shown in table that only one ‘1’ is always
retained in the counter and simply shifted “around the ring” advancing one stage for each clock pulse.
 The basic operation of counter is also illustrated in the timing diagram.
 An N-bit ring counter has ‘N’ different states. For example a 4-bit ring counter has 4 different states as
shown in truth table.

5.9 APPLICATIONS OF COUNTERS & RING COUNTER

Application of counters:
1.Digital clocks:- Synchronous decade counters are used for implementation of various counting operations,
exclusively for seconds and minutes.
2. Auto-parking control:- This application illustrated the use of an UP/DOWN counter to solve parking
problems.
3. Parallel-to-serial data conversion:- Parallel-to-serial conversion is normally accomplished using a
counter to provide a binary sequence for data. Select inputs for a data selector
4. Industrial digital control system:- Counters are used in systems such as counting of objects or finished
products, 5. Frequency Measurements :Counters are also used for frequency measurement and frequency
changing,
6. Speed measurement: Counters are also used for speed and time measurement

Application of Ring counter:

Ring counters are used in those applications in which several operations are to be controlled
sequentially.
1.Gating wave form generator: As a ring counter produces a pulse once in every n clock pulses, it may be
used to open an electronic gate once in every nth clock pulse.
2.Stepping switch : If an LED is connected to the output of each flip flop then a sequentially lighted
illumination can be obtained.
3. Johnson counter or twisted Ring counter : If complemented output of last Flip flop is connected back
to D input of first flip flop then it is called Johnson counter. It produces 2N states where N is no of flip
flops where as normal ring counter produces N states only.
4.Controlling operations : in resistance welding the operations called squeeze, hold, weld and off are to be
performed sequentially. A ring counter is used to initiate these operations.
5. Stepper motor control
6. Divided by N counter: The input frequency of a counter is divided by N where N is no of flip flops.