SEL 4253 Asas VLSI Digit

Static CMOS and Ratioed Logics

These set of transparencies are adapted from

lecture notes CSE477 VLSI Digital Circuits at Penn. State Univ., taught by Mary Jane
Irwin and Vijay Narayanan
slides for text J. M. Rabaey et al., Digital Integrated Circuits: A Design Perspective, 2nd
ed. ©2002, J. Rabaey et al.

CSE477 Static CMOS, Ratioed Logic.1 Irwin&Vijay, PSU, 2002

 CMOS Circuit Styles

Static complementary CMOS - except during switching, output
connected to either VDD or GND via a low-resistance path
 high noise margins
- full rail to rail swing
- VOH and VOL are at VDD and GND, respectively
 low output impedance, high input impedance
 no steady state path between VDD and GND (no static power
consumption)
 delay a function of load capacitance and transistor resistance
 comparable rise and fall times (with appropriate transistor sizing)

Dynamic CMOS - relies on temporary storage of signal values

on the capacitance of high-impedance circuit nodes
 simpler, faster gates
 increased sensitivity to noise

CSE477 Static CMOS, Ratioed Logic.2 Irwin&Vijay, PSU, 2002

Static CMOS - most widely used logic style.

 Static Complementary CMOS

Pull-up network (PUN) and pull-down network (PDN)

VDD
PMOS transistors only
In1
pull-up: make a connection from VDD to F
In2 PUN
…

when F(In1, In2, …, InN) = 1

InN
F(In1, In2, …, InN)
In1
pull-down: make a connection from F to GND
In2 PDN
…

when F(In1, In2, …, InN) = 0

InN
NMOS transistors only

PUN and PDN are dual logic networks

CSE477 Static CMOS, Ratioed Logic.3 Irwin&Vijay, PSU, 2002

One and only one of the networks (PUN or PDN) maybe conducting in steady
state (output node is always a low-impedance node in steady state).
 Threshold Drops

VDD VDD
PUN
S D
VDD

D 0 → VDD S 0 → VDD - VTn

VGS
CL CL

PDN VDD → 0 VDD → |VTp|

VGS
D CL S CL
VDD

S D

CSE477 Static CMOS, Ratioed Logic.4 Irwin&Vijay, PSU, 2002

NMOS transistors produce strong zeros; PMOS transistors generate strong

ones. Hence, we use NMOS for PDN so that output can reach 0 V when it is
supposed to be LOW. If we use PMOS for PDN, that output will be |VTp|, not 0 V.
Similar reason for not using NMOS in PUN.

The two circuits on the right cut-off before the ideal voltage level is reached
(when |VGS| < |VT|).
 Construction of PDN

NMOS devices in series implement a NAND function

A•B
A

NMOS devices in parallel implement a NOR function

A+B
A B

CSE477 Static CMOS, Ratioed Logic.5 Irwin&Vijay, PSU, 2002

 Dual PUN and PDN

PUN and PDN are dual networks
 DeMorgan’s theorems

A+B=A•B

A•B=A+B

 a parallel connection of transistors in the PUN corresponds to a

series connection of the PDN, and vice versa.

Complementary gate is naturally inverting (NAND, NOR,

AOI, OAI)

Number of transistors for an N-input logic gate is 2N

CSE477 Static CMOS, Ratioed Logic.6 Irwin&Vijay, PSU, 2002

 CMOS NAND

A B F
0 0 1
A B
0 1 1
1 0 1
A•B
A 1 1 0

A
B

CSE477 Static CMOS, Ratioed Logic.7 Irwin&Vijay, PSU, 2002

 CMOS NOR

A B F
B
0 0 1
A 0 1 0

A+B 1 0 0
1 1 0
A B

A
B

CSE477 Static CMOS, Ratioed Logic.8 Irwin&Vijay, PSU, 2002

 Complex CMOS Gate

B
A
C

D
OUT = !( D + A(B + C) )
A
D
B C

CSE477 Static CMOS, Ratioed Logic.9 Irwin&Vijay, PSU, 2002

Since OUT = D + A(B + C), i.e. has long bar, we draw PDN first. Then we
synthesize PUN from the PDN structure.
 OAI21 Logic Graph

X PUN
A
j C
B C

X i VDD
X = !( C(A + B) )
C
i B A
j
A B
PDN
A GND
B
C

CSE477 Static CMOS, Ratioed Logic.10 Irwin&Vijay, PSU, 2002

OAI is short for OrAndInvert. 21 refers the number of inputs for the OR gates (in
this case only one OR gate exists because 1-input OR gate is equivalent to a
wire).

The diagram on the right is called a logic graph. The diagram can be used as a
systematic approach to derive order of input signal wires so gate can be laid out
to minimize area. For the gate above, a bad ordering is B, C, A. An example of
good ordering is C, A, B.

Note that PUN and PDN are duals (parallel <-> series).

Vertices (X, i, GND, j, VDD) represent nodes of the circuit.

 Two Stick Diagrams of !( C(A + B) )

A C B A B C

VDD VDD

X X

GND GND

uninterrupted diffusion strip

CSE477 Static CMOS, Ratioed Logic.11 Irwin&Vijay, PSU, 2002

Input ordering of A, C, B is a bad ordering (see previous slide for the only other
bad ordering).

Layout area for the arrangement on the right is minimized because the Active
layer for NMOS (also called n-diffusion layer) is continuous. Arrangement on the
left requires two separate n-diffusion layers, hence a gap between the two
strips.

We use green for n-diffusion, brown for p-diffusion, red for polysilicon, blue for
metal1, purple for metal2, and black square for Contact-to-Active, Contact-to-
Poly, and via1.
 Consistent Euler Path

An uninterrupted diffusion strip is possible only if there exists
a Euler path in the logic graph
 Euler path: a path through all nodes in the graph such that each edge
is visited once and only once.
X

C
i
X VDD

B A
j A, B, C ordering

GND

For a single poly strip for every input signal, the Euler paths in
the PUN and PDN must be consistent (the same).
CSE477 Static CMOS, Ratioed Logic.12 Irwin&Vijay, PSU, 2002

The sequence of signals on the path (in this example: A, B, C) is the signal
ordering for the inputs to be used in stick diagram.

PUN and PDN Euler paths should be consistent (same sequence).

If we can define a Euler path, then we can generate a layout with no diffusion
breaks.

Referring to the stick diagram on the right in previous slide (redrawn here):
For PDN, we begin with node i, then we meet signal A (i.e. polysilicon wire),
then we meet node GND, then we meet signal B (i.e. polysilicon wire), then we
meet node i again (hence both nodes are connected together using metal1
layer), then we meet signal C (i.e. polysilicon wire), then we meet node X.
For PUN, we begin with node VDD, then we meet signal A (i.e. polysilicon wire),
then we meet node j, then we meet signal B (i.e. polysilicon wire), then we meet
node X (this node is connected to the previous X node using metal1 layer), then
we meet signal C (i.e. polysilicon wire), then we meet node VDD again.

A B C
Exercise: Draw stick diagram with C, A, B input ordering. VDD

GND
 OAI22 Logic Graph

X PUN
A C

B D D C

X VDD
X = !( (A+B)(C+D) )

C D
B A

A B PDN
A GND
B
C
D

CSE477 Static CMOS, Ratioed Logic.13 Irwin&Vijay, PSU, 2002

Examples of consistent Euler path: ABDC, BDCA.

Examples of bad input ordering: DACB, BCAD.

 OAI22 Stick Diagram

A B D C

VDD

GND

Some functions have no consistent Euler path. For example:

y = !(a + bc + de).

CSE477 Static CMOS, Ratioed Logic.14 Irwin&Vijay, PSU, 2002

Since no consistent Euler path exists for y = a + bc+ de, it is impossible to draw
a single strip of n-diffusion and p-diffusion, with the same polysilicon ordering for
both NMOS and PMOS. The best we can do is to have a single strip for n-
diffusion and two strips of p-diffusions.

Exercise: Draw a compact stick diagram for y.

 VTC is Data-Dependent
A M3 B
A M2
VGS2 = VA –VDS1
B M1
VGS1 = VB
3 0.5 µm/0.25 µm NMOS
0.75 µm/0.25 µm PMOS
A, B: 0 -> 1
M4 B = 1, A: 0 -> 1
2 A = 1, B: 0 -> 1
For this case, both
F= A • B PMOS are either on or
D off together. When on,
W p effectively is
1 doubled (wrt to
S inverter circuit). Hence
D VTC moves to the
Cint right.
S 0
0 1 2

The threshold voltage of M2 is higher than M1 due to the body

effect (γ)
VTn1 = VTn0
V Tn 2 = V Tn 0 + γ ( )
− 2φ F + V SB 2 − − 2φ F = V Tn 0 + γ ( − 2φ F + V DS1 − − 2φ F )
VSB of M2 is not zero (when VB = 0) due to the presence of Cint
CSE477 Static CMOS, Ratioed Logic.15 Irwin&Vijay, PSU, 2002

VTC characteristics are dependent upon the gate inputs (so the noise margins
are also data dependent!)

Case 1 – both transistors in the PUN are on simultaneously (A = B = 0),

representing a strong pull-up, i.e. large W p. Referring to Inverter transparencies
pp. 16, 18, and 22, which say that VM increases if pull-up current is bigger, the
VTC is located to the right.

Cases 2 & 3 - only one of the pull-up devices is on. So the VTC is shifted left as
a result of the weaker PUN.

There is a small difference between Cases 2 and 3, which can be attributed to

the body effect on M2.
 Switch Delay Model

A Req
A

Rp
Rp Rp
B
A B Rp
A Rp Cint
Rn CL A
A Rn CL
A Rn Rn CL
Rn
Cint
A B
B
NOR2
NAND2 INV

CSE477 Static CMOS, Ratioed Logic.16 Irwin&Vijay, PSU, 2002

Note capacitance on the internal node – due to the source and drain diffusion
capacitances and overlap and channel capacitances of the series transistors.
 Input Pattern Effects on Delay

Delay is dependent on the pattern
of inputs

Low to high output transition
Rp Rp  both inputs go low
A B - delay is 0.69 Rp/2 CL
 one input goes low
Rn CL - delay is 0.69 Rp CL

A
High to low output transition

 both inputs go high
Rn
Cint - delay is 0.69 2Rn CL
B

CSE477 Static CMOS, Ratioed Logic.17 Irwin&Vijay, PSU, 2002

 Delay Dependence on Input Patterns

Input Data Delay

Pattern (psec)
A=B=0→1 80

A=1, B=0→1 70

A= 0→1, B=1 70

A=B=1→0 80

A=1, B=1→0 150

A= 1→0, B=1 130

- v(B) waveform is exactly similar to v(A) NMOS = 0.9 µm/0.3 µm

- v(OutBTran) is output waveform when PMOS = 0.75 µm/0.3 µm
A = VDD and B = v(B) CL = 10 fF
CSE477 Static CMOS, Ratioed Logic.18 Irwin&Vijay, PSU, 2002

Reason for difference in the last two delays is due to internal node capacitance
of the pull-down stack. When A transitions from 1 0, the pull-up only has to
charge CL; when A = 1 and B transitions, pull-up has to charge up both CL and
Cint.

For output high-to-low transitions (first three cases) delay depends on state of
Cint. Delay is worst when internal node is charged up to VDD – VT2 (refer circuit
on p. 15).

Conclusion: Estimates of delay can be fairly complex – have to consider internal

node capacitances and the input data patterns.
 Transistor Sizing

Rp Rp Rp
2 A B 2 4 B

Rn Rp Cint
CL 4
2 A
B

Rn Rn Rn CL
2 Cint
1
A A B 1

CSE477 Static CMOS, Ratioed Logic.19 Irwin&Vijay, PSU, 2002

Assumes Rp = 2Rn and Lp = Ln.

For an inverter, to get equal resistances for both pull-up and pull-down, W p =
2W n.

Our goal is to design circuits with worst case delay equal to that of the reference
inverter. The number besides each transistor in the circuits above denotes the
size of W of each transistor relative to the size of W for the inverter.

For NAND circuit, W for NMOS is doubled so that equivalent resistance of each
transistor is halved. Since we have two transistors in series, total pull-down
resistance is equal to that of the inverter, thus equal high-to-low delay.

Rp
2 A

1 Rn CL
A
 Transistor Sizing of Complex CMOS Gate

B 8
A 4
C 8

D 4
OUT = D + A • (B + C)
A 2
D 1
B 2 C 2

CSE477 Static CMOS, Ratioed Logic.20 Irwin&Vijay, PSU, 2002

Also note structure of pull-up and pull-down. The circuit is designed as above to
minimize diffusion cap at output (only one PMOS drain is connected to output).

Very slow circuit if D PMOS is moved up, and B & C NMOS also moved up. In
this case we have at the output node
for pull-up: drain capacitances of A & C transistors
for pull-down: drain capacitances of D, B & C transistors
 Fan-In Considerations

A B C D

A CL Distributed RC model
B C3 (Elmore delay)
C C2 tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)
D C1
Propagation delay deteriorates
rapidly as a function of fan-in –
quadratically in the worst case.

CSE477 Static CMOS, Ratioed Logic.21 Irwin&Vijay, PSU, 2002

 tp as a Function of Fan-In

NAND gate
1250
quadratic
1000
Gates with a
750 tpHL fan-in greater
tp (psec)

500
than 4 should
be avoided
250 tpLH
linear
0
2 4 6 8 10 12 14 16
fan-in

CSE477 Static CMOS, Ratioed Logic.22 Irwin&Vijay, PSU, 2002

Each NAND gate has fan-out of one inverter (W n = 0.5 micron, W p = 1.5 micron)

tpLH increases linearly due to the linearly increasing value of the diffusion
capacitance of PMOS transistors

tpHL increases quadratically due to the simultaneous increase in pull-down

resistances and internal capacitances
 Fast Complex Gates: Design Technique 1

Transistor sizing
 As long as fan-out capacitance dominates. Otherwise no delay
gain because while we reduce resistance, we also increase
capacitance!

Progressive sizing

M1 > M2 > M3 > … > MN (the

InN MN CL FET closest to the output is
the smallest)

In3 M3 C3 Can reduce delay by more than

20%; decreasing gains as
In2 M2 C2 technology shrinks
In1 M1 C1

CSE477 Static CMOS, Ratioed Logic.23 Irwin&Vijay, PSU, 2002

M1 has to carry the discharge current from M2, M3, …, MN and CL so make it
the largest transistor.

MN only has to discharge the current from CL.

 Fast Complex Gates: Design Technique 2

Transistor ordering

critical path critical path

0→1
1 In1
In3 M3 CL charged M3 CL charged
1 1
In2 M2
In2 M2 C2 discharged
C2 charged
1
In1 In3 M1 C1 discharged
M1 C1 charged
0→1

delay determined by time to delay determined by time to

discharge CL, C1 and C2 discharge CL only

CSE477 Static CMOS, Ratioed Logic.24 Irwin&Vijay, PSU, 2002

Place latest arriving signal (critical path) closest to the output

 Fast Complex Gates: Design Technique 3

Alternative logic structures

F = ABCDEFGH

Alternative 2

Alternative 1
CSE477 Static CMOS, Ratioed Logic.25 Irwin&Vijay, PSU, 2002

Reduction in fan-in offsets, by far, the extra delay incurred by the NOR gate
(second configuration).

Only simulation will tell which of the last two configurations is faster, lower
power.
 Ratioed Logic

V DD V DD VD D

Resistive Depletion PMOS

Load RL Load VT < 0 Load
V SS
F F F
In 1 In 1 In 1
In 2 PDN In 2 PDN In 2 PDN
In 3 In 3 In 3

V SS V SS VS S
(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS

Goal: to reduce the num ber of devices over complem entary CMOS

CSE477 Static CMOS, Ratioed Logic.26 Irwin&Vijay, PSU, 2002

The main concept of ratioed logic

1) Instead of using PUN and PDN (2N transistors), use a simple load device
and PDN only.
2) The load device can be a passive or an active device.
 Ratioed Logic

V DD

• N transistors + Load
Resistive
Load • VOH = VDD
RL
R PDN
• V OL =
R PDN + R L V DD
F • Assymmetrical response (tr > tf)

In1 • Static power consumption

In2 PDN
In3 • tpLH = 0.69RLCL

V SS

CSE477 Static CMOS, Ratioed Logic.27 Irwin&Vijay, PSU, 2002

1) The over-simplified concept

- when the PDN is off, VOH is pulled high by the load to strong logic
‘1’
- when the PDN is on, the VOL will be determined by the voltage
division
- VOL = ( RPDN/(RPDN+RL) )VDD
2) To keep the NML high, RL >> RPDN. This is why it is called ratioed. The
transistor must be carefully sized.
3) On the contrary, RL must be small enough to allow fast switching
1) tPLH = 0.69RLCL
2) tPHL = 0.69(RL||RPN)CL
4) tPLH is the main concern. RL >> RPDN to maintain high noise margin, but small
enough to enable fast switching.
5) Note that for ratioless logic (e.g. Complimentary CMOS) NMH and NML do not
depend on the transistor sizing.
6) Note also when the PDN is on, leakage current flows from VDD to VSS even in
steady state.
 Active Loads

V DD V DD

Depletion PMOS
Load VT < 0 V Load
VSS
F F
In1 In1
In2 PDN In2 PDN
In3 In3

VSS VSS

depletion load NMOS pseudo-NMOS

CSE477 Static CMOS, Ratioed Logic.28 Irwin&Vijay, PSU, 2002

The left diagram shows the usage of depletion load NMOS as load device. Yes,
all transistors are NMOS. Depletion mode NMOS has VT < 0 V. This method
was used during the NMOS era. The depletion NMOS is ON when VGS = 0 V. In
this case, the depletion load transistor is always on.

The second figure shows the pseudo-NMOS inverter. It resembles depletion

load, but gives superior characteristics. Unlike the depletion transistor, the
PMOS transistor does not have body effect since its source is always at VDD,
hence its VSB is constant at 0 V.

The PMOS is driven by VGSP = -VDD resulting in higher load current, compared to
the other circuit, hence better rise time.

For pseudo-NMOS inverter, assuming VOL is quite close to VSS when Vin = VDD,
we make assumption that NMOS is linear and PMOS is velocity saturated.
Equate currents
 V 2DSATp 

( )
2 
V OL 
k n (V DD − V Tn )V OL −
  = k p  V DD − V Tp V DSATp − 
 2   2
   
Assuming VDD – VTn >> VOL, VDD – |VTp| >> VDSATp, and VTn = |VTp|

kp
V OL ≈ V DSATp
kn
 Load Lines of Ratioed Gates
From Rabaey 1st ed.

1
Current source

0.75
IL(Normalized)

Pseudo-NMOS
0.5

Depletion load
0.25
Resistive load

0
0.0 1.0 2.0 3.0 4.0 5.0
V out (V)

CSE477 Static CMOS, Ratioed Logic.29 Irwin&Vijay, PSU, 2002

When using resistive load, IL = (VDD - VOUT)/Rl. The current drops as the output rises.
 Pseudo-NMOS NOR Gate

VDD

F
CL
A B C D

VOH = VDD (similar to complementary CMOS)

SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!

CSE477 Static CMOS, Ratioed Logic.30 Irwin&Vijay, PSU, 2002

Compared to complimentary CMOS, VOL != 0 V due to ratioed nature of pseudo-

NMOS structure.

All ratioed logic have these common attributes

1) the VTC is assymmetrical
2) consumption of static power when output is low, due to direct current path
between VDD and VSS through the load device
3) transistor scaling is very crucial
4) it uses only N+1 transistors instead of 2N for complimentary CMOS
 Pseudo-NMOS VTC

3.0

2.5

2.0 (W/L)p = 4

1.5
Vout [V]

(W/L)p = 2
1.0

(W/L)p = 0.5
0.5

(W/L)p = 0.25 (W/L)p = 1

0.0
0.0 0.5 1.0 1.5 2.0 2.5
V in [V]

CSE477 Static CMOS, Ratioed Logic.31 Irwin&Vijay, PSU, 2002

The VTC is for pseudo-NMOS inverter with NMOS size of 0.5 m/0.25 m. It
demonstrates the effect of load transistor size on VTC.

From the curves, higher (W/L)p gives higher VOL and higher static power
consumption (and vice versa).

Exercise: Calculate VOL using approx. eq. on p. 4 for case (W/L)p = 4. Use
transistor parameters on MOSFET transparency p. 22. Hint: Answer in text
p. 266 is wrong!

Exercise: Repeat for case (W/L)p = 2.

Exercise: Explain why answer is more accurate for 2nd case.