Hamacher et al, Computer Organization ECECS 326

Chapter 2: Addressing Methods & Program

Sequencing
n−bits
main memory: consists of a large number
0 word 0
of storage cells each of which can store
1 word 1
a binary digit (called a bit). These bits
address

are usually grouped together into words.

i word i The number of bits in a word is called
i+1 word i+1 the word length. Main memory is then
accessed on a word basis — each word
N−1 word N−1
having a unique address.
Main memory of N
memory operations: Fetch (or Read) and
words where N= for
Store (or Write).


some . 


Chapter 2: Addressing Methods & Program Sequencing 1
Hamacher et al, Computer Organization ECECS 326
Instructions & Instruction Sequencing
4 basic classes of instructions:
data transfer between MM and CPU registers
arithmetic and logic operations
program sequencing and control
I/O transfers
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Data Transfer & Arithmetic/Logic Instrs

instructions classified by number of operands:



3-address, 2-address,  -address, 1-address,
and 0-address.

Consider the operation: C  A B.

3-address instructions: Add A,B,C

2-address instructions: Move B,C

Add A,C


-address instructions: Load R(i),A

Add B,R(i)
Store R(i),C

1-address instructions: Load A

Add B
Store C

Data Transfer & Arithmetic/Logic Instrs 3

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Sequencing (or Branch) Instructions
2 types:
unconditional: br x
conditional: br R0=0,X
Using part of the machine state to determine the next course of
action: to branch or to continue in a straight line manner.
Condition Codes.
Sequencing (or Branch) Instructions 4
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Instruction Sequencing
Typically program instructions are executed in a
straight-line-sequence until one of the sequencing/control instruction
is executed.
Recall that maintenance of the current instruction address is
provided by a CPU register called the program counter (PC). Thus,
when a sequencing/control instruction is executed, it may cause a
modification of the contents of the PC.
Instruction Sequencing 5
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Instruction Execution
Instruction execution is a 3-phase process:

instr fetch: select an instr. from MM based on the

current value of the PC & place it in the IR.
instr decode: decode and fetch the operand
values.
instr execute: perform the appropriate data
transformations and store the results. In the
case of sequencing/branch instructions, update
the PC if necessary.

This process is called the fetch/decode/execute

cycle. In an operating computer, the
fetch/decode/execute cycle is iteratively executed
until a halt instruction is executed.

Note 1: Provided the instruction is not a sequencing/control

instr: Sometime during the fetch/decode/execute process the
value of the PC is incremented to point to the next instruction.

Note 2: All of this is a lie. Fortunately, it is a gross

generalization that will work for now.

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Addressing Modes
Types:
1. Register mode
2. Absolute mode
3. Immediate mode
4. Indirect mode
5. Index mode
6. Autoincrement mode
7. Autodecrement mode
Addressing Modes 7
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Addressing Modes: Register mode
PC Add R4,R5
Description: The operand is the contents
of a CPU register; the name of the register
R4 45 is given in the instruction.
R5 55
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Addressing Modes: Absolute mode
Instruction
Memory Description: The effective
(memory) address of the
location of the operand is
given explicitly as part of the
Operand instruction.
Addressing Modes: Absolute mode 9
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Addressing Modes: Immediate mode
Instruction
Description: The operand is given explicitly as
part of the instruction.
Operand
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Addressing Modes: Indirect mode
Instruction
Description: The effective
Memory address of the operand is
contained in a memory location
(or CPU register) whose
address is explicitly given in the
instruction.
Operand
Addressing Modes: Indirect mode 11
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Addressing Modes: Indexed mode
Description: The
Instruction effective address of the
operand is computed
by adding an index
operand value (commonly from
specifier Memory
a CPU register) to the
operand address given
in the instruction. When
+ Operand a CPU register holds
the PC, this addressing
register mode can be used
file
to get PC relative
addressing.
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Addressing Modes: Autoincrement mode
Description: The
Memory
Instruction effective address of the
operand is the contents
of a register specified
Operand in the instruction.
After accessing the
+ operand, the contents
register of the register are
file
incremented to point to
the next item on the list.
Addressing Modes: Autoincrement mode 13
Hamacher et al, Computer Organization ECECS 326
Addressing Modes: Autodecrement mode
Instruction Description: The
Memory contents of a
register specified
in the instruction is
decremented. The new
− Operand
register value is used
register as the effective address
file
of the operand.
Addressing Modes: Autodecrement mode 14