5.

Combinational Components 5-1

Chapter 5. Combinational Components

Introduction

☞ A combinational circuit is a logic circuit whose outputs at any time are deter-
mined directly and only from the present input combination.
✏ A combinational circuit performs a specific information-processing op-
eration fully specified logically by a set of Boolean functions.
☞ A sequential circuit is one that employ memory elements in addition to (com-
binational) logic gates—their outputs are determined from the present input
combination as well as the state of the memory cells.
✏ The state of the memory elements, in turn, is a function of the previous
inputs (and the previous state).
✏ Its behavior therefore is specified by a time sequence of inputs and inter-
nal states.

x1 z1
x2 .
Combinational
.
z2
. Logic .
. .
xn Circuit
zm

Figure 1: A combinational circuit.

Analysis Procedure

1. Make sure that the given circuit is combinational.

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5. Combinational Components 5-2

2. Derivation of the Boolean functions:

(a) Label all gate outputs that are functions of the input variables only. De-
termine the functions.
(b) Label all gate outputs that are functions of the input variables and previ-
ously labeled gate outputs, and find the functions.
(c) Repeat previous step until all the primary outputs of are obtained.
3. Derivation of the truth table (for n input variables):
(a) List all the 2 input combinations from 0 to 2
n
1. n

(b) Partition the circuit into small single-output blocks and label the output
of each block.
(c) Obtain the truth table of the blocks depending on the input variables only.
(d) Proceed to obtain the truth tables for other blocks that depend on previ-
ously defined truth tables.
A • T3

B • • T1
C F1

• T2
• T4
D •
F2
T5
Fig. 3-5 Logic Diagram for Analysis Example

Example 1 (Derivation of the Boolean functions)

T1 = B 0C
T2 = A0 B
T3 = A +T 1

T4 = T2 D
T5 = T2 +D
F2 = T5
F1 = T3 +T 4

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5. Combinational Components 5-3
Example 2 (Derivation of the truth table)
Verify that the following circuit is a full adder.
X • T1
Y • S
Z •
• T2
• T3
• •
•
•

• C
•

Fig. 3-6 Logic Diagram for Binary Adder

TABLE 3-1
Truth Table for Binary Adder

X Y Z C C T1 T2 T3 S

0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 1 1 1
0 1 0 0 1 0 1 1 1
0 1 1 1 0 0 1 0 0
1 0 0 0 1 0 1 1 1
1 0 1 1 0 0 1 0 0
1 1 0 1 0 0 1 0 0
1 1 1 1 0 1 1 0 1

Table 3-1 Truth Table for Binary Adder

Logic Simulation

☞ Logic simulation is a fast and accurate approach to analyzing a combinational

circuit.
☞ It usually generates waveforms instead of Boolean equations.
☞ The input can be a schematic or a netlist (containing inputs, gates, outputs,
and interconnections).
✏ Input methods can be formatted text, HDL (Hardware Description Lan-
guage) code, schematic, etc.

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2005
5. Combinational Components 5-4
Example 3 (Simulation of the binary adder)
We assume the inputs change every 20ns, and the gate delay is 1ns for all the gates.
Note that the gate delay will affect the operating speed of the circuit.
X

S
Y
AND3 OR2

OR3
AND2

AND2
INV

AND2
OR3

AND2

Fig. 3-7 Xilinx Foundation Schematic for Binary Adder in Figure 3-6
0.0 20ns 40ns 60ns 80ns 100ns 120ns 140ns

iX Cs
iY Cs
iZ Cs

oS
oC

Fig. 3-8 Waveforms for the Binary Adder Schematic in Figure 3-7

Hardware Description Language (HDL)

✯ A hardware description language is a programming language oriented to

hardware structure and behavior.
✏ Structure level
✏ Register-transfer-language (RTL) level
✏ Behavior level
✯ Popular HDLs:

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5. Combinational Components 5-5

✩ VHDL (VHSIC Hardware Description Language): a part of the Very-

High-Speed Integrated Circuits (VHSIC) program from the US Depart-
ment of Defense.
✩ Verilog: originally a proprietary language of a company, Gateway De-
sign Automation, which was bought out by Cadence Design Systems,
Inc.
✩ Both are IEEE standards.

Design Procedure

1. From the specifications, determine the inputs, outputs, and their symbols.
2. Derive the truth table (functions) from the relationship between the inputs
and outputs.
3. Derive the simplified Boolean functions for each output function.
☞ Under certain criteria: number of literals, number of gates, number of
inputs to a gate (fanin), propagation delay, number of interconnections,
fanout, power, etc.
4. Draw the logic diagram.
5. Verify the design.

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5. Combinational Components 5-6
Example 4 (BCD-to-Seven-Segment Decoder)
The BCD-to-seven-segment decoder produces the seven outputs (a; b; c; d; e; f; g )
from the 4-bit BCD input.
a
f b
e g c
d
(a) Segment designation (b) Numeric designation for display

Fig. 3-12 Seven-Segment Display

TABLE 3-3
Truth Table for BCD–to–Seven-Segment
Decoder

BCD Input Seven-Segment Decoder

A B C D a b c d e f g

0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
0 0 1 0 1 1 0 1 1 0 1
0 0 1 1 1 1 1 1 0 0 1
0 1 0 0 0 1 1 0 0 1 1
0 1 0 1 1 0 1 1 0 1 1
0 1 1 0 1 0 1 1 1 1 1
0 1 1 1 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1 0 1 1
All other inputs 0 0 0 0 0 0 0

Table 3-3 Truth Table for BCD–to–Seven-Segment Decoder

☞ The logic-0 denotes that the corresponding segment is turned off, while logic-
1 denotes a turned-on segment.
✏ The don’t-care conditions help minimizing the logic circuit, but they also
produce meaningless displays for the unused input combinations, so they
are all assigned 0 here.
☞ The number of gates can be reduced by sharing the common terms.

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5. Combinational Components 5-7

Half-Adder and Full-Adder

☞ The most basic arithmetic operation is the addition of 2 bits. A combinational

circuit that performs this operation is called a half-adder (HA).
☞ A combinational circuit that performs the addition of 3 bits is called a full-
adder (FA), which can be implemented by 2 half-adders.

x y x y S C
0 0 0 0 S = x0 y + xy0 = x y 

HA 0 1 1 0
C = xy
1 0 1 0

C S 1 1 0 1

Figure 2: Half-adder.

xy z x y z S C yz yz
x 00 01 11 10 x 00 01 11 10
0 0 0 0 0 0 1 1 0 1
0 0 1 1 0 1 1 1 1 1 1 1
FA
0 1 0 1 0 S C
C S
0 1 1 0 1
S = x0 y0z + x0 yz0 + xy0z0 + xyz = x y z
 
1 0 0 1 0
1 0 1 0 1 C = xy + yz + zx
1 1 0 0 1
1 1 1 1 1

Figure 3: Full-adder.

Subtractors

☞ Subtraction = addition of minuend and 2’s-complemented subtrahend.

☞ Also can implement subtraction directly—with half-subtractors and full-
subtractors.

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2005
5. Combinational Components 5-8
Half-subtractor Full-subtractor
x y D B x y z D B
D=x y z
 
0 0 0 0 0 0 0 0 0
0 1 1 1 0 0 1 1 1 B = x0y + x0z + yz
1 0 1 0 0 1 0 1 1
1 1 0 0 0 1 1 0 1

D=x y 
1 0 0 1 0
1 0 1 0 0
B = x0 y 1 1 0 0 0
1 1 1 1 1

Figure 4: Half-subtractor and full-subtractor.

Ripple-Carry Adders
Consider the n-bit binary addition:

(C n+1 Sn Sn 1


S )  (A A


A ) + (B B


B );
1 n n 1 1 n n 1 1

where C1 is the carry-in and C n+1 is the carry-out or overflow.

☞ S =A B C.
i i i i

☞ C =AB +BC +AC.

i+1 i i i i i i

☞ Alternatively, C = A B + C (A  B ).
i+1 i i i i i

☞ The computation time of a ripple-carry adder grows linearly with respect to

the word length n.
✏ T = O(n) due to the carry chain.

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5. Combinational Components 5-9

xi yi ci ci+1 si xi yi xi yi
ci 00 01 11 10 ci 00 01 11 10
0 0 0 0 0 0 1 3 2 0 1 3 2
0 0 1 0 1
0 1 0 0 1 0 1 1 0 1
0 1 1 1 0 4 5 7 6 4 5 7 6
1 0 0 0 1
1 0 1 1 0 1 1 1 1 1 1 1
1 1 0 1 0
1 1 1 1 1
+ yi O
si = x i O + ci + yi )
ci+1 = x i y i + ci (x i O

(a) Truth table for full adder (b) Map representation

xi yi

X Y

c out Adder c0
ci+1
ci

FA
S

si

(c) Full adder logic schematic (e) Graphic symbol

x7 y7 x6 y6 x5 y5 x4 y4 x3 y3 x2 y2 x1 y1 x0 y0

c7 c6 c5 c4 c3 c2 c1
cout FA FA FA FA FA FA FA FA c0

s7 s6 s5 s4 s3 s2 s1 s0

(d) 8−bit adder unit

Figure 5: Ripple-carry adder [Gajski].

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5. Combinational Components 5-10

Carry-Look-Ahead (CLA) Adders

✯ Carry lookahead is an important technique to speed up the addi-

tion/subtraction process, which eliminates the need to propagate the carries.
✯ The carry-generate function is defined as gx
y. i i i

✯ The carry-propagate function is defined as p  x  y (or sometimes as

p  x + y ).
i i i

i i i

✯ The look-ahead carry is c +1 i= x y + x c + y c = x y + (x + y )c = g + p c .

i i i i i i i i i i i i i i

✯ The summation is s i =x y c =p c.

i i i i i

ci+1 = gi +pc i i

ci+2 = gi+1 +p i+1 ci+1 =g +pi+1 i+1 gi +p pc i+1 i i

ci+3 = gi+2 +p i+2 ci+2 =g +pi+2 i+2 gi+1 +p p i+2 i+1 gi +p p pc i+2 i+1 i i

ci+4 = gi+3 +p i+3 ci+3 =g +pi+3 i+3 gi+2 +p p i+3 i+2 gi+1 +p p p i+3 i+2 i+1 gi +p i+3 pi+2pi+1pi c

☞ We do not have to wait for c to compute c +1.

i i

☞ Each of the carries has a fixed delay time from the time the carry-generate &
carry-propagate terms are available.
☞ However, be aware that NOT every gate has the same delay time. In general,
gates with a larger number of inputs have longer gate delays.
☞ The fanout of the carry-generate & carry-propagate terms also affects the
overall delay of the adder, so a CLA generator usually is limited to four bits.
Exercise 1
(a) Show that c +4 has a longer delay than c +1 .
i i

(b) Assume each two-input gate has a delay  , then what will be the delays for
c +1 and c +4 , respectively, counting from the time the carry-generate & carry-
i i

propagate terms are available?

(c) What will be the delay for c + ? i n 2

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5. Combinational Components 5-11

☞ Roughly, in the worst case an n-bit ripple-carry adder has 2n gate delays, but
an n-bit CLA adder has 4 log4 n gate delays, assuming only 2-input gates.

x i+3 y i+3 x i+2 y i+2 x i+1 y i+1 xi yi

2.4 4.2 2.4 4.2 2.4 4.2 2.4 4.2

gi pi
ci+3 ci+2 ci+1
ci+4 2.4 2.4 2.4 2.4 2.4 2.4 2.4 2.4 ci

FA 4.2 FA 4.2 FA 4.2 FA 4.2

s i+3 s i+2 s i+1 si

(a) 4−bit slice of a ripple−carry adder
x i+3 y i+3 x i+2 y i+2 x i+1 y i+1 xi yi

2.4 4.2 2.4 4.2 2.4 4.2 2.4 4.2

g i+3 p i+3 g i+2 p i+2 g i+1 p i+1 gi pi

4.2 4.2 4.2 4.2

s i+3 s i+2 s i+1 si

ci+4 CLA generator ci

g (i, i+3) p (i, i+3) c i+3 c i+2 c i+1

(b) 4−bit adder slice with CLA generator

g i+3 p i+3 g i+2 p i+2 g i+1 p i+1 gi pi

ci
2.4 2.4 3.2 3.2 2.4 2.4 3.2 2.4 2.4 2.4

3.2 3.2 2.4 2.4

ci+4 2.4
2.4

g (i, i+3) p (i, i+3) c i+3 c i+2 c i+1

(c) Logic schematic of CLA

Figure 6: CLA generator [Gajski].

Consider c +4 = g +3 + p +3g +2 + p +3p +2g +1 + p +3p +2p +1g

i i i i i i i i i i i +p i+3 pi+2pi+1pi ci
again. It can be rewritten as

ci+4 =g (i;i+3) +p (i;i+3) ci ;

where
g(i;i+3) =g +p i+3 i+3 gi+2 +p i+3 pi+2gi+1 +p i+3 pi+2pi+1gi ;

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5. Combinational Components 5-12

and
p(i;i+3) =p i+3 pi+2pi+1pi :

For example, a 16-bit CLA generator can be implemented as follows.

c4 = g(0;3) +p (0;3) c0

c8 = g(4;7) +p (4;7) c4

c12 = g(8;11) +p (8;11) c8

c16 = g(12;15) +p (12;15) c12

x15 y15 x14 y14 x13 y13 x12 y12 x11 y11 x10 y10 x9 y9 x8 y8 x7 y7 x6 y6 x5 y5 x4 y4 x3 y3 x2 y2 x1 y1 x0 y0

s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0

c12 c8 c4
c16 CLA CLA CLA CLA c0

(a) Single−level CLA generator

c16 CLA CLA CLA CLA

c12 c8 c4

c16 c0
CLA

c12 c8 c4
(b) 2−level CLA generator

Figure 7: Two-level, 16-bit CLA generator [Gajski].

Adders/Subtractors

✯ Binary subtraction normally is performed by adding the minuend to the two’s

complement of the subtrahend.
✯ Most calculators and some computers perform arithmetic operations directly
in the decimal number system, and represent decimal numbers in binary-
coded (i.e., BCD) form.

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2005
5. Combinational Components 5-13

A B

S Function Comment
S
0 A+B addition Adder/Subtractor
c out
1 A + B’+ 1 subtraction

F
(a) Truth table (b) Graphic symbol

a7 b7 a6 b6 a5 b5 a4 b4 a3 b3 a2 b2 a1 b1 a0 b0

c0
FA FA FA FA FA FA FA FA

f7 f6 f5 f4 f3 f2 f1 f0

(c) Logic schematic

Figure 8: Two’s-complement adder/subtractor [Gajski].

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2005
5. Combinational Components 5-14

Logic Unit (LU)

✯ A logic unit (LU) performs one of several Boolean functions on any two
operands, i.e., S = f (X; Y ). j

✯ We need selection inputs to specify which of the available functions we are

going to perform.
✯ For all 16 functions of two variables, we need four selection inputs: S3 , S2 ,
S1 , and S0.

✩ The encoding of the selection variables for a given function is such that
S = 1 iff m = 1 for that function.
i i

✩ When S3 S2 S1S0 is interpreted as a binary number, it is equal to the index

of the function selected.
✩ s i = S m + S m + S m + S m = S x0 y0 + S x0 y + S x y0 + S x y :
0 0 1 1 2 2 3 3 0 i i 1 i i 2 i i 3 i i

xi yi

S0 xi yi f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f 10 f 11 f 12 f 13 f 14 f 15
S1 m0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 S0
S2 m1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 S1
m2 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 S2
S3
m3 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 S3

(a) Boolean functions of 2 variables

LU

x7 y7 x6 y6 x5 y5 x4 y4 x3 y3 x2 y2 x1 y1 x0 y0
si

(b) Logic unit implementation

X Y
LU LU LU LU LU LU LU LU
S3
S2
S1 Logic Unit
S0

s7 s6 s5 s4 s3 s2 s1 s0
S
(c) Graphic symbol (d) 8−bit logic unit

Figure 9: An LU that can perform all 16 Boolean functions of two variables [Gajski].

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5. Combinational Components 5-15

Arithmetic-Logic Unit (ALU)

✯ An arithmetic-logic unit (ALU) performs the basic arithmetic and logic op-
erations in a processor.
✩ Arithmetic operations: addition, subtraction, increment, decrement, etc.
✩ Logic operations: AND, OR, identity, complement, etc.
✯ All arithmetic operations are based on addition.
✩ We design the ALU by modifying the inputs of a ripple-carry or CLA
adder.
✩ The modifying logic for arithmetic operations is called an arithmetic ex-
tender (AE).
✩ The modifying logic for logic operations is called a logic extender (LE).

a3 b3 a2 b2 a1 b1 a0 b0

LE AE LE AE LE AE LE AE

x3 y3 x2 y2 x1 y1 x0 y0
c3 c2 c1
c4 FA FA FA FA c0

f3 f2 f1 f0

Figure 10: Four-bit adder with AEs and LEs [Gajski].

Example 5
Consider the four-bit ALU with four arithmetic operations (addition, subtraction,
increment, and decrement) and four logic operations (AND, OR, identity, and
complement).
We use mode control variable M : if M = 1 then the ALU performs arithmetic
operations, and if M = 0 then the ALU performs logic operations.

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU

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5. Combinational Components 5-16

The AE design is shown in Fig. 11; the LE design is shown in Fig. 12; and the
final ALU design is shown in Fig. 13. 2
M S1 S0 Function name F X Y c 0

1 0 0 decrement A−1 A all 1s 0

1 0 1 add A+B A B 0
’
1 1 0 subtract A + B’+ 1 A B 1
1 1 1 increment A+1 A all 0s 1

(a) Functional table

M S1 S0 bi yi
bi
1 0 0 0 1 S 1 S0
1 0 0 1 1 bi 00 01 11 10 S0
0 1 3 2
S1
1 0 1 0 0 0 1 1
M
1 0 1 1 1 4 5 7 6

1 1 1
1 1 0 0 1

1 1 0 1 0 AE
1 1 1 0 0 y i = M S1’bi + M S’0 b’
i
yi
1 1 1 1 0

(b) Truth table (c) Map representation (d) Logic schematic

Figure 11: AE design [Gajski].

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2005
5. Combinational Components 5-17

M S1 S0 xi
M S1 S0 Function name F X Y c0
0 0 0 a ’i
0 0 0 Complement A’ A’ 0 0
0 0 1 a i bi
0 0 1 AND A AND B A AND B 0 0
0 1 0 ai
0 1 0 Identity A A 0 0
0 1 1 a i + bi
0 1 1 OR A OR B A OR B 0 0
1 x x ai

(a) Functional table (b) Truth table

a i bi

M=0 M=1
S 1 S0
a i bi 00 01 11 10 00 01 11 10 S0
0 1 3 2 16 17 19 18

S1
00 1
4 5 7 6 20 21 23 22
M
1
01 1
12 13 15 14 28 29 31 30

11 1 1 1 1 1 1 1
8 9 11 10 24 25 27 26

10 1 1 1 1 1 1
LE

x i = M’S1’S ’0 a ’i + M’S1 S 0 bi + S 0 a i bi + S1 a i + M a i
xi
(c) Map representation (d) Logic schematic

Figure 12: LE design [Gajski].

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2005
5. Combinational Components 5-18

a3 b3 a2 b2 a1 b1 a0 b0

S0
S1
M

L A L A L A L A

x3 y3 x2 y2 x1 y1 x0 y0
c3 c2 c1
c0
c4 FA FA FA FA

f3 f2 f1 f0
(a) 4−bit ALU

A B

S0
S1
ALU
M
c out

F
(b) Graphic symbol

Figure 13: Final ALU design [Gajski].

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU

2005
5. Combinational Components 5-19

Code Converter
y z CD CD
Circuit using A B C D w x 00 01 11 10 00 01 11 10
AB AB
BCD code 0 0 0 0 0 0 1 1 00 00 1 1 1
0 0 0 1 0 1 0 0 01 1 1 1 01 1
A B C D
0 0 1 0 0 1 0 1 11 X X X X 11 X X X X
0 0 1 1 0 1 1 0 10 1 1 X X 10 1 X X
Code converter
0 1 0 0 0 1 1 1 w = A + BC + BD x = B 0C + B 0D + BC 0 D0
0 1 0 1 1 0 0 0
w x y z CD CD
0 1 1 0 1 0 0 1 00 01 11 10 00 01 11 10
AB AB
Circuit using 0 1 1 1 1 0 1 0 00 1 1 00 1 1
Excess-3 code 1 0 0 0 1 0 1 1 01 1 1 01 1 1
1 0 0 1 1 1 0 0 11 X X X X 11 X X X X
10 1 X X 10 1 X X
y = CD + C 0D0 z = D0
Figure 14: BCD to excess-3 code conversion.

✯ The expressions obtained may be manipulated algebraically for the purpose

of using common gates for 2 or more outputs.
w = A + BC + BD = A + B (C + D)
x = B 0 C + B 0 D + BC 0D0 = B 0 (C + D) + B (C + D)0
y = CD + C 0D0 = CD + (C + D)0
z = D0

Decoders and Encoders

✯ A decoder is a combinational circuit that converts binary information from n

input lines to a maximum of 2 unique output lines.
n

✩ Can be implemented with AND gates.

✯ An encoder is a combinational circuit that performs the inverse operation of
a decoder.
✩ Can be implemented with OR gates.

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU

2005
5. Combinational Components 5-20

Decimal 8 3
 Binary 3 8
 Decimal
World Encoder System Decoder World

Figure 15: Encoder and decoder.

A0
E A0 C1 C0
1 0 0 1
Decoder
E
1 0 1 1 1 0

0 x 0 0
C1 C0
(a) Graphic symbol (b) Truth table

A0
C 0 = E A’0 C0

C 1 = E A0 C1
E

(c) Boolean expression (d) Logic diagram

Figure 16: A 1-to-2 decoder [Gajski].

☞ The decoder output variables are mutually exclusive because only one output
can be equal to 1 at any time.
☞ The output line whose value is 1 represents the minterm equivalent of the
binary number presently available in the input lines.
☞ A decoder with an enable (E) input is also called a demultiplexer (DMUX or
DEMUX).
☞ Larger decoders can be implemented using smaller decoders.

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU

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5. Combinational Components 5-21
E A2 A1 A0 C7 C6 C5 C4 C3 C2 C1 C0
1 0 0 0 0 0 0 0 0 0 0 1
1 0 0 1 0 0 0 0 0 0 1 0
1 0 1 0 0 0 0 0 0 1 0 0
1 0 1 1 0 0 0 0 1 0 0 0
1 1 0 0 0 0 0 1 0 0 0 0
1 1 0 1 0 0 1 0 0 0 0 0
1 1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 1 0 0 0 0 0 0 0
0 x x x 0 0 0 0 0 0 0 0

(a) Truth table

E A2 A1 A0

E E A2 A1 A0
1 0

E
1 0
E E
1 0 1 0

E E
3 2 1 0 3 2 1 0

E E E E
1 0 1 0 1 0 1 0 C7 C6 C5 C4 C3 C2 C1 C0

C7 C6 C5 C4 C3 C2 C1 C0

(b) Implementation with 1−to−2 decoders (c) Implementation with 2−to−4 decoders

Figure 17: A 3-to-8 decoder [Gajski].

☞ A decoder can provide all 2 minterms of n input variables. n

☞ Any combinational circuit with n inputs and m outputs can be implemented

with an n-to-2 decoder in conjunction with m external OR gates.
n

☞ The Boolean functions for the circuit should be expressed in sum of

minterms.

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU

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5. Combinational Components 5-22

D0 = A2 A1 A0

• • •
•
D1 = A2 A1 A0

A0 • • •
D2 = A2 A1 A0
• • •

A1
•
• • D3 = A2 A1 A0
•
• •
• D4 = A2 A1 A0
A2 • •
•
D5 = A2 A1 A0
•

• D6 = A2 A1 A0
•

D7 = A2 A1 A0

Fig. 3-13 3-to-8-Line Decoder

Figure 18: Direct implementation of the 3-to-8 decoder [Mano & Kime].

Exercise 2
(a) Show how to implement f1 = ABC + A0C 0 and f =
2 AC 0 + B 0C using a
3-to-8 decoder and 2 OR gates.
(b) Since a NAND gate produces the AND operation with an inverted output, it be-
comes more economical to generate the decoder minterms in their complemented
form. Show how to do that. 2

Combinational Circuit Design Using Decoders

✯ An n-input decoder provides all the 2 minterms.

n

✯ Any Boolean function can be expressed as a sum of minterms, so it can be

generated by a decoder plus OR gates.

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU

2005
5. Combinational Components 5-23
Example 6
Implement the binary adder fS; C g = X + Y + Z (where + is the arithmetic
addition) using a decoder and OR gates.

(
S X; Y; Z ) = (1; 2; 4; 7); C (X; Y; Z ) = (3; 5; 6; 7)
3–to–8
Decoder
0
1
Z 20 S
2
3
Y 21 4
5 C
X 22 6
7 •

Fig. 3-16 Implementing a Binary Adder Using a Decoder

2
☞ A function with k > 2 =2 minterms can be expressed in its complement form
n

with 2 n
k minterms.

✏ NOR gates are used instead of OR gates.

☞ If NAND gates are used for the decoder, then the output OR gates are re-
placed by NAND gates.

Multiplexers/Selectors

✯ A multiplexer (MUX) is a combinational circuit that selects (usually by n

select lines) binary information from one of many (usually 2 ) input lines n

and directs it to a single output line.

✩ Also called a selector.
✯ A multiplexer bears no resemblance to a decoder. On the contrary, it can be
viewed as extended from a decoder (see Fig. 20).

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU

2005
5. Combinational Components 5-24

S1 S0 Y
D3 D2 D1 D0
0 0 D0
3 2 1 0
S1 0 1 D1
Selector
S0
1 0 D2
Y
1 1 D3

(a) Graphic symbol (b) Truth table

S0
S1

D0
Y = S 1’S0’D 0 + S 1’S0 D 1
+ S 1S’0 D2 + S 1S0 D3 D1
Y
D2

D3

(c) Boolean expression (d) Logic diagram

Figure 19: A 4-to-1 multiplexer (selector) [Gajski].

I0
I1 .
Y
I2
.

I3 . .

ss1 .
2 4 Decoder


0 .

Figure 20: A MUX can be considered as extended from a decoder.

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU

2005
5. Combinational Components 5-25

☞ Two or more multiplexers may be enclosed within one IC package, sharing

selection and enable inputs.
☞ MUX = decoder + OR gate + selectable/controllable minterms.

☞ An n-variable Boolean function can be implemented with a 2 -to-1 or 2 1- n n

to-1 MUX (see Fig. 21): if m is to be included in f , set I = 1, else set

i i

I = 0.
i

A B C f
0 0 0 0
C
0 0 1 1
I0 C I0
0
II1
C 0 I1 4 1
0 1 0 1 1
C0 1
II23 8 1 Y f
1 I2 MUX Y f
0 1 1 0 0  
1
II45 MUX
0 I3
1 0 0 1 1
1 0 1 1
1 0
0 I67 s2 s1 s0 s1 s0
1 1 0 0
0 A B C A B
1 1 1 0

A I0
BCI0 I1 I3 I2 1 I1
A 00 01 11 10 4 1
A0 I2 MUX Y f

0 0 1 0 1
0 I3
1 1
A
1
1
0
0
0
A0 s1 s0
B C

Figure 21: Boolean function implementation using MUX.

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU

2005
5. Combinational Components 5-26

C2 C1 C0 Y
0 0 0 D0
0 0 1 D1
0 1 0 D2
0 1 1 D3
1 0 0 D4
1 0 1 D5
1 1 0 D6
1 1 1 D7

(a) Truth table

D7 D6 D5 D4 D3 D2 D1 D0

1 0 1 0 1 0 1 0

C2

1 0 1 0

C1

1 0
C0

Y
(b) Implementation with 2−to−1 selectors
C2 C1 C0 Y
0 0 0 D0
0 0 1 D1
0 1 0 D2
0 1 1 D3
1 0 0 D4
1 0 1 D5
1 1 0 D6
1 1 1 D7

(a) Truth table

D7 D6 D5 D4 D3 D2 D1 D0
76543210

C0
Decoder

C1
C2

Y
(b) Implementation with a decoder

Figure 22: Two 8-to-1 MUX implementations [Gajski].

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU

2005
5. Combinational Components 5-27

Buses

✯ Bus is a common communication channel which is routed around modules

(e.g., controller, ALU, register file, memories, etc.) on a microchip or PCB.
✯ To construct a bus, we use a component called the tristate driver, which has
three possible output states, i.e., 0, 1, and Z (high impedance).
✯ Functionally, a bus is equivalent to a selector—it has many inputs but allows
only one data on the bus at a time.

E Y
E
0 Z
D Y
1 D

(a) Tristate driver symbol (b) Truth table for tristate driver

S Bus
S Y
D0
0 D0
Y
D1 1 D1

(c) 2−input bus (d) Truth table for 2−input bus

S1 S0

Decoder
3 2 1 0

Bus S1 S0 Y
0 0 D0
D0
0 1 D1

D1 1 0 D2
Y 1 D3
1
D2

D3

(e) 4−input bus (f) Truth table for 4−input bus

Figure 23: Bus implementation [Gajski].

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU

2005
5. Combinational Components 5-28

Priority Encoders

✯ A priority encoder has n inputs, D 1 ; D 2; : : : ; D0, where n = 2 for n n

m

some m. It has m outputs, A 1; A 2; : : : ; A0, in addition to a specific

m m

output called Any, which will be 1 iff any of the inputs has a value different
from 0.
✯ The outputs A 1; A 2; : : : ; A0 represent the index of the most significant
m m

input bit that has a value 1.

✯ A 2-to-1 priority encoder, e.g., can be implemented using only a two-input
OR gate (see Fig. 5.18, p. 191, of the textbook).

D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 A2 A1 A0 Any
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 0 1 x 0 0 1 1
0 0 0 0 0 1 x x 0 1 0 1
0 0 0 0 1 x x x 0 1 1 1
0 0 0 1 x x x x 1 0 0 1
0 0 1 x x x x x 1 0 1 1
0 1 x x x x x x 1 1 0 1
1 x x x x x x x 1 1 1 1
(a) Truth table

D7 D6 D5 D4 D3 D2 D1 D0 D 3 D 2D 1D 0
D 7 D 6D 5D 4

1 0 1 0 1 0 1 0
3 2 1 0 3 2 1 0
encoder encoder encoder encoder
encoder encoder

1 0 1 0 1 0 1 0
S S
encoder selector encoder selector

1 0 1 0 1 0
encoder S S
selector selector
1 0 1 0 1 0
S S
encoder selector selector

Any A2 A1 A0
Any A2 A1 A0

(b) Implementation with 2−to−1 encoders and selectors (c) Implementation using 4−to−2 encoders

Figure 24: An 8-to-3 priority encoder [Gajski].

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU

2005
5. Combinational Components 5-29

Magnitude Comparators

A magnitude
A<B
A=B
B comparator
A>B

Figure 25: Block diagram of the magnitude comparator.

✯ If A and B are n-bit numbers, then a single combinational circuit module has
22 rows in its truth table, and becomes too cumbersome even with n = 3.
n

✯ We shall investigate the regularity possessed by the comparator circuit, and

seek to reduce the design effort. A regular circuit usually can be described
(designed) by way of an algorithm.

Let n = 4, i.e., A = a a a a , and B = b b b b . Define the equality indicator

3 2 1 0 3 2 1 0

xi  a  b = a b + a0 b0 , i = 0; 1; 2; 3.
i i i i i i

(A = B ) = x x x x 3 2 1 0

(A > B ) = a b0 + x a b0 + x x a b0 + x x x a b0
3 3 3 2 2 3 2 1 1 3 2 1 0 0

(A < B ) = a0 b + x a0 b + x x a0 b + x x x a0 b
3 3 3 2 2 3 2 1 1 3 2 1 0 0

In the last 2 equations, we need the components a b0 and a0 b . However, note that
x = a  b = (a  b )0 = (a b0 + a0 b )0, i.e., the components can be shared.
i i i i

i i i i i i i i i

Exercise 3
(a) Implement the comparator based on the above algorithm.
(b) How do you extend the algorithm to an arbitrary n? 2
Now let G = 1 when A > B , L = 1 when A < B , and G = L = 0 when A = B .
From the above algorithm, we obtain

Gi = (a i ) ((a = b ) and (G
> bi or i i i 1 > Li 1 ));
Li = (a i < b ) or ((a = b ) and (G
i i i i 1 < Li 1 )):
This leads to regular implementation of magnitude comparators as shown below.

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU

2005
5. Combinational Components 5-30

a1 b1

a 1 b1 a 0 b0 G L

0 0 0 0 0 0
0 0 0 1 0 1
0 0 1 0 1 0 G a0
0 0 1 1 0 0
0 1 0 0 0 1
0 1 0 1 0 1
0 1 1 0 0 1
0 1 1 1 0 1
1 0 0 0 1 0
1 0 0 1 1 0
1 0 1 0 1 0
1 0 1 1 1 0 L b0
1 1 0 0 0 0
1 1 0 1 0 1
1 1 1 0 1 0
1 1 1 1 0 0 2−bit comparator

(a) Truth table (c) Logic schematic

a 0 b0 a 0 b0
a 1 b1 00 01 11 10 a 1 b1 00 01 11 10
0 1 3 2 16 17 19 18

00 1 00 1
4 5 7 6 20 21 23 22

01 01 1 1 1 1
12 13 15 14 28 29 31 30

11 1 11 1
8 9 11 10 24 25 27 26

10 1 1 1 1 10

G = a 1 b’1 + a 1 a 0 b’0 + a 0 b’1 b0’ L = a’ ’ ’ ’

1 b1 + a 1 a 0 b0 + a 0 b1 b0

(b) Map representation

x7 y7 x6 y6 x5 y5 x4 y4 x3 y3 x2 y2 x1 y1 x0 y0

G7 G6 G5 G2 a1 b1
G4 G3 G1
G G G G G G G a0
L7 L6 L5 L4 L3 L2 L1
L L L L L L L b0

(a) Serial implementation

x7 y7 x6 y6 x5 y5 x4 y4 x3 y3 x2 y2 x1 y1 x0 y0

a1 b1 a0
G L b0 G L G L G L

G L G L

G L

(b) Parallel implementation

Figure 26: A 2-bit and an 8-bit magnitude comparators [Gajski].

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU

2005
5. Combinational Components 5-31

Shifters and Rotators

✯ A shifter shifts one bit position of its content to the left or right at a time,
taking the input bit from the right or left when it shifts.
✯ A rotator rotates one bit position of its content to the left or right at a time,
routing the output bit back to its input.

S2 S1 S0 Y Comment
0 0 x D no shift
0 1 x not used
1 0 0 shl(D) shift left
1 0 1 rtl(D) rotate left
1 1 0 shr(D) shift right
1 1 1 rtr(D) rotate right

(a) Functional table

d7 d6 d5 d4 d3 d2 d1 d0
Right
input

Left
input

1 0 1 0
S0
Selector Selector

3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
Selector Selector Selector Selector Selector Selector Selector Selector
S1
S2

y7 y6 y5 y4 y3 y2 y1 y0

(b) Shifter implemented with 4−to−1 selectors

Figure 27: An 8-bit shifter for shifting or rotating one bit position to the left or right [Gajski].

☞ An m-bit shift to the right represents division by 2 . m

✏ Sign extension has to be performed during an arithmetic right shift of a

2’s-complement number.
☞ An m-bit shift to the left represents multiplication by 2 . m

✏ For arithmetic left shift, 0’s have to be entered from the right input. In
addition, the MSB must be made the duplicate of the sign bit after the
left shift.

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU

2005
5. Combinational Components 5-32

✯ A barrel shifter shifts any number of positions at a time.

✯ A barrel rotator rotates any number of positions at a time.

S2 S1 S0 y7 y6 y5 y4 y3 y2 y1 y0
0 0 0 d 7 d6 d5 d4 d3 d2 d1 d0
0 0 1 d 0 d7 d6 d5 d4 d3 d2 d1
0 1 0 d 1 d0 d7 d6 d5 d4 d3 d2
0 1 1 d 2 d1 d0 d7 d6 d5 d4 d3
1 0 0 d 3 d2 d1 d0 d7 d6 d5 d4
1 0 1 d 4 d3 d2 d1 d0 d7 d6 d5
1 1 0 d 5 d4 d3 d2 d1 d0 d7 d6
1 1 1 d 6 d5 d4 d3 d2 d1 d0 d7

(a) Truth table

d7 d6 d5 d4 d3 d2 d1 d0

1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

S0

1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

S1

1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

S2

y7 y6 y5 y4 y3 y2 y1 y0

(b) Rotator implemented with 2−to−1 selectors

Figure 28: An 8-bit barrel right rotator [Gajski].

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU

2005
5. Combinational Components 5-33

Read-Only Memories

✯ Read-only memory (ROM) = decoder (AND array) + OR gates (OR array).

✩ It inherently has a 2-level AND-OR (or any possible 2-level) structure,
thus can implement concurrently any number of combinational functions
which have the same input set.
✯ ROM is used to implement complex combinational circuits within one IC
package or as permanent storage for binary information.

A0
n inputs 2n m
 A1 n 2n
 OR
ROM Decoder






Array
An 1

m outputs address word lines F1 F2 Fm

Figure 29: Read-only memory (ROM).

☞ There are 2 distinct addresses in a 2

n n
 m ROM, which address to 2 n
distinct
m-bit words of information.

✏ It can implement m arbitrary functions of n inputs.

☞ A ROM is sometimes specified by the total number of bits it contains, which
is 2  m. The same capacity, however, can come from arrays with various
n

dimensions.
✏ For example, a 2K ROM may be arranged as 2048 words  1 bit, 512
words  4 bits, 256 words  8 bits, 128 words  16 bits, etc.
☞ Types of ROM:
✏ ROM: mask programmable ROM (costly if quantity is small)
✏ PROM: (field) programmable ROM
✏ EPROM: erasable PROM
✏ EEPROM: electrically erasable PROM

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU

2005
5. Combinational Components 5-34

Computational Programmable
symbols symbols
A A B CD
B
C
D

A A B CD
B
C
D

Figure 30: Programmable symbols of AND and OR [Gajski].

OR array
0
1
2
3
A0 4
5
A1 4−to−16 6
decoder 7
A2 8
9
A3
10
11
12
13
14
15

F3 F2 F1 F0

Figure 31: A 16  4 ROM [Gajski].

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU

2005
5. Combinational Components 5-35

A3 A 2 A1 A0 F3 F2 F1 F0
ai bi (S) (ai ) (bi ) (ci ) (c )(f i)
i+1

S 0 0 0 0 x x 0 0
0 0 0 1 x x 0 1
0 0 1 0 x x 0 1
0 0 1 1 x x 1 0
0 1 0 0 x x 0 1
0 1 0 1 x x 1 0
0 1 1 0 x x 1 0
0 1 1 1 x x 1 1
FA c i+1 FA c i FA 1 0 0 0 x x 0 1
1 0 0 1 x x 1 0
1 0 1 0 x x 0 0
1 0 1 1 x x 0 1
1 1 0 0 x x 1 0
1 1 0 1 x x 1 1
fi 1 1 1 0 x x 0 1
1 1 1 1 x x 1 0

(a) Adder/subtractor bit slice (b) Truth table

OR array
0
1
2
3
A0 4
5
A1 4−to−16 6
decoder 7
A2 8
9
A3
10
11
12
13
14
15

F3 F2 F1 F0

(c) ROM program

Figure 32: An implementation (programming) of the adder/subtractor bit slice using the 16  4
ROM [Gajski].

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU

2005
5. Combinational Components 5-36

Programmable Logic Arrays

✯ For cases where the number of don’t-cares is excessive, it is better to use a

programmable logic array (PLA).
✯ A ROM can be programmed only in its OR array. On the contrary, a PLA
can be programmed both in its AND array and its OR array.
k product terms
A0 .
A1 AND OR A . .
AND Array



Array


Array . .
An 1 B .



. . f1 = A0B 0 + AB
F1 F2 Fm OR Array
. . f2 = AB + AB 0

Figure 33: Programmable logic array (PLA).

☞ The size of a PLA is specified by the number of inputs n, the number of

product terms k , and the number of outputs m. The number of programmed
fuses therefore is 2n  k + k  m + m.
✏ The PLA is said to be a n  k  m PLA.
☞ To minimize the size of the PLA, it is important to simplify the output func-
tions such that the total number of product terms used by all output functions
is a minimum. Note that complemented outputs (f 0) are allowed.i

☞ The PLA also may be mask-programmable or field-programmable.

✏ The FPLA can be programmed by the user, by means of a hardware
programmer.

✯ The programmable array logic (PAL) is a programmable logic device with a

fixed OR array and a programmable AND array.
✯ It is easier to program, but is not as flexible as compared with the PLA.
✯ Unlike the PLA, a product term can not be shared among 2 or more OR
gates. Therefore, each function can be simplified by itself without regard to
common product terms.

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU

2005
5. Combinational Components 5-37

A3 A 2 A1 A0

OR array

0
1
2
3
4
5
6
7

AND array

0 1
Output array

F3 F2 F1 F0

Figure 34: The PLA structure [Gajski].

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU

2005
5. Combinational Components 5-38

xi yi
ci 00 01 11 10
0 1 3 2

A3 A 2 A1 A0 F3 F2 F1 F0 1 1
0
xi yi ci s i ci+1
4 5 7 6

x 0 0 0 x x 0 0
x 0 0 1 x x 0 1 1 1 1
x 0 1 0 x x 0 1
x 0 1 1 x x 1 0
x 1 0 0 x x 0 1 00 01 11 10
x 1 0 1 x x 1 0 0 1 3 2

x 1 1 0 x x 1 0 1
x 1 1 1 x x 1 1 0
4 5 7 6

1 1 1 1

(a) Truth table (b) Map representation

(x i) (y i ) (c i )
A3 A 2 A1 A0

OR array

0 x ’i y ’i ci

1 x ’i y i ci’

2 x i y ’i ci’

3 x i y i ci

4 xi yi
5 x i ci
6 y i ci

AND array

0 1

F3 F2 F1 F0
(not used) (si ) (c i+1 )

(c) PLA implementation

Figure 35: The full adder implemented by a 4  8  4 PLA [Gajski].

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU

2005
5. Combinational Components 5-39

Fixed Programmable
Inputs Programmable Outputs
AND array
Connections OR array
(decoder)

(a) Programmable read-only memory (PROM)

Programmable Programmable
Inputs Fixed Outputs
Connections AND array OR array

(b) Programmable array logic (PAL) device

Programmable Programmable Programmable

Inputs Programmable Outputs
Connections AND array Connections OR array

(c) Programmable logic array (PLA) device

Fig. 6-23 Basic Configuration of Three PLDs

Figure 36: Summary of three PLDs [Mano & Kime].

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU

2005