CURRICULUM VITAE

Anuj Kumar Bansal

Born on India in 1977, Indian Passport no. M6829998 validity up to 25thFeb, 2025
1101, KM03, JP Cosmos, Sector-134,.Noida 201304
Tel: +91-8171423034, 7830003034
https://www.indiamart.com/bsr-infotech-noida/
Email: anujkbansal@gmail.com; anujbansal.bsr2020@gmail.com

Academic Qualifications :
 M.Tech. in Instrumentation in 2000, N.I.T Kurukshetra, Kurukshetra, Haryana, INDIA
 M.Sc.in Physics with Electronics specialization in 1998, I.I.T. Roorkee, Uttarakhand, INDIA

Personality :
Innovative, creative and analytical person that enjoy to acquire new knowledge and experience and to work with challenging
tasks. Approaches problem solving in a systematic and organized way. Has the ability to reach at a very detailed level while still
maintaining overview and orientation.

Experience :
More than 20 years of professional experience from working with innovative and cutting-edge companies. I have worked
extensively with all phases of the embedded product development i.e. strategic planning, budgeting, requirements,
specification, electronic design, mechanical design, HW/FW/FPGA (logical, digital, PCB) implementation, testing, validation and
documentation. I have successfully managed multi projects in single time frame. Since last few years, taking end to end
ownership of high-end designs with compliance testing & field implementation. Working closely with System Designers, HW
team, FW team and Software team.
My Primary skill is bare metal, low level Firmware designing and secondary skill is multiple project management of different
domains and different technologies.

Core Technical Highlights :

 End to End Product/Board designing for Medical, Railway, Industrial Automation, EDA and Metering companies
 Worked on Vehicle diagnosis kits, firmware based tachometer, harmonics analysis for tool industries
 Blood Bank and Dialysis equipment designing/re-designing as per ISO 13485 and FEDA standards
 SoC (FPGA+ARM) based design in which multiple standard interfaces like DDR memories, PCIE Gen 2, Interconnects, fast
I/O transceivers etc. worked with internal AMBA/AXI/AXI Stream interfaces
 Studied on Peripheral, Processor, Platform modelling in OVPsim Simulator, EQMU, SystemC, TLM 2.0 interface
 High end three/single phase energy metering design and analog panel metering design for Indian clients
 Involved in Hardware Circuit & Firmware designing of multiple railway products i.e GPS based Passenger Information
System (PIS), Integrated Passenger Information System (IPIS), Earth Leakage Detector, Hot Axle Hot Wheel etc. with
railway vendors. Followed RDSO specification and STR for functional as well as compliance testing
 Successfully Start to End product design of home automation products like touch switch boards and its Wireless interfaces
and networking with home energy meter
 Worked and managed multiple board design projects include its h/w design, DSP f/w design and FPGA/CPLD design for
elevator system and automotive
 Involved in embedded OS based FW design for Programmable Logic Controller and code written for low level boot loader,
50 types of ladder instructions, PLC-GUI interfacing for ladder programming and industrial protocols
 R&D of physical layer for 802.11a/b/g wireless modem which finally developed on Spartan 3 FPGA and Blackfin DSP. V&V
for couple of building automation products
 Worked for R&D firm of energy meters with DSP functions like sampling & quantization, FIR filter, 90-degree delay filter,
FFT and metering parameters on 218x DSP core, AD micro converter and metering ASICs
 FW design both for BARE METAL applications and OS based applications. Good experience on boot loaders for DSP and uC
 Application software designing in VC++ and Android App designing in Android Studio
 Strictly followed design & QA standards, country & domain specific standards, safety & environment standards etc.
 Pre certification & qualification thereby allowing customers to take a product from concept to realization.
 Guide team on designing of mechanical parts either metal or plastic, 3D printing, die moulds and mould samples

1
Managerial Specialties :
 Managed multiple domain R&D team of medical equipment’s with very closely coordination with production team
 Created project specific infrastructures, testing labs, teams with clear vision & targets in multiple times for various
companies
 Leadership skills for mentoring, motivation and consensus building to create high performance self-motivated teams
 Project management, multi project execution, proposal writing, technical estimation, resource estimation, configuration
management, risk management and their mitigation, quality audits
 Have worked and help sales team to enlarge businesses in many eastern countries Japan, China and Singapore
 Handled non-technical issues like HR, admin, transport, patent & trademark registration, library, interviews, appraisals etc.

Technical Skills :
 uC and DSPs ARM-v7,v8, Cortex-A/R/M, TMC320, DSP Blackfin series, ADSP218X and 219X series,
Multiple 8 and 16 bits uC of TI, Renesas, Atmel, NXP, PIC, HOLTEK, ST, Freescale etc.
 Firmware Design Tools Keil, Analog Studio, CCS, HEW, EZ-ICE, PALMiCE2, Atmel Studio, PetaLinux
 Embedded Operating System Window CE, NORTI, uTRON, LINUX, Android
 Hardware Architecture Harvard Architecture, von Neumann Architecture, Super Harvard, RISC, CISC
 Hardware Interfacing Buses I2C, SPI 4.0, UART, USB, 51core external bus, DDR3, PCI-3.0, PCIE-3.0, AXI, AXI-Lite, AXI-
Stream, High Speed Transceivers, CISC based backplane
 VLSI Design Languages VHDL, Verilog, System Verilog
 FPGA and SoCs Xilinx Spartan 3, 6 & 7, Zynq 7000, Zynq UltraScale 20nm/14nm SoC
 FPGA Design Tools Vivado, IP Integrator, Chipscope, Quartus, ISE, Modelsim, Chip Scope Embedded Logic
 Soft Processor Microblaze, Zynq-7000-PS
 Modelling Languages SystemC, TLM2.0
 Modelling Tool OVPsim Simulator, QEMU
 PCB Design Tools OrCAD, Altium, PCAD, DipTrace
 Mechanical Design Tools SolidWorks Plastic, AutoCAD
 High Level Languages C, C++, VC++, Java, Android Programming
 GUI Design Tools Android Studio, Visual Studio, Turbo C Compiler
 USB Renesas RL78/G1C uC based PHID, PCDC, HCDC, Android HCDC classes
 Wireless Protocols OFDM based 802.11a/b/g physical layer, Wi-Fi, Zigbee, Bluetooth
 Industrial Protocols RS-485, RS-422, Modbus-RTU, Modbus- TCP/IP, ANSI C12.18/C12.19/C12.21, IEC1806,
Allen Bradley DH485, Allen Bradley DH+, GE, OMRON, Siemens, Koyo Device Net, Koyo K- Sequence and Mitsubishi
 Automotive Protocol & Tools CAN 2.0, CAPL, CAN Analyzer, CANoe, ECU Networking, CAN Network Diagnosis Tools
 MCT detector & accessories Sensor MCT-5-TE3-0.25 (2um to 5um), HY5605, MCT1000 preamplifier
 HW lab instruments CRO RIGOL DS1052E, MSO5000, Tektronix TBS1000, DPO7000, Multimeter Fluke87V
 HW lab instruments Signal generator DDS150, Scientech1500, Keysight waveform generator 33511B
 Digital lab instruments Keysight U43018, logic analyser 16860A
 EMI EMC pre compliance test lab Tektronix spectrum analyser RSA306B, RSA5000B
 Energy Metering test lab 0.01 class metering test machine of TOSHIBA
 H/W Testing Tools Others Lux Meter, High Voltage Insulation Tester, Variable DC/AC supply, Voltage variac,
Current variac, H.V tester (2000V), I.R. tester (500V), LCR meter, High Temperature Tester (0-1000C)
 Standards EMI/ EMC/ESD, IEC, ANSI, BIS, EN, CE, UL, RoHS, ISO 9001, CMMI5, Six-Sigma, FDA
 Project Management Microsoft Project, Jira, Wrike, ePMS, VSS, BitRix
 Production/Account/Logistic SAP

2
Professional Profile :
1. BSR from 2010 to till now, I am responsible for designing of high-end products in the R&D. Responsible for project flows,
design concepts, client interaction and supply chain management of product design till the end market. I was providing
solutions to various Indian companies on railway, medical, semi-EDA, metering and industrial domain.
Designation : Director
Role : Product Owner/Sr. Embedded Consultant
National : Multiple offices of clients, Noida, G.Noida, Faridabad, Delhi, Gurgaon

2. PATNI (Acquired by Cap Gemini) 2004 to 2010, I was responsible for project management, FW-HW designing of multiple
domains of worldwide customers. Visited onsite locations and worked with international teams. I was responsible for team
building, drive innovation and excellence, training, team & project management etc. in later stage of Patni.
Designation : Sr. Hardware Lead/Software Specialist /Senior Software Engineer
Role : Project Manager/Team Lead
National : Multiple offices of Patni in Mumbai, Noida, Pune and Bangalore
International : Multiple on-site assignments in Japan, Singapore & Germany

3. Technology and Research third party developer for Analog Device (Acquired by Landis-Gyr Ltd.) from 2000 to 2004
responsible for digital hardware, firmware – uC, DSP, FPGA, protocol design of energy meter (Both single and three phase),
physical layer of wireless 802.11a/b/g modem and power line modem.
Designation : SE/SSE
National : Worked in Client Locations Jaipur (Genus), Mumbai (EMCO)
International : Visited Hong Kong and China couple of times

3
Major Project Details
Project : Vehicle engine diagnosis via vibration sensor and harmonics analysis (Tachometer)
Role : Product Owner – Scratch to End responsibility, R&D, Strategic planner
uC and Design Language : Renesas RL78, Renesas RA2A, Renesas Embedded ‘C’, Analog Device 3-D vibration meter
Tools : DipTrace, CS+, Visual Studio
Standard Studied : Vibration, harmonics
Description :
Engine health via vibration sensing of engine, battery voltage sensing and engine oil temperature sensing via RTD are the three
main algorithms implemented into microcontroller. Analog front end design was completed after many iteration in filtering
circuit.
Responsibilities :
 Detailed design specifications are generated from the PRD
 Study lot of motion, velocity, acceleration, position, magnetic etc. sensors, later decided vibration sensor is best
 Analog front end design, sample by sample analysis of ac signal coming from analog vibration sensor
 Interfacing and calibration routines implementation in uC with vibration sensor and RTD
 Prototype creation, Apart from HW & FW, three PCB layout iteration, FFT algorithm, hw/fw filtering, spacing with Analog
and digital power section etc.

Projects (Study & Proposal) : Multiple – RISC V instruction modelling, Embedded Linux porting and Kernel upgradation for
RISC V, Drilling Machine, Oil Extractor, Telecommunication packets and protocols etc.
Role : Study research and technical documents of related technologies, Proposal writing
Standards : RISC V, Imperas Software manuals for OVP, System C, TLM 2.0, Cadence and OrCAD pcb file
generation standards like IPC NC-349, TDM & FDM along with Fiber interfacing standards
Tool : GNU compiler, OVP, QEMU, Cadence and OrCAD pcb file generation tools
Description & Responsibilities:
Client given task to study implementation of instruction modelling in RISC V microcontroller. Started project from study of RISC
V core, its available variant, extra possibilities in RISC V than available range of microcontrollers mainly ARM. Next understood
the flow of OVP tools where modelling of instruction to be designed and execute with the interface of already available
processor and peripheral models of RISC V core. QEMU is also one of the tool to execute such types of models.
In next stage client provided RISC V instruction device driver development on Kernel of Linux in Ubantu Linux OS based
machine. A embedded Linux operated RISC V card was ready for which we have to implement device driver for new instruction
in Linux Kernel. Installation of various tools like GNU compile, OVP emulator, QEMU emulator along with different types of
utilities was the part of this experimental project.
One of another client wanted to develop low cost drilling machine using existing design tool of PCBs. Every pcb design tool
generate drill file of targeted pcb in the layout to gerber generation process. There are multiple types of format used in
generation of drilling file, one of them IPC NC-349 was the targeted one. CNC machine commands to be extract from drilling file
and passed to main processing engine for circular interpolation of x and y axis motor controlled drills.
Same type of study and experiments also done for telecommunication project.

Projects (Design) : Multiple – Blood Collection Monitor, Automated Peritoneal Dialysis etc.
Dev Tools : R2A1 Renesas kit, E2Studio, E2 debugger, DipTrace, Solidworks, Nextion HMI editor
Description :
Blood Bank and Dialysis equipment designed/re-designed under ISO 13485 and FEDA standards. Taken care of board design,
design of interfaces i.e. load cells, HMI, communication, heater, temperature sensors, liquid flow etc. Helped team into define
and evaluate the mechanical, electronic and electrical specifications of the system, evaluated sub-components, and verified the
final system.
Responsibilities :
 Designed HMI screens and interfaced with arm based Renesas RA series microcontroller
 Control high power operated heaters and pinch valves through optical isolation
 Interfaced load cell of 1mV/V sensitivity with internal 24 bit sigma delta ADC of Microcontroller

4
 A GUI creation and attached with uC database for Nextion 4 inch and 7 inch HMIs
 Precisely flow management of dialysis solution
 Closely involved in design cabinets with Mechanical team

Project : Vehicle Diagnosis Kit Design with Android Apps

Role : Product Owner – Scratch to End responsibility, Hardware re-engineering and new development
uC and Design Language : Renesas RL78/G13, Renesas ‘C’, Android Java, OBD2
Tools : CS+ ver 8.0, Android Studio ver 4.0
Standard Studied :
Description :
OBD-II is a standardized protocol in all vehicles made since 1996, and it's used to transmit information from car's computer to
code readers and other diagnostic tools. With the right adapter, data from car's OBD-II port can be transferred to phone over
Bluetooth.
Responsibilities :
 Connection development for all types of Physical layers supported by OBD
 Hardware interface between Light Vehicle diagnosis port and uC, its higher layer and complete features of protocol
implementation in firmware
 First Android program design only for all the cars of Maruti; Data capturing, analysis and stored, Later added multiple cars
and extra analysis features, data saving on local mobile and cloud interfacing

Project : Ultra-Fast Zynq SoC based Acquisition Card (Phase 1)

Role : Designer, Project Owner
Dev Boards : Zynq-7020 SoC (FPGA + Dual 866MHz ARM) on the Zedboard, AD9434 ADC evaluation card
Standard Studied : AMBA, AXI4, AXI4-Lite, AXI4-Stream, AXI interconnect, AXI IPs
Development & Debugging : Vivado, SDK, Schematic Editor - IP integrator, GDB, Integrated Logic Analyzer
Testing Equipment’s : Logic Analyzer - 16860A, Signal Generator- DDS150, CRO - MSO5000
Language : Verilog, Embedded ‘C’, Schematic Editor – IP core-based strategy
Description :
Zynq SoC on the Zedboard receives digital o/p from the ADC and sends them to the PC, after proper formatting, through a Gbit
Ethernet link. Board would have one acquisition channel running at 1 GS/s. Such a fast rate allows for better performances both
in pulse shape discrimination and pile-up rejection especially when using detectors with fast response (for instance Silicon
Photo Multiplier and fast Scintillators with rising times of the order of 10ns).
Responsibilities :
 Zynq architecture study, PL & PS features and interfacing study, familiarity with dev tool chain and multiple supported
tools of Vivado, high end testing equipment’s based HW lab formation at client side
 1GS/s was achieved by 500MHz clock by using two ADCs running with clocks having opposite phases. The FPGA i/o de-
serializers are used to convert it to a 4x12 bit-wide bus running at 125MHz.
 IP integrator used to create and interfaced AXI based signal generator IP (later ADC-SoC SPI IP is interfaced), AXI based
DMA IP with stream, master & slave interfaces, AXI interconnection with HP & GP ports and Zynq PS IP
 Insertion of more Integrated Logic Analyser probes (to debug some critical signals of the synthesized netlist)
 Vivado implementation i.e. place and route, synthesis, I/O pin assignments, Timing constraints definition
 A bare metal code written on Zynq PS to interfacing with Zynq PL, configuration of Ethernet, SPI & DDR3 controller

Project : Ultra-Fast Zynq SoC based Acquisition Card (Phase 2)

Role : Architect, Linux bootloader and Linux application FW designer
Development Tools : PetaLinux, Altium, LogiCORE IP
Description :
Most of the hardware circuit to design customized 1GS/s acquisition card was based on Zed board and AD ADC card like ADC
front end, reset circuitry, power section, clock requirements, Ethernet port, USB to UART port, DDR3 memory etc. along with
new fast connectors & ports. PCIE Gen2 channel implemented with Zynq PL fast transceivers, HDMI port for display of messages
& graphs. PS firmware was written on Linux OS.

5
Responsibilities :
 High speed PCB designing & layout reviewing and take care of 8-layer ultra-fast speed board with signal integrity issues
 FW design same as phase 1, along with Linux OS installation, bootloader creation and application code writing on Zynq PS
 High speed data transmission (design and testing) after analysing SystemC/spice modelling, SystemC models for digital
block of transceivers etc.
 PCIE Gen2 single lane (5Gb/s) block configuration in Zynq-7030 as well as data transmission testing

Projects (Design) : Multiple – Integrated Passenger Information System for stations (IPIS), GPS based Passenger
Information System for coaches (PIS), Railway Signal Lights (20 variants), Earth Leakage Detector (ELD), GPS Clock etc.
Role : Functional design & testing, Collaboration with client teams for compliance testing
Standards : RDSO/SPN/TC/67/2012, RDSO/SPN/TC-61/2015, RDSO/PE/SPEC/EMU/0065, RDSO/SPN/153/10,
RDSO/SPN/199/2011, RDSO/SPN/256/2002, RDSO/SPN/TC-62/2008
Tool : ARM chain, Renesas RL78 chain, CS5460 power measurement, Current sensor ACS712, TCS3471,
Cypress CY7C64225 USB to UART Bridge, Audio Codec ADAU1761
Infrared Sensor : MCT-4.5-TE2-0.25-HGCdTe Detector-peak wave length 2um to 5um
Description & Responsibilities:
Multiple railway products were designed in last several years. As a consultant my primary job was to study railway specification,
find out the design points, design embedded product basis on design points, its functional testing, proto type delivery and after
that coordination with client team to complete compliance testing or RDSO testing.
HAHW was different in the sense that I had to find the suitable sensor to measure remote temperature of moving hot objects,
its supportive components, its testing equipment’s and test lab creation which we did and developed the prototype board to
analyse readings as per the RDSO specification.

Project : Touch Switch Boards Designing & Wireless Networking (Multiple Variant)
Role : Product Owner – Scratch to End responsibility, R&D, Strategic planner, Budget Analyst
uC and Design Language : Renesas R8C27, R8C33t ‘C’, Texas CapTIvate ‘C’, Java
Tools : OrCAD, HEW, CCS, Android Studio, CubeSuit+
Standard Studied : Zigbee Lighting, Zigbee Home Automation, Wi-Fi, Bluetooth
Description :
Started R&D to provide a alternate of mechanical switch board where electric switches could be ON/OFF by simple finger touch.
Project divided into three isolated parts, capacitive touch, triac based AC switching and power supply. Touch switch boards
were consumer able decorative show piece type electric switch boards those could be controlled by finger touch, IR remote,
centralised unit or Android app. The speed of the fan or the dimming of the light can be controlled by just sliding the finger.
Maximum eight touch switch devices could be connected on Wi-Fi PLAN or Bluetooth PLAN. Complete systems had expedition
to connect all electronics devices used in domestic boundaries without wire.
Responsibilities :
 MRD – Marketing Design Document creation
 PRD – Product Design Document creation
 Detailed design specifications are generated from the PRD
 Prototype creation, Apart from HW & FW, three PCB layout iteration to fixed touch sensing by modification in track
spacing, width, length, pads, hw/fw filtering, spacing with Analog and digital power section etc.
 Multiple iteration due to change in front end design, features enhancement, advance microcontrollers, other advance
components, wireless networking and fitting on CAD pieces
 Rigorous Testing, test lab creation. Assembly, manufacturing, packaging & transport issues
 Android Program for touch switches

Projects : Energy Meter and Panel Meter Design

Role : Functional design & testing, Collaboration with client teams for compliance testing
Standards : DLMS, IEC
Tool : Renesas, Texas
Description & Responsibilities:

6
Ground up development of a CT operated smart meter on an Arm Cortex M3 platform, Guide the mechanical design, firmware
architecture, IEC and DLMS protocols, wireless comms and PC based application for reading data and storage in a database for
billing purposes.
Ground up development a three phase 4 element whole current meter with the same features and work content as the LTCT
meter above
Ground up development of a 2-element single phase panel meter on Renesas platform
Three phase cirrus ASIC based panel meter with multiple logging and soft features

Project : FPGA based low cost router design

Role : Product Owner, Verilog based RTL coder, System Verilog based testbences designer
Tools : OrCAD 16.1, Xilinx ISE 11 suits, VCS compiler, DVE and testbench debugger
Dev Boards : Spartan 6 dev board
Standard Studied : UVM 1.2 User’s Guide
Description :
The router has 16 input and 16 output ports. Each input and output port consists of 3 signals, serial data, frame and valid. These
signals are represented in a bit-vector format. To drive an individual port, the specific bit position corresponding to the port
number must be specified.
For example, if input port 3 is to be driven, then the corresponding signals shall be din[3], frame_in[3] and valid_in[3]. If output
port 7 is to be sampled, then the corresponding signals shall be dout[7], frame_out[7] and valid_out[7].
Responsibilities :
 Identify the control and data signals of the DUT. Draw timing diagram for sending and receiving a packet of data through
the DUT
 Design, compile and simulate System Verilog testench. Functional coverage analysis, the random-based tests are then
constrained to focus on corner-cases not yet reached via broad-spectrum testing.

Project : LED Display Boards (Three Major Projects in 3-4 Years)

Role : Product Owner – End to End responsibility, R&D, Strategic planner, Budget Analyst, FW/HW/PCB
Designer/VC++ application GUI Designer, Communicator, Production, Sales and Marketing
Tools : OrCAD, Keil, HEW, Atmel Studio, CubeSuit+, Visual Studio 2010
Language : Renesas R8C33t ‘C’, Atmel ARM ‘C’, 51 core ‘C’, VC++
Team Size :3
Description :
 Designed and manufactured of small and big both types of LED display boards. Small boards (either 64by16 or 96by16 LED
Matrix) were based on NXP micro RD2 and Big boards were based on ARM or RL78 series of Renesas. Big boards were
divided on small modules (32by16 LED matrix) those were controlled by single master board. Master and slave modules
were connected by RS485 and maximum 32 slave boards could be connected in daisy chain network.
 Developed VC++ based GUI to load any font data, graphical files, paint files etc in HW. Message editor box was something
like Microsoft word editor where user could type data in any available font, size, symbol, bold, italic etc. and back end of
GUI will translate your data into bit form and upload into HW. By this approach, language bar was restricted and user could
upload any language into HW.
 A LED display board project for railway supplier, strictly followed IEC standards i.e. IEC 60571 – railway specific, IEC61373
– shock & vibration, IEC61000 – EMI/EMC, IEC60529 – enclosure/IP code , IEC60068 – environment/dust etc.

Project : Discrete / Multiple

Role : Consultant, Design, FW/HW/PCB Designer
HAHW is one of the projects where I was taking care of complete designing from mechanical, electrical, electronics to validation
and verification. It is fully automated wayside detection system. It consists of data acquisition equipment deployed by the side
of railway track which acquires temperatures of axle boxes and wheels treads/rims. After analysis of captured data with
predefines equations, it transfer result into server which always available to users of system through a website. Complete
standard testing as per the RDSO specifications were involve in the later stage of the project.

7
In one another project, Interface master unit and MCT optical sensors/arrays to find out remote body temperature, remote
unnatural activities, and composition of gases; and pressure sensor to find out flow of gases and thermistor & RTD to find out
temperature as well as current control to cool the Peltier TE.
Developed PCDC and PHID class of USB interface along with Bluetooth interface to communicate Android based mobile
monitoring or calibration application. Directly used most of the libraries of Renesas RL78 series for USB driver.
Designed solar chargers of different current & voltage ranges. Finalize hardware power components i.e. power supplies, power
diodes and power MOSFET etc. There are 12 different bi-products were designed and launched into market i.e. solar home
lighting units, solar DC bulbs, solar street lights, solar mobile charger etc.

Project : ATMK2 SIM50 FPGA, ATMK2 CIM & SOM24 FPGA

Client : A leading railway manufacturer of Australia
Role : Project Manager
Type : System Verilog, Verilog, VHDL, Open Verification Methodology (OVM)
Tool : Rivera Pro 2011, Questa Sim, Active-HDL, Modelsim, Xilinx ISE 11 suite
Description :
The SIM50 FPGA module provides the interfacing between the SIM50 AFE and the common core FPGA modules that provide a
2oo2 failsafe interface to the system controlling processors. The SIM AFE provides TRUE & COMP versions of the set of 12 50V
i/p signals. Both sets of signals convert the i/p signal level to a PWM signal with the COMP signals being approximately twice
the frequency of the TRUE.
The CIM (Coded i/p Module) acts as interface between an OC-Enabled westlock and any voltage free contact. CIM supplies a
coded signal to detect the open/closed status of voltage-free contacts. The SOM24 (Serial o/p Module) is compatible with a
range of 24Vdc devices to be developed for Modular Signalling Network Rail signals. The SOM24 is managed by a PM (Processor
Module) over the Serial Module Bus.
Responsibilities :
 Proposal creation for client, Project management of 4 member team
 Testbench written for Common Apply Calibration, TRUE TDM sliding Sum, COMP Clock Sync, COMP Dynamic Check and
COMP TDM Sliding Sum modules using VHDL language
 Executed System Verilog based test methodology along with core design and using its modern processes like classes,
clocking blocks, assertion, checkers, interfaces etc.
 Verified 5 block level modules functionally, developed the Score-Board and Monitor, prepared the assertion plan targeting
100% code and functional coverage.

Project : Functional and timing verification of low cost PLC

Role : Requirement Gathering and Project Planning
Project Description :
Rockwell Singapore was developing a modern PLC “Optimus” and expresses its desire about functional and timing verification of
PLC firmware to team. In first round two team member worked together with Rockwell team to finalize the requirement, scope
and timing estimation.
Responsibilities :
 Study of functional documents of Firmware, ladder instructions and supported protocols
 A project plan creation with the help of Rockwell engineers and our team members
 Up-coming project proposal creation, timing estimation and task structuring
 Final settlement of project timing, team members and pricing.

Project : BUS/Train display and announcement system

Client : Mobitech/Euridis
Role : Project Manager, Analyst
Type : Market Analysis, BoM comparison
Project Description :
Client wants to launch its LED display and announcement system in India, so they desire that system’s mechanical, electrical
and electronics parts should change as per Indian environment. They also have pricing limit (BoM) for Indian version. Team

8
study their complete system and propose effective solution through that client could redesign its CAD, hardware & wiring and
port its firmware to new set of uC’s. Client also needs GUI up gradation to support different regional languages of India.
Responsibilities :
 Proposal creation for client
 Project management, task structuring and communication with third parties.
 Multiple report submissions for mechanical, pcbs, cabelling and electronic BoM pricing.
 Coordination of CAD team located in different location.
 Search, test and verify suitable font creation tool to create characters of Indian languages.

Project : Re-design HW and DSP code porting for one of train ECU card
Client : Dimetronics – A leading automotive third-party developer
Type : Hardware/Firmware Development, DSP Algorithm, BoM Finalization
Tool : FPAA Anadigm AN12xxx, CCS Texas TMS320 DSP, ePMS
Description :
Spanish Automotive clients had electronic card for train ECU to find the speed and direction of train. Card receives FSK
modulated signals from small cards situated on poles nearby railway track and refine analog signal after bypass from multiple
series of analog filters. Refine analog signal interface with Texas DSP where geortezal filter and other digital signal processing
algorithms find out the speed and direction of train. Client wanted to upgrade the hardware, move multiple series of analog
filter into FPAA and porting the DSP code into one of the latest DSP of Texas. FPAA algorithm was tested by simulated
environment of signal analyser and modulator.
Responsibilities :
 Proposal creation, management of 4-member team, weekly status & client meetings and communication with third parties
 Development and simulation of FPAA logic. Old HW had three layer of bandpass filter which was transferred into FPAA
using Anadigm design tools. Its pole and gain factors were tuned as per old design
 Texas DSP Firmware porting, code review and firmware testing was our tasks
 Re-design timings and constants of geortezal filter as per speed of the new DSP and latest HW

Projects : TKE Hardware Boards Re-Design (Three + one hardware cards for Elevator system)
Type : Development for elevator, Hardware/Firmware/FPGA/CPLD Development, BoM Finalization
Tools : PCAD ver6.0, Quartus II ver7.2, CCS, ePMS
Description :
The aim of this project was to redesign & develop the three hardware boards used in elevator system. One of the boards is used
to read the current position of elevator by few encrypted pulses those are coming from other cards of system and decrypted by
logic implemented in PALs. PALs logic moved into CPLD or FPGA, which design, code and simulation came in our scope.
Second TAC50 DSP board was used to calculate the velocity of elevator by controlling VFD drive. The project included the
necessary porting of the TAC50 DSP firmware to work with the chosen platform.
Third x86 processor-based CPU card which had shared data & address buses to read memories of others boards and DSP card.
All three cards and few another (those were not in our scope) were interfaced by backplane and X86 CISC bus. After completing
and porting the design; logic boards was tested on a client provided simulation engine of emulator.
Responsibilities :
 Daily client meetings to understand their existing design i.e. elevator system, PAL equations and timings, DSP logic, signal
communication, x86 processor card design and bus interface etc.
 Daily team meetings to improve system and technology understanding. More focus to come in synchronization as it was
the very old and one of the biggest designs and lot of data, specification, and design files were missed
 Circuit design, FPGA & CPLD selection, schematic, PCB design and firmware development& review
 FPGA & CPLD code development and simulation. Schematic approach was mostly used for VLSI code.
 DSP ‘C’ code porting and driver development for new components and their rigorous testing.
 Management of 8-member strong team. Project management, quality audit, task structuring and communication with
third parties, weekly delivery report to client and senior management are the major tasks on PM front.

Project : Re-Design of Load-weigher Board for Elevator System

9
Type : Hardware development, BoM finalization & Firmware development
Tool : PCAD ver6.0, Microchip MPLAB
Description :
The client is the world's premier manufacturer, installer, and service provider of vertical and horizontal transportation
technology. It developed and supplied elevator, escalators and moving walk ways. The project involved designing the Load-
weigher board for the elevator system. The function of this board was to take analogue inputs from the LVDT (Linear Voltage
Differential Transducer) and generating the digital data corresponding to LVDT signal and sending these digital data to the Main
Controller of elevator system through RS-422 channel.
Responsibilities :
 Requirements analysis for designing of Load-weigher Board
 Electronic components selection and ordering to develop the board
 Schematic design, PCB (Printed Circuit Board) layout design, and Firmware development
 Firmware development and Testing, PCB Assembly, Integration Testing and Delivery.

Project : iPOD/MP3 Interface

Client : A Leading Automotive Product Vendor in Europe (Visited Germany for Client Meeting)
Type : Protocol Analysis, Onsite/Offshore
Platform : CAN, CDEF, S1nn_Analyzer
Project Description :
The aim of this project is to find out a fast and accurate analysis of the error logs of the communication between the two
automotive devices that would aid in pin-pointing the problems within the sub-system. The scope of work includes the
Understanding of the modules involved in communication between the 2 devices with respect to their software, firmware and
hardware & analysis of the error logs so as to identify the problem area. Project have a quick analysis of the error log, to
identify the modules involved in the particular error scenario, understanding of only those modules/areas associated with the
control flow causing the error and examining the details to ascertain the problem area.
Responsibilities
 Analysing the protocol flow and Identifying the exceptional in protocol flow
 Writing the analysis report and Project management

Project : Mitsubishi PLC (QnU Series) Protocol Analysis

Client : A Leading Automation Product Vendor in JAPAN
Type : Reverse Engineering
Software : Dis-assembler (OllyDbg, PE BrowseDbg), Microsoft Visual C++, GX Developer
Project Description
The aim of this project is to analysis the communication protocol between Mitsubishi QnU series PLC and GX Developer tool.
The GX Developer is executed using dis-assemblers in debugging mode and Intel's 32-Bit assembly instructions are decoded to
analysis the communication protocol. The connection authentication packets are diagnosed to find encryption algorithm. A test
tool is also developed in C to verify the encryption algorithm.
Responsibilities :
 Analyzing the protocol flow & Identifying the encryption algorithm.
 Writing equivalent C code, reviewing and final testing along with Team and project management.

Project : Scion PLC Tool Development

Client : A Leading Automation Product Vendor in JAPAN
Platform : Windows 2000, Visual studio 6.0
Project Description
Client is involved in developing the controlling software for Programmable Logic Controllers. This software is meant for
programming the PLC devices as per the user logic using ladder programs. System is targeting the lower end applications with
limited IO requirements and basic functionalities including simple motion control and PID control.
Responsibilities :
 Communication design creation.

10
 Development of Modbus and K-Sequence protocol layer in IDM based OPC Server.

Project : FW Development of "Programmable Logic Controller (PLC)"

Client : A Leading Automation Product Vendor in JAPAN
Platform : Embedded ‘C’, NORTI OS, HEW for H8S series uC, PALMiCE2
Description :
The aim of this project was to develop a new "PLC" in low cost compare to existed PLC. This PLC targeted low end
customer/market where small electronics is required to control machines or equipment. Controller provided high end features
like High speed counters, PID's, MATH instructions, analog and digital card support apart from giving normal PLC features like
ladder Program execution, MODBUS and ASCII communication etc.
Responsibilities :
 Requirement gathering, task structuring and configuration management
 Bootloader writing, initialization routine creation, integrity with multiple types of digital, analog and mixed IO modules.
System initialization with the help of RTOS, Interrupt management, OS task structuring
 Ladder instruction designing in assembly and Embedded ‘C’. Ladder instruction testing with the help of external hardware
i.e. wave generator, motors, drivers, AC drives, etc. Timing analysis of ladder instructions
 Unit test case creation, Integration test case creation, FW testing and system testing
 A close relationship with GUI team which was simultaneously developing ladder programming and configuration tool
 GUI had to integrate OPC client and server which had the VC++ based protocol layers those were developed by FW team

Projects : HMI Control Software, PCI Interface Card

Role : Protocol designer, PCI3.0 interfacing, PCI standard studied
Platform : WIN CE, Embedded ‘C’, Protocol Analyzer
Description :
The HMI project involved the core design of high-end industrial HMI. It can communicate with the PLC's of Allen Bradley, GE,
OMRON, Siemens, Koyo and Mitsubishi on serial and Ethernet port. Its GUI provides the support of basic industrial objects like
PDI, graphs, Modbus register, Modbus coils etc.
Designed interface link of PCI card which connects PC and HMI via the plug and play PCI bus using AB DF1 (com port 1) drivers
to AB’s DH+/DH-485 (port 2). The DH+/DH-485 card is a PCI card to access AB’s DH+ network. This allowed HMI, PLC, SCADA and
other applications access to any DH+ node including PLC’s and SLC’s.
Responsibilities :
 Designing and porting of protocol of other PLC manufacturers on Win CE platform
 HMI protocol design and testing with PLC's of other manufacturers. HMI code modification and retested
 Added DH+ for three different baud rates 57.6, 115.2 and 230.4 Kbaud. Updating and modified few bugs in PCI driver
 Testing and Verification with multiple PLCs and HMIs of other vendors
 Guided application team which was developing GUI for PCI card to provide understanding of DH+, DH-485 and PCI3.0

Projects : BCM ECU Test Plan Creation, Cluster Code Mapping Specification vs Design, Cluster Test Case Creation
Type : Verification & Validation
Tool : CANoe, CAN Analyzer, CAPL Scripting Atomized, CAN 2.0, CAN network diagnosis tools
Description :
Client already had a working code for an automotive product (BCM, Body Control Module). Client wanted team to write the test
procedure to test their automotive software. Scope of one of these projects was to develop test procedures as per the system
specifications sent by client and creation of test scripts for those test procedures.
Responsibilities :
 Test scripts were written in CAPL language and were being used to program CANoe to test the software functionality.
 Communication with the OSC and solved the issues related to the CAPL scripting and ambiguity /misinterpretation of the
specifications.
 Reviewed all the work products before delivering to the client.

Projects : FPGA Design Verification

11
Type : Functional as well as timing verification for north American client
Platform : Xilinx Spartan 3 S100E FPGA with ModelSim 5.7 XE free&5.8 PE licensed, VHDL, Tcl/Tk
Description :
Team executed two FPGA validation projects of building automation domain back to back. Verification of the design was
classified under functional and timing verification. Developed BFMs are triggered using the test cases generating the various
interfacing signals. Functional verification verified the functionality implemented in the design without considering any timing
constraints. Timing verification verified the design performance considering the timing parameters applied to the design after
synthesis.
Responsibilities :
 Bus Functional Model (BFMs) creation in VHDL language
 As peripherals of both projects was different except ColdFire uC so developed BFMs was different
 Testbenches were created into VHDL and code tested by Tcl/Tk scripting for both functional and timing

Projects : Wi-Fi/Power line MODEM Physical Layer-802.11a/b/g and HOMEPLUG standards

Type : R&D, Prototyping
Platform : Xilinx ise6.1, Spartan 3, Blackfin compiler/emulator
Language : VHDL, Embedded ‘C’, Blackfin Assembly
Description :
Worked in a modem design team which was developing physical layer and MAC of Wi-Fi Modem based upon 802.11a/b/g
standard and Power line Modem based upon Homeplug standard. Physical layer was developed in FPGA & Blackfin DSP and
MAC layer was only in DSP. USB interface was provided for PC communication.
Responsibilities :
 Worked on FPGA tasks and developed scrambler, convolution encoder, bit interleaver, OFDM modulation-demodulation,
synchronization tasks and interfacing of blocks as well as different chips
 Designed and analysed the timing & performance of FPGA’s functions
 Find out the GATE count and timings of individual blocks
 Our team joined VLSI training program in October 2003, which was organized by CG-CoreEl group in Noida

Projects : Three Phase 3P– 3W & 3P – 4W, Industrial Tri-Vector, Single Phase Energy Meter
Type : Development, Enhancement, Multiple types of design and versions
DSP Processors : 218X DSP series, ADSP2185, ADSP2186, ADSP2188, ADSP2189
Micro controller : Aduc814, TEMIC T89C51RD2, NEC 78K4series, ST
Technology : Digital Signal Processing, FIR-IIR Filters, Delay Filters, FFT
Tools : Kiel Compiler, Analog Device IDEs
Description :
These were either Analog uCAD814 based or Analog DSP 218X based highly sophisticated "Electronic Energy Meters" to
measure voltage, current, power, active energy, frequency & meter calibration pulse etc. All the basic parameters related with
electricity were provided by either uCAD814 or DSP 218x to another peripheral uC which was used for the database
management of energy.
DSP was used for very fast computation of high-end energy metering data like harmonics, active power, reactive power,
metering filtering etc. In one variant of meter, TCP/IP was used for e-mail & outer communication.
Responsibilities :
 16-bit Analog device AD78xx series ADC, Analog Device 218x DSP and any suitable microcontroller was used as per the
project or tender requirement. My involvement was basically in any new design to upgrade or modified digital HW, DSP
FW and microcontroller FW.
 Very first design of DSP meter was booted by uC. uC read DSP program byte by byte through shared bus and sent to DSP. I
modified boot process as DSP can fetch pre bootloader automatically at power up. Pre bootloader is designed in such
manner that program code could be fetched easily after that.
 Designed different types of FIR digital filters for CT phase compensation, delay filters for reactive energy and FFT for
Harmonics according to different sampling rate and quantization.

12
 Development of firmware-based metrology for 0.5 class and class 1 single & three phase meters for domestic use on
ADuC812, ADuC814 & ADuC824 micro along with the additional features i.e. TOU, maximum demand, monthly log, instant
logs etc. using a variety of extra microcontrollers like NEC, ST, 8051 core etc.
 Developed firmware for device drivers for LCD, RTC, EEPROM, interfacing between microcontrollers etc. based on I2C, SPI,
RS232 and RS485. Developed ‘C’ program of handheld terminal for billing.
 Since we were serving a worldwide customer base, implemented data exchange protocols like IEC1806, DLMS, ANSI
C12.18/C12.19/C12.21 etc. A modulation methodology was designed for EURIDIS protocol.
 For an important project of 0.2 class meter; ported the DSP FW code from 2189DSP of 48KB program memory to 2188DSP
of 24KB program memory with the help of run time switching of boot loaders and overlay functionality of Analog Device
218x series DSPs.

13