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Lecture 5, Transistor matching and good 18-Mar-08

layout techniques

1. Transistor mismatch – its causes Part 1: Device Matching

and how to estimate its magnitude
(especially transistor matching)
2. Layout techniques for good
matching
3. Layout techniques to minimize
parasitic effects
Neuromorphic Engineering 2
Spring 08
Delbruck/Indiveri/Liu

Transistor matching data Statistical rule for matching

From Brad Minch, formerly Cornell, now at Olin Tech (aka Pelgrom’s rule)
Teresa Serrano-Gotarredona, Bernabe Linares-Barranco
AΔX
Inst. of Microelectronics, Sevilla, Spain Zero order rule: σ (X ) =
(X is some quantity like VT) WL
1. The variance goes as 1/area, i.e., σ goes as
1/dimension
2. Only applies for local, identically-drawn neighbors.
3. There are many refinements to account for spatial
locality, large scale effects (tilt), etc.
4. Statistical transistor models try to model individual
parameter variations, e.g. VT, β, κ, W/L

Small transistors → Big mismatch

1. All devices follow
area rule
2. Caps match 1-2
than FETs
(Inter-die)
3. pfets match worse
than nfets (usually)
border effects are
removed here. I0 ∝
exp(-VT) and VT
has normal
distribution…

Lecture 5, Transistor matching and good

layout techniques, http://avlsi.ini.uzh.ch 1
Lecture 5, Transistor matching and good 18-Mar-08
layout techniques

Dominant cause of FET mismatch is random

dopant fluctuation
Magnitude of VT mismatch

AVT
σ (VT ) = , what is AVT ?
WL
• AVT is reported to be ~1 mV*um per nm
oxide thickness (JSSC, 39:1, 2004 p157-
168)
– Example: 0.35um process with Tox=7nm,
AVT=7mV*um.
– FET with W=L=2um
(With λ=0.2um, this is 10/10 λ),
σ(VT)=7mV*um/sqrt(2um*2um)=3.5mV
Cheng, Roy, Asenov ESSCIRC 2003 – Minch measured value is 2.4mV

σ (VT )
0.35u process

σ (log I ds )

• To zero order, weak inversion mismatch goes as

σ ( I ds ) ⎛ σ (VT ) ⎞
= σ (log I ds ) = exp ⎜ ⎟
I ds ⎝ UT ⎠
• It is reported that weak inversion (sometimes) has
additional mismatch not accounted for by σ(VT)

Ids Ids
Serrano-Gotarredeno, Linares-Barranco 2000

Mismatch process scaling

Reducing mismatch by design
Objectives:
Good event-threshold uniformity
Fast response under wide illumination range
I0

I0

A
random variation
1. From 1.2u to 0.35u, FETs with same λ dim have same Δ logI
mismatch. (not true for deeper submicron, gets worse).
2. Cap matching depends on absolute size.

Lecture 5, Transistor matching and good

layout techniques, http://avlsi.ini.uzh.ch 2
Lecture 5, Transistor matching and good 18-Mar-08
layout techniques

e.g. 3:1 capacitor

Not
ratio
Part 2: Layout for good device very
precise
matching

Much better
(if you can
afford it)

Use same orientation: e.g. Use common-centroid to cancel

diff pair/current mirror gradients: e.g. diff pair with common
centroid transistors

better

Even better:
1. Use dummy devices on ends
2. Use common centroid

Lecture 5, Transistor matching and good

layout techniques, http://avlsi.ini.uzh.ch 3
Lecture 5, Transistor matching and good 18-Mar-08
layout techniques

Use dummy devices to create identical

Surroundings affect matching local surroundings

Relative
capacitance

Checklist of Matching Techniques

1. Same dimensions
2. Same structure (do not match nFETs with
pFETs)
3. As large as possible Part 2: General layout techniques
4. Close to one another
5. Same orientation
6. Laid out in a common-centroid arrangement
7. Surrounding circuits should be similar
8. Same temperature

Latchup: avoid it by using lots of substrate

Layout Techniques for Good Performance and well contacts
• Every node has a parasitic capacitance and
resistance
• Layout of mixed analog and digital circuits
should be carefully planned to minimize parasitic
effects and undesirable coupling
• Digital circuits should have their own power
supply lines.
• Digital ground should not be connected to
the substrate!

Lecture 5, Transistor matching and good

layout techniques, http://avlsi.ini.uzh.ch 4
Lecture 5, Transistor matching and good 18-Mar-08
layout techniques

Shielding from substrate noise Never connect digital ground to the substrate
• V=LdI/dt noise on digital ground yanks around local
substrate. This can move backgate on analog FETs,
severely affecting them.
Digital circuit
Analog circuit

Lab exercise LVS

Shielding from minority carriers Layout vs. Schematic

Steps for LVS exercise Papers about transistor mismatch

1. Draw schematic/simulate 1. Lakshmikumar, K.R. Hadaway, R.A. Copeland, M.A. “Characterisation and modeling of mismatch in MOS
transistors for precision analog design”, IEEE J. Solid-State Circuits 1986, 21:6, p 1057-1066
2. Draw layout 2. M. J. M. Pelgrom, A. C. J. Duinmaiger, and A. P. G. Welbers, “Matching properties of MOS transistors for
3. Extract schematic and layout to SPICE netlist 3.
precision analog design,” IEEE J. Solid-State Circuits, vol. 24, pp. 1433-1439, Oct. 1989.
Aleksandra Pavasovi, Andreas G. Andreou and Charles R. Westgate, “Characterization of subthreshold MOS
4. Run LVS tool to compare netlists mismatch in transistors for VLSI systems”, Analog Int. Circuits and Signal Processing, 1994, 6:1, p 75-85
4. Forti, F. Wright, M.E. “Measurement of MOS current mismatch in the weak inversion region”, IEEE J. Solid-
5. Interpret output to spot differences State Circuits 1994, 29:2, p 138-142
5. T. Mizuno, J. Okamura, A. Toriumi, "Experimental Study of Threshold Voltage Fluctuation due to statistical
6. Fix layout (or maybe schematic) – iterate to 3. variation of channel dopant number in MOSFETs," IEEE Trans. Electron Devices, vol. ED-41, pp. 2216-2221,
1994.
6. Teresa Serrano-Gotarredona and Bernabé Linares-Barranco, "A New 5-Parameter MOS Transistor Mismatch
Note: LVS has many options, e.g. check transistor Model," IEEE Electron Device Letters, vol. 21, No. 1, pp. 37-39. January 2000. (PDF 144K, 3 pages)

geometry, check R & C values, collapse 7. Teresa Serrano-Gotarredona and Bernabé Linares-Barranco, "Systematic Width-and-Length Dependent CMOS