Basics of MOSFET Transistors

S. Tewksbury
Jan, 2006

Table of Contents

1. INTRODUCTION........................................................................................................................................... 1

2. MOSFET BEHAVIOR................................................................................................................................... 2
2.1 NMOS/PMOS SCHEMATIC SYMBOLS............................................................................................................. 2
2.2 CURRENT-VOLTAGE RELATIONSHIPS FOR NMOS AND PMOS TRANSISTORS......................................................... 3
2.3 OTHER "SCHEMATIC" SYMBOLS (NOT FORMAL) SHOWING BEHAVIOR..................................................................... 5
3 THE NMOS AND PMOS TRANSISTOR STRUCTURE.............................................................................7

4. FABRICATING THE NMOS CIRCUIT: CLASSIC SELF-ALIGNED POLYSILICON GATE........10

4.1 SOME CONSTRAINTS IMPACTING FABRICATION................................................................................................. 10
4.2 NMOS TRANSISTOR.....................................................................................................................................11
4.3 PMOS TRANSISTOR..................................................................................................................................... 18
4.4 SUBSTRATE CONTACTS................................................................................................................................... 19
5. FROM TRANSISTOR SCHEMATIC TO MASK LAYOUT.................................................................. 21

6. A COUPLE OF COMMENTS..................................................................................................................... 22

1. Introduction
The basic principles underlying MOS Field Effect Transistors (MOSFETs) are summarized
here. Silicon MOSFETs have become the dominant devices for VLSI digital and analog circuits
and are expected to continue their dominance for some time to come. As seen later, the outputs
of MOSFETs in digital logic cells typically drive the gates of MOSFETs appearing in other logic
cells. That leads to the outputs seeing a capacitive load, rather than the resistive load seen in
technologies using bipolar circuits. Once the capacitance driven by the logic cells have
charged/discharged to their steady state values, no further current needs (ideally) to flow in the
circuits, with no static power (P = I*V) being dissipated once the capacitors have been charged.
The term "ideally" is used above since very small leakage currents do flow and lead to a very
small steady state power.
The discussions here start with the electronic symbol for a MOSFET and extend down into
the physical structure and behavior of a MOSFET device. This is the inverse of most
presentations but is better suited for a class more interested in using MOSFETs to build circuits
than in understanding the detailed physics underlying their operation. After presenting the basic
structure of a MOSFET, the general steps used to fabricate the MOSFET are reviewed. The
design of the mask layout is directly tied to the sequence of microfabrication steps used to
generate the device structure.
 There are two distinctive types of MOSFET. For one type, the NMOS transistor, a gate
voltage to create a thin conducting layer between the N-type source and drain regions. For the
second type, the PMOS, a gate voltage is used to turn on and off a thin conducting later between
the P-type source and drain regions. These NMOS/PMOS transistor are characterized by
threshold voltages, namely the gate voltage at which the transistor's source-to-drain connection
turns ON and OFF. The NMOS transistor turns ON for gate voltages greater than its threshold
voltage whereas the PMOS transistor turns ON for gate voltages less than its threshold voltages.
In this sense, the control of the PMOS transistor is opposite to (the inverse of) that of the NMOS
transistor.
SGround
DV
V
GVdd
NMOS
PMOS
inLoad
out
Capacitance
Transistor
C

Figure 1
Figure 1 shows the simple CMOS inverter, consisting of a PMOS transistor and an NMOS
transistor. The output is shown driving a load capacitor (since a logic circuit like the inverter
will be driving the gate inputs of other logic circuits and the gate acts as a capacitor). At all
times either the PMOS transistor will be on or the NMOS transistor will be on but at no time will
both transistors be on at the same time (achieved by proper selection of the thresholds of the
PMOS and NMOS transistors. When ON, the PMOS transistor “pulls up” the output Vout to the
supply voltage Vdd. When ON, the NMOS transistor “pulls down” the output Vout to the
ground voltage.

2. MOSFET Behavior

2.1 NMOS/PMOS Schematic Symbols

Figure 2 shows the schematic symbols for the NMOS and PMOS transistors. The gate (G),
souorce (S), and drain (D) are labeled for each. The circle at the gate input to the PMOS
transistor reflects the fact, noted above, that the PMOS response to input gate voltages is
opposite to (the inverse of) that of the NMOS transistor.
 SSource
Da.
G
b.Gate
NMOS
PMOS Voltage
transistor
- 0.
Reference
Voltage zero voltage
Vds
for transistor
gs

Figure 2.

2.2 Current-Voltage Relationships for NMOS and PMOS Transistors

As MOS technologies have evolved to increasingly small devices, the relationship between
the current Ids flowing between the drain and source and the applied voltages (Vgs and Vds) has
become increasingly complex. Vgs is the "gate-source voltage", i.e., the gate voltage relative to
the source voltage (which is taken as the reference voltage for the device). Similarly, Vds is the
"drain-source" voltage, also relative to the source voltage. Contemporary MOSFET devices
scaled to minimum size have evolved from larger dimensioned MOSFETs whose current-voltage
relationship is less complex. These larger dimensioned MOSFETs are modeled using the so-
called "long-channel" model. For the NMOS transistor, the current-voltage relationship is given
by equation 1.
The PMOS "long-channel" current-voltage relationship in equation (2) is similar to that of
the NMOS transistor, but with the sign Vgs -Vt. of changed. This reflects the fact that PMOS
transistors are OFF when the gate voltage is greater than the transistor's threshold voltage and are
ON when the gate voltage is less than the transistor's threshold voltage.

The current-voltage relationship for NMOS transistors (long channel) is:

 For Vgs − ς τ < 0, ς τ τηε ΝΜΟΣ τρανσιστορ ∀
τηρεσηολδ ϖολταγε∀
,
Ιδσ = 0

Φορς γσ − ς τ ≥ 0, τηερε αρε τωο χασεσ δεπενδινγ ον ωηετηερ ορ

νοτ τηε τρανσιστορ ισ ιν σατυρατιον.
1. Φορ ς δσ ≤ (ς γσ − ς τ ) (Τηε λινεαρ ρεγιον)
(1)
Ω   ς 2
Ιδσ = ( µ ν Χοξ ) ∗   ∗ (ς γσ − ς τ) ∗ ς δσ − δσ 
 Λ  2 

2. Φορ ς δσ ≥ (ς γσ − ς ) (Τηε σατυρατιον ρεγιον)

 µ Χ  Ω  2
Ιδσ = Ιδσ,σατ =  ν οξ  ∗   ∗ {(ς γσ − ς τ) }
 2   Λ 

The current-voltage relationship for PMOS transistors (long channel) is:

For Vt − ς γσ < 0, ς τ τηε ΠΜΟΣ τρανσιστορ ∀
τηρεσηολδ ϖολταγε∀
,
Ιδσ = 0

Φορς τ − ς γσ ≥ 0, τηερε αρε τωο χασεσ δεπενδινγ ον ωηετηερ ορ

νοτ τηε τρανσιστορ ισ ιν σατυρατιον.
1. Φορ ς δσ ≤ (ς τ − ς γσ ) (Τηε λινεαρ ρεγιον)
2
Ω   ς 2
Ιδσ = ( µ ν Χοξ ) ∗   ∗ (ς τ − ς γσ ) ∗ ς δσ − δσ 
 Λ  2 

2. Φορ ς δσ ≥ (ς τ − ς γσ ) (Τηε σατυρατιον ρεγιον)

 µ Χ  Ω  2
Ιδσ = Ιδσ,σατ =  ν οξ  ∗   ∗ {(ς τ − ς γσ ) }
 2   Λ

In the above equations, the current is given as the “drain-to-source” current. I have written
the equations to represent the current flowing from the source to the drain for convenience
when considering CMOS circuits. In that case, the source voltage (reference voltage) is
equal to the supply voltage (e.g., 5 volts for 5 volt logic). If the supply voltage is applied to
the top of the transistor, the PMOS current above is flowing downward. This can be
confusing but I am simply avoiding complications regarding negative currents and
directions of current flow.

In equations (1) and (2), the following device parameters are used.
 µ n : The electron mobility for the NMOS device.
mp : The hole mobility for the PMOS device.
L : The " length" of the gate (distance from source to drain).
W : The " width" of the gate.
dox : The thickness of the gate oxide.
K ox *e 0
Cox* = is the gate capacitance per unit area.
dox
Cox = C*ox * ( L * W ) is the gate capacitance.
K ox = 3.9 : The dielectric constant of the insulator
between the gate metal and the semiconductor.
- 14
e 0 = 8.85 ´ 10 F/cm : The permittivity of free space.

The electron mobility for NMOS devices is typically about 1000 cm2/volt-sec whereas the hole
mobility for PMOS devices is typically about half that value (500 cm2/volt-sec).
For older MOS circuits (using 5 volt power supplies), the threshold voltage for the NMOS
transistor was about 2 volts. If the input voltage is below 2 volts, the transistor is turned off. If
above 2 volts, the transistor is turned ON. When the gate voltage switches from 0 volts (logic
"0") to 5 volts (logic "1") on the NMOS transistor,
a. the NMOS transistor turns on when the gate voltage passes 2 volts,
b. then enter into the saturation region (the drain voltage will normally be high when the
NMOS transistor is OFF and therefore will be initially greater than Vgs -Vt),
c. and finally enter into the linear region when the drain voltage, heading towards 0 volts,
becomes less than Vgs -Vt.
The PMOS transistor similarly passes through first the saturation region and then the linear
region as it switches from OFF to ON.
If you look at the current-voltage relationships when the device is not in the OFF state, you
will see that the MOSFET acts as a gate-controlled current source when operating in the
saturation region and acts as a gate-controlled resistance when operating in the linear region for
Vds very small relative to Vgs - Vt, allowing the term proportional to (Vds)2 to be ignored
compared to the linear term in Vds.

2.3 Other "Schematic" Symbols (not formal) Showing Behavior

The NMOS and PMOS symbols shown in Figure 2 represent, to some extent, a cross
sectional view of the device structure. In terms of electrical behavior, those symbols are not very
effective since both imply a direct conductor connecting the source and drain. In Figure 3, I
have shown other ways of viewing the MOSFET as a symbol better representing its electrical
behavior.
Figure 3a shows the MOSFET with a switch in the path between the source and drain. If the
MOSFET is ON, the switch is closed whereas the switch in open if the MOSFET is OFF. Given
the current-voltage equations, this basically means that the state of the drain-to-source switch is
controlled by the gate signal. For an NMOS (PMOS) transistor, if the gate voltage is 0 (5) volts,
the transistor is OFF(ON) and the switch is open(closed).
The simple switch model in Figure 3a ignores any resistance appearing between the source
and drain when the transistor is ON. Figure 3b shows a resistance added to the switch
connection between source and drain, providing a simple model of the device for calculating RC
time constant effects. The only question relates to what value of resistance to use. One approach
(recognizing that we are seeking simple approximations) is to use the resistance at the point
where Vds. has half its value where the behavior switches into the saturation region (i.e., where
Vds = 0.5 ∗ (ς γσ − ς τ) ) . Using equation 1, this would give an rough estimate of

 Ω  ς 2
Ids = ( µ ν Χοξ ) ∗   ∗ (ς γσ − ς τ) ∗ ς δσ − δσ 
 Λ  2 
(3)
1 δΙ  Ω  ς − ςτ
≈ δσ = (µ νΧ οξ ) ∗   ∗ γσ
Ρ δσ δς δσ ς δσ = 0.5∗ (ς γσ −ς τ )  Λ 2

If Cload is the capacitive load driven by the MOSFET, then the RC rise time would be
t RC = Ρ δσ ∗ Χλοαδ.

Switch
R
(a)
(b)
(c)
dsIds = 0
or
Ids = Ids,sat

Figure 3
Yet another simple model of the MOSFET is to assume that, in the ON state, the MOSFET
is in saturation, with a constant current given by the last equation in (1). The time required to
charge the load capacitor from 0 volts to 5 volts would then be
 Q = Χλοαδ ∗ ς 0 = ∫τ Ιδσ σατ ∗ δτ =Ιδσ σατ ∗ τ
, , χηαργε γιϖινγ τηε χηαργινγ τιµε

Χλοαδ ∗ ς 0
τχηαργε =
Ιδσ,σατ
ωηερε Ιδσ, σατ ισ τηε σατυρατιον χυρρεντ ανδς 0 ισ τηε ϖολταγε χηανγε
ον τηε λοαδ χαπαχιτανχε.

Figure 3c illustrates this "electrical" symbol for the MOSFET.

3 The NMOS and PMOS Transistor Structure.

The basic physical structure of the MOSFET must be understood since your design of the
layout masks directly implements that physical structure. For this class, we will be using a "long
channel" technology using the classical mask levels used back in the days before 5 micron
feature sizes. Current technologies, leading to deep submicron MOSFET device sizes, require
hundreds of fabrication steps to complete the overall MOSFET. In our case of the simpler
technology, we will only need five masks to create a CMOS circuit (using NMOS and PMOS
transistors).
Figure 4 shows the basic physical structure (simplest representation, refined later) of an
NMOS transistor. NMOS transistors are constructed on P-type silicon substrates and use heavily
doped (N++) regions with low resistivity to connect the source and drain leads to the gate region
(between the edges of the N++ regions on the two sides). Figure 4a shows the circuit symbol for
the NMOS transistor while Figures 4b and 4c show a simplified cross sectional view of the
device. In Figure 4b, a sufficiently positive gate voltage (i.e., greater than the threshold voltage)
has been applied and the NMOS transistor is "ON" (indicated by the layer of electrons that forms
near the silicon/insulator interface). The layer of electrons appearing at that interface has the
effect of creating a conducting "N-type" channel between the source and drain. This thin layer
(actually very thin) is called the "inversion layer" since the effect is as if the P-type material
under the gate (i.e., hole rich semiconductor) had changed to N-type material (i.e., electron rich
semiconductor). Also shown is the depletion layer that forms at the interface between the P-type
substrate and the N++ source and drain regions (this interface corresponds to a classical diode
and the depletion layer arises for the same reason). A ground connection is made to the back
side of the substrate. This reflects the fact that all voltages in our MOS circuit will be positive
voltages (supply voltage equal to a positive
Figure 4c is similar to Figure 4b but in this case the gate voltage is below threshold and the
NMOS transistor is OFF (there is no "N-type" inversion layer connecting the source and drain).
If you look from the source side through the substrate to the drain side, you will see two diodes.
One is necessarily reverse biased (they are facing in opposite directions) and no current is
flowing).
 Conductor
Electron
Substrate
ÒInsulatorÓ
Thin
N++
Depletion
(a)
(b)
(c)P-Type
Region
Source
Drain
Gate inversion
plate
layer
(depletion
(top
around
layer
region)
grounded
gate
of
Substrate
when
capacitor)
N-P
when
MOSFET
junctions
MOSFET
oxide isisON
OFF

Figure 4
In Figure 3, the depletion layer and the inversion layer are shown. These form naturally
within the semiconductor and are not "fabricated structures". Figure 4 shows the fabricated
structures. In Figure 4a and 4b, the source, drain, and gate wire connections were shown floating
into the air. In a real device, they must be created on top of an insulator. The addition of the
necessary thick insulating layer and the substrate biasing contacts (discussed below) are the main
changes in Figure 5 compared to Figure 4.
N-Type
P++
Thick
N++
P++
Thin
Thin
P-Type
Gate
(a)
(b)Region
oxide
Substrate
gate
Substrate
Source
Drain NMOS
PMOS transistor
Substrate
oxide
gate
oxide

Figure 5

Figure 5a shows an NMOS transistor, created on a P-type substrate. We will need to

fabricate PMOS transistors on this same substrate but PMOS transistors require an N-type
substrate (and P++ source and drain regions). Figure 5b shows the way this is achieved, namely
be creating a deep N-type layer (an "N-Well") on the P-type substrate and then fabricating the
PMOS transistor in this N-well. The only other complication is that we need to apply the most
positive voltage (e.g., 5 volts for 5 volt power supplies) to the "back" of the N-well and we can't
do that. Instead, the "backside ground" for NMOS shown in Figures 4a and 4b is applied to the
top of the integrated circuit, called a "substrate contact", in this case to the P-type semiconductor
substrate. For the PMOS, the +5 volt substrate contact is also applied to the top of the N-well.
Note: You will need to add these substrate contacts when completing your layouts. To
obtain a good contact, it is best to have heavily doped silicon (which acts somewhat like a
metal). The substrate contact is therefore achieved for the NMOS transistor by adding a P++
region to the P-type material and then connecting the substrate contact to it. This P++ region can
be obtained at the same time that you create the P++ source and drain regions for the PMOS
transistor. The substrate contact for the PMOS transistor is achieved by adding an N++ region
(done at the same fabrication step when you add the N++ regions for the NMOS transistors) to
the P-well.

4. Fabricating the NMOS Circuit: Classic Self-Aligned Polysilicon Gate

4.1 Some Constraints Impacting Fabrication

Only fabrication of the NMOS circuit is discussed here. Our objective is to understand the
role of the various masks that you will be designing in the VLSI layout software. CMOS
technologies have become quite complex, with multiple planes of interconnection lines above the
substrate, sophisticated techniques to ensure that the very small devices continue to operate
similar to devices from earlier generation technologies (i.e., times when devices were larger),
and several other factors. To understand the underlying themes of custom VLSI design, it is not
necessary for you to understand all of the details of these very complex, contemporary
technologies. For this reason, the fabrication steps discussed below are the minimal steps, and
assume a single level (plane) of metalization for interconnects.
• The tyranny of alignment (make analogy to aligning a plate of glass on top of
another plate of glass. Then - when you draw a square at a particular location in your
drawing, you must understand that the actual fabrication may cause that square to move,
relative to other structures below and above it.
• The biggest challenge relates to aligning the edges of the source and drain regions
with the gate metal on top of the thin gate oxide.
• High temperature (1000 degrees C) processes are required at various steps along
the way. Aluminum would essentially melt at those temperatures. Therefore, difficult to
use aluminum as the material for the gate plate of the devices capacitor. Aluminum can
come only at end.
• Doped silicon crystals are not insulators. Although they are not excellent
conductors such as aluminum or copper, they are not terrible conductors for some
applications (so long as their size/length can be sufficiently small that the resistance is
acceptable). In particular, silicon crystals are "semi"-conductors. Addition of higher
densities of dopants leads to lower resistance. For example, the source and drain regions
of the MOS transistors in Figures 4 and 5 are doped very heavily (the reason for the
notation N++ and P++), and have very low resistance. The source (drain) region act as
conductors, extending the external wire contacting the source region to the edge of the
active region (gate region) under the gate electrode.
 • If, instead of having a pure crystal of silicon, you have a tightly packed material
of small silicon crystallites (by small, I mean submicron-scale dimensions), conduction
can proceed through the points where the crystallites touch. If this material (called
polysilicon) is very heavily doped (e.g., N++ or P++), it will, as in the pure silicon
crystal case, have a low resistance (higher than similarly doped single crystals but often
useful as a local "conductor." This polysilicon will be used to create the gate electrode,
since aluminum metal would melt at the high processing temperatures used (as noted
above).

4.2 NMOS Transistor

The technology described here (and usable in your layout design of digital circuits) uses
polysilicon as the material for the gate electrode. The technology is called "self-aligning gate"
since the fabrication sequence automatically aligns the edge of the gate electrode with the edges
of the source and drain regions, eliminating the most critical of the alignment challenges.
The fabrication process is a sequence of steps in which material is deposited (or implanted)
on the overall silicon wafer and then material is removed from selected regions to create a
pattern in the uniform layer of material. The deposition steps in the technology described below,
as just noted, cover the entire wafer with a thin film of material. There is no connection to any
specific circuit function in these steps. The steps that imprint the silicon wafer with a specific
MOS circuit are those in which material is removed from selected regions, customizing the
uniform layer of material. We will see below that after a few steps of deposition and patterning
have been completed, a three dimensional structure is emerging and this structure can be used to
implant donor/acceptor dopants in regions defined by the three dimensional structure.
A patterning step requires a "picture" of the pattern desired. That picture is called a "mask."
The pattern is imprinted onto the silicon wafer by first coating the silicon wafer with a
photosensitive film, shining light through the mask to expose the film, and then developing the
film. Unlike photographic film (where film remains but light transmission characteristics
change), the photosensitive film being used here is removed or not removed from areas
(depending on which regions have been exposed), exposing the underlying material). The
subsequent step will removed material in the holes in the photosensitive film, exposing the
material to the etchant (or plasma) while the regions where the photosensitive film remains are
not etched (i.e. the photosensitive film "resists" the etching). All the above is simply to say that
this photosensitive film is called a photoresist (combining the photosensitive nature for exposure
with the resisting nature during etching).

The fabrication process for the technology described here proceeds through the following
sequence of deposition/patterning steps.
1. The starting point is a clean silicon wafer, doped either N-type or P-type. For our example,
the wafer is doped P-type since we will be building NMOS transistors.
2. A thick (several microns) insulator is grown on the wafer and covers the entire surface
(Figure 6). .
 Grown
P-Type
(a) Si SiO 2 insulator
wafer (oxide)layer
with oxide layergrown on surface
Substrate

Figure 6a
3. Mask 1: Diffusion Mask. The first patterning (mask level) will create a hole in the thick
oxide extending down to the surface of the silicon. Within this hole, source, drain, and gate
structures will be created as we proceed). This is the first mask, and is called the diffusion
mask (don't worry about whether names make sense - they do once you've become familiar
with the reasons why they were chosen). Figure 6b shows the desired result of this step -
namely creation of a hole in the thick oxide within which we will be building the entire
NMOS transistor. Figure 7 shows how this is achieved.
In Figure 7a, the red lines represent the mask (looking down from the top, this would be a
transparent hole in a non-transparent plate). Light shines through that hole in the mask,
exposing the film of photoresist. Figure 7b shows the subsequent sequence (i) development
of the photoresist leading to a hole exposing the thick oxide, (ii) etching the oxide (with the
resist protecting the oxide not exposed in the hole) and (iii) the removal of the photoresist
leaving the oxide-covered wafer with a hole extending down to the silicon substrate.
Thick
P-Type
Substrate
oxide

Figure 6b
 Photoresis
Developed
After
Light
P-Type
Thick
ÒMaskÓ
Exposed
P-Type
Unexposed
etching
removing
passing
(b)oxide
(a) photoresist,
passing
away
through
the the
photoresist
Light
light
exposing
thick
hole
tofrom light source
the
oxide,
layer,
Substrate
transfer
photoresist
oxide
Substrate
thick
tphotoresist
the
theoxide
pattern
resulting
P-type
in mask
layer.
substrate
onstructure
mask to is (hole
exposed.
in thick
the
film
film
photographic
oxide
film extendingfilm.down to
silicon substrate) is seen.

Figure 6b
4. Next, a thin oxide (the thin gate oxide shown in Figures 4 and 5) is grown over the entire
wafer.
5. After growing the thin oxide, a layer of polysilicon is deposited on top of the thin oxide
layer of the previous step. This polysilicon will provide the gate material. Figure 7a shows
 the result of these two depositions (ignore for now the photoresist piece, which is done
next).
(b)
(a)
(c)
This
P-Type
Earlier
Structure
Current
stepÕspolysilicon
after deposition
etchinglayout
of polysilicon,
of pattern
thin gate
with
oxide,
followed
previous
followed
bydiffusion
etching
by oflayer
thin layout
deposition
oxide
polysilicon
Substrate
diffusion
(thickofoxide
polysilicon,
not much followed
affected),
pattern
by deposition,
and removalexposure,
of photoresist.
and
developing
layer
layout
layoutof photoresist.
pattern

Figure 7

6. Mask 2: Polysilicon Gate Mask. The next etching step will remove polysilicon from
selected areas. Since the polysilicon will be used as the gate electrode, the polysilicon
 pattern will represent the gate of the device. However, polysilicon has a not terribly bad
resistivity and can, for short lines, be used for interconnections. For this reason, polysilicon
interconnection lines are also defined at this point. Figure 7b shows the result of this
patterning. This step requires that the polysilicon layout shape in LASI be placed correctly
relative to the diffusion layer layout shape done previously. Figure 7c shows the polysilicon
layout shape for this step drawn in proper alignment with respect to the diffusion layer
pattern.
7. Implanting of dopants for the source and drain regions. The next step uses an "ion
implanter" to "shoot" dopant ions at then surface of the silicon. Figure 8 illustrates this step.
Ions impinging directly on the silicon surface are implanted "into" the silicon. However,
they do not have sufficient energy to go very far into the silicon. These ions will provide
the doping of the source and drain regions (the N++ regions, which will have lower
resistivities than normally doped silicon.
Those ions impinging onto the polysilicon layer are also implanted, in this case implanted
"into" the polysilicon. However, the ions do not have enough energy to travel very far into
the polysilicon. For this reason, they do not reach the thin oxide or the silicon underlying
the polysilicon. They do, on the other hand, dope the polysilicon, leading the polysilicon to
have lower resistivities, sufficiently low to be used as the gate electrode.
Finally, those ions impinging on the thick oxide are implanted "into" the oxide (but doing
this doesn't change the fact that the oxide is an insulator.
8. High temperature process. After implanting the dopants (which appear near the surface of
the silicon), the silicon crystal will be greatly damaged in the source and drain regions and
the dopants will not extend far enough into the silicon. To repair (anneal) the damage to the
silicon crystal in the drain/source regions and to drive the dopants into the silicon, the wafer
is heated for a specified time at high temperature (typically about 1200 degrees centigrade).
Figure 8 shows the result of device structure after implanting and annealing.
Polysilicon,
Source
P-Type
Thick& though
Drain not
colored,
Substrate
Oxide is doped.

Figure 8.
9. Deposit a thick oxide (silicon dioxide) over the entire wafer. Figure 9 shows the structure at
this stage. This second oxide provides protection of the NMOS transistor that has been
fabricated.
 P-Type
Thick
Substrate
Oxide

Figure 9.

Polysilicon
(b)
(a)
Diffusion
Contact
P-Type
Thick
Substrate
pattern
pattern
Oxide to
polysilicon
drain

Figure 10
10. Mask 3: Contact holes. Addition of contact holes from surface of thick oxide to source,
drain, and polysilicon to allow the final metal interconnections to extend down to these
layers. Note: the contact to the polysilicon layer is never made inside the diffusion layer to
avoid tampering with this sensitive structure with the thin oxide. As shown in Figure 7c, the
polysilicon extends outside the diffusion hole and contact holes to polysilicon are made in
that region outside of the diffusion hole. Figure 10a shows a cross section with the via holes
to the source and drain regions. Figure 10b, like Figure 7c showing the LASI layout pattern,
shows the contact to the polysilicon outside the diffusion hole.
11. Metal deposition Next, we add the metal interconnections. First, aluminum (in the simple
process we are using) is deposited over the entire wafer. During this step, the deposited
aluminum also fills the contact holes. Figure 11 illustrates the result after depositing the
metal film.

P-Type
Thick
Substrate
Oxide

Figure 11
11. Mask 4: Metal interconnections. The last mask patterns the film of metal to create the
desired circuit "wires". Figure 12a illustrates (not very effectively) the result of this step.
Figure 12b adds the metal interconnection patterns to the previous mask patterns. NOTE: I
have not tried to satisfy all of the design rules when drawing the simple mask patterns.
Instead my intent has been to provide a starting point for understanding the
relationship between the fabrication steps and the "drawings" you will be creating in
the LASI drawing environment.
 (b
(a)
P-Type
Thick
Patterns
Metalprior
1 to metal interconnections are shown
Substrate
interconnections
Oxide with thin lines.

Figure 12

4.3 PMOS Transistor

If we are using a P-type substrate (as in the examples used in Section 4.2 for the NMOS
transistors, we need to handle the problem of providing the N-type substrate in which to build the
PMOS transistor. As noted earlier, this is achieved by fabricating an N-type well in the P-type
substrate. I won't go through the details of the various steps used to integrate this fabrication
step with those described in Section 4.2 (the basic issue relates to the thick oxide starting point
used in Section 4.2). Figure 13b illustrates the PMOS transistor fabricated in an N-type well.
Figure 13a illustrates the fabrication of the N-type well. This is done at the very start of the
fabrication process. The thick oxide has been grown. A hole large enough for the well is etched
in the thick oxide (an N-well pattern will need to be added to your LASI drawing to do this).
Then donors with very high energy are implanted into the hole, penetrating rather deeply into the
silicon. After the implant, the silicon is again subjected to a high temperature heat treatment to
repair the implant damage to the silicon. After creating the N-type well, the thick oxide will
need to be regrown in order to refill the opening created to implant the N-type well. One way to
restore a thick oxide that doesn't have significantly less thickness in the hole created for the N-
type well creation is to etch away all of the thick oxide after implanting the N-type well and then
regrowing a new oxide from scratch. Once the thick oxide has been reestablished across the
entire wafer, the steps defined in section 4.2 to create the N++ source-drain regions for the
NMOS transistor are completed, then the steps to create the P++ source drain regions for the
PMOS transistor are completed, after which the etching of contact holes and patterning of the
interconnection metal lines can proceed for both transistors simultaneously.
Thick
P++
P-Type
Thick
N-Type
source
Substrate
(b)&
(a) Well
drain
Oxide
Oxide

Figure 13

4.4 Substrate contacts

As mentioned near the beginning of this report, it is necessary to connect the P-type
substrate used for the NMOS transistors to ground (lowest power supply voltage) and to connect
the N-type well used for the PMOS transistor to +5 volts (or the highest power supply voltage) in
order to maintain the diodes (source/drain regions to substrate) reverse biased. One part of this
task involves making a contact hole and completing an aluminum connection to the P-type or the
N-type substrate. There is a subtlety here that impacts how this is done. In particular, aluminum
is actually a p-type dopant in silicon. Aluminum connected directly to the N-type well could
easily create (by self-doping the silicon near the contact point) a p-n diode (basically a bad
contact). However, if aluminum connects to an N++ region, the strong N++ doping ensures that
diode-like behavior does not occur and instead the desired ohmic contact is achieved.
N++
P++
P-Type
Source
N-well
Thick
Drain
N-Type
region
source
Substrate
(b)
(a) formed
&Well
drain
Substrate
when
Contact
Oxidefabrication
NMOS
Contacttransistor

Figure 14
The question then, for making a contact to the N-type well used for the PMOS transistor,
how to provide the needed N++ doping at the contact point. In fact, an step creating an N++
region does occur in the overall fabrication (namely when the N++ source and drain regions for
the NMOS transistor are created). Refer back to Figure 8 and step 8 of the NMOS transistor
fabrication described in Section 4.2. The "diffusion layer" mask caused a hole to be created in
the thick oxide. Then, in Figure 8, a thin oxide was grown followed by deposition of the
polysilicon. When the polysilicon was patterned, the polysilicon left in the hole made in the
thick oxide prevented the donors from reaching the silicon, creating the gate. If we had not
drawn a polysilicon pattern crossing over the diffusion pattern, then the entire portion of silicon
exposed by the hole in the thick oxide would have been doped N++.
Figure 14 illustrates what I am trying to say. In Figure 14a, I have assumed that the PMOS
device structure is fabricated before the NMOS device structure and we are now in the process of
fabricating the NMOS device. An NMOS device diffusion pattern is used to open a hole in the
thick oxide above the N-type well. Both the polysilicon and the thin oxide are etched away
before the N++ doping step using ion implantation. After implanting and annealing, we are
left with the desired N++ region in the N-type well. In a similar manner, when fabricating the
PMOS transistor, we could open a hole in the thick oxide over the NMOS transistor's P-type
substrate and implant a P++ region in that P-type substrate.
After the devices (source, gate, drain) for both the NMOS and the PMOS transistors have
been created, the contact holes are formed, aluminum is deposited, and then the aluminum is
patterned to create the interconnections for both the NMOS and PMOS transistors during the
same fabrication step. Figure 14b illustrates the PMOS transistor and it's substrate bias contact.
The NMOS transistor would look the same except there would not be an N-type well and the
source/drain regions would be N++.

5. From Transistor Schematic to Mask Layout

To put things together, I will comment briefly on the mask layout for a simply CMOS
inverter digital circuit. Figure 15 shows on the left the transistor-level circuit diagram for a
standard CMOS inverter. Here, a PMOS transistor is connected to +5 volts, an NMOS transistor
is connected to ground. The connection of the PMOS "pullup" (to +5 volts) transistor to the
NMOS "pulldown" (to ground) transistor provides the negation of the input to the inverter. On
the right is an example of a layout of this inverter. I won't go into details regarding the layout.
You should be able to see the correspondence between the fabrication steps described in the
sections above and the inverter circuit. I have include the N-type well for the PMOS transistor
and the substrate contacts for the NMOS and for the PMOS transistors. When you are drawing
the layout, you will be doing what is shown in the figure, generally drawing rectangles and, for
more complex shapes, using multiple rectangles.
 NMOS
N-well
PMOS
Contact
Polysilicon
Aluminum
Output
Input
+5 volts
Ground
diffusion
diffusion
hole
metalmask
mask

Figure 15

6. A Couple of Comments
At this point, a couple of comments are appropriate to prepare you for the layout design.
The picture of the layout in Figure 15 was created using a simple drawing program (like
PowerPoint but a Macintosh vector drawing tool). When you "draw" the layout using the LASI
layout software, your first impression will be that this is a really bad drawing tool. Indeed, if
considered simply as a drawing tool, it is bad. However, beneath that drawing interface is a
substantial amount of understanding about VLSI circuits. It also has mechanisms to edit your
drawing that will seem awkward at first but which, in fact, are to help you maintain a correct
drawing according to the rules that will be enforced below the surface of the user interface. For
example, the software knows in great detail all of the positioning and sizing constraints (the so-
called "design rules") that must be satisfied for a set of supported technologies (they extend to
submicron circuits). You will need to verify that your layout satisfies these rules and the
underlying software does that for you. Be patient as you become familiar with the manipulation
of your designs using LASI and it will become more self-evident as you proceed.
One question that may arise is "how do I know how well my circuit is performing after I
finish 'drawing' it." Spice is the standard circuit simulation software tool (for example PSpice
was probably included as part of your undergraduate training - this is the PC version of the
classic Spice circuit simulator). The models for these micron and submicron transistors and
interconnections are very complex, with a bewildering number of parameters needed to simulate
a circuit, even if as simple as the inverter in Figure 15. LASI in fact knows how to analyze your
layout drawings and extract the Spice (PSpice) parameters, creating the Spice/Pspice circuit file
needed. All you will need to do with the generated circuit file is specify the input signals and
supply voltages. Again, this is one of the capabilities lying underneath the basic drawing
capabilities.
Why is this capability important? The inverter in Figure 15 is a digital circuit in the sense
that its inputs and outputs switch between the logic values of "0" and "1". But this is an overly
simplified model. In fact, it is an analog circuit if you consider how the signals change in time.
There are resistances and capacitance associated with all the elements (not only transistors but
also interconnections (including the polysilicon lines and the diffusion regions). If you change
the length or width of a polysilicon line, for example, the resistance and capacitance of that line
changes. If you change the length or width of the gate region of a transistor, you change not only
the current for a given voltage but also the parasitic resistance and capacitance of the transistor.
For accurate simulation, you would need to create a Spice circuit file that includes all these
levels of detail. For the inverter in Figure 15, it is possible to create the Spice circuit file
manually (it is, after all, the simplest of all digital circuits). But what would you do if your
circuit contains 1000 transistors. Even that is very small compared to today's circuits with
hundreds of millions of transistors. It is for this reason that the capability of the layout software
to generate from your layout the Spice file including all these details is of fundamental
importance.
A last comment relates to what happens when you have finished a verified layout for a
circuit. Due to the long delays that occur, we will not be able to take this last step but you could
use your LASI file to send your design to a microfabrication foundry. The educational program
for this is called MOSIS. After several months (a problem with a course), you would receive a
handful of your circuits, fabricated and packaged. In this last step, someone else is doing all the
work so your job is done when you have completed (including verification and simulation) your
layout.
We will be designing digital circuits (they are the easiest to design systematically).
However, the same CMOS technology used for digital circuits can also be used to realize analog
circuits. The LASI tool is fully capable of supporting analog circuit design and simulation. The
VLSI design book by Jake Baker is suggested as a useful textbook (recommended but not
required) because it contains guidance on how to design the full range of digital and analog
circuits. I recommend it to those who plan on working in microelectronics since it is the best
overall reference book on the topic that I know (and it was created in conjunction with the LASI
design software, which is used throughout the book to illustrate various circuit designs).
 Finally, why was this overview created? Mainly to allow the VLSI design book by Baker to
be included as a recommended, rather than required, book. To replace that book (which some
students find hard to follow), I will be posting other course notes, seeking to guide you through
the first part of the course on custom VLSI design.