EE133

Analog Communication
Laboratory
Phase Locked Loop (PLL)
Basics

Where would you find a PLL?

Any way of synchronizing two signals?
High Q oscillator (difficult to modulate) and
low Q oscillator (low frequency stability), any
way of transferring some of the high Q
oscillator characteristics?
Any way of generating multiples or fractional
frequencies using a single signal as a
reference?
Any easy method of generating and
demodulate FM signals?

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 PLL Block Diagram
Basic parts

Phase detector : compares phase between the VCO

output and the incoming signal. Produces an output
that is some function of the phase difference.
VCO: simply generates a signal whose frequency is
some function of the control voltage.

PLL’s Basic Idea

Phase detector drives the VCO
frequency is a way such that the phase
difference decreases.
Finally, the loop acquires lock and
input and output frequencies have a
fixed phase relationship while tracking
each other.

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 Basic Components
Phase detector
Transfer function: KΦ [V/radians].
Implemented as: four quad multiplier, XOR
gate, state machine.

Basic Components
Voltage controlled oscillator (VCO).
Frequency is the first derivative of phase.
Transfer function: KVCO/s [radians/(V•s)]

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 Basic Components
Low pass filter
Removes high frequency components
coming from the phase detector.
Determines loop order and loop dynamics.

Putting All Together

Linear model

θo K Φ KVCO F ( s )
Transfer function : =
θ i s + K Φ KVCO F ( s )
θe s
Error function : =
θ i s + K Φ KVCO F ( s )
Loop gain : K Φ KVCO F ( s )
s 2θ i
Steady state error : lim sθ e =
s →0 s + K Φ KVCO F ( s )

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 Selecting your filter
No filter.
First order system.
Simplicity and stability.
Steady state error and bandwidth are
tightly linked.
Useful if you have a huge bandwidth
available and no other constraints.
Example: harmonic locked oscillators

Selecting your filter

One pole RC filter
Second order system
Wide loop bandwidth (small steady state
error) may lead to a poor transient
response (ripple, overshoot).
We need some way of decoupling all
these factors.

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 Selecting your filter
One pole one zero RC filter
Small gain→
gain→ small damping
As gain increases damping first decreases but
then increases again.
Good transient response, good bandwidth easy
to design.

1
p1 =
2π ( R1 + R2 )C
1
z1 =
2πR2C

Second order system with

stabilizing zero
For a (one pole, one zero) passive filter, the
transfer function becomes:

( sτ 2 + 1)
KVCO K Φ
H ( s) =
(τ 1 + τ 2 )
(1 + KVCO K Φτ 2 ) KVCO K Φ
s +s
2
+
(τ 1 + τ 2 ) (τ 1 + τ 2 )
KVCO K Φ
ωn =
τ1 + τ 2
1 ⎛ 1 ⎞
ξ = ωn ⎜⎜τ 2 + ⎟⎟
2 ⎝ K VCO K Φ ⎠

τ 1 = R1C1
τ 2 = R2C1
s 2 + 2ξω n +ωn2

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 Second order system

Parameters:
Natural frequency: ωn
Damping coefficient: ξ
Related to:
How fast your system should settle.
How much overshoot you are willing to
tolerate.

Root Locus
Single pole low pass filter

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 Root Locus
One pole one zero LP filter

Acquiring Lock
Some important parameters:
Capture/lock-
Capture/lock-in range: range of frequencies over
which the PLL is able to acquire lock given that it
was initially unlocked.
Tracking/Hold-
Tracking/Hold-in range: range of frequencies over
which the PLL can track and follow the input
signal once it has acquired locked.

Usually: Lock in range ≤ Tracking range

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 Acquiring Lock
Pull-in range: frequency range over which
the PLL will always lock.
Pull-out range: maximum frequency step
that can be applied without losing lock.

Tracking Range
Basically given by the loop gain and phase
detector range.
Δω LOCK = K Φ KVCO (Phase detector range in rad)

Watch out for finite output range of real-life

blocks.

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 Capture Range
Involves a non-linear process where
the linear model breaks down.
Transient from Transient from
fi=1.0MHz fi=1.0MHz

Capture Range
Non-linear response

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 Capture Range
What is going on?

PLL Simulation
The F(s) is
SPICE model simply an RC;
A=1 (no gain)

Again, as in O/A
“summing node” in model, this block is
the O/A-like model indeed a multiplier
of PLL (see SPICE deck)

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 PLL simulation
Time domain simulation (SPICE): very
small time step required (long
simulation time).
Frequency domain simulators: initial
conditions may be difficult to set, but it
is very efficient (short simulation time).

PLL Applications
FM demodulator.

FM Modulator

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 PLL Applications
Frequency Synthesis

Simple Design Example

FM signal: 450 KHz
Frequency deviation: ±7.5 KHz
Voice signal: 6 KHz
Modulation index=7.5KHz/6KHz=1.25
VCO: 450 KHz ±10 KHz (VC=2-
5VDC)→KVCO=41.9 Krad/(V•s)
Phase detector: 5/4π V/rad (PC2)
One pole, one zero filter.
Minimize overshoot.

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 Simple Design Example
VCO range of 450KHz ± 10KHz ensure
the incoming signal is within the
capture and tracking range of a
MC14046.
Assume a 6KHz square wave audio
signal that shifts the VCO to 457.5KHz
and 442.5KHz during the positive and
negative cycle.

Simple Design Example

This means we have only 84 μs to acquire
lock.
Assume 84μs is about 4 time constants, this
mean a single time constant is about 21 μs.
This give us a ωn= 48Krad/s.
Let C=1.5nF and R3=10R4→ R3=4.3K Ω and
R4=430Ω.
Check damping factor →ξ=1.47 OK
3dB close loop bandwidth is about: 22KHz

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 Final Comments
PLL model usually assumes linearity.
VCO tuning range is usually non linear.
Phase detector can also be non linear.
Bandwidth is usually limited to about
one tenth of your reference frequency.
Leave enough margin for part to part
variations.

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