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Analog-to-Digital Converters

Naiyavudhi Wongkomet, Thaweesak Thantipwan, and Atit Tamtrakarn

Faculty of Engineering, Chulalongkorn University

Phayathai Rd. Pathumwan Bangkok, Thailand 10330.

Phone: +66-2218-6488, Fax: +66-2218-6488,

Email: naiyavud@ee.eng.chula.ac.th

This paper presents two opamp design examples for double sampling technique [1]. The second is a 3.3V 16-

modern analog-to-digital converters. The first opamp, bit 1-MS/s Nyquist-rate sigma-delta ADC [2]. Both

designed for a low-voltage low-power high-speed pipeline converters are designed in a 3.3-V, 0.5-µm CMOS

ADC, is a two-stage with folded-cascode as the first stage technology.

and feature common-mode stabilized active load and The outline of this paper is as follows. Section 2

closed-loop pole placement techniques. The second opamp, describes the first opamp, while Section 3 describes the

designed for a high-accuracy high-speed sigma-delta ADC, second opamp. Simulation results are summarized in

is a two-stage opamp employing a modified cascode Section 4. Section 5 is the conclusion.

compensation to improve the bandwidth without

increasing the power consumption. Both opamps are

designed in a 0.5-µm CMOS technology and achieve DC 2. Low-voltage low-power high-gain opamp

gain over 90dB and unity-gain bandwidth over 200MHz.

Vdd

M 18 M 19

M3 M4 V cmfb

V out+

1. Introduction CC

M6 M7 CC V out-

systems where analog signals are quantized into digital M 14 M 10 M 11 M 15

data for processing in the digital domain. Hence, the V in - V in +

M1 M2

performance of the system inevitably relies on the

performance of analog-to-digital converters. The demands M5 M 12 M8 M9 M 13 M 16 M 17

for high-resolution and high-speed converters have

Gnd

continually increased in telecommunications, digital signal

processing, and industrial applications. Meanwhile, the Figure 1. Low voltage opamp with common-mode

operating voltage of integrated circuits becomes lower stabilized active load.

every year following advances in CMOS technology , thus

reducing the signal swing and increasing the power For low-voltage supply, the opamp needs wide input

consumption. In contrast, portable devices require that the voltage range and wide output voltage swing. Cascode

power consumption is minimized to maximize the battery topology is not preferred because the output voltage swing

life. All of these requirements imply that the opamps, the is limited by the cascode devices. Typically, the

core of practically all analog-to-digital converters, need to conventional two-stage topology is the best candidate but

have high speed, high gain, large output swing, and low this topology does not have enough DC gain for high-

noise, while can operate at low supply voltage and resolution applications. Moreover, for fully differential

consume as little power as possible. topology, a two-stage opamp normally requires a

This paper discusses two opamps which have been common-mode feedback (CMFB) amplifier to sense

designed for two analog-to-digital converters. The first is

common-mode output voltage, invert the phase, and If mismatches exist between M12-M15 and M8-M11, the

feedback to the first stage. This consumes additional common-mode impedance would increase slightly while

power because the CMFB amplifier must be as fast as the the differential-mode impedance could increase, decrease,

main amplifier. or even become negative depending on the direction and

The proposed opamp as shown in Figure 1 is suitable magnitude of the mismatch. Through derivation and simu-

for low-voltage high accuracy applications. The input lation, it was confirmed that transistor mismatches up to

stage is a folded-cascode stage with common-mode two percents result in negligible effect to the opamp

stabilized active load [3-4] and the second stage is a class transient response.

A common source. The cascode compensation scheme [5] This opamp is a two-zero three-pole system and is

is chosen for this opamp rather than the conventional difficult to design with conventional design techniques. A

miller compensation to achieve lower power consumption. good approach is to use closed-loop pole placement

The common-mode stabilized active load, modified technique [7]. The closed-loop pole placement technique is

from reference [3] and [4] by adding cascode devices, the method that fixes position of poles and zeros when the

consists of eight equal size transistors M8-M15, is preferred system is closed loop and then find out what the value of

as load of the first stage rather than normal cascode active physical device parameters are. This technique simplifies

load . With this load, differential signals see high load the design of such complex system.

impedance since transconductance of M12-M15 are From the differential half-circuit model in Figure 2 and

cancelled by the transconductance of M8-M11. its small-signal model in Figure 3, the closed-loop transfer

Meanwhile, the common-mode signal impedance is low function can be derived as shown below

and thus the common-mode voltage in the first stage g m1 (3)

( g m 2 g m3 − C 2 CC s 2 )

output is stable without a CMFB circuit. This scheme C 2 CT2

H cl ( s) =

eliminates the need to reverse the phase of common-mode g (C + CC ) − βg m1CC 2 g m 2 g m 3CC βg g g

s 3 + m2 L s + s + m1 m 22 m3

feedback signal and allows a simple switched-capacitor C 2

T C C

2 T

2

C 2 CT

CMFB [6] to be applied to the second stage directly.

where CT = C1CL+C1CC+CLCC, C1 is the parasitic

Simplified equations of common-mode output impedance,

capacitance at the drain of M1, C2 is the parasitic

Ro,cm, and differential-mode output impedance, Ro,dm, are

capacitance at the gate of M3.

shown below.

The denominator of the closed-loop transfer function in

1 Eq.(5), denoted as D(s), indicates the positions of closed-

Ro ,cm ≈ (1)

2g m loop poles in terms of α , ξ and ω n as shown here

r (2 + g m ro ) D( s ) = ( s + αξω n )( s 2 + 2ξω n s + ω n2 ) (4)

Ro ,dm = o (2)

2 These parameters are related to physical device para-

meters. The optimum value of these parameters can be

obtained by the desired step response and numerical

optimization. In this design, α =0.9 and ξ =0.85 are the

I1 I3 optimum values in term of power consumption.

CC

Eq.(3) and Eq. (4) show that this opamp has two zeros,

M 2 one real pole, and two complex poles. The location of

C L v od poles and zeros are shown in Figure 4. Since the zeros are

at the same frequency but on different half of the plane,

v id M 1

I2 M 3 the zeros do not degrade phase margin. Moreover, the

zeros are at much higher frequency, thus do not effect the

Figure 2. The differential half-circuit model of the opamp amplifier response.

in Figure 1

Im(s)

CC

ω n2

-gm2v1

vs Re(s)

vi gm3v2 αζω n

Cin CL

βvo gm1vi C1 v1 v2 C2 vo

ζω n

Figure 3. Small-signal model of the circuit in Figure 2 Figure 4. Pole-zero plot diagram.

3. High-speed high-gain opamp M6a M0 (Bpctrl) M6b

M1a M1b

ID6

In most switched-capacitor applications, the (Out+)

(in+) ID1 (in-)

(Out-)

requirements for opamps are large bandwidth, high slew Cc M2a M2b Cc

rate, high gain (>90 dB), wide swing and low noise CL M3a M3b CL

because the systems operate at frequency several times

M5a M4a M4b M5b

higher than the signal bandwidths. The two-stage opamp

in Figure 5 with PMOS-input telescopic configuration as Figure 6. Amplifier with cascode compensation.

the first stage and NMOS common source as the second

stage can satisfy the high gain, low noise and wide swing Vdd

Bp1

M5 M9 M7

O ut

the lowest number of transistors generating noise. To M1

Bp2

M2

Bn

at even higher frequency to ensure stability. Since the M3 M4 M 10

V ss

locations of parasitic poles depend on the opamp Figure 7. Amplifier with Ahuja compensation

compensation, this is an important issue to explore in order

to maximize the bandwidth and minimize the power Cc

(1) (2)

This paper proposes a modified cascode compensation Vin

Out

gm1.

technique as shown in Figure 5. This compensation Vin gm5.

V2

technique yields a higher bandwidth than typical cascode C1 C2 CL

compensation [5] as shown in Figure 6 and Ahuja Figure 8. Small-signal model of amplifier with cascode

compensation [8] as shown in Figure 7 because its nearest compensation.

parasitic poles come from NMOS rather than PMOS.

Compared to Ahuja compensation, this technique removes gm2.V1 gm3.V3

(1) (2) (3)

M8 in Figure 7 by utilizing M3s in the active load as Vin gm1. C3 Cc

shown in Figure 5; hence, the two compensation schemes Vin Cgd5

Out

have identical small-signal models. The advantages of the C1 C2

conversion of PMOS (M8) to NMOS (M3s). Figure 9. Small-signal model of amplifier with modified

Next, the small-signal differences between the cascode compensation.

traditional cascode compensation and the modified

cascode compensation will be investigated. Figure 8

shows the small-signal model of an amplifier with cascode and the two complex poles are approximately the roots of

compensation. For open-loop, the opamp has one real pole [

s 2 (C gd 5 + C2 )(CC + CL )C1 + (CC + C1 )C2C gd 5 + (C gd 5 + C2 )CC CL ]

located at low frequency, two complex poles and two real

zeros. The unity gain frequency is given by + s[g m2 C2 (CL + CC + C gd 5 ) + g m 2C gd 5CL + g m5C gd 5 (CC + C1 ) ]

ωu = g m1 / CC (5) + s[g m2 ]

g m5 (C gd 5 + CC ) = 0

The two zeros are located at (7)

Z 1, 2 = ± gm 2 gm5 / C 2 C C (6) For the modified cascode compensation, the small-

signal model is shown in Figure 9. The opamp has two

real poles, two complex poles and one left-half-plane zero.

(Bpctrl)

M6a M0 M6b One real pole is at low frequency and another is at very

M1a M1b

ID6 high frequency.

(in+) ID1 (in-)

(Out+) (Out-) P4 = − g m 2 / C1 (8)

Cc M2a M2b Cc

The unity-gain frequency is approximately

CL M3a M3b CL

ωu = g m1 / CC (9)

M5a M4a M4b M5b the left-half-plane zero is located at

Figure 5. Amplifier with modified cascode Z1 = − g m3 / CC (10)

compensation and the complex poles are approximately the roots of

[

s 2 (Cgd 5 + C2 )(CC + CL )C3 + (CC + C3 )C2Cgd 5 + (Cgd 5 + C2 )CC CL ] Table 2. Summary of opamp specifications

+ s[gm3 ]

C2 (CL + CC + Cgd 5 ) + g m3Cgd 5CL + g m5Cgd 5 (CC + C3 )

Specifications Opamp with Opamp with

+ s[g m3 ]

g m5 (Cgd 5 + CC ) = 0 common- modified

(11) mode cascode

Equation (7) and (11) are almost identical. The two stabilized compensatio

differences are the substitution of C1 and gm2 in Equation active load n

(7) with C3 and gm3 in Equation (11), respectively. DC gain (dB) 91 99

To illustrate the effectiveness of the proposed Unity-gain BW 202 368

compensation technique, we designed two amplifiers with (MHz)

identical bias current, device sizing, load capacitance, and Phase margin 64 @ β=0.5 67 @ β=1

compensation capacitor, but with different compensation (Degree)

techniques. According to Equation (5) and (9), both CL (pF) 2 1.5

amplifiers have the same unity-gain bandwidth. The key CC (pF) 0.8 1

difference, however, is the much higher frequency of the Settling time (ns) 14.1 (99.9%) 8.7 (99.99%)

complex poles (P2,P3) as shown in Table 1, and thus better Noise (nV/rt.Hz) 287@1kHz 110@1kHz

phase margin. This results from that M2 in the cascode 10.2@1MHz 4.1@1MHz

compensation is a PMOS, while M3 in the modified Supply voltage (V) 2.5 3.3

cascode compensation is an NMOS. Another advantage of Output swing (V) ±2 ±2.6

the new compensation is that there is a left-half-plane zero Power consumption 3 11.1

near unity-gain frequency which can slightly improve the (mW)

phase margin and the settling.

One drawback of the modified cascode compensation is

that the falling slew rate becomes slower than the rising

slew rate. This, however, can be compensated by 6. References

increasing the bias current of the second stage. [1] A. Tamtrakarn and N. Wongkomet. “A 2.5-V 10-Bit 40-

MS/s Double Sampling Pipeline A/D Converter”, Asia-

Table 1. Open-loop poles and zeros of opamps with Pacific Conference on Circuits and System, 2002.

different compensation. Both opamps have ID1=0.3mA, [2] T. Thantipwan and N. Wongkomet. “A Power-Optimized

ID6=1mA, Cc=1pF, CL= 1.8pF, ωu = 280 MHz. 16-Bit 1MS/s Nyquist-Rate Sigma-Delta Analog-to-Digital

Converter”, Chulalongkorn Univer-sity. To be published.

Pole & Zero Cascode comp Modified comp [3] M. Waltari and K. Halonen, “A Switched-Opamp with Fast

P1 -11 kHz -3.3kHz Common Mode Feedback”, Proceedings of the 6th IEEE

P2,3 -119±458i MHz -313±752i MHz International Conference on Electronics, Circuit and

P4 - -889 MHz Systems 1999, Vol. 3, pp. 1523-1525, 1999.

Z1 -1 GHz -565 MHz [4] M. Waltari and K. Halonen, “A 10-Bit 220-Msample/s

Z2 940 MHz - CMOS Sample-and-Hold Circuit”, Proceeding of the 1998

IEEE International Symposium on Circuits and Systems,

Vol. 1, pp. 253-256, 1998.

4. Implementation and simulation results [5] D. B. Ribner and M. A. Copeland, “Design Techniques for

Cascoded CMOS Op Amps with Improved PSRR and

The two proposed amplifiers are designed in a 0.5-µm Common-Mode Input Range”, IEEE Journal of Solid-State

CMOS process. Table 2 summarizes all the simulated Circuits, Vol. SC-19, No. 6, pp. 919-925, December 1984.

specifications. One of the amplifier is being fabricated [6] R. Castello and P. R. Gray, “A High-Performance

and the other will be fabricated shortly. Micropower Switched-Capacitor Filter”, IEEE Journal of

Solid-State Circuits, Vol. SC-20, No. 6, pp. 1122-1132,

December 1985.

5. Conclusions [7] A. R. Feldman, “High-Speed, Low-Power Sigma-Delta

Modulators for RF Baseband Channel Applications”,

This paper describes two amplifiers for modern high Memorandum No. UCB/ERL M97/62, Electronics

performance analog-to-digital converters. Both amplifiers Research Laboratory, U. C. Berkeley, 1997.

are two-stage with folded-cascode as the first stage. [8] B. Ahuja, “An Improved Frequency Compensation

Several design techniques are discussed such as common- Technique for CMOS Operational Amplifier”, IEEE JSSC,

mode stabilized active load, closed-loop pole placement, Vol. 18, No. 6, pp. 629-1633, Dec, 1983.

and modified cascode compensation.

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