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ABSTRACT
 ABSTRACT

Quadrature Amplitude Modulation (QAM) is used

for transmission at high data rate in band-limited channels. A great deal

of attention has been devoted to derive expressions for bit error

probability of QAM. In this paper, a generalized expression for bit error

rate (BER) for odd bit QAM using symmetry properties of Gray code is

derived and its performance is compared with existing closed form

expression for arbitrary QAM constellation. New BER expression offers

a convenient way to evaluate the performance of odd bit QAM for

various cases of practical interest.

This method of modulation has the advantage of

reducing or eliminating intermodulation interference caused by a

continuous carrier near the modulation sidebands. 

INTRODUCTION TO
QAM
 1. QAM:

Quadrature amplitude modulation (QAM) is both an analog and a digital

modulation scheme. It conveys two analog message signals, or two digital bit
streams, by changing the amplitudes of two carrier waves, using the amplitude-
shift keying (ASK) digital modulation scheme or amplitude modulation (AM)
analog modulation scheme.

These two waves, usually sinusoids, are out of phase with

each other by 90° and are thus called Quadrature carriers or Quadrature
components — hence the name of the scheme. The modulated waves are summed,
and the resulting waveform is a combination of both phase-shift keying (PSK) and
amplitude-shift keying, or in the analog case of phase modulation (PM) and
amplitude modulation. In the digital QAM case, a finite number of at least two
phases, and at least two amplitudes are used. PSK modulators are often designed
using the QAM principle, but are not considered as QAM since the amplitude of
the modulated carrier signal is constant.
 2. DIGITAL QAM:

Like all modulation schemes, QAM conveys data by changing some aspect of a
carrier signal, or the carrier wave, in response to a data signal. In the case of QAM,
the amplitude of two waves, 90 degrees out-of-phase with each other (in
Quadrature) are changed (modulated or keyed) to represent the data signal.
Amplitude modulating two carriers in Quadrature can be equivalently viewed as
both amplitude modulating and phase modulating a single carrier.

Phase modulation (analog PM) and phase-shift keying (digital PSK) can be
regarded as a special case of QAM, where the magnitude of the modulating signal
is a constant, with only the phase varying. This can also be extended to frequency

modulation (FM) and frequency-shift keying (FSK), for these can be regarded as a
special case of phase modulation.
 2. Analog QAM:

When transmitting two signals by modulating them with QAM, the transmitted
signal will be of the form:

where I(t) and Q(t) are the modulating signals and f0 is the carrier frequency.

At the receiver, these two modulating signals can be demodulated using a coherent
demodulator. Such a receiver multiplies the received signal separately with both a
cosine and sine signal to produce the received estimates of I(t) and Q(t)
respectively. Because of the orthogonality property of the carrier signals, it is
possible to detect the modulating signals independently.

In the ideal case I(t) is demodulated by multiplying the transmitted

signal with a cosine signal:

Using standard trigonometric identities, we can write it as:

Low-pass filtering ri(t) removes the high frequency terms (containing 4πf0t),
leaving only the I(t) term. This filtered signal is unaffected by Q(t), showing that
the in-phase component can be received independently of the Quadrature
component. Similarly, we may multiply s(t) by a sine wave and then low-pass filter
to extract Q(t).

The phase of the received signal is assumed to be known accurately at the receiver.
If the demodulating phase is even a little off, it results in crosstalk between the
modulated signals. This issue of carrier synchronization at the receiver must be
handled somehow in QAM systems. The coherent demodulator needs to be exactly
in phase with the received signal, or otherwise the modulated signals cannot be
independently received. For example analog television systems transmit a burst of
the transmitting colour subcarrier after each horizontal synchronization pulse for
reference.

Analog QAM is used in NTSC and PAL television systems, where the I- and Q-
signals carry the components of chroma (colour) information. "Compatible QAM"
or C-QUAM is used in AM stereo radio to carry the stereo difference information.

Fourier analysis of QAM:

In the frequency domain, QAM has a similar spectral pattern to DSB-SC

modulation. Using the properties of the Fourier transform, we find that:

where S(f), MI(f) and MQ(f) are the Fourier transforms (frequency-domain
representations) of s(t), I(t) and Q(t), respectively.
 Quantized QAM:

As with many digital modulation schemes, the constellation

diagram is a useful representation. In QAM, the constellation points are usually
arranged in a square grid with equal vertical and horizontal spacing, although other
configurations are possible (e.g. Cross-QAM). Since in digital telecommunications
the data are usually binary, the number of points in the grid is usually a power of 2
(2, 4, 8 ...). Since QAM is usually square, some of these are rare—the most
common forms are 16-QAM, 64-QAM, 128-QAM and 256-QAM. By moving to a
higher-order constellation, it is possible to transmit more bits per symbol.
However, if the mean energy of the constellation is to remain the same (by way of
making a fair comparison), the points must be closer together and are thus more
susceptible to noise and other corruption; this results in a higher bit error rate and
so higher-order QAM can deliver more data less reliably than lower-order QAM,
for constant mean constellation energy.

If data-rates beyond those offered by 8- PSK are required, it

is more usual to move to QAM since it achieves a greater distance between
adjacent points in the I-Q plane by distributing the points more evenly. The
complicating factor is that the points are no longer all the same amplitude and so
the demodulator must now correctly detect both phase and amplitude, rather than
just phase.
Transmitter:

The following picture shows the ideal structure of a QAM transmitter, with a
carrier frequency f0 and the frequency response of the transmitter's filter Ht:

First the flow of bits to be transmitted is split into two equal parts: this process
generates two independent signals to be transmitted. They are encoded separately
just like they were in an amplitude-shift keying (ASK) modulator. Then one
channel (the one "in phase") is multiplied by a cosine, while the other channel (in
"Quadrature") is multiplied by a sine. This way there is a phase of 90° between
them. They are simply added one to the other and sent through the real channel.

The sent signal can be expressed in the form:

Where vc[n] and vs[n] are the voltages applied in response to the nth symbol to the
cosine and sine waves respectively.
Receiver:

The receiver simply performs the inverse process of the transmitter. Its ideal
structure is shown in the picture below with Hr the receive filter's frequency
response:

Multiplying by a cosine (or a sine) and by a low-pass filter it is possible to extract

the component in phase (or in Quadrature). Then there is only an ASK
demodulator and the two flows of data are merged back.

In practice, there is an unknown phase delay between the transmitter and receiver
that must be compensated by synchronization of the receivers local oscillator, i.e.
the sine and cosine functions in the above figure. In mobile applications, there will
often be an offset in the relative frequency as well, due to the possible presence of
a Doppler shift proportional to the relative velocity of the transmitter and receiver.
Both the phase and frequency variations introduced by the channel must be
compensated by properly tuning the sine and cosine components, which requires a
phase reference, and is typically accomplished using a Phase-Locked Loop (PLL).
Quantized QAM performance:

The following definitions are needed in determining error rates:

 M = Number of symbols in modulation constellation

 Eb = Energy-per-bit
 Es = Energy-per-symbol = kEb with k bits per symbol
 N0 = Noise power spectral density (W/Hz)
 Pb = Probability of bit-error
 Pbc = Probability of bit-error per carrier
 Ps = Probability of symbol-error
 Psc = Probability of symbol-error per carrier

 .

Q(x) is related to the complementary Gaussian error function

by:

, which is the probability that x will be

under the tail of the Gaussian PDF towards positive infinity.

The error rates quoted here are those in additive white Gaussian noise (AWGN).

Where coordinates for constellation points are given in this article, note that they
represent a non-normalized constellation. That is, if a particular mean average
energy were required (e.g. unit average energy), the constellation would need to be
linearly scaled.
Rectangular QAM:

Rectangular QAM constellations are, in general, sub-optimal in the

sense that they do not maximally space the constellation points for a given energy.
However, they have the considerable advantage that they may be easily transmitted
as two pulse amplitude modulation (PAM) signals on quadrature carriers, and can
be easily demodulated. The non-square constellations, dealt with below, achieve
marginally better bit-error rate (BER) but are harder to modulate and demodulate.

Constellation diagram for rectangular 16-QAM.

The first rectangular QAM constellation usually encountered is 16-

QAM, the constellation diagram for which is shown here. A Gray coded bit-
assignment is also given. The reason that 16-QAM is usually the first is that a brief
consideration reveals that 2-QAM and 4-QAM are in fact binary phase-shift keying
(BPSK) and Quadrature phase-shift keying (QPSK), respectively.
 Expressions for the symbol-error rate of rectangular QAM
are not hard to derive but yield rather unpleasant expressions. For an even number
of bits per symbol, k, exact expressions are available. They are most easily
expressed in a per carrier sense:

so

The bit-error rate depends on the bit to symbol mapping, but for and a
Gray-coded assignment -- so that we can assume each symbol error causes only
one bit error -- the bit-error rate is approximately

Since the carriers are independent, the overall bit error rate is the same as the per-
carrier error rate, just like BPSK and QPSK.

.
Interference and noise:

In moving to a higher order QAM constellation (higher data rate and mode) in
hostile RF/microwave QAM application environments, such as in broadcasting or
telecommunications, interference typically increases. Reduced noise immunity due
to constellation separation makes it difficult to achieve theoretical performance
thresholds. There are several test parameter measurements which help determine
an optimal QAM mode for a specific operating environment.

The following three are most significant:

 Carrier/interference ratio.
 Carrier-to-noise ratio.
 Threshold-to-noise ratio,

Applications:

Systems ranging from cellular technology through wireless systems including

WiMAX, and Wi-Fi 802.11 use a variety of forms of QAM, and the use of QAM
will only increase within the field of radio communications.
INTRODUCTION

TO

FPGA
 FPGA

5. INTRODUCTION

5.1 How are FPGA programs created?

Individually defining the many switch connections and cell logic functions
would be a daunting task. Fortunately, this task is handled by special software.
The software translates a user's schematic diagrams or textual hardware description
language code then places and routes the translated design. Most of the software
packages have hooks to allow the user to influence implementation, placement and
routing to obtain better performance and utilization of the device. Libraries of
more complex function macros (eg. adders) further simplify the design process by
providing common circuits that are already optimized for speed or area.

Short for Field-Programmable Gate Array, a type of logic chip that can be
programmed. An FPGA is similar to a PLD, but whereas PLDs are generally
limited to hundreds of gates, FPGAs support thousands of gates. They are
especially popular for prototyping integrated circuit designs. Once the design is set,
hardwired chips are produced for faster performance.
5.2 What are FPGAs?

FPGAs are programmable digital logic chips. What that means

is that you can program them to do almost any digital function.

5.3 Here's the general workflow when working with FPGAs:

You use a computer to describe a "logic function" that you want. You
might draw a schematic, or create a text file describing the function, doesn't matter.

You compile the "logic function" on your computer, using a

software provided by the FPGA vendor. That creates a binary file that can be
downloaded into the FPGA.

You connect a cable from your computer to the FPGA, and

download the binary file to the FPGA.

That's it! Your FPGA behaves according to your "logic function".

5.4 Keep in mind that :

You can download FPGAs as many time as you want - no limit -

with different functionalities every time if you want. If you make a mistake in your
design, just fix your "logic function", re-compile and re-download it.
No PCB, solder or component to change.

The designs can run much faster than if you were to design a board with
discrete components, since everything runs within the FPGA, on its silicon die.

FPGAs loose their functionality when the power goes away (like RAM
in a computer that looses its content). You have to re-download them when power
goes back up to restore the functionality.

5.5 Who makes FPGAs?

There are (at least) 5 companies making FPGAs in the world. The
first two (Xilinx and Altera) hold the bulk of the market.

Xilinx is the biggest name in the FPGA world. It tends to be the

density and technology leader.

Altera is the second FPGA heavyweight, also a well-known name.

Lattice, Actel, Quick logic are much smaller and are the "specialty shops".

5.6 Xilinx

Xilinx has traditionally been the silicon technology leader. Xilinx

general philosophy is to provide all the features possible, at the cost of extra
complexity.

 Biggest and most flexible (feature-full) devices.

 Complex architecture, powerful devices.
5.7 Altera

 Altera philosophy is to provide the features that most people want while
keeping their devices easy to use.
 Lean and efficient devices architecture.
 Powerful devices.
 Lattice, Actel and Quick logic.
 These companies have specialty products.
 Lattice, better known for its CPLDs, have also an "instant-on" FPGA family.
INTRODUCTION TO
VLSI
 6. VLSI

6.1 INTRODUCTION TO VLSI

The electronics industry has achieved a phenomenal growth over

the last two decades mainly due to the rapid advances in integration technologies,
large-scale systems design – in short, due to the advent of VLSI. The number of
applications of integrated circuits in high-performance to the advent of VLSI. The
number of applications of integrated circuits in high-performance computing,
telecommunications, and consumer electronics has been rising steadily, and at a
very fast pace. Typically, the required computational power of these applications is
the driving force for the fast development of this field. One of the most important
characteristics of information services is their increasing need for very high
processing power and bandwidth. The other important characteristics is that the
information services tend to become more and more personalized, which means
that the devices must be more intelligent to answer individual demands, and at the
same time they must be portable to allow more flexibility and mobility.

As more and more complex functions are required in various data

processing and telecommunications devices, the need to integrate these functions
in a small system, package is also increasing. The level of integration as measured
by the number of logic gates in a monolithic chip has been steadily rising for
almost three decades, mainly due to the rapid progress in processing technology
and interconnect technology.
 The monolithic integration of a large number of functions on a
single chip usually provides:

 Less area/volume and therefore compactness

 Less power consumption
 Less testing requirements at system level
 Higher reliability, mainly due to improved on chip interconnects
 Higher speed, due to significantly reduced interconnection length
 Significant cost saving

Therefore, the current trend of integration will also continue in the foreseeable
future. Advances in device manufacturing technology and especially the steady
reduction of minimum feature size support this trend. A minimum size of 0.25
microns was readily achieved.

Logic chips such as microprocessor chips and digital signal processing

chips contain not only large arrays of memory (SRAM) cells, but also many
different functional units. As a result, their design complexity is considered
much higher than that of memory chips. Sophisticated computer- aided design
tools and methodologies are developed and applied in order to manage the
rapidly increasing design complexity.
 6.2 VLSI DESIGN FLOW
6.3 EXPLAINATION

FIG provides a more simplified view of the VLSI design flow,

taking into account the various representations or abstractions of design –
behavioral, logic, circuit and mask layout. Note that the verification of design
plays a very important role in every step during this process. The failure to
properly verify a design in its early phases typically causes significant and
expensive re-design at a later stage, which ultimately increase the time – to –
market.

Although the design process has been described in linear fashion for
simplicity, in reality there are much iteration back and forth, especially between
any to neighboring steps, and occasionally even. Remotely separated pairs.
Although top-down design flow provides and excellent process control, in
reality, there is no truly unidirectional top down design flow. Both top-down
and bottom-up approaches have to be combined. For instance, if a chip designer
defined architecture without close estimation of the corresponding chip area
then it is very likely that the resulting chip layout exceeds the area limit of the
available technology. In such a case, in order to fit the architecture into the
allowable chip area, some functions may have to be removed and the design
process must be repeated. Such changes may require significant modification of
the original requirements. Thus, it is very important to feed forward low-level
information to higher level as early as possible.
INTRODUCTION TO
VHDL
 7. VHDL

7.1 INTRODUCTION

VHDL is a programming language that has been designed and

optimized for describing the behavior of digital systems.

VHDL has many features appropriate for describing the behavior of

electronic components ranging from simple logic gates to complete microprocessor
and custom chips. Features of VHDL allow electrical aspects of circuit behavior
(such as rise and fall times of signals, delays through gates, and functional
operation) to be precisely described.

The resulting VHDL simulation models can then be used as building blocks
in larger circuits (using schematics, block diagrams or system-level VHDL
descriptions) for the purpose of simulation.

VHDL is also a general-purpose programming language: just as high level

programming languages allow complex design concepts to be expressed as
computer programs, VHDL allows the behavior of complex electronic circuits to
be captured into a design system for automatic circuit synthesis or for system
simulation. Like Pascal, C and C++, VHDL includes features useful for structured
design techniques, and offers a rich set of control and data representation features.
Unlike these other programming languages, VHDL provides features allowing
concurrent events to be described. This is important because the hardware
described using VHDL is inherently concurrent in its operation.

One of the most important applications of VHDL is to capture the

performance specification for a circuit, in the form of what is commonly referred
to as a test bench. Test benches are VHDL descriptions of circuit stimuli and
corresponding expected outputs that verify the behavior of a circuit over time.

Test benches should be an integral part of any VHDL project and should be
created in tandem with other descriptions of the circuit.

7.2 A standard language

One of the most compelling reasons for you to become experienced with and
knowledgeable in VHDL is its adoption as a standard in the electronic design
community. Using a standard language such as VHDL virtually guarantees that
you will not have to throw away and recapture design concepts simply because the
design entry method you have chosen is not supported in a newer generation of
design tools.

Using a standard language also means that you are more likely to be able to
take advantage of the most up-to-date design tools and that you will have access
to a knowledge base of thousands of other engineers, many of whom are solving
problems similar to your own.
7.3 FEATURE OF VHDL

VHDL is the imagination of the following languages

 Concurrent languages
 Sequential languages
 Net - list languages
 Timing specification
 Simulation languages
 Test languages

Powerful language constructs

Example: if – else, with – select

Supports design libraries

Facilitates device independent design and portability.

7.4 ADVANTAGES OF VHDL

7.4.1 Improve design quality

 Verifies functions at higher levels

 Verifies that implementation matches functionality desired
 Promotes design component re-use and sharing

7.4.2 Automates low – level design details

 Reduce design time

 Reduce design cost
 Eliminate low-level errors

7.4.3 Makes the design specification more technology – independent

 Supports multiple vendors’ programmable device.

 Facilitates updating design
 Standardizes documentation.
7.5 When should you use VHDL?

Why choose to use VHDL for your design efforts? There are many likely reasons.
If you ask most VHDL tool vendors this question, the first answer you will get is,
“It will improve your productivity. “But just what does this mean? Can you really
expect to get your projects done faster using VHDL than by using your existing
design methods?

The answer is yes, but probably not the first time you use it, and only if you apply
VHDL in a structured manner, VHDL (like a structured software design language)
is most beneficial when you use a structured, top-down approach to design. Real
increases in productivity will come later, when you have climbed higher on the
VHDL learning curve and have accumulated a library of reusable VHDL
components.

Productivity increases will also occur when you begin to use VHDL to
enhance communication between team members and when you take advantage of
the more powerful tools for simulation and design verification that are available. In
addition, VHDL allows you to design at a more abstract level. Instead of focusing
on a gate-level implementation, you can address the behavioral function of the
design. How will VHDL increase your productivity? By making it easy to build
and use libraries of commonly used VHDL modules. VHDL makes design reuse
feel natural. As you discover the benefits of reusable code, you will soon find
yourself thinking of ways to write your VHDL statements in ways that make them
general purpose. Writing portable code will become an automatic reflex.
 Another important reason to use VHDL is the rapid pace of development in
electronic design automation (EDA) tools and in target technologies. Using a
standard language such as VHDL can greatly improve your chances of moving into
more advanced tools (for example, from a basic low-cost simulator to a more
advanced one) without having to re-enter your circuit descriptions. Your ability to
retarget circuits to new types of device targets (for example, ASICs, FPGAs, and
complex PLDs) will also be improved by using a standard design entry method.

VHDL includes many high-level language features that allow you to

describe combinational logic circuits. In this and other VHDL source files listed in
this document, VHDL keywords are highlighted in bold face type. In some VHDL
books and software documents, using upper case characters for keywords and
lower case characters for identifiers highlights keywords. Some other books and
manuals use lower case for keywords and upper case for identifiers. Whatever
forms you encounter or choose to use, keep in mind that VHDL itself is case-
insensitive: keywords can be entered using either upper or lower case, and
identifiers (such as signal and variable names) nay be entered in either case as well,
with no distinction being made between identifiers that are written in either case.

One more note: In the above context, the VHDL symbol <= is an assignment
operator that assigns the value on its right to the signal on its left. Any text that
follows “--” is a comment and is used for documentation only.
 SOURCE CODING

TRANSMITTER SECTION:

ADDGEN:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity addgen is

port(

clk : in std_logic;
en: in std_logic;
rst: in std_logic;
addout: out std_logic_vector(1 downto 0));

end entity;
architecture addgen1 of addgen is
---signal en: std_logic;
signal addsign: std_logic_vector(1 downto 0);
begin

process(clk, rst,en, addsign) is

begin

if(rst='0') then
addsign<= "00";

elsif(clk='1' and clk'event) then

if(en ='1') then
addsign<= addsign + '1' ;

end if;
end if;

addout<= addsign;
end process;
end;
COS WAVE:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY cos_tb IS
END;

ARCHITECTURE cos_tb_arch OF cos_tb IS

SIGNAL cosout : std_logic_vector (7 downto 0);
 SIGNAL rst : std_logic;
SIGNAL clk : std_logic:='0';
SIGNAL fg4 : std_logic;
COMPONENT cos
PORT (
cosout : out std_logic_vector (7 downto 0);
rst : in std_logic;
clk : in std_logic;
fg4 : out std_logic);
END COMPONENT;
BEGIN
DUT: cos
PORT MAP (
cosout => cosout,
rst => rst,
clk => clk,
fg4 => fg4);

clk <= not clk after 5 ns;

rst <= '0','1' after 5 ns;
END;

SINE WAVE:

library ieee;
Use ieee.std_logic_1164.all;

Entity halfsine is
port (
clk : in std_logic;
 rst : in std_logic;
fg1 : out std_logic;
sinout1 : out std_logic_vector(7 downto 0)
);
end;

Architecture sine of halfsine is

type state is(s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15);
signal ps,ns:state;

begin
process(clk,rst)
begin
if(rst='0')then
ps<=s0;
elsif(clk='1' and clk'event)then
ps<=ns;
end if;
end process;

process(ps,rst)
begin
case ps is
when s0=>
sinout1<=X"00";
fg1 <='0';
if(rst='0')then
ns <=s0;
else
ns<=s1;
end if;

when s1=>
sinout1<=X"0c";
fg1 <='0';
if(rst='0')then
ns <=s0;
else
ns<=s2;
end if;
when s2=>
sinout1<=X"18";
fg1 <='0';
if(rst='0')then
ns <=s0;
else
ns<=s3;
end if;

when s3=>
sinout1<=X"23";
fg1 <='0';
if(rst='0')then
ns <=s0;
else
ns<=s4;
end if;

when s4=>
sinout1<=X"2d";
fg1 <='0';
if(rst='0')then
ns <=s0;
else
ns<=s5;
end if;

when s5=>
sinout1<=X"35";
fg1 <='0';
if(rst='0')then
ns <=s0;
else
ns<=s6;
end if;

when s6=>
sinout1<=X"3b";
fg1 <='0';
 if(rst='0')then
ns <=s0;
else
ns<=s7;
end if;

when s7=>
sinout1<=X"3e";
fg1 <='0';
if(rst='0')then
ns <=s0;
else
ns<=s8;
end if;

when s8=>
sinout1<=X"3f";
fg1 <='0';
if(rst='0')then
ns <=s0;
else
ns<=s9;
end if;

when s9=>
sinout1<=X"3e";
fg1 <='0';
if(rst='0')then
ns <=s0;
else
ns<=s10;
end if;

when s10=>
sinout1<=X"3b";
fg1 <='0';
if(rst='0')then
ns <=s0;
else
ns<=s11;
 end if;

when s11=>
sinout1<=X"35";
fg1 <='0';
if(rst='0')then
ns <=s0;
else
ns<=s12;
end if;

when s12=>
sinout1<=X"2d";
fg1 <='0';
if(rst='0')then
ns <=s0;
else
ns<=s13;
end if;

when s13=>
sinout1<=X"23";
fg1 <='0';
if(rst='0')then
ns <=s0;
else
ns<=s14;
end if;

when s14=>
sinout1<=X"18";
fg1 <='0';
if(rst='0')then
ns <=s0;
else
ns<=s15;
end if;

when s15=>
sinout1<=X"0c";
 fg1 <='1';
if(rst='0')then
ns <=s0;
else
ns<=s0;
end if;

end case;
end process;
end;

MUX SHIFT:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity muxshift is

port(
 din : in std_logic_vector(7 downto 0);
sel : in std_logic;
muxshiftout: out std_logic_vector(7 downto 0));

end entity;

architecture muxshift of muxshift is

begin

process(din, sel) is
begin

case(sel) is

when '0'=>
muxshiftout<= din;

when '1' =>

muxshiftout<= din(7) & din (7 downto 1);

when others=>
null;
end case;
end process;
end;

TOP:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity toptx is
port(
clk: in std_logic;
rst: in std_logic;
datain: in std_logic_vector(11 downto 0);
cs: out std_logic;
dac_data: out std_logic_vector(7 downto 0));

end entity;

architecture toptx of toptx is

--component clk_div is
--
-- port ( nreset : in std_logic; -- Reset
-- clk_in : in std_logic; -- Clock Input
-- clk_out : out std_logic);-- Clock Output
--
--end component;

component splitter is
port(

din: in std_logic_vector(11 downto 0);

sel: in std_logic_vector(1 downto 0);
shiftout: out std_logic_vector(2 downto 0));

end component;

component addgen is

port(

clk : in std_logic;
rst: in std_logic;
addout: out std_logic_vector(1 downto 0);
en: in std_logic);

end component;
component sine is
port (
clk : in std_logic;
rst : in std_logic;
fg2 : out std_logic;
sinout : out std_logic_vector(7 downto 0)
);
end component;

component cos is
port (
clk : in std_logic;
rst : in std_logic;
fg4 : out std_logic;
cosout : out std_logic_vector(7 downto 0)
);
end component;

component invsin is
port (
clk : in std_logic;
rst : in std_logic;
fg6 : out std_logic;
invsinout : out std_logic_vector(7 downto 0)
);
end component;

component invcos is
port (
clk : in std_logic;
rst : in std_logic;
fg8 : out std_logic;
invcosout : out std_logic_vector(7 downto 0)
);
end component;

component mux is
port(

sinein: in std_logic_vector(7 downto 0);

cosin: in std_logic_vector(7 downto 0);
invsin: in std_logic_vector(7 downto 0);
invcos: in std_logic_vector(7 downto 0);
qpskout: out std_logic_vector(7 downto 0);
sel: in std_logic_vector(1 downto 0));

end component;

component muxshift is

port(
din : in std_logic_vector(7 downto 0);
sel : in std_logic;
muxshiftout: out std_logic_vector(7 downto 0));

end component;

--component dac is
-- generic ( width : integer := 8);
--
-- port ( clk_in : in std_logic;
-- nreset : in std_logic;
-- Data_in : in std_logic_vector(width-1 downto 0);
-- cs : out std_logic; -- Chip select of the DAC
-- Data : out std_logic_vector(width-1 downto 0)); -- Data for
DAC
--end component;

signal addout: std_logic_vector(1 downto 0);

signal rst_sin, rst_cos, rst_invsin, rst_invcos: std_logic;
signal temp_data: std_logic_vector(7 downto 0);
signal enable: std_logic;
signal shiftout: std_logic_vector(2 downto 0);
signal shiftout1: std_logic_vector(7 downto 0);
signal fg2, fg4, fg6, fg8, clkmain: std_logic;
signal sinout, cosout, invsinout, invcosout, qpskout: std_logic_vector(7 downto 0);
signal sig: std_logic;
signal s2: std_logic_vector(2 downto 1);

begin

enable<= fg2 or fg4 or fg6 or fg8;

rst_sin<= (not shiftout(2)) and (not shiftout(1));
rst_cos<= (not shiftout(2)) and (shiftout(1));
rst_invsin<= ( shiftout(2)) and (not shiftout(1));
rst_invcos<= (shiftout(2)) and (shiftout(1));
--dac_data<= (not(temp_data(7)) & (temp_data(6 downto 0)));
sig<= shiftout(0);
s2<= shiftout(2 downto 1);

--u1: clk_div
--
--port map(
--
-- nreset=> rst,
-- clk_in => clk,
-- clk_out=> clkmain);
--
u2: splitter

port map(

din=> datain,
sel=> addout,
shiftout=> shiftout);

u3: addgen

port map(

clk=> clk,
 en=> enable,
rst=>rst,
addout=> addout);

u4: sine

port map(
clk=> clk,
rst=> rst_sin,
fg2=>fg2,
sinout=> sinout);

u5: cos

port map(
clk=> clk,
rst=> rst_cos,
fg4=> fg4,
cosout=> cosout);

u6: invsin

port map(
clk=> clk,
rst=> rst_invsin,
fg6=>fg6,
invsinout=> invsinout);

u7: invcos

port map(
clk=> clk,
rst=> rst_invcos,
fg8=> fg8,
invcosout=> invcosout);

u8: mux

port map(
 sinein=> sinout,
cosin=> cosout,
invsin=> invsinout,
invcos=> invcosout,
qpskout=> qpskout,
sel=> s2);

u9: muxshift

port map(
din=>qpskout,
sel=>sig,
muxshiftout=>shiftout1);

--u10: dac
--
-- generic map ( width => 8)
--
-- port map( clk_in => clkmain,
-- nreset => rst,
-- Data_in => shiftout1,
-- cs => cs,
-- Data => temp_data);
--

end;

RECEIVER SECTION:

COMPARATOR:

Library ieee;
Use ieee.std_logic_1164.all;
Entity comparator is
port(
from_sine_full : in std_logic_vector(19 downto 0);
from_cos_full : in std_logic_vector(19 downto 0);
from_inv_sine_full : in std_logic_vector(19 downto 0);
from_inv_cos_full : in std_logic_vector(19 downto 0);
from_sine_half : in std_logic_vector(19 downto 0);
from_cos_half : in std_logic_vector(19 downto 0);
from_inv_sine_half : in std_logic_vector(19 downto 0);
from_inv_cos_half : in std_logic_vector(19 downto 0);
output : out std_logic_vector(2 downto 0)
);
End Entity;

Architecture comparator of comparator is

begin

process(from_sine_full,from_cos_full,from_inv_sine_full,from_inv_cos_full,from
_sine_half,from_cos_half,from_inv_sine_half,from_inv_cos_half)is
begin
if(from_sine_full =X"192FB")then
output <= "000";
elsif(from_sine_half= X"207DB")then
output <= "001";
elsif(from_cos_full= X"192FB")then
output <= "010";
elsif(from_cos_half= X"207DB")then
output <= "011";
elsif(from_inv_sine_full= X"192FB")then
output <= "100";
elsif(from_inv_sine_half= X"207DB")then
output <= "101";
elsif(from_inv_cos_full= X"192FB")then
output <= "110";
elsif(from_inv_cos_half= X"207DB")then
output <= "111";
end if;
end process;
end architecture;

MULTIPLIER:

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;

Entity multiplier is
 port(
ip_sample : in std_logic_vector(63 downto 0);
op_sine_full : out std_logic_vector(19 downto 0);
op_Inv_sine_full : out std_logic_vector(19 downto 0);
op_cos_full : out std_logic_vector(19 downto 0);
op_Inv_cos_full : out std_logic_vector(19 downto 0);
op_sine_half : out std_logic_vector(19 downto 0);
op_Inv_sine_half : out std_logic_vector(19 downto 0);
op_cos_half : out std_logic_vector(19 downto 0);
op_Inv_cos_half : out std_logic_vector(19 downto 0)
);
End Entity;

Architecture multiplier of multiplier is

signal inter1 : std_logic_vector(15 downto 0);

signal inter2 : std_logic_vector(15 downto 0);
signal inter3 : std_logic_vector(15 downto 0);
signal inter4 : std_logic_vector(15 downto 0);
signal inter5 : std_logic_vector(15 downto 0);
signal inter6 : std_logic_vector(15 downto 0);
signal inter7 : std_logic_vector(15 downto 0);
signal inter8 : std_logic_vector(15 downto 0);

signal inter_cos1 : std_logic_vector(15 downto 0);

signal inter_cos2 : std_logic_vector(15 downto 0);
signal inter_cos3 : std_logic_vector(15 downto 0);
signal inter_cos4 : std_logic_vector(15 downto 0);
signal inter_cos5 : std_logic_vector(15 downto 0);
signal inter_cos6 : std_logic_vector(15 downto 0);
signal inter_cos7 : std_logic_vector(15 downto 0);
signal inter_cos8 : std_logic_vector(15 downto 0);

signal inter_inv_cos1: std_logic_vector(15 downto 0);

signal inter_inv_cos2: std_logic_vector(15 downto 0);
signal inter_inv_cos3: std_logic_vector(15 downto 0);
signal inter_inv_cos4: std_logic_vector(15 downto 0);
signal inter_inv_cos5: std_logic_vector(15 downto 0);
signal inter_inv_cos6: std_logic_vector(15 downto 0);
signal inter_inv_cos7: std_logic_vector(15 downto 0);
signal inter_inv_cos8: std_logic_vector(15 downto 0);

signal inter_inv_sine1: std_logic_vector(15 downto 0);

signal inter_inv_sine2: std_logic_vector(15 downto 0);
signal inter_inv_sine3: std_logic_vector(15 downto 0);
signal inter_inv_sine4: std_logic_vector(15 downto 0);
signal inter_inv_sine5: std_logic_vector(15 downto 0);
signal inter_inv_sine6: std_logic_vector(15 downto 0);
signal inter_inv_sine7: std_logic_vector(15 downto 0);
signal inter_inv_sine8: std_logic_vector(15 downto 0);

signal inter1_half : std_logic_vector(15 downto 0);

signal inter2_half : std_logic_vector(15 downto 0);
signal inter3_half : std_logic_vector(15 downto 0);
signal inter4_half : std_logic_vector(15 downto 0);
signal inter5_half : std_logic_vector(15 downto 0);
signal inter6_half : std_logic_vector(15 downto 0);
signal inter7_half : std_logic_vector(15 downto 0);
signal inter8_half : std_logic_vector(15 downto 0);

signal inter_cos1_half : std_logic_vector(15 downto 0);

signal inter_cos2_half : std_logic_vector(15 downto 0);
signal inter_cos3_half : std_logic_vector(15 downto 0);
signal inter_cos4_half : std_logic_vector(15 downto 0);
signal inter_cos5_half : std_logic_vector(15 downto 0);
signal inter_cos6_half : std_logic_vector(15 downto 0);
signal inter_cos7_half : std_logic_vector(15 downto 0);
signal inter_cos8_half : std_logic_vector(15 downto 0);

signal inter_inv_cos1_half: std_logic_vector(15 downto 0);

signal inter_inv_cos2_half: std_logic_vector(15 downto 0);
signal inter_inv_cos3_half: std_logic_vector(15 downto 0);
signal inter_inv_cos4_half: std_logic_vector(15 downto 0);
signal inter_inv_cos5_half: std_logic_vector(15 downto 0);
signal inter_inv_cos6_half: std_logic_vector(15 downto 0);
signal inter_inv_cos7_half: std_logic_vector(15 downto 0);
signal inter_inv_cos8_half: std_logic_vector(15 downto 0);

signal inter_inv_sine1_half: std_logic_vector(15 downto 0);

signal inter_inv_sine2_half: std_logic_vector(15 downto 0);
signal inter_inv_sine3_half: std_logic_vector(15 downto 0);
signal inter_inv_sine4_half: std_logic_vector(15 downto 0);
signal inter_inv_sine5_half: std_logic_vector(15 downto 0);
signal inter_inv_sine6_half: std_logic_vector(15 downto 0);
signal inter_inv_sine7_half: std_logic_vector(15 downto 0);
signal inter_inv_sine8_half: std_logic_vector(15 downto 0);

begin

--Multiplier + Adder section For SINE Wave

process(ip_sample)is
begin

inter1 <= ip_sample(63 downto 56)* X"a5";

inter2 <= ip_sample(55 downto 48)* X"80";
inter3 <= ip_sample(47 downto 40)* X"a5";
inter4 <= ip_sample(39 downto 32)* X"00";
inter5 <= ip_sample(31 downto 24)* X"5a";
inter6 <= ip_sample(23 downto 16)* X"7f";
inter7 <= ip_sample(15 downto 8) * X"5a";
inter8 <= ip_sample(7 downto 0) * X"00";

end process;

process(inter1,inter2,inter3,inter4,inter5,inter6,inter7,inter8)is
begin

op_sine_full <=("0000"&inter1)+("0000"&inter2)+("0000"&inter3)+
("0000"&inter4)+("0000"&inter5)+("0000"&inter6)+("0000"&inter7)+
("0000"&inter8);
end process;

--Multiplier + Adder section For COSINE Wave

process(ip_sample)is
begin

inter_cos1 <= ip_sample(63 downto 56)* X"5a";

inter_cos2 <= ip_sample(55 downto 48)* X"00";
inter_cos3 <= ip_sample(47 downto 40)* X"a5";
inter_cos4 <= ip_sample(39 downto 32)* X"80";
inter_cos5 <= ip_sample(31 downto 24)* X"a5";
inter_cos6 <= ip_sample(23 downto 16)* X"00";
inter_cos7 <= ip_sample(15 downto 8) * X"5a";
inter_cos8 <= ip_sample(7 downto 0) * X"7f";

end process;

process(inter_cos1,inter_cos2,inter_cos3,inter_cos4,inter_cos5,inter_cos6,inter_co
s7,inter_cos8)is
begin

op_cos_full <= ("0000"&inter_cos1)+("0000"&inter_cos2)+("0000"&inter_cos3)+

("0000"&inter_cos4)+("0000"&inter_cos5)+("0000"&inter_cos6)+
("0000"&inter_cos7)+("0000"&inter_cos8);
end process;

--Multiplier + Adder section For INV_SINE Wave

process(ip_sample)is
begin

inter_inv_sine1 <= ip_sample(63 downto 56)* X"5a";

inter_inv_sine2 <= ip_sample(55 downto 48)* X"7f";
inter_inv_sine3 <= ip_sample(47 downto 40)* X"5a";
inter_inv_sine4 <= ip_sample(39 downto 32)* X"00";
inter_inv_sine5 <= ip_sample(31 downto 24)* X"a5";
inter_inv_sine6 <= ip_sample(23 downto 16)* X"80";
inter_inv_sine7 <= ip_sample(15 downto 8) * X"a5";
inter_inv_sine8 <= ip_sample(7 downto 0) * X"00";

end process;

process(inter_inv_sine1,inter_inv_sine2,inter_inv_sine3,inter_inv_sine4,inter_inv_
sine5,inter_inv_sine6,inter_inv_sine7,inter_inv_sine8)
begin
op_inv_sine_full <= ("0000"&inter_inv_sine1)+("0000"&inter_inv_sine2)+
("0000"&inter_inv_sine3)+("0000"&inter_inv_sine4)+("0000"&inter_inv_sine5)+
("0000"&inter_inv_sine6)+("0000"&inter_inv_sine7)+("0000"&inter_inv_sine8);
end process;

--Multiplier + Adder section For INV_COSINE Wave

process(ip_sample)
begin

inter_inv_cos1 <= ip_sample(63 downto 56)* X"a5";

inter_inv_cos2 <= ip_sample(55 downto 48)* X"00";
inter_inv_cos3 <= ip_sample(47 downto 40)* X"5a";
inter_inv_cos4 <= ip_sample(39 downto 32)* X"7f";
inter_inv_cos5 <= ip_sample(31 downto 24)* X"5a";
inter_inv_cos6 <= ip_sample(23 downto 16)* X"00";
inter_inv_cos7 <= ip_sample(15 downto 8) * X"a5";
inter_inv_cos8 <= ip_sample(7 downto 0) * X"80";

end process;

process(inter_inv_cos1,inter_inv_cos2,inter_inv_cos3,inter_inv_cos4,inter_inv_co
s5,inter_inv_cos6,inter_inv_cos7,inter_inv_cos8)
begin

op_inv_cos_full <= ("0000"&inter_inv_cos1)+("0000"&inter_inv_cos2)+

("0000"&inter_inv_cos3)+("0000"&inter_inv_cos4)+("0000"&inter_inv_cos5)+
("0000"&inter_inv_cos6)+("0000"&inter_inv_cos7)+("0000"&inter_inv_cos8);
end process;

--Multiplier + Adder section For SINE Wave(HALF)

process(ip_sample)is
begin

inter1_half <= ip_sample(63 downto 56)* X"D2";

inter2_half <= ip_sample(55 downto 48)* X"C0";
inter3_half <= ip_sample(47 downto 40)* X"D2";
inter4_half <= ip_sample(39 downto 32)* X"00";
inter5_half <= ip_sample(31 downto 24)* X"2D";
inter6_half <= ip_sample(23 downto 16)* X"3f";
inter7_half <= ip_sample(15 downto 8) * X"2D";
inter8_half <= ip_sample(7 downto 0) * X"00";

end process;

process(inter1_half,inter2_half,inter3_half,inter4_half,inter5_half,inter6_half,inter
7_half,inter8_half)is
begin

op_sine_half <=("0000"&inter1_half)+("0000"&inter2_half)+
("0000"&inter3_half)+("0000"&inter4_half)+("0000"&inter5_half)+
("0000"&inter6_half)+("0000"&inter7_half)+("0000"&inter8_half);
end process;

--Multiplier + Adder section For COSINE Wave(Half)

process(ip_sample)is
begin

inter_cos1_half <= ip_sample(63 downto 56)* X"2D";

inter_cos2_half <= ip_sample(55 downto 48)* X"00";
inter_cos3_half <= ip_sample(47 downto 40)* X"D2";
inter_cos4_half <= ip_sample(39 downto 32)* X"C0";
inter_cos5_half <= ip_sample(31 downto 24)* X"D2";
inter_cos6_half <= ip_sample(23 downto 16)* X"00";
inter_cos7_half <= ip_sample(15 downto 8) * X"2D";
inter_cos8_half <= ip_sample(7 downto 0) * X"3f";

end process;

process(inter_cos1_half,inter_cos2_half,inter_cos3_half,inter_cos4_half,inter_cos5
_half,inter_cos6_half,inter_cos7_half,inter_cos8_half)is
begin

op_cos_half <= ("0000"&inter_cos1_half)+("0000"&inter_cos2_half)+

("0000"&inter_cos3_half)+("0000"&inter_cos4_half)+("0000"&inter_cos5_half)+
("0000"&inter_cos6_half)+("0000"&inter_cos7_half)+("0000"&inter_cos8_half);
end process;

--Multiplier + Adder section For INV_SINE Wave(Half)

process(ip_sample)is
begin

inter_inv_sine1_half <= ip_sample(63 downto 56)* X"2D";

inter_inv_sine2_half <= ip_sample(55 downto 48)* X"3f";
inter_inv_sine3_half <= ip_sample(47 downto 40)* X"2D";
inter_inv_sine4_half <= ip_sample(39 downto 32)* X"00";
inter_inv_sine5_half <= ip_sample(31 downto 24)* X"D2";
inter_inv_sine6_half <= ip_sample(23 downto 16)* X"C0";
inter_inv_sine7_half <= ip_sample(15 downto 8) * X"D2";
inter_inv_sine8_half <= ip_sample(7 downto 0) * X"00";

end process;

process(inter_inv_sine1_half,inter_inv_sine2_half,inter_inv_sine3_half,inter_inv_s
ine4_half,inter_inv_sine5_half,inter_inv_sine6_half,inter_inv_sine7_half,inter_inv
_sine8_half)
begin

op_inv_sine_half <= ("0000"&inter_inv_sine1_half)+

("0000"&inter_inv_sine2_half)+("0000"&inter_inv_sine3_half)+
("0000"&inter_inv_sine4_half)+("0000"&inter_inv_sine5_half)+
("0000"&inter_inv_sine6_half)+("0000"&inter_inv_sine7_half)+
("0000"&inter_inv_sine8_half);
end process;

--Multiplier + Adder section For INV_COSINE Wave(Half)

process(ip_sample)
begin

inter_inv_cos1_half <= ip_sample(63 downto 56)* X"D2";

inter_inv_cos2_half <= ip_sample(55 downto 48)* X"00";
inter_inv_cos3_half <= ip_sample(47 downto 40)* X"2D";
inter_inv_cos4_half <= ip_sample(39 downto 32)* X"3f";
inter_inv_cos5_half <= ip_sample(31 downto 24)* X"2D";
inter_inv_cos6_half <= ip_sample(23 downto 16)* X"00";
inter_inv_cos7_half <= ip_sample(15 downto 8) * X"D2";
inter_inv_cos8_half <= ip_sample(7 downto 0) * X"C0";
end process;

process(inter_inv_cos1_half,inter_inv_cos2_half,inter_inv_cos3_half,inter_inv_co
s4_half,inter_inv_cos5_half,inter_inv_cos6_half,inter_inv_cos7_half,inter_inv_cos
8_half)
begin

op_inv_cos_half <= (("0000"&inter_inv_cos1_half)+

("0000"&inter_inv_cos2_half)+("0000"&inter_inv_cos3_half)+
("0000"&inter_inv_cos4_half)+("0000"&inter_inv_cos5_half)+
("0000"&inter_inv_cos6_half)+("0000"&inter_inv_cos7_half)+
("0000"&inter_inv_cos8_half));
end process;

end architecture;

ADC:

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;

Entity from_adc is
port(
clk : in std_logic;
rst : in std_logic;
sample : out std_logic_vector(63 downto 0)
 );
End entity;

Architecture from_adc of from_adc is

signal sample_store :std_logic_vector(255 downto 0):=

X"2D00D2C0D2002D3F5a7f5a00a580a500D2002D3F2D00D2C0a580a5005a7f5
a00";
--Cos(Half) --Inv_Sin(Full)
--Inv_cos(Half) --Sine(Full)
signal count : integer;

begin

process(clk,rst)is
variable cnt :integer;
begin
if(rst='0')then
sample <= (others =>'Z');
cnt := -1;

elsif(clk='1' and clk'event)then

if(cnt /= 3)then
cnt := cnt + 1;
else
cnt := cnt;
end if;
end if;
count <= cnt;
end process;

process(count,sample_store)is
begin

case count is

when 0 => sample <= sample_store(63 downto 0);

when 1 => sample <= sample_store(127 downto 64);
when 2 => sample <= sample_store(191 downto 128);
when 3 => sample <= sample_store(255 downto 192);
when others => sample <= (others =>'Z');

end case;

end process;

end architecture;
SIMULATION

OUTPUT

TRANSMITTER SIMULATION WAVEFORM

RECEIVER SIMULATION WAVEFORM
CONCLUSION
BIBILOGRAPHY

BIBILOGRAPHY
 Digital system design using VHDL by Charles Roth.

 www.xilinx.com

 www.fpga4fun.com

 www.vlsi.ee.upatras.com

 www.science101.com