CHINTAN SHUKLA

555 E Washington Ave, #1103W

shuklachintan@yahoo.com
Sunnyvale, CA 94086 (510) 921-0953

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SYNOPSIS
• MS + 2 years of experience in hardware development.
• Strong background in digital design, hardware debugging, design verification and
testing.
• Proficient in power analysis and validation of server chipset.
• Extensive knowledge of Logic Design and Computer Architecture.
• Experience in all phases of product development including design, verification and test.
• In depth knowledge of hardware development concepts, practices and procedures.
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SKILL SET
• Hardware Descriptive Languages: Verilog
• Programming languages: C, Perl
• Digital Design, Simulation and test tools: Cadence Virtuoso (Schematic and Layout
Editor), Synopsys Primetime, ICC (Place and Route), ORCAD (Schematic and Layout
Editor), Xilinx Ise 10.1, Tango, Blizzard (Bin-Split predictor for post silicon), Eden,
Greenstone Debugger, Modelsim, VCS, Verdi/Debussy, Aspen, Vulcan (Power
estimation tool).
• Synthesis Tools: Synopsys Design Compiler.
• Operating Systems: Microsoft Windows, UNIX, Linux.
• Other Skills:
o Extensive experience in technical writing, documentation and presentation.
o Strong organizational and inter-personal skills.
o Excellent problem solving skills and adept in multi-tasking.
o Exceptional team player.
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WORK EXPERIENCE
Intel Corporation, Santa Clara, CA
Position: Power Validation Intern Aug 2008 –
Dec 2009
• Responsible for power validation of all individual blocks for the next generation x86 server
processor.
• Collaborated with RTL design and physical design teams to converge the chip’s power to
meet specification.
• Used benchmarks and generated fsdb dump to get accurate information for estimating
power activity of the signals in RTL.
• Managed the auto-regression environment for tracking power estimates.
• Devised a scan chain insertion plan for data path blocks.
• Performed Formal Equivalence Verification for individual blocks and fixed the discrepancies.
• Enhanced efficiency of detecting mismatches between signal names in RTL and schematic
by writing automation scripts (Perl).
• Performed static timing analysis using internal tool (rali) and estimated the amount of low
leakage cells.
• Estimated the post-silicon die yield for different versions of die using Blizzard.
• Documented reports for signal activity of each block on a biweekly basis.

Achievements: Received Intel Spontaneous Award for getting LLC power test to work.
• Gained the knowledge of design flow: from RTL build to timing fix.
• Implemented test plan methodology for the same.

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NetworkSound Inc, San Jose, CA Feb 2008- May
2008
Position: Hardware Design Intern
• Created schematic design for standard cells used in PCB for audio mixer.
• Performed Place and Route for the standard cells using PADS.
• Created gerber files to be sent in the PCB foundry for production.
• Validated the product functionality using test equipments like oscilloscope.
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Bhavani Labeling Systems, India Dec 2004- Feb
2005
Position: Maintenance Engineer
• Troubleshooting the faults occurring in PCB’s by replacing the RC components of faulty
machines.
• Responsible for monitoring the production line of the customized packaging machines.
• Ordering different parts of the assembly line, after verifying the most efficient and cost
effective parts from vendors.
• Active member of the on-site maintenance team.

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EDUCATION
San Jose State University MS in Electrical Engineering, Dec
2008
Cumulative GPA: 3.7 / 4.0
North Maharashtra University, India BS in Elect. & Communication, Jan
2006
GPA: 3.6/ 4.0
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RELEVANT ACADEMIC PROJECTS
DRAM Using Traditional Threshold logic
• Designed a 256x256 array DRAM using TSMC 0.18u process. It is a single port design which
ran at a maximum frequency of 500Mhz with a supply voltage of 1.8V.
• Designed with the min no. of Drivers used in the decoder by implementing the optimization
in the truth table of the Decoder. Reduction achieved in the no. of drivers was from 256 to
32.
• Sense amplifier was used for sensing the voltage difference on the bit lines and a pass gate
logic mux was used for transitioning the logic from basic array to output.
• Layout was done with min area utilization.
8-Bit ALU
• Designed an 8-bit ALU with IBM 0.13u process and deep sub micron layout rules with a four
phase clocked dynamic logic in.
• Building block is pipelined, and run with a 3.125GHz clock with a 1.2V power supply.
• Constraints like phase time, clock period, pre-charge time , Inverter low to high time,
Inverter high to low time and N-tree time have to be met.
• Circuit design, Timing, Sizing, Verification with the help of test bench, and Layout of the
block was performed using CADENCE VIRTUOSO.
USB 2.0
• Performed a detailed analysis on the USB 2.0 specifications and implemented the whole
design flow using DC-Topo and Synopsys ICC.
• The different implemented blocks are CRC-tx and CRC-rx, Bit stuffing and unstuffing, NRZI
encoder and decoder.
• Performed simulations using VCS simulator.
• The design was synthesized and mapped to TSMC 90nm library .
• This generated netlist was checked for all the critical paths by performing Static Timing
Analysis using Synopsys Primetime tool.
• During the complete flow, extensive use of shell scripting and various data manipulation and
extraction was done using PERL.
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RELEVANT COURSEWORK & CONTENTS
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• ASIC CMOS Design: Flip flops, SRAM, DRAM, Flash memory, FIFO, ALU design, Johnson
counter, Gray code, Binary code, Ripple counter, domino logic, PCI bus, Mealy/Moore finite
state machine.
• Advanced Computer Architecture: DLX pipeline, Static and Dynamic Instruction
scheduling, Data Hazards, Cache, Tomasulo Algorithm, Cache coherence, Forwarding
technique , PCIe and ISA Bus Architecture.
• Design and Test Methodology: Design for testability, BIST, JTAG, IDDQ Testing, Stuck at
fault analysis, Scan chain testing, Boundary scan.
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ACTIVITIES & ACCOLADES

• Active member of IEEE society in SJSU.

• Participated in the name sending contest of the TEMPEL1 comet crash organized by NASA on
a worldwide basis.