Beruflich Dokumente
Kultur Dokumente
171
Winter
2015
Homework
6
Solutions
1. [10]
In
the
communications
scheme
below
three
data
bits
x,y,z
are
transmitted
along
with
a
parity
bit
from
the
source
to
the
destination.
The
data
should
have
odd
parity.
Design
both
the
parity
generator
and
parity
checker
functions.
The
parity
checker
should
output
a
1
if
there
is
a
parity
error.
Use
the
fewest
gates
possible.
You
may
use
only
2-‐input
XOR
and
XNOR
gates.
! 55;!
2. [10]
Design
a
16-‐to-‐1
mux
using
the
fewest
number
of
8x1
and
2x1
multiplexers.
4.65
s0 s0
s1 s1
s2 s2
s3 0 0
1 1
8x1
2 2
MUX
3 3
4 4
5 5
6 6
7 7
s
2x1 y
0
MUX
1
s0
s1
s2
8 0
9 1
8x1
For
full
credit
must
show
select
bits
and
10
11
2
3
MUX
module Mux_2x1 (
output y_out,
input in1, in0, sel);
not (sel_bar, sel);
and (y0, in0, sel);
and (y1, in1, sel);
or (y_out, in0, in1, sel_bar
);
3. [10]
Modify
the
4-‐bit
ripple
carry
adder
below
to
provide
an
overflow
output
signal
if
the
result
is
an
overflow.
Use
an
additional
input
TC
(Twos
Complement)
which
is
1
to
indicate
the
A
and
B
inputs
are
in
twos
complement
representation
(unsigned
binary
if
0).
A3 B3 A2 B2 A1 B1 A0 B0
CI3 CI2 CI1 CI0 = 0
A B CI A B CI A B CI A B CI GND
CO S CO S CO S CO S
CO3 CO2 CO1
CO4 S3 S2 S1 S0
Figure 4.5.6 Modular logic circuit for a 4-bit Adder constructed from four Full Adders.
Sandige,
Alternatively,
you
could
Digital
construct
a
tDesign Essentials,
ruth
table
1e, ©2002, Prentice Hall
for
Overflow(CO3,CO4,TC)
and
obtain
the
minimum
SOP
expression 𝑂𝑣𝑒𝑟𝑓𝑙𝑜𝑤 = 𝐶𝑂3 ∙ 𝐶𝑂4 + 𝑇𝐶 ∙ 𝐶𝑂4 + 𝑇𝐶 ∙ 𝐶𝑂3 ∙ 𝐶𝑂4
and
implement
it
as
a
two-‐level
AND/OR
circuit.
4. [10]
Create
a
table
to
show
the
functionality
of
the
circuit
below.
Hint:
it’s
an
arithmetic
unit.
What
functions
does
it
perform
based
upon
the
inputs?