Yuanxing Li

Tel: 213-400-0766 Address: 1141 W 28 St., Apt 8

Email: yuanxinl@usc.edu Los Angeles, CA, 90007

EDUCATION
University of Southern California, Los Angeles, CA May 2011
Master of Science, Electrical Engineering
Emphasis in Digital System Design and Computer Engineering; GPA: 3.2/4.0
Relevant Coursework: Digital System Design; VLSI System Design; Computer Systems Architecture;
Real Time Computer Systems; Analog and Non-Linear Integrated Circuit Design
Xidian University, Xi’an, China July 2008
Bachelor of Science, Electrical Science & Technology
Emphasis in Electrical Materials; GPA: 86/100

SKILLS
Programming: VHDL, Verilog, C/C++, Perl, TCL Script, Matlab, HTML.
CAD/EDA Tools: ModelSim, Cadence Virtuoso, Hspice, Xilinx ISE, LTspice, Cacti,etc.
Operating System: Win7/Vista/XP, UNIX.
Languages: Chinese Mandarin (native), English (Fluent), Japanese (entry level).

PROJECT EXPERENCE

Tomasulo Out of Order CPU (VHDL, Xilinx ISE, NEXYS 2 board)

• Designed and implemented Out of Order CPU based on classic Tomasulo architecture.
• Solved the dependency and prediction problems for OoO structure, improved the CPU throughput.
• Tested the synthesized CPU on Digilent NEXYS 2 board with 10+ selected instruction streams.
DDR2 DRAM Controller (Verilog, NC-Verilog, TCL script, Synopsis Design Compiler, Prime time)
• Designed a controller for Micron 512MB DDR2 module. Supporting scalar, block transaction.
• The code was synthesized using Synopsis Design Compiler with the help of TCL script.
• Tested with post synthesis simulation and primetime analysis.
MIPS architecture 5 stage pipeline CPU (Verilog, ePD)
• Designed a 5 stage Pipeline MIPS CPU with forwarding, stall and branch prediction mechanism.
• Tested it with instruction streams covering WAR, RAW, WAW hazards, prediction trace back, etc.
16 bit RCA/CLA Full Adder, 32 bit Multiplier, SDRAM Cell (layout, Cadence Virtuoso)
• Designed schematics and layouts with Cadence Virtuoso.
• Stroke the best Delay/Area product design according to the simulation result.
Low-Voltage, Low-Power, High-Speed High-Gain CMOS Operational Amplifier (LTspice)
• Designed and simulated schematics with LTspice.
Digital Neuron (Cadence Virtuoso, Hspice)
• Designed schematics and layouts with Cadence Virtuoso.
• Delay/Area analyzing according to the Hspice simulation result.

WORK EXPERENCE
Shaanxi University of Science & Technology, Xi’an, China 2008-2009
Research Assistant
• Assisted Prof. Shi on computer simulation technology data analyzing.
• Assisted in calculating research of Nano composites surface characterization.
Xidian University, Xi’an, China 2007-2008
Research Assistant
• Developed and improved projects on basic logic design with Verilog.