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• Terminology
• Specification and Design Details of a Series-210 DMD
• Series 210 System Reference Design concept, including key attributes and important design
considerations
• System connector
2.0 Terminology
The primary features of the Series 210 DMD are illustrated in the Figure 1
• WLP Chip – Wafer level package DMD chip which contains the DMD active array
• DMD Active Array – The array of active DMD mirrors
• Window glass – Clear glass cover that protects the DMD active area
• Frame – part used to cover and protect the wire bond wires
• Ceramic – the main support structure of the DMD for the mechanical datums and electrical
interface
• System Connector – the electrical interface connector in the system
• DMD Test Pads – electrical interface pads used for testing at Texas Instruments
Ensure the LGA pads are not directly or inadvertently connected or shorted by a
mounting plate or something that would short the pads together or connect them to
ground. The DMD data sheet identifies the BTB connector pins and signal names.
Figure 3 illustrates the electrical interface features.
The absolute minimum and maximum operating temperatures apply to both the
measurement point (TC3) and the active array. A summary of the minimum and
maximum temperatures is shown in Table 2.
The array temperature can not be measured directly but must be computed analytically
from information in the DMD data sheet, the thermocouple measurement (see TC3 in
Figure 4), and the thermal load absorbed from the illumination energy. The relationship
to calculate the array temperature from the reference ceramic temperature (TC3) is
shown in the DMD data sheet and below. The thermal resistance (R Array-To-Ceramic) from
the array to the ceramic measurement point (TC3) is 5 oC/W (see data sheet).
The thermal load on the DMD results from the DMD electrical power, and the absorbed
energy from the optical illumination. The electrical load is defined in the DMD data
sheet as 0.075 watts. The absorbed energy from the optical load will need to be
determined for the specific application.
Where:
TArray = computed array temperature (°C)
TCeramic = measured ceramic temperature (°C) (TC3 location in DMD data sheet)
Q ELE = Nominal electrical power = 0.075 watts (from DMD data sheet)
The Series 210 DMD does not have a specifically defined thermal contact area to aid in
conducting the thermal load from the DMD. For this reason the typical application for
the Series 210 DMD would be for an absorbed illumination load less than 0.055 watts.
This load is expected to be distributed across the entire active array. For a display
application this would be less than 20 lumens measured on the screen, or about 40
lumens of illumination directly on the DMD.
The amount of energy can vary over time with many illumination sources so it is
important to verify the amount of illumination energy when verifying the thermal design
of an application each time a temperature measurement is taken.
The DMD is characterized for an illumination load which is distributed across the active
array. Applications with illumination that has high energy density (for example, highly
collimated laser beams) have not been characterized and need to be investigated for
the specific illumination source and application.
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Copyright © 2009 Texas Instruments Incorporated
8
3.4.2 Sample Array Calculation for a 1-Chip Display Application
For a typical 1-Chip display application with a total projection efficiency from the DMD
to the screen of 87% the illumination heat load is 0.00274 times the measured screen
lumens. This assumes a spectral efficiency of 300 lumens/watt for the projected light
and illumination distribution of 83.7% on the active array and 16.3% on the array border
and window aperture. An example of the array temperature calculation for a display
application is shown below.
Q ILL = 0.00274 • SL
Where:
TArray = computed array temperature (°C)
TCeramic = measured ceramic temperature (°C) (TC3 location in DMD data sheet)
Q ELE = Nominal electrical power = 0.075 watts (from DMD data sheet)
Loads in excess of the specified limits can result in mechanical failure of the DMD package.
The functional design objectives of the mounting system include the following:
• Establish (and maintain) the physical placement of the DMD’s Active Array relative to
the optical system.
• Establish (and maintain) a low electrical impedance connection between the DMD’s
Electrical Interface and the system connector on the flex or printed circuit board.
• Establish (and maintain) a dust-proof seal between the DMD and the optical chassis.
The system reference design presented in this Application Note achieves the design
objectives listed above.
The simplest form for the Datum ‘B’ interface is a precision 1.5 mm diameter pin. However,
other shapes could be used to create a more robust feature that would be easier to
manufacture. An example is shown in Figure 6 above.
To avoid bending and damaging the DMD ceramic package the mounting forces should be
applied perpendicular to the substrate and directly opposite the ceramic Datum ‘A’ areas.
The optical chassis features that contact the DMD Datum ‘B’ and Datum ‘C’ should be lower
in height than the ceramic thickness and associated tolerance. The lower height will prevent
interference with the mating connector or supporting parts associated with it. This clearance
is illustrated in Figure 7.
The three Datum ‘A’ tabs need to be coplanar to ensure uniform focus of the array and
repeatability between systems. The coplanar requirements are established by the depth of
focus of the specific optical design.
This concept represents a “drop-in-place“ design where the DMD is not adjusted during or
after assembly for optical alignment. This simplifies the assembly of the DMD to the optics
but does require adequate tolerances between the optical chassis features for mounting the
DMD and other optical components to ensure proper optical performance. The tolerance
requirements will vary for each specific optical design but the capability of manufacturing the
parts needs to be considered when doing the optical design. The key areas for
consideration are the alignment of the illumination to the array, the amount of overfill, and
the focus across the array.
This concept utilizes the fourth tab and threaded boss described previously for strength and
better shock resistance. The optical interface includes typical features for mounting and
securing the DMD to the optics chassis. The clamp is used to secure the Datum ‘A’ and
Datum ‘B’ of the DMD to the corresponding features on the optics chassis. Control of loads
on the DMD are heavily dependant on the assembly process rather than the specifics of
design parts or features.
The clamp design has raised areas which correspond to areas on the side of the DMD
ceramic opposite the Datum ‘A’ areas. The raised areas are shown in Figure 12. The use
of the raised areas helps to ensure the mounting load is applied to the Datum ‘A’ areas of
the DMD. The selection of the material and finish of the clamp should be such that the LGA
pads are not electrically connected or shorted together.
This mounting concept design is simple and has the fewest number of parts. This concept
does not include a flexible feature or compliant part like a coil spring to absorb the part
manufacturing variations or tolerances. When installing the DMD to the optical chassis
using the 4 screws into the optics threaded bosses, ensure the loads applied to the DMD by
tightening the screws do not exceed the DMD specification. The control of the loads applied
to the DMD must be done by a combination of part tolerances and assembly processes. A
summary of these is below:
• Partial tighten all 4 screws prior to final tightening
• Controlling the maximum torque on the screws in the threaded bosses
• Use alternating order when tightening the screws for both partial and final torque
• Tolerance the critical dimension on the optical interface and clamp to minimize the gap
between the threaded boss and the clamp. This gap is illustrated in the Figure 12.
This concept is an example of mounting the DMD. Specific requirements like size or other
geometry configuration associated with a specific implementation may require alternate
designs for a final product. Space available and the control of the loads on the DMD are
critical considerations.