DOC/LP/01/28.02.

02

LESSON PLAN LP – EC1401

Sub Code/Name: EC1401 - VLSI DESIGN LP Rev. No: 01
Unit : I Branch : EC Semester: VII Date: 29/06/09
Page 01 of 06

UNIT I CMOS TECHNOLOGY 9

Syllabus:
An overview of Silicon semiconductor technology, Basic CMOS technology:
n well, P well, Twin tub and SOI Process. Interconnects, circuit elements:
Resistors, capacitors, electrically alterable ROMs, bipolar transistors, Latch up
and prevention.
Layout design rules, physical design: basic concepts, CAD tool sets, physical
design of logic gates: Inverter, NAND, NOR, Design Hierarchies.
. Objective:
To understand the various CMOS technologies and the Layout design rules
Session Teachin
No. Topics to be covered Time Ref Method

10. Overview of Silicon semiconductor technology 50m 1,3,4,7 BB

11 Fabrication of NMOS 50m 1,3,4,7 BB
12 CMOS technology : nwell, P well 50m 1 BB
13 Twin tub and SOI Process 50m 1 BB
14 Interconnects, circuit elements: Resistors, 50m 1 BB
capacitors,
15 Electrically alterable ROMs, Bipolar transistors 50m 1 BB
16 Latch up and prevention 50m 1 BB

17 Layout design rules 50m 1,4,7 BB

18 Physical design: basic concepts , CAD tool sets 50m 1,4,7 BB

19 Physical design of logic gates: Inverter ,.NAND, 50m 1,2,7 BB

NOR, Design Hierarchies
20 CAT
 DOC/LP/01/28.02.02

LESSON PLAN LP – EC1401

Sub Code/Name: EC1401 - VLSI DESIGN LP Rev. No: 01
Unit : II Branch : EC Semester: VII Date: 29/06/09
Page 02 of 06

UNIT II MOS TRANSISTOR THEORY

9
Syllabus:
NMOS, PMOS Enhancement transistor, Threshold voltage, Body effect, MOS
DC equations, channel length modulation, Mobility variation, MOS models,
small signal AC characteristics, complementary CMOS inverter DC
characteristics, Noise Margin, Rise time, fall time, power dissipation,
transmission gate, tristate inverter.

Objective:
 To comprehend the MOS and CMOS transistor theory
Session Topics to be covered Time Ref Teachin
No. Method
1 NMOS, PMOS Enhancement transistor 50m 1,3,4 BB
2 MOS DC equations 50m 1,4 BB
3 Threshold voltage, Body effect, channel length 50m 1,4 BB
modulation
4 Mobility variation, MOS models 50m 1 BB
5 Small signal AC characteristics, CMOS inverter 50m 1 BB
DC characteristics
6 CMOS Inverter DC characteristics 50m 1 BB
7 Noise Margin, Rise time, fall time 50m 1 BB
8 Power dissipation, transmission gate 50m 1,7 BB
9 Tristate inverter 50m 1 BB
 DOC/LP/01/28.02.02

LESSON PLAN LP – EC1401

SubCode/Name EC1401 - VLSI DESIGN LP Rev. No: 01
Unit : III Branch : EC Semester: VII Date: 29/06/09
Page 03 of 06

UNIT III SPECIFICATION USING VERILOG HDL 9

9
Syllabus:
Basic Concepts: VLSI Design flow, identifiers, gate primitives, value set, ports, gate delays,
structural gate level and switch level modeling, Design hierarchies, Behavioral and RTL
modeling: Operators, timing controls, Procedural assignments conditional statements, Data
flow modeling and RTL.
Structural gate level description of decoder, equality detector, comparator, priority encoder,
D-latch, D-ff, half adder, Full adder, Ripple Carry adder.

Objective:
 To understand the concepts of modeling a digital system using Hardware
Description Language.

Session Topics to be covered Time Ref Teaching

No. Method
21. VLSI Design flow, identifiers, gate primitives 50m 2,6 BB
22. Value set, ports, gate delays 50m 2,6 BB
23. Structural gate level modeling 50m 2,6 BB
24. Switch level modeling 50m 2,6 BB
25. Design hierarchies, Behavioral and RTL 50m 2,6 BB
modeling: Operators
26. Timing controls, Procedural assignments 50m 2,6 BB
27. Conditional statements, Data flow modeling 50m 2,6 BB
and RTL
28. Structural gate level description of decoder, 50m 2,6 BB
equality detector, comparator
29. Priority encoder, D-latch, D-ff, Half adder, 50m 2,6 BB
Full adder, Ripple Carry adder.
 DOC/LP/01/28.02.02

LESSON PLAN LP – EC1401

Sub Code/Name: EC1401 - VLSI DESIGN LP Rev. No: 01
Date:29/06/09
Unit : IV Branch : EC Semester: VII Page 04 of 06

UNIT IV CMOS CHIP DESIGN 9

Syllabus:
Logic design with CMOS: MOSFETS as switches, Basic logic gates in CMOS, Complex
logic gates, Transmission gates: Muxes and latches, CMOS chip design options: Full custom
ASICs, Std. Cell based ASICs, Gate Array based ASICs Channelled, Channelless and
structured GA, Programmable logic structures; 22V10, Programming of PALs,
Programmable Interconnect, Reprogrammable GA: Xilinx programmable GA, ASIC design
flow.
Objective: To Understand the concepts of designing VLSI subsystems and the chip design
using programmable devices

Session Topics to be covered Time Ref Teaching

No. Method
30. MOSFETS as switches, Basic logic gates in 50m 1 BB
CMOS
31. Complex logic gates, Transmission gates: Muxes 50m 1,7 BB
and latches
32. Full custom ASIC, Std. Cell based ASIC, Gate 50m 1,3 BB
Array based ASIC
33. Channeled, Channel less and structured GA 50m 1,3 BB
34. Programmable logic structures: 22V10, 50m 1 BB
Programming of PALs
35. Programmable Interconnect 50m 1 BB

36. Xilinx programmable GA 50m 1 BB

37. ASIC design flow 50m 3 BB
38 CAT-II
 DOC/LP/01/28.02.02

LESSON PLAN LP – EC1401

SubCode/Name: EC1401 - VLSI DESIGN LP Rev. No: 01
Unit : V Branch : EC Date:29/06/09
Semester: VII Page 05 of 06

UNIT V CMOS TESTING 9

Syllabus:

Need for testing, manufacturing test principles, Design strategies for test, Chip level and
system level test techniques

Objective:
To understand the the concepts of CMOS testing

Session Topics to be covered Time Ref Teachin

No. Method
39. Need for testing 50m 1 BB
40. Manufacturing test principles 150m 1 BB
43. Design strategies for test 150m 1 BB
46.Chip Chip level test techniques 50m 1 BB

47 System level test techniques 50m 1 BB

48 CAT-III
 DOC/LP/01/28.02.02

LESSON PLAN LP – EC1401

SubCode/Name: EC1401 - VLSI DESIGN LP Rev. No: 01
Date:29/06/09
Branch : EC Semester: VII Page 06 of 06

Course Delivery Plan:

1 2 3 4 5 6 7 8 9 10 11 12 13 14
Week
I II I II I II I II I II I II I II I II I II I II I II I II I II I II
                       
Units

TEXT BOOKS:
1. Weste & Eshraghian: Principles of CMOS VLSI design (2/e) Addison
Wesley, 1993 for UNIT I through UNIT IV.
2. Samir Palnitkar; Verilog HDL - Guide to Digital design and synthesis, III
edition, Pearson Education, 2003 for UNIT V

REFERENCES:
3. M.J.S.Smith : Application Specific integrated circuits, Pearson Education,
1997.
4. Wayne Wolf, Modern VLSI Design, Pearson Education 2003.
5. Bob Zeidmin ; Introduction to verilog, Prentice Hall, 1999
6. J . Bhaskar : Verilog HDL Primer, BSP, 2002.
7. E. Fabricious , Introduction to VLSI design, McGraw-Hill 1990.
8. C. Roth, Digital Systems Design Using VHDL, Thomson Learning, 2000.

Prepared by Approved by
Name D.DHANASEKARAN / DR R.AMUTHA
M.ANUSHYA
Designation Asst- professor/ Lecturer HOD, Department of EC
Date