DIGITAL VOLTMETERS

Advantages of Digital Voltmeter

The DVMs have number of advantages over conventional analog voltmeters, which
1. Due to the digital display, the human reading errors, interpolation errors and parallax errors are
reduced.
2. They have input range from +1.000 V to +1000 V with the automatic range selection and the
overload indication.
3. The accuracy is high upto ± 0.005 % of the reading.
4. The resolution is better as 1µV reading can be measured on 1 V range.
5. The input Impedance is as high as 10 MΩ.
6. The reading speed is very high due to digital display.
7. They can be programmed and well suited for computerized control
8. The output in digital form can be directly recorded and it is suitable for further processing also.
9. With the development of IC chips, the cost of DVMs, size and power requirements of DVMs are
drastically reduced.
10. Due to small size, they are portable.
11. The internal calibration does not depend on the measuring circuit.
12. The BCD output can be printed or used for digital processing.
13. The inclusion of additional circuitry make them suitable for the measurement of quantities like
current, impedance, capacitance, temperature.

Basic Block Diagram of DVM

Any digital instrument requires analog to digital converter at its input Hence first block in a general
DVM Is ADC as shown In the Fig. 3.1.

Fig. 3.1 Bask block diagram of DVM

Every ADC requires a reference. The reference is generated internally and reference generator
circuitry depends on the type of ADC technique used. The output of ADC is decoded and signal is
processed in the decoding stage. Such a decoding is necessary to drive the seven segment display.
The data from decoder is then transmitted to the display. The data transmission element may be a
latches, counters etc. as per the requirement A digital display shows the necessary digital result of the
measurement.

Classification of Digital Voltmeter

The digital voltmeters are classified mainly based on the technique used for the ADC.
Depending on this, digital voltmeters are mainly classified as,
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 I) NON-INTEGRATING TYPE II) INTEGRATING TYPE
Non – integrating type digital voltmeter are further classified as
a) Potentiometric type: These are sub classified as,
1. Successive approximation type
2. Null balance type
b) Ramp type

Integrating type digital voltmeter are further classified as

a) Voltage to frequency converter type
b) Dual slope integrating type

Ramp Type DVM

It uses a linear ramp technique or staircase ramp technique. The staircase ramp technique is simpler
than the linear ramp technique.
Linear Ramp Technique
The basic principle of such measurement is based on the measurement of the time taken by a linear
ramp to rise from OV to the level of the input voltage or to decrease the level of the input voltage to
zero. This time Is measured with the help of electronic time interval counter and the count is
displayed in the numeric form with the of a digital display.

Fig: 3.2 Voltage to Time conversion

Basically it consists of a linear ramp which is positive going or negative going. The range of the ramp
is ±12 V while the base range is ±10 V. The conversion from a voltage to a time interval is shown in
the Fig. 3.2.
At the start of measurement, a ramp voltage is initiated which Is continuously compared with the
input voltage. When these two voltages are same, the comparator generates a pulse which opens a
gate I.e. the Input comparator generates a start pulse. The ramp continues to decrease and finally
reaches to 0 V or ground potential. This is sensed by the second comparator or ground comparator. At
exactly 0 V, this comparator produces a stop pulse which closes the gate. The number of clock pulses
is measured by the counter. Thus the time duration for which the gate is opened, is proportional to the

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input voltage. In the time interval between start and stop pulses, the gate remains open and the
oscillator circuit drives the counter. The magnitude of the count indicates the magnitude of the input
voltage, which is displayed by the display. The block diagram of linear ramp DVM is shown in the
Fig. 3.3.

Fig: 3.3 Linear ramp type DVM

Properly attenuated input signal is applied as one input to the input comparator. The ramp
generator generates the proper linear ramp signal which is applied to both the comparators. Initially
the logic circuit sends a reset signal to the counter and the readout. The comparators are designed in
such a way that when both the input signals of comparator are equal then only the comparator
changes its state The input comparator is used to send the start pulse while the ground comparator Is
used to send the stop pulse.
When the input and ramp are applied to the input comparator, and at the point when negative going
ramp becomes equal to input voltages the comparator sends start pulse, due to which gate opens. The
oscillator drives the counter. The counter starts counting the pulses received from the oscillator. Now
the same ramp is applied to the ground comparator and it is decreasing. Thus when ramp becomes
zero, both the inputs of ground comparator becomes zero (grounded) I.e. equal and It sends a stop
pulse to the gate due to which gate gets closed. Thus the counter stops receiving the pulses from the
local oscillator. A definite number of pulses will be counted by the counter, during the start and stop
pulses which is measure of the input voltage. This Is displayed by the digital readout.
The advantages of this technique are:
i) The circuit is easy to design.
ii) The cost is low.
iii) The output pulse can be transferred over long feeder lines without loss of information.
iv) The input signal is converted to time, which is easy to digitise.
v) By adding external logic, the polarity of the input also can be displayed.
vi) The resolution of the readout is directly proportional to the frequency of the local oscillator. So
adjusting the frequency of the local oscillator, better resolution can be obtained.
The disadvantages of this technique are:

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i) The ramp requires excellent characteristics regarding its linearity.
ii) The accuracy depends on slope of the ramp and stability of the local oscillator.
iii) Large errors are possible if noise is superimposed on the input signal.
iv) The offsets and drifts in the two comparators may cause errors.
v) The speed of measurement is low.
vi) The awing of the ramp is ± 12 V, this limits the base range of measurement to ± 10 V.

DUAL SLOPE INTEGRATING TYPE DVM (voltage to time conversion)

In ramp techniques, superimposed noise can cause large errors. In the dual ramp technique, noise is
averaged out by the positive and negative ramps using the process of integration.
Principle of Dual Slope Type DVM As illustrated in Fig. 3.4, the input voltage ‘ei’ is integrated, with
the slope of the integrator output proportional to the test input voltage. After a fixed time, equal to 11
the input voltage is disconnected and the integrator input is connected to a negative voltage -er. The
integrator output will have a negative slope which is constant and proportional to the magnitude of
the input voltage. The block diagram is given in Fig. 3.5.

Fig 3.4: Basic principle of dual slope type DVM

Fig 3.5: Block diagram of dual slope type DVM

At the start a pulse resets the counter and the F/F output to logic level ‘0’. S, is closed and Sr is open.
The capacitor begins to charge. As soon as the integrator output exceeds zero, the comparator output
voltage changes state, which opens the gate so that the oscillator clock pulses are fed to the counter.

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(When the ramp voltage starts, the comparator goes to state 1, the gate opens and clock pulse drives
the counter.) When the counter reaches maximum count, i.e. the counter is made to run for a time ‘ti’
in this case 9999, on the next clock pulse all digits go to 0000 and the counter activates the F/F to
logic level ‘I’. This activates the switch drive, e is disconnected and —e1. is connected to the
integrator. The integrator output will have a negative slope which is constant, i.e. integrator output
now decreases linearly to 0 volts. Comparator output state changes again and locks the gate. The
discharge time r, is now proportional to the input voltage. The counter indicates the count during time
When the negative slope of the integrator reaches zero, the comparator switches to state 0 and the
gate closes. i.e. the capacitor C is now discharged with a constant slope. As soon as the comparator
input (zero detector) finds that e, is zero, the counter is stopped. The pulses counted by the counter
thus have a direct relation with the input voltage.

During charging

------ (1)

------ (2)
(2)- (1)

The dual slope technique has excellent noise rejection because noise superimposed ac is averaged
out in the process of integration. The speed accuracy are readily varied according to specific
requirements; also an accuracy of± 0.05% in 100 ms is available.

A constant input voltage is integrated and the slope of the output ramp proportional to the input
voltage. When the output reaches a certain value, is discharged to 0 and another cycle begins. The
frequency of the output waveform is proportional to the voltage. The block diagram is illustrated in
fig. 3.6
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 Fig: 3.6 Block diagram of integrating type DVM

The input voltage produces a charging current, ei/R1 that charges the capacitor ‘C’ to the reference
voltage er. When er is reached, the comparator changes state, so as to trigger the precision pulse
generator. The pulse generator produces a pulse of precision charge content that rapidly discharges
the capacitor. The rate of charging and discharging produces a signal frequency that is directly
proportional to ei.

The output frequency is proportional to the input voltage ei. This DVM has the disadvantage that it
requires excellent characteristics in linearity of the ramp. The ac noise and supply noise are averaged
out.

SUCCESSIVE APPROXIMATIONS
The successive approximation principle can be easily understood using a simple example: the
determination of the weight of an object. By using a balance and placing the object on one side and
an approximate weight on the other side, the weight of the object is determined. If the weight placed
is more than the unknown weight, the weight is removed and another weight of smaller value is
placed and again the measurement is performed. Now if it is found that the weight placed is less than
that of the object, another weight of smaller value is added to the weight already present, and the
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measurement is performed. If it is found to be greater than the unknown weight the added weight is
removed and another weight of smaller value is added. In this manner by adding and removing the
appropriate weight, the weight of the unknown object is determined. The successive approximation
DVM works on the same principle.

When the start pulse signal activates the control circuit, the successive approximation register (SAR)
is cleared. The output of the SAR is 00000000. Vout of the D/A converter is 0. Now, if Vin> Vout
the comparator output is positive. During the first clock pulse, the control circuit sets the D7 to 1, and
Vout jumps to the half reference voltage. The SAR output is 10000000. If Vout is greater than Vin,
the comparator output is negative and the control circuit resets D7. However, if Vin, is greater than
Vout, the comparator output is positive and the control circuits keeps D7 set. Similarly the rest of the
bits beginning from D7 to D0 arc set and tested. Therefore, the measurement is completed in 8 clock
pulses.

Fig 3.7 Block diagram of Successive approximation DVM

When D7 set = Vref *(D7) = 5(1/2)= 2.5; Vin<Vout; D7 reset. 10000000

When D6 set = Vref * (D6) = 5(1/4)= 1.25; Vin<Vout; D6 reset. 01000000
When D5 set = Vref * (D5) = 5(1/8)= 0.625; Vin>Vout; D5 set. 00100000
When D4 set = Vref * (D5+D4) = 5(1/8+1/16)= 0.9375; Vin>Vout; D4 set. 00110000
When D3 set = Vref * (D5+D4+D3) = 5(1/8+1/16+/32)= 1.93; Vin<Vout; D3 reset. 00111000
When D2 set = Vref * (D5+D4+D2) = 5(1/8+1/16+/64)= 1.015; Vin<Vout; D2 reset. 00110100

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At the beginning of the measurement cycle, a start pulse is applied to the start-stop multivibrator.
This sets a 1 in the MSB of the control register and a 0 in all bits (assuming an 8-bit control) its
reading would be 10000000. This initial setting of the register causes the output of the DAC
converter to be half the Reference voltage, i.e. 1/2 V. This converter output is compared to the
unknown input by the comparator. If the input voltage is greater than the converter reference voltage,
the comparator output produces an output that causes the control register to retain the 1 setting in its
MSB and the converter continues to supply its reference output voltage of 1/2 Vref.
The ring counter then advances one count, shifting a I in the second MSB of the control register and
its reading becomes 11000000. This causes the D/A converter to increase its reference output by 1
increment to 1/4 V, i.e. 1/2 V + 1/4 V. and again it is compared with the unknown input. If in this
case the total reference voltage exceeds the unknown voltage, the comparator produces an output that
causes the control register to reset its second MSB to 0. The converter output then returns to its
previous value of 1/2 V and awaits another input from the SAR. When the ring counter advances by
1, the third MSB is set to 1 and the converter output rises by the next increment of 1/2 V + 1/8 V.

Principle of Operation: The signal waveform is converted to trigger pulses and applied continuously
to an AND gate, as shown in Fig. 3.9. A pulse of 1s is applied to the other terminal, and the number
of pulses counted during this period indicates the frequency. The signal whose frequency is to be
measured is converted into a train of pulses, one pulse for each cycle of the signal. The number of
pulses occurring in a definite interval of time is then counted by an electronic counter. Since each
pulse represents the cycle of the unknown signal, the number of counts is a direct indication of the
frequency of the signal (unknown). Since electronic counters have a high speed of operation, high
frequency signals can be measured.

Fig: 3.9 Principle of digital frequency

The block diagram of a basic circuit of a digital frequency meter is shown in Fig. 3.10

Fig: 3.10 Basic circuit of digital frequency meter

The signal may be amplified before being applied to the Schmitt trigger. The Schmitt trigger converts
the input signal into a square wave with fast rise and fall times, which is then differentiated and
clipped. As a result, the output from the Schmitt trigger is a train of pulses, one pulse for each cycle
of the signal.
The output pulses from the Schmitt trigger are fed to a START/STOP gate. When this gate is
enabled, the input pulses pass through this gate and are fed directly to the electronic counter, which
counts the number of pulses.
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When this gate is disabled, the counter stops counting the incoming pulses. The counter displays the
number of pulses that have passed through it in the time interval between start and stop. If this
interval is known, the unknown frequency can be measured.

The basic circuit for frequency measurement is as shown in Fig. 3.10. The output of thc unknown
frequency is applied to a Schmitt trigger, producing positive pulses at the output. These pulses are
called the counter signals and are present at point A of the main gate. Positive pulses from the time
base selector are present at point B of the START gate and at point B of the STOP gate.

Fig: 3.10 Basic circuit of digital frequency meter using gate control F/F

Initially the Flip-Flop (F/F- 1) is at its logic 1 state. The resulting voltage from output Y is applied to
point A of the STOP gate and enables this gate. The logic o stage at the output F of the F/F-1 is
applied to the input A of the START gate and disables the gate. As the STOP gate is enabled, the
positive pulses from the time base pass through the STOP gate to the Set (S) input of the FIF—2
thereby setting F/F—2 to the 1 state and keeping it there. The resulting 0 output level from F of F/F—
2 is applied to terminal B of the main gate. Hence no pulses from the unknown frequency source can
pass through the main gate.

In order to start the operation, a positive pulse is applied to (read input) reset input of F/F-1, thereby
causing its state to change. Hence = 1, Y = 0, and as a result the STOP gate is disabled and the
START gate enabled. This same read pulse is simultaneously applied to the reset input of all decade
counters, so that they are reset to 0 and the counting can start. When the next pulse from the time base
arrives, it is able to pass through the START gate to reset F/F—2, therefore, the F/F—2 output
changes state from 0 to 1, hence F changes from 0 to 1. This resulting positive voltage from F called
the gating signal, is applied to input B of the main gate thereby enabling the gate.
Now the pulses from the unknown frequency source pass through the main gate to the counter and the
counter starts counting. This same pulse from the START gate is applied to the set input of F/F—1,
changing its state from 0 to 1. This disables the START gate and enables the STOP gate. However,
till the main gate is enabled, pulses from the unknown frequency continue to pass through the main
gate to the counter.
The next pulse from the time base selector passes through the enabled STOP gate to the set input
terminal of F/F—2, changing its output back to 1 and = 0. Therefore the main gate is disabled,
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disconnecting the unknown frequency signal from the counter. The counter counts the number of
pulses occurring between two successive pulses from the time base selector. If the time interval
between this two successive pulses from the time base selector is 1 second, then the number of pulses
counted within this interval is the frequency of the unknown frequency source, in Hertz.
The assembly consisting of two F/Fs and two gates is called a gate control F/F. The block diagram of
a digital frequency meter is shown in Fig. 3.11.

Fig. 3.11 Block diagram of digital frequency meter

Microprocessor Based Ramp Type DVM:

A basic block diagram of a Microprocessor Based Ramp Type DVM and its operating waveform is
shown in Fig. (a) and (b) respectively. Depending on the command fed to the control input of the
multiplexer by the microprocessor, input 1 of the comparator can be consecutively connected to the
input 1, 2 or 3 of the multiplexer.
The multiplexer has three inputs — input 1 is connected to ground potential, input 2 is the unknown
input, and input 3 is the reference voltage input. The comparator has two inputs — input 1 accepts the
output signal from the multiplexer and input 2 accepts the ramp voltage from the ramp generator.
The microprocessor remains suspended in the resting state until it receives a command to start
conversion. During the resting period, it regularly sends reset signals to the ramp generator. Each
time the ramp generator is reset, its capacitor discharges. It produces a ramp, i.e. a sawtooth voltage
whose duration, Tr and amplitude, Vm remain constant. The time duration between the consecutive
pulses is sufficiently large enough for the capacitor to get discharged.
Whenever a conversion command arrives at the microprocessor at a time tl, the multiplexer first
connects input 1 of the comparator to its input 1 (i.e. ground potential) and brings the former to
ground potential.
The microprocessor pauses until another saw tooth pulse begins. When input 2 voltage, arriving from
the ramp generator becomes equal to equal to input 1 of the comparator, the comparator sends a
signal to the microprocessor, that ramp voltage is zero. The microprocessor measures this time
interval Δt1 (shown in Fig. (b)), by counting the number of clock pulses supplied by the clock
generator during this time interval. Let the count during this time be N1, which is then stored by the
microprocessor. A command from the microprocessor now causes the comparator input 1 to be
connected to input 2 of the multiplexer. This connects the unknown voltage, V x to the input 1 of the
comparator. At an instant, when the ramp voltage equals the unknown voltage, the comparator sends

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a signal to the microprocessor the measure the time interval Δt2 (Fig. (b)). The count N2, during this
time interval is also stored.

Now, the next command from the microprocessor causes the comparator input 1 to be connected to
the input 3 of the multiplexer, which is the reference voltage (full scale voltage). The value of the
reference voltage sets the upper limit of measurement, that is, full scale value. At the instant, when
the ramp voltage equals the reference voltage, a pulse is sent to the microprocessor from the
comparator output to measure this time interval, Δt3 (Fig (b)). The count, N3 during this time interval
is also stored.

The microprocessor then computes the unknown voltage Vx by the equation

where C is the coefficient dependent on the characteristics of the instrument and the units selected to
express the result.
Hence from the Fig. (b),

Since the clock pulse repetition frequency fc and full scale voltage Vfs, are maintained at a very high
level of stability and clock pulses allowed to fall within all the time intervals come from a common
source, the above equation may be rewritten as
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where N1, N2, N3 are the counts representing respectively, the zero drift, the unknown voltage, and
the full scale voltage.
Advantages
1. Its scale size remains constant due to zero drift correction and maximum.
2. The accuracy of the instrument is not affected by the time and temperature instabilities of the
circuit element values.
3. There is a good repeatability in switching instants in the presence of noise and interference.
This is because the ramp approaches the point at which the comparator operates always the
same side and always the same rate.
Disadvantages
1. Noise and interference cannot be suppressed.

DIGITAL PHASE ANGLE METER

This phase meter uses two flip-flops. The two signals, having some phase difference, must have same
frequency. In this meter, both the signals are shaped to a square waveform without any change in
their phase relationship.

The function of the two flip-flops is to generate gate controlling signals. One of the flip-flops enables
the gate, while other flip-flop disables the gate. The number of pulses allowed to pass during the
period of enabling and disabling the gate are counted which are proportional to the phase difference
between the two signals.
The schematic block diagram of the phase meter using flip-flops is as shown in the fig.

The phase meter consists of two preamplifiers, zero crossing detectors, J-K flip-flops and output
control gate. Let the phase difference between the two inputs signals be Ф. Note that the frequency
of the two signals is exactly same.
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During the positive half cycle, when the amplitude of signal v1 crosses zero, the zero crossing
detector senses the zero crossing and changes its state. This causes first J-K flip-flop to be set. This
enables the AND gate and allows the reference dock pulses to fed directly to the counter. Now second
signal v2 is having same frequency but its phase is lagging than that of the signal v1 by Ф0. Thus
during positive half cycle, when the amplitude of the signal v2 crosses zero, the second zero crossing
detector senses it and changes the state of second J-K flip-flop. This sets second J-K flip-flop. The
output of second J-K flip-flop is used to clear the first J-K flip-flop. Thus output of the first J-K flip-
flop goes low. This disables AND gate and counter stops counting.
Thus the total number of pulses counted is directly proportional to the phase difference. The
waveforms for the phase meter with flip-flops are as shown in the Fig.

The advantages of the phase meter using flip-flop are:

(i) High accuracy. (ii) Any phase difference i.e. leading or lagging can be detected and measured.
(iii) Circuit design is simple and speed of operation is fast.
(iv) Applicable for wide frequency range with higher reliability that the analog phase meter.
The disadvantages of the phase meter using flip-flop are:
(i) The frequency of both the input signals must be same.
(ii) It is difficult to measure small phase differences.
(iii) For accurate results, the clock frequency should be 360 times the input frequency.
(iv) Errors are incorporated due to false triggering
(v) At low frequency operations, gating errors are included.
(vi) For accurate reference dock oscillator needs to be frequently calibrated.
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3- ½ and 4- ½ Digit

The resolution of digital meters depends on the number of digits used in the display. The three digit
display for 0-1 V range can indicate the values from 0 to 999 mV with the smallest increment of
1mV.

Practically one more digit which can display only 0 or 1 is added.This digit is called half digit and
display is called 3- ½ digit display. This is shown in the Fig.

In such a display the meter can read the values above 999 up to 1999, to give the overlap between the
ranges for convenience. This process is called over-ranging.

In case of 4 -½ digit display, there are 4 full digits and 1 half digit. The number obtained is from 0 to
19999. For this operation the time period required for counting operation should be reduced. This can
be achieved by changing the frequency of the clock signal. The wave shaping and amplifier circuitry
should be more accurate for 4- ½ digit display. It is necessary to add one more BCD counter, latch,
BCD to 7 segment decoder and 7 segment display unit. The resolution of 4-½ digit display is better
than 3-½ digit display while the accuracy is 10 times better.

Resolution and Sensitivity

If n is the number of full digits then the resolution of a DVM is given by,

Where R = Resolution
Thus for 3 digit display, n - 3

The sensitivity is the smallest change in the input which a digital meter should be able to detect.
Hence, it is the full scale value of the lowest range multiplied by the resolution of the meter.

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