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Introduction to the Synchronous Digital

Hierarchy (SDH)
The History of Digital Transmission

z ’70s - introduction of PCM into Telecom networks


z 32 PCM streams are Synchronously Multiplexed to 2.048
Mbit/s (E1)
z Multiplexing to higher rates via PDH
z 1985 Bellcore proposes SONET
z 1988 SDH standard introduced.
PDH: Plesiochronous Digital Hierarchy

z Multiplex levels:
ƒ 2.048 Mbit/s
ƒ 8.448 Mbit/s
ƒ 34.368 Mbit/s
ƒ 139.264 Mbit/s
z Uses Positive justification to adapt frequency differences
z Overheads: CRC
z Defects: LOS, LOF, AIS
Plesiochronous Multiplexing

z Before SDH transmission networks were based on the


PDH hierarchy.
z Plesiochronous means nearly synchronous.
z 2 Mbit/s service signals are multiplexed to 140 Mbit/s for
transmission over optical fiber or radio.
z Multiplexing of 2 Mbit/s to 140 Mbit/s requires two
intermediate multiplexing stages of 8 Mbit/s and 34 Mbit/s.
z Multiplexing of 2 Mbit/s to 140 Mbit/s requires multiplex
equipment known as 2, 3 and 4 DME.
z Alarm and performance management requires separate
equipment in PDH.
PDH vs. SDH Hierarchy

z PDH transmission rates:


z SDH is designed to unify all transmission rates into a
single Mapping hierarchy
Japan North Europe
America

397.2 M bit/s

x4

97.728 M bit/s 274.176 M bit/s 139.264Mbit/s

x3 x6 x 4

32.084 M bit/s 44.738 M bit/s 34.368 Mbit/s

x5 x7 x 4

6.312 M bit/s 6.312 Mbit/s 8.448 M bit/s

x4 x4
x 4

1.544 M bit/s 2.048 M bit/s


PDH Multiplexing

z PDH Multiplexing of 2 Mbit/s to 140 Mbit/s requires 22


PDH multiplexers:
ƒ 16 x 2DME
ƒ 4 x 3DME
ƒ 1 x 4DME
z Also a total of 106 cables required.
2 Mb it/s 8 Mbi t/s 3 4 Mb it/s 140 Mbi t/s

1 2
D
M 3
E D
M
E

4
D
M
E

3
D
M
2 E
D
M
64 E
PDH Add/Drop

z If a small number of 2 Mbit/s streams passing through a


site need to be dropped then in PDH this requires large
amount of equipment to multiplex down to 2Mbit/s.
What is SDH?

z The basis of Synchronous Digital Hierarchy (SDH) is


synchronous multiplexing - data from multiple tributary
sources is byte interleaved.
z In SDH the multiplexed channels are in fixed locations
relative to the framing byte.
z Demultiplexing is achieved by gating out the required
bytes from the digital stream.
z This allows a single channel to be ‘dropped’ from the data
stream without demultiplexing intermediate rates as is
required in PDH.
SDH Rates

z SDH is a transport hierarchy based on multiples of 155.52


Mbit/s
z The basic unit of SDH is STM-1:
STM-1 = 155.52 Mbit/s
STM-4 = 622.08 Mbit/s
STM-16 = 2588.32 Mbit/s
STM-64 = 9953.28 Mbit/s
z Each rate is an exact multiple of the lower rate therefore
the hierarchy is synchronous.
SDH Hierarchy

z SDH defines a multiplexing hierarchy that allows all


existing PDH rates to be transported synchronously.
z The following diagram shows these multiplexing paths:
x1
139264 kb/s
STM-N AUG AU-4 VC-4 C-4
xN x3

x3 x1
HOP
TUG-3 TU-3 VC-3

44736 kb/s
AU-3 VC-3 C-3 (DS3)
34368 kb/s
x7

x7
x1
TUG-2 TU-2 VC-2 C-2
6312 kb /s
x3
(DS2)
TU-12 VC-12 C12 LOP
x4 204 8 kb/s

TU-11 VC-11 C-11


154 4 kb/s
(DS1)
Example: Multiplex path for the E1

xN x3 x7 x3

STM-N AUG AU-4 VC-4 TUG-3 TUG-2 TU-12 VC-12 C-12

Section overhead
Pointer processor

HO path overhead

Pointer processor

LO path overhead
Transport of PDH payloads

z SDH is essentially a transport mechanism for carrying a


large number of PDH payloads.
z A mechanism is required to map PDH rates into the STM
frame.
z This function is performed by the container (C).
z A PDH channel must be synchronised before it can be
mapped into a container.
z The synchroniser adapts the rate of an incoming PDH
signal to SDH rate.
SDH and non-synchronous signals

z At the PDH/SDH boundary Bit stuffing is performed when


the PDH signal is mapped into its container.

Bit stuffing

PDH

SDH
SDH virtual Containers

z Once a container has been created, path overhead byte


are added to create a virtual container.
z Path overheads contain alarm, performance and other
management information.
z A path through an SDH network exists from the point
where a PDH signal is put into a container to where the
signal is recovered from the container.
z The path overheads travel with the container over the
path.
Mapping Virtual Containers

z C-4 container being mapped into an STM frame via a VC-4


virtual container

Container-4

VC-4 POH Container-4 VC-4

AU-4 PTR VC-4 AU-4

AU-4 PTR VC-4 AUG

SOH AUG AUG STM-N

Logical association
T1517990-95
Physical association

NOTE – Unshaded areas are phase aligned. Phase alignment between the unshaded and shaded areas is defined by the
pointer (PTR) and is indicated by the arrow.
2 Mbit/s PCM30 frame structure

z The SDH frame rate is inherited from PCM.


z As with PCM, the SDH has 8 bits per time slot.
z As with PCM, the SDH frame rate in 125 us per frame.
z The following diagram shows the PCM30 frame:

125 us

TS0 TS1 TS15 TS16 TS17 TS30 TS31 TS0


Basic SDH frame structure

z STM-N frame structure is shown in the Figure below. The


three main areas of the STM-N frame are indicated:
ƒ SOH;
ƒ Administrative Unit pointer(s);
ƒ Information payload.
270 × N columns (bytes)

9×N 261 × N

1
Section overhead
SOH
3
4 Administrative unit pointer(s)
9 rows
5 STM-N payload

Section overhead
SOH

9
T15180 00-9 5
Different clock rates in SDH

z SDH will still work if there are two different clocks in the
network and the network becomes asynchronous.
z Pointers are used adjust for the new frequency.

Pointer
processing
ocurrs here

STM -N S TM -N STM -N
NE #1 N E #2

f +δf
f
Administrative Units in the STM-N

z The VC-4 is mapped into an STM frame via the


administrative group (AU).
z The VC-4 associated with each AU-4 does not have a
fixed phase with respect to the STM-N frame.
z The location of the first byte of the VC-n is indicated by the
AU-n pointer.
N × 2 7 0 b yt e s
N × 9 N × 2 6 1 b yt e s S T M -N

3 RS OH

1 A U -n P T R s V C -4 -X c

J1

B3

5 M SO H C2

G 1
F ix e d
F2 C - 4 -X c
st u f f
H4

F3

K3

N1

1 X- 1 X × 260

X × 2 6 1 b y te s
T 1 5 18 2 3 0 - 95

P TR P o in t e r
Tributary Units in a VC-4

z The VC-4 can carry a container -4 (C-4). The C4 carries a


140 Mbit/s PDH signal.
z The VC-4 forms what is known as an high order path.
z If lower speed PDH signals need to be transported these
are mapped into a tributary unit (TU).
z The TUs are then multiplexed into a VC-4.
z The VC-n associated with each TU-n does not have a
fixed phase relationship with respect to the start of the VC-
4.
z The TU-n pointer is in a fixed location in the VC-4 and the
location of the first byte of the VC-n is indicated by the TU-
n pointer.
Tributary Units in a VC-4

86 Columns

TUG-2 TUG-2

TUG-3
TU-2 TU-1 (7 × TUG-2)
PTR PTRs
.. POH
..
Fixed stuff
Fixed stuff

POH POH
..... ...

VC-2 VC-1

..
..

PTR Pointer
3 VC-12s or 4 VC-11s
in 1 × TUG-2

T1518100-95
Tributary units

V5
z 2 Mbit/s are mapped asynchronously into
RR R RR RR R

32 bytes
a VC-12.
RR R RR RR R
J2
z VC-12s are distributed over four frames
C1 C2 O O O O R R known as a VC multiframe.
32 bytes

140
R RR RR RR R z The figure shows this over a period of
bytes N2
C1 C2 O O O O R R 500 µs.
32 bytes

R RR RR RR R

z V5 byte:
K4
C 1 C2 R R R R R S 1
S2 D D D D D D D

31 bytes

R RR RR RR R

T1523020-96

D Data bit BIP-2 REI RFI Signal Label RDI


R Fix ed stuff bit 1 2 3 4 5 6 7 8
O Overhead bit
S Justification opportunity bit
C Justification c ontrol bit
STM Section Overheads

9 Bytes
z Nine rows of nine bytes at
the front of the SDH frame A1 A1 A1 A2 A2 A2 J0
form the section overhead. B1 E1 E1 F1 RSOH
z The first three rows are the D1 D2 D3
regenerator section 9 rows
overhead. B2 B2 B2 K1 K2
z The last six rows are the D4 D5 D6
multiplex section overhead. D7 D8 D9
MSOH

D10 D11 D12

S1 Z1 Z1 Z2 Z2 M1 E2 E2
VC-4 path overheads

z The first column of the VC-4 Old VC-4 POH new VC-4 POH
is the VC-4 path overhead.
J1 J1

z The overheads have been B3 B3

C2 C2
modified in the latest
G1 G1
release of G.707
9 rows F2 9 rows F2

H4 H4

Z3 F3

Z4 K3

Z5 N1
VC-12 overhead

old VC-12 OH new VC-12 OH


VC-12 VC-12
z The first byte of the VC-12 is
V5 V5
the VC-12 path overhead.
125 us 125 us
35 by tes 35 by tes
z The VC-12 frame is spread
over four frames to form a J2 J2
VC-12 multiframe. 125 us 125 us
35 by tes 35 by tes

z Each of the four frames in


the multiframe contains an Z6 N2

overhead byte. 125 us 125 us


35 by tes 35 by tes
z The overheads have been
modified in the latest release Z7 K4

of G.707 125 us
35 by tes
125 us
35 by tes
V5 Byte

z The bits in the V5 byte are allocated as follows:

BIP-2 REI RFI Signal Label RDI


1 2 3 4 5 6 7 8
Framing bytes (A1 & A2)

z The framing byte locate the beginning of the STM frame

Byte comments
A1 First framing byte A1:11110110

A2 Second framing byte


A2:00101000
Synchronisation status marker byte (S1).

z The synchronisation status marker byte contains


information about the quality of the embedded timing

Byte comments
S1 Synchronistion status marker byte

S1 Byte: bit 5 -8
0000 Quality unknown
0010 Traceable to PRC G.811
0100 Traceable to Transit G.812
1000 Traceable to Local G.812
1011 Derived from SETS
1111 Don't use for Synchronisation.
Other bytes are reserved.
Bit interleaved parity (B1, B2, B3)

z The BIP is calculated over the previous frame/multiframe


BIP Bits & Bytes Coverage

B1 parity - Entire frame B2 parity: Mux OH + AU-4

Regen OH Regen OH

AU-4 AU-4
9 rows 9 rows

Mux OH Mux OH

9 column s 261 co lumns 9 columns 26 1 columns

B3 parity - Virtual Container V5 bits 1 & 2: TU-12 frame

AU-4 AU-4
Regen OH Regen OH TU-1 2 poin ter
VC-4
VC-4 VC-4 Payload
Path OH
9 rows 9 rows
Path
VC-4 Path
Payload
T U-12
Mux OH OH Mux OH OH
Payload

9 column s 261 co lumns 9 columns 26 1 columns


Bit interleaved parity (B1, B2, B3)

Byte comments
B1 Bit interleaved parity - 8 bits for entire previous frame
before scrambling.
B2 Three bytes of a 24 bit multiplex section bit interleaved
#1,2,3 parity - Calculated over the previous STM-1 frame
excluding the first three rows of the SOH before
scrambling.
B3 Bit interleaved parity - 8 bits for entire previous frame
before scrambling.
The BIP is calculated over the previous VC-4.
V5 VC-12 path bit interleaved parity - 2 bits for previous frame
The BIP is calculated over the previous VC-12 frame
including VC-12 path overheads but excludes V1, V2, V3.
Orderwire (E1 & E2)

z The E byte carry the orderwire channels.


z The relief byte is used for ring protection

ƒ E1 – Regenerator section orderwire

ƒ E2 – Multiplex section orderwire


DCC channels (D1 to D3 and D4 to D12)

z The DCC channels are used Element Management


Software to pass management information between sites.

Byte comments
D1 to Regenerator section data communications channel
D3 (DCC)
The D1 to D3 bytes are a 192 kbit/s DCC channel.

D4 to Multiplex section data communications channel


D12 The D4 to D12 bytes are a 576 kbit/s DCC channel.
User channels (F1, F2, F3 & N2)

z The user channels appear at a front panel connector for


use by the network operator.

Byte comments
F1 64 kbit/s user channel.
User The FLX150/600 supports either G.703 co-directional or
channel contradirectional interface.
This user channel can be passed through at a
regenerator.

F2 VC-4 path user channel

Z3 (F3) VC-4 path user channel

Z6 (N2) Network operator byte -


Section/Path trace bytes (J0, J1, J2)

z The section/path trace supports a string assigned to a


path, this verifies continued connection to the intended
transmitter

Byte comments
J0 Regenerator section trace use is not defined in ITU-T.
Trace value can be entered for section id between
national boundaries.

J1 ITU-T: High order path access point identifier.

J2 Path trace byte


Remote error indication

z MS REI (M1) Indicates the count of the interleaved bit


blocks (1 to N) that have detected an error.

Byte comments
M1 Multiplex section remote error indication (MS
REI)
High order path management

z Signal label (C2)


Byte com m en ts
C2 Signal label: This byte indicates the composition of the
VC-4
.

z Path Status
Byte comments
G1 Path status byte. This byte is sent from the receiver
back to the originator.

z Multiframe Pointer
Byte comments
H4 VC-4 multiframe pointer.
Indicates the multiframe position indicator for the VC-12
Low order path management

z The VC-12 path overhead signals are held in the V5 byte.

Byte Comments
V5 Remote error indication (REI): set to one if one
bit 3 or more error is detected at receiver in the BIP-2.
Standard implementation on FLX and FLM
V5 Remote failure indication (RFI). Set to one if a
bit 4 failure is declared .

V5 VC-12 signal label.


bit 5-7
V5 VC-12 path remote defect indication (RDI) Set to
bit 8 1 if an AIS or a signal failure condition is
received.
SDH layers

z The following diagram shows 2Mbit/s multiplexed to STM-


1.
z The transmission path passes through five layers in this
connection.
SDH PDH
1
LPA
Low er O rder Cr os s
Pat h Connec tion
Lay er LPT
LPC

HPA
Higher O rder Cross
Pat h Connec tion HPT
Lay er
H PC

M SA
M ultiple xer
S ection
Lay er M ST

RSA
Regenerator
S ection
Lay er R ST

P hys ica l
M edia
Lay er PPI
S PI
Termination points

z Within a layer each path ends at a ‘termination point’


z A path in SDH can be visualised as a pipe, In the diagram
the 140Mbit/s path passes unaltered through the multiplex
section0
hi gh or de r p ath
M ux se ctio n
A DM

1 40 Mb it/s 14 0 M bi t/s

A DM S TM-1 ring A DM

A DM

140 Mbit/ s in 140 M bit/s out


S ection O H in Se ction O H out
Layers - Example

V C - 12 P at h r e m a in s u n in te r r u p te d b e tw e e n te r m in a tio n p o in ts

M u x s e ct io n

M ux R egen R egen
M u x se ct io n s e ct io n s e c tio n s e c tio n

E1 E1

AD M
S T M -1
r in g A DM D X C 4 /4 Te rm in a l
ST M - 1 ST M-4

E1

V C - 12 V C -1 2 V C -4 R e ge n V C -1 2
te rm in atio n X -c o n ne c t X - c on n ec t T e rm in atio n
L ow e r O rd e r
P a th
L a ye r

H ig h e r O rd e r
P a th
L a ye r

M u ltip le x
S e c tio n
L a ye r

R eg e ne r ato r
S e c tio n
L a ye r

P hy s ic a l
in ter fac e
L a ye r
Alarms and layers

STM Physical
Media
Layer
LO S LOS
z Each defect indication
is associated with a
R eg en er ator LO F LOF
Sectio n
Layer
RS-BIP RS-BIP layer
Mu ltiplexer MS-AIS MS-AIS
Sectio n MS-BIP MS-BIP
Layer MS-RDI MS-RDI
AU-AIS AU-AIS
AU-LO P AU-LOP

H igher Order VC-4 BIP VC-4 BIP Low order path


Path VC-4 REI VC-4 RE I
Layer VC-4 RDI VC-4 RDI Mux section
VC-4 LOM VC-4 LOM
E1 E1

ADM
STM-1
Lo wer Order VC-12 AIS VC-12 AIS ring ADM
Path VC-12 LO P VC-12 LOP
Layer VC-12 BIP VC-12 BIP
VC-12 REI VC-12 REI
VC-12 RFI VC-12 RFI
VC-12 RDI VC-12 RDI

PDH Physical
In terface LO S LOS
Layer
Signalling interactions

z Each signal has a consequent action. These are


described in the G.782 diagram
P h y s ic a l
Re g e n Se c tio n M u ltip le x Se c t io n H ig h e r O rd e r P a t h Lo w e r O rd e r P a t h
Se c tio n

SPI RST N o te 1 M ST M SA HPO M H UG H PC HPT HPA LP O M LU G LP C L PT LP A

LO S
D e te c ti o n
"1 "
LO F G e n e ra ti o n

R S- B IP E r ro r ( B 1 ) "1 " "1 " In s e rti o n o f A IS s i g n a l

A IS A l a rm In d i c a t o
i n Si g n a l
R e g e n s ig n a l p a s se d th ro u g h F EB E F a r e n d b l o c k e rr o r
"1 " F ER F F a r e n d re c e i v e f a i l u r e
M S- A I S
LO S Lo s s of s ig na l
M S- Ex c Er ro r (B 2 ) LO F L o s s o f fr a m e
LO M L o ss o f m u l t i fra m e
M S- B IP E rr o r ( B 2 ) LO P L o s s o f p o i n te r
A U - A IS
T IM T ra c e i d e n ti f i e r m i s m a tc h
SL M Si g n a l l a b e l M i s m a tc h
M S- FE R F U N EQ Un e q u p i p e d si g n a l p e r G 7 0 9

M S- FE R F

"1 "

A U - A IS

A U - LO P U n u se d
H PC
H O P a t h s ig n a l p a s s e d th r o u g h
O u t p u t / HP- UN EQ
H O V C w it h PO H a n d u n s p e c if ie d p a y lo a d "1 "

H O u n e q u ip p e d s ig n a l

HP- UN EQ
"1 "
H P - TIM

H P - SL M

H P -B IP E rr o r ( B 3)

H P - FE B E
TU - A IS
H P - FE R F

H P - FE R F

H P - FE B E
"1 "
TU - A IS

H P - LO M / TU -L O P U n u se d
LP C
L O P a t h s ig n a l p a s s e d t h r o u g h
O u t p u t / L P -U N EQ
L O VC w it h P O H a n d u n s p e c if ie d p a y lo a d "1 "

L O u n e q u ip p e d sig n a l

LP - U N EQ
"1 "
LP - TIM

LP - SLM

L P -B IP Er ro r ( V 5 )
LP - FE B E

LP - FE R F

LP - FE R F

LP - FE B E

SD H M a in t e n a n c e Sig n a l In t e r a c t io n G .7 8 2 1 0 N o v e m b e r 1 9 92
SETS: Synchronous Equipment Timing
Source

z The SETS function controls the selection of the timing


source to be used as a reference in the SDH equipment
z The SETG function is a DPLL function that smoothes the
clock and provides holdover on loss of clock.

Select Select
Output clk
A C

STM-N in Select Sys clk


PDH in B SETG
Ext ref
Sync distribution in the SDH network

z SDH can be used as a PRC


PRC

timing transport in a
telecommunications
network. st
1 NE
st
1 NE
z In this case a SETG (DPLL)
is in the clock path at each nd
2 NE
nd
2 NE
network element (NE)
z The PRC is the network recovery
Timing Timing
recovery
providers primary reference
clock th th
N NE N NE
z The G.812 clock is the
network providers exchange
clock.
G.812 G.812
clock clock