Digital Experiments Emphasizing Troubleshooting

Digital Experiments Emphasizing Troubleshooting
Third Edition
Digital Experiments Emphasizing Troubleshooting

To Accompany FLOYD, DIGITAL FUNDAMENTALS, Fifth Edition
Jerry V. Cox
Mayland Technical College
Merrill, an imprint of Macmillan Publishing Company New York Maxwell Macmillan Canada Toronto Maxwell Macmillan International New York Oxford Singapore Sydney
,-,
Editor: David Garza Production Supervisor: York Production Services Developmental Editor: Carol Hinklin Robison Production Manager: Aliza Greenblatt Cover Designer: Robert Vega Cover Illustration: The Image Bank Photograph:
Rob Atkins
This book was set in Times Roman by ATLIS Graphics & Design, Inc., and was printed and bound by Semline. The cover was printed by Phoenix Color Corp. Copyright © 1994 by Macmillan Publishing Company, a division of Macmillan, Inc. Merrill is an imprint of Macmillan Publishing Company. Printed in the United States of America All rights reserved. No part of this book may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying, recording, or any information storage and retrieval system, without permission in writing from the Publisher. Earlier editions copyright e 1986 and 1990 by Merrill Publishing Company.
Library
of Congress
CataJoging-in-Publication
Data
Cox, Jerry V. Digital experiments: emphasizing troubleshooting f Jerry V. Cox. -3rded. p. cm. - (Merrill's international series in electrical and electronics technology) "To accompany Floyd, Digital fundamentals." ISBN 0-02-325341-X I. Digital electronics-Experiments. 2. Logic circuits-Experiments. I. Floyd, Thomas L. Digital fundamentals. II. Title. III. Series. TK7868.D5C69 1993 62 I.39'5 '078--dc20 93-15931 CIP Printing:
34
567
Year:
567890
NOTICE TO THE READER
The publisher and the author(s) do not warrant or guarantee any of the products and/or equipment described herein nor has the publisher or the author(s) made any independent analysis in connection with any of the products, equipment, or information used herein. The reader is directed to the manufacturer for any warranty or guarantee for any claim, loss, damages, costs, or expense, arising out of or incurred by the reader in connection with the use or operation of the products and/or equipment. The reader is expressly advised to adopt all safety precautions that might be indicated by the activities and experiments described herein. The reader assumes all risks in connection with such instructions.
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MERRILL'S INTERNATIONAL SERIES IN ENGINEERING TECHNOLOGY

INTRODUCTION TO ENGINEERING TECHNOLOGY Digital Electronics Floyd, Digital Fundamentals, 5th Edition, 0-02-338502-2 Foster, Sequential Logic Tutor: A Software Tutorial Using Animated Hypertext, 0-02-338731-9 Foster, Combinational Logic Tutor: A Software Tutorial Using Animated Hypertext, 0-02-338735-1 McCalla, Digital Logic and Computer Design, 0-675-21170-0 Reis, Digital Electronics through Project Analysis, 0-675-21141-7 Tocci, Fundamentals of Pulse and Digital Circuits, 3rd Edition, 0-675-20033-4 Microprocessor Technology Antonakos, The 68000 Microprocessor: Hardware and Software Principles and Applications, 2nd Edition, 0-02-303603-6 Antonakos, An Introduction to the Intel Family of Microprocessors: A Hands-On Approach Utilizing the 8088 Microprocessor, 0-675-22173-0 Brey, 8086/8066, 80286, 80386, and 80486 Assembly Language Programming, 0-02-314247-2 Brey, The Advanced Intel Microprocessor, 0-02-314245-6 Brey, The Intel Microprocessors: 8086/8088, 80186, 80286,80386, and 80486. Architecture, Programming, and Interfacing, 3rd Edition, 0-02-314250-2 Brey, Microprocessors and Peripherals: Hardware, Software, Interfacing, and Applications, 2nd Edition, 0-675-20884-X Driscoll, Coughlin, & Villanucci, Data Acquisition and Process Control with the MC68HC11 Microcontroller, 0-02-330555-X Gaonkar, Microprocessor Architecture, Programming, and Applications with the 8085/8080A, 2nd Edition, 0-675-20675-6 Gaonkar, The Z80 Microprocessor: Architecture, Interfacing, Programming, and Design, 2nd Edition, 0-02-340484-1 Goody, Programming and Interfacing the 8086/8088 Microprocessor: A Product-Development Laboratory Process, 0-675-21312-6 MacKenzie, The 8051 Microcontroller, 0-02-373650-X Miller, The 68000 Family of Microprocessors: Architecture, Programming, and Applications, 2nd Edition, 0-02-381560-4 Quinn, The 6800 Microprocessor, 0-675-20515-8 Subbarao, 16/32 Bit Microprocessors: 68000/68010/68020 Software, Hardware, and Design Applications, 0-675-21119-0 Electronic Communications Monaco, Introduction to Microwave Technology, 0-675-21030-5 Monaco, Preparing for the FCC Radio- Telephone Operator's License Examination, 0-675-21313-4 Schoenbeck, Electronic Communications: Modulation and Transmission, 2nd Edition, 0-675-21311-8 Young, Electronic Communication Techniques, 3rd Edition, 0-02-431201-0
Pond, Introduction to Engineering Edition, 0-02-396031-0 ELECTRONICS Electronics TECHNOLOGY
Technology, 2nd
Reference
Adamson, The Electronics Dictionary for Technicians, 0-02-300820-2 Berlin, The Illustrated Electronics Dictionary, 0-675-20451-8 Reis, Becoming an Electronics Technician: Securing Your High-Tech Future, 0-02-399231-X DC/AC Circuits Boylestad, DC/AC: The Basics, 0-675-20918-8 Boylestad, Introductory Circuit Analysis, 7th Edition, 0-02-313161-6 Ciccarelli, Circuit Modeling: Exercises and Software, 2nd Edition,0-02-322455-X Floyd, Electric Circuits Fundamentals, 2nd Edition, 0-675-21408-4 Floyd, Electronics Fundamentals: Circuits, Devices, and Applications, 2nd Edition, 0-675-21310-X Floyd, Principles of Electric Circuits, 4th Edition, 0-02-338531-6 Floyd, Principles of Electric Circuits: Electron Flow Version, 3rd Edition, 0-02-338501-4 Keown, PSpice and Circuit Analysis, 2nd Edition, 0-02-363526-6 Monssen, PSpice with Circuit Analysis, 0-675-21376-2 Murphy, DC Circuit Tutor: A Software Tutorial Using Animated Hypertext, 0-02-385141-4 Murphy, AC Circuit Tutor: A Software Tutorial Using Animated Hypertext, 0-02-385144-9 Tocci, Introduction to Electric Circuit Analysis, 2nd Edition, 0-675-20002-4 Devices and Linear Circuits Berlin & Getz, Fundamentals of Operational Amplifiers and Linear Integrated Circuits, 0-675-21002-X Berube, Electronic Devices and Circuits Using MICROCAP /1,0-02-309160-6 Berube, Electronic Devices and Circuits Using MICROCAP /11,0-02-309151-7 Bogart, Electronic Devices and Circuits, 3rd Edition, 0-02-311701-X Bogart, Linear Electronics, 0-02-311601-3 Floyd, Basic Operational Amplifiers and Linear Integrated Circuits, 0-02-338641-X Floyd, Electronic Devices, 3rd Edition, 0-675-22170-6 FLoyd, Electronic Devices: Electron Flow Version, 0-02-338540-5 Floyd, Fundamentals of Linear Circuits, 0-02-338481-6 Schwartz, Survey of Electronics, 3rd Edition, 0-675-20162-4 Stanley, Operational Amplifiers with Linear Integrated Circuits, 3rd Edition, 0-02-415556-X Tocci, Electronic Devices: Conventional Flow Version, 3rd Edition, 0-675-21150-6 Tocci & Oliver, Fundamentals of Electronic Devices, 4th Edition, 0-675-21259-6
Zanger & Zanger, Fiber Optics: Communication Other Applications, 0-675-20944-7 Microcomputer Servicing
and
Adamson, Microcomputer Repair, 0-02-300825-3 Asser, Stigliano, & Bahrenburg, Microcomputer Servicing: Practical Systems and Troubleshooting, 2nd Edition, 0-02-304241-9 Asser, Stigliano, & Bahrenburg, Microcomputer Theory and Servicing, 2nd Edition, 0-02-304231-1 Programming Adamson, Applied Pascal for Technology, 0-675-20771-1 Adamson, Structured BASIC Applied to Technology, 2nd Edition,0-02-300827-X Adamson, Structured C for Technology, 0-675-20993-5 Adamson, Structured C for Technology (with disk), 0-675-21289-8 Nashelsky & Boylestad, BASIC Applied to Circuit Analysis, 0-675-20161-6 Instrumentation and Measurement Berlin & Getz, Principles of Electronic Instrumentation and Measurement, 0-675-20449-6 Buchla & McLachlan, Applied Electronic Instrumentation and Measurement, 0-675-21162-X Gillies, Instrumentation and Measurements for Electronic Technicians, 2nd Edition, 0-02-343051-6 Transform Analysis Kulathinal, Transform Analysis and Electronic Networks with Applications, 0-675-20765-7 Biomedical Equipment Technology and Aston, Principles of Biomedical Instrumentation Measurement, 0-675-20943-9 Mathematics Monaco, Essential Mathematics for Electronics Technicians, 0-675-21172-7 Davis, Technical Mathematics, 0-675-20338-4 Davis, Technical Mathematics with Calculus, 0-675-20965-X INDUSTRIAL ELECTRONICSIINDUSTRIAL TECHNOLOGY Bateson, Introduction to Control System Technology, 4th Edition, 0-02-306463-3 Fuller, Robotics: Introduction, Programming, and Projects, 0-675-21078-X Goetsch, Industrial Safety and Health: In the Age of High Technology, 0-02-344207-7 Goetsch, Industrial Supervision: In the Age of High Technology, 0-675-22137-4 Geotsch, Introduction to Total Quality: Quality, Productivity, and Competitiveness, 0-02-344221-2 Horath, Computer Numerical Control Programming of Machines, 0-02-357201-9 Hubert, Electric Machines.· Theory, Operation, Applications, Adjustment, and Control, 0-675-20765-7 Humphries, Motors and Controls, 0-675-20235-3 Hutchins, Introduction to Quality: Management, Assurance, and Control, 0-675-20896-3 Laviana, Basic Computer Numerical Control Programming, 0-675-21298-7 Pond, Fundamentals of Statistical Quality Control
Reis, Electronic Project Design and Fabrication, 2nd Edition, 0-02-399230-1 Rosenblatt & Friedman, Direct and Alternating Current Machinery, 2nd Edition, 0-675-20160-8 Smith, Statistical Process Control and Quality Improvement, 0-675-21160-3 Webb, Programmable Logic Controllers: Principles and Applications, 2nd Edition, 0-02-424970-X Webb & Greshock, Industrial Control Electronics, 2nd Edition, 0-02-424864-9 MECHANICAUCIVIL TECHNOLOGY
Dalton, The Technology of Metallurgy, 0-02-326900-6 Keyser, Materials Science in Engineering, 4th Edition, 0-675-20401-1 Kokernak, Fluid Power Technology, 0-02-305705-X Kraut, Fluid Mechanics for Technicians, 0-675-21330-4 Mott, Applied Fluid Mechanics, 4th Edition, 0-02-384231-8 Mott, Machine Elements in Mechanical Design, 2nd Edition, 0-675-22289-3 Rolle, Thermodynamics and Heat Power, 4th Edition, 0-02-403201-8 Spiegel & Limbrunner, Applied Statics and Strength of Materials, 2nd Edition, 0-02-414961-6 Spiegel & Limbrunner, Applied Strength of Materials, 0-02-414970-5 Wolansky & Akers, Modern Hydraulics: The Basics at Work,0-675-20987-0 Wolf, Statics and Strength of Materials: A Parallel Approach to Understanding Structures, 0-675-20622-7 DRAFTING TECHNOLOGY
Cooper, Introduction to VersaCAD, 0-675-21164-6 Ethier, AutoCAD in 3 Dimensions, 0-02-334232-3 Goetsch & Rickman, Computer-Aided Drafting with AutoCAD, 0-675-20915-3 Kirkpatrick & Kirkpatrick, AutoCAD for Interior Design and Space Planning, 0-02-364455-9 Kirkpatrick, The AutoCAD Book: Drawing, Modeling, and Applications, 2nd Edition, 0-675-22288-5 Kirkpatrick, The AutoCAD Book: Drawing, Modeling, and Applications, Including Release 12, 3rd Edition, 0-02-364440-0 Lamit & Lloyd, Drafting for Electronics, 2nd Edition, 0-02-367342-7 Lamit & Paige, Computer-Aided Design and Drafting, 0-675-20475-5 Maruggi, Technical Graphics: Electronics Worktext, 2nd Edition, 0-675-21378-9 Maruggi, The Technology of Drafting, 0-675-20762-2 Sell, Basic Technical Drawing, 0-675-21001-1 TECHNICAL WRITING
Croft, Getting a Job: Resume Writing, Job Application Letters, and Interview Strategies, 0-675-20917-X Panares, A Handbook of English for Technical Students, 0-675-20650-2 Pfeiffer, Proposal Writing: The Art of Friendly Persuausion, 0-675-20988-9 Pfeiffer, Technical Writing: A Practical Approach, 2nd Edition, 0-02-395111-7 Roze, Technical Communications: The Practical Craft, 2nd Edition, 0-02-404171-8 Weisman, Basic Technical Writing, 6th Edition, 0-675-21256-1
Preface
This book is an experiment manual for an introductory course in digital electronics. It is intended to complement Digital Fundamentals, Fifth Edition, by Thomas L. Floyd. Its purposes are to provide valuable laboratory experiences for students and to give them background and instructions on how to build, apply, and troubleshoot digital/logic circuits. In this edition a number of sections have been expanded and clarified. Also, The Troubleshooting Chart is introduced in Experiment 10, "Exclusive-OR Gates". A troubleshooting chart generally follows the form: Symptom-Cause-Possible Solution. These charts, a valuable tool for the technician, are frequently found in the Maintenance Manuals of commercial equipment. A major emphasis is on digital troubleshooting. The Appendix, entitled "Systematic Approach to Troubleshooting Digital and Microcomputer Systems," describes a step-by-step method of first isolating the failure (the short or open) and then determining whether it is a component or manufacturing problem. The sequence of steps used is designed to prevent the replacement of parts that are not defective and to reduce the time spent searching in areas of the circuit or system that are not defective. The text develops the methods of troubleshooting as the logic devices are introduced and makes frequent references to the Appendix. The Appendix has sufficient detail to make it an independent reference and guide. A flowchart is used as a pictorial aid to show how to apply the logic probe and pulser to determine which
of the ten possible digital failures is at fault. Two examples are included to illustrate how specific problems are solved. The section on troubleshooting microprocessor systems features a discussion of the problems that are encountered with the data, address, and control buses, as well as ones on memories and input and output devices. The necessity to follow a step-by-step plan to solve a problem is emphasized in every experiment. This procedural approach not only saves time in the long run but also develops a better understanding of how the circuit operates. Another benefit is that at the same time the student becomes acquainted with the procedures used in automatic test equipment because they are also programmed to follow a sequence of predetermined tests. This is an extremely important skill to possess because a large number of technicians are involved in developing and modifying the test programs for test equipment. The experiments all have a similar format. Each experiment begins with a set of Objectives, which state the goals of the unit. Also, as part of the objectives, a definition of the principal idea of the unit is included. The Reference Reading section directs students to the appropriate sections in Floyd's book, and the Materials Needed lists the equipment necessary to perform the experiment. The Discussion section provides general background information on the circuit or device, including how it is intended to be used. In addition, the special features of the circuit are pointed out. The Procedure gives step-by-step instructions
ix
for the experiment. Often students are required to fill out data tables and/or to complete diagrams to demonstrate if the experiment was perforrned correctly or if the results were reasonable. To illustrate systems applications, a simple IC tester, an A/D converter, a "football game," and so forth, are used to show how components are connected together and how they function as a system. Many of the integrated circuits are first introduced in one experiment and then reused in later experiments to show how they are applied in other circuits. Applications are further emphasized by showing how devices such as converters, encoders, counters, and registers are expanded or cascaded from four bits to eight bits, for example. Whenever a device has the capability of being cascaded or expanded, this feature is demonstrated in the experiment in order to illustrate the versatility of these devices. Most of the key parameters found in manufacturers' data sheets are explained over the course of the experiments. To help students gain familiarity with the manufacturers' data books, the experiments require frequent reference to these data sheets. In addition, a number of the experiments use the new IEEE/IEC dependency notation. The material is arranged in the following general groups: 1. 2. 3. 4. 5. 6. Logic Gates Combinational Logic Sequential Logic Memories Interfacing Arithmetic Logic Unit
Notice that analog-to-digital and digital-to-analog devices are included as part of the interfacing group. Also note that flip-flops are organized by the method in which they are triggered (such as level, pulse, and edge) instead of by type (such as R-S, D, and J-K). The grouping of flip-flops by the method of triggering emphasizes these important differences when applying the devices. Each experiment contains a Troubleshooting section to develop skills in analyzing problems in digital systems. The section usually points out a problem unique to that experiment, with an explanation of how to troubleshoot that problem. Naturally, the techniques learned in the first experiments will be used in later experiments. Therefore, the student's abilities to analyze and solve problems progress as they complete each unit.
A set of Exercises is provided both to test comprehension of the main principles of the unit and also to provide an opportunity to apply the knowledge obtained to new situations. A student notebook is strongly suggested to record these answers along with any comments on the experiment. Another option is to record the answers in the available space in the manual, whenever possible. Such recording will enhance the value of the manual as a future reference, since other tables and figures have already been filled in or completed by the student. The test equipment and materials required for this manual are available from many sources and generally can be found in most digital laboratories. A list and description of the test equipment, integrated circuits, and all other components required for this manual are provided in Table 1-1 at the end of Experiment 1. The logic probe and logic pulser are used in many of the experiments. Therefore, Experiment 2, Logic Probe and Logic Pulser, describes the operation of these useful devices. As mentioned earlier, this manual is designed to accompany Floyd's Digital Fundamentals, and thus the experiments follow that text whenever possible. The sections of Floyd's text that are recommended as background reading for each experiment are listed under Reference Reading. However, the experiments are general enough that they could be used with any other digital text. Since each chapter of this manual contains a Discussion Section, this book is ideally : suited for an in-house training program. An instructor's manual is also available from Merrill/Macmillan. Suggestions and comments from numerous instructors have helped me bring this manual to its third edition. I appreciate the suggestions of the following reviewers: Leonard J. Bundra, Lincoln Technical Institute, Allentown, Pennsylvania; Tom Chatagnier, Diablo Valley College, Pleasant Hill, California; Francis Erazmus, Computer Hardware Institute (CHI), Southhampton, Pennsylvania; Terrence Lewis, Computer Processing Institute, Cambridge, Massachusetts; Ed Risinger, Electronic Computer Programming Institute (ECPI), Virginia Beach, Virginia; Richard Schulmeister, Heald College, San Francisco, California; Jerry Stierwalt, Tulsa Vo- Tech School, Tulsa, Oklahoma; Louis Snyder, North Harris College, Houston, Texas; and of course, Tom Floyd. Jerry V. Cox
Contents
21 Pulse-Triggered Flip-Flops 131 22 One-Shots 139 Equipment 1 2 Logic Probe and Logic Pulser 7 23 Asynchronous Counters 145 24 Synchronous Counters 151 3 Logic Inverter 13 4 AND/NAND Logic Gates 19 25 Counter Applications 157 5 OR/NOR Logic Gates 25 26 Universal Shift Register 163 6 CMOS Logic Gates 33 27 Register Files with Open-Collector 7 Logic Gate Characteristics 37 Outputs 169 8 Logic Gate Applications 43 28 Random- Access Memories (RAMs) 9 Universal Property of NAND/NOR with 3-State Input/Output (I/O) 175 Gates 47 29 Digital-to-Analog (D/A) Conversion 183 10 Exclusive-OR Gates 57 Analog-to-Digital (A/D) Conversion 189 11 Implementation of Logic Networks 65 /~~ CMOS Analog Multiplexer/ 12 Comparators 73 Demultiplexer 197 13 Parallel Binary Adder/Subtractor 79 32 Applications of the Schmitt Trigger 201 14 Parity Generator/Checker 87 33 Arithmetic Logic Unit (ALU) 207 15 Data Selectors/Multiplexers 95 16 Encoders 101 17 Decoders/Demultiplexers 105 Appendix 18 Code Converters 111 Systematic Approach to Troubleshooting 19 Latches 119 Digital and Microcomputing 20 Edge- Triggered Flip-Flops 125 Systems 215
1 Familiarization with Laboratory
xi
1
Familiarization with Laboratory Equipment
OBJECTIVES
After completion of this experiment, you will be able to: o Use the logic trainer for basic operations with the logic switches, logic pulse outputs, clocks, displays, and breadboard. o Explain and use basic safety rules.
REFERENCE READING
Floyd, Digital Fundamentals, 5th ed., Section 1-2, Logic Levels and Digital Waveforms
MATERIALS NEEDED
Logic trainer
DISCUSSION
Logic Levels
In most digital systems there are two voltage levels: HIGH and LOW. The HIGH logic level (logicall) for Transistor-Transistor Logic (TTL) is between 2.0 V and 5.0 V. The LOW logic level (logical 0) is between 0.0 V and 0.8 V. Voltages between 0.8 V and 2.0 V are invalid. Any time a voltage is in this range (0.8 to 2.0 V), a faulty circuit is indicated. This voltage level (0.8 to 2.0 V) is usually called afloating, or bad, level. Of course, this voltage range is passed through very quickly, when a logic level switches from a HIGH to a LOW (or LOW to HIGH).
All TTL devices require a power supply voltage of + 5 V and ground (0 V) for normal operation. However, some of the other devices, such as Complementary Metal Oxide Semiconductor (CMOS) and linear op-amps, require other voltages. The required supply voltages as well as the logic level voltages for all devices are always given in the manufacturer's data sheets. A complete list of all the integrated circuits (ICs) , resistors, capacitors, and diodes required to perform the experiments in this manual is given in Table 1-1 at the end of this experiment. You should also have available to you a 1TL data book produced by one of the major IC manufacturers. You will be required to refer to this data book to obtain important technical information about the ICs used in each experiment. (Note: Appendix B in Floyd contains data sheets from Texas Instruments, but some chips in these experiments may be from National Semiconductor.) A list and description of the equipment required to perform the experiments in this manual follow.
Equipment List 1. Oscilloscope: A dual-trace, lO-MHz oscilloscope is desirable; however, a single-trace, 5-MHz oscilloscope with external trigger would be sufficient. The experiments in this manual assume that you have available appropriate instruction materials for operation of the oscilloscope. These materials can usually be obtained from the oscilloscope manufacturer. 2. Logic probe and logic pulser: See Experi-
Copyright © 1994 by Merrill Publishing Company, an imprint of Macmillan Publishing Company. All rights reserved.
ment 2 for a description of the logic probe and the logic pulser, which are used as troubleshooting instruments in many of the experiments. 3. Logic trainer requirements: The logic trainer is a setup containing power supplies, clock and pulse generators, logic-level outputs, displays, and a breadboard socket. Whenever any of these functions is required in an experiment, the logic trainer will be specified in the Materials Needed section. A number of commercial units are available meeting the following logic trainer requirements. (a) Power supplies: + 12 V at 100 mA, -12 Vat 100 mA, +5 Vat 500 mAo (b) Clock generator: I Hz, IkHz, 100kHz. A clock generator produces a train of pulses (HIGH and LOW logic levels) whose frequency is determined by the value of a timing capacitor/resistor. The timing components are changed by a selector switch with fixed component values or by adjustable components. (c) Pulse outputs (two required): A pulser is a logic switch that produces a single clock pulse. Some pulsers may maintain the pulse output for the duration of time the button is depressed. Other pulsers always produce a pulse of the same duration (approximately 10 J-Ls)egardless of how long the button is r depressed. You will be able to measure
your pulser output as part of the Procedure steps that follow. Pulser signals are used as RESETs, single clock pulses, and so on. A mechanical switch is unusable for pulsers, because when it is opened or closed it invariably produces multiple pulses, called contact bounce. Another important feature is that each pulser should have a normally HIGH and a normally LOW output. In other words, the pulsers should have complementary outputs, that is, a positive- and a negative-going pulse produced simultaneously at different output terminals. (d) Logic-level switches (eight required): A logic-level switch is a switch that produces a single logic-level output, either a 0 or a I. It is permissible to use mechanical switches for most experiments. However, some of the flip-flop experiments require a debounced switch (one that produces a single pulse per operation). The experiment procedure will specify when a debounced logic switch is required. If mechanical switches are used, extra care must be taken to avoid making wiring errors with the switch outputs, because the outputs of a mechanical switch may be connected directly to +5 V and ground whereas the output of a solidstate device would limit the maximum current. Keep in mind that if you need more than eight logic-level switches, you can
FIGURE 1-1 Breadboard. (Courtesy of RSP Electronics Corp .• Handy Products Division)
Copyright © 1994 by Merrill Publishing Company. an imprint of Macmillan Publishing Company. All rights reserved.
always use a jumper connected to ground or + 5 V to produce a logic 0 or 1. (e) LED displays (eight required): A display is a device that produces a visual indication of an electronic signal. The LED should turn ON when a HIGH logic level (1) is applied to its input. The LED should be OFF when a LOW logic level (0) is applied or if no connection is made to it. (f) Solderless breadboard socket: The breadboard is designed to allow you to connect the various ICs and other components used in these experiments. It should be large enough to accommodate up to eight 16-pin ICs. Refer to the breadboard manufacturer's data sheet to determine the arrangement of the solderless terminals and the type of hookup wire recommended. An example of a breadboard is shown in Figure 1-1. Safety The use of safe working habits requires no extra steps, but it does require common sense, proper use of the
equipment, and orderliness. Therefore you should begin each experiment by arranging the tools, instruments, and equipment in a neat and orderly fashion. Secure loose clothing, cables, and so forth as far away as possible from any equipment with moving parts. Always use goggles, gloves, or other protective devices when required. Line (power) voltages present a major hazard. Power tools and nonisolated equipment should use polarized 3-prong plugs. Many electrical shocks occur because of improper grounding. A piece of equipment can operate normally even with its metal case electrically "hot." If you are grounded and touch this "hot" cabinet, you will receive an electrical shock. If you are servicing a piece of electrical equipment, verify that the power is removed by measuring with a known good instrument. Do not assume that the switch will remove power. When you are working on an electrical device with the power applied, you should be familiar with the manufacturer's recommended safety precautions. In general, these precautions include using proper test equipment and working on an insulated mat with
Po wer sup ply +5 V
,.....,.....
Part of electrically connected power bus terminals on breadboard /Jumper

L, L, L, L.
Displays
.,...,'"
Ground~
1""'''''''
l... .,..__
Part of a second bus

(a)
h- ..,..
Logic switches
Displays
L,
L,
Scope probe
I
Scope
FIGURE 1-2
(b)
Copyright © 1994 by Merrill Publishing Company,
an imprint of Macmillan
Publishing Company.
All rights reserved.
insulated shoes. Even low voltages « 40 V) should be given the same respect as line voltages. Never work alone. Also, know how to respond to an emergency (such as removing power, using eyewash, and preventing further injury), and know how to report an emergency (in addition to notifying the instructor). Be aware of the location of the firstaid kit and the fire extinguisher. Finally, it would be very desirable for everyone to have a proper knowledge of first aid and artificial respiration (CPR).
FIGURE 1-3
Clock JUU"L Display L,
D
(a) Setup for measuring clock pulses Pulser Positive pulse L,
Scope
PROCEDURE
Power Connections on Breadboard 1. Refer to Figure 1-2(a) for the connections.
Notice that you are to use the breadboard as a means of connecting the power supply and ground to the displays. By examining the breadboard, note that there are a number of rows that have a large number of electrically connected terminals. These provide a convenient means of connecting power and ground to the ICs that are installed in the center of the board. The ICs are installed so as to straddle the center groove, providing several terminals (usually four) for making interconnections between other ICs. In this portion of the experiment, displays L} and L4 should be ON and L2 and L3 should be OFF.
Display
.n/
""1..J""
Negative pulse
C
...c= =
L,
Scope
(b) Setup for measuring pulser outputs
Logic Switches
,"0
2. Next refer to Figure 1-2(b), which shows two of the logic switches connected to the displays. You are b~SiCallYjust turning the light ON and OFF. You can a so observe the logic levels change on the scope. Th operation can be summarized as follows: Logic switch OFF
the scope. Use the space provided to record the horizontal and vertical scope settings . You will notice that at this frequency the LED glows dimly. Vertical deflection
_ _
= logic LOW = LED OFF Logic switch ON = logic 1state = logic HIGH = LED ON
= logic 0 state
Horizontal deflection
\\'D Clock
3. Refer to Figure 1-3(a) for the clock-measurin.g circuit~.Your clock generator should provide several outpu frequencies. A useful range is 1 Hz, 1 kHz, and 00 kHz. Set the clock frequency to 1 Hz and observe the signal on the scope and on the display . You Iwill probably notice that it is very difficult to observe the scope trace at this low frequency. However, Iyou should notice that the display is blinking at a 1 az rate. 4. Next select a frequency of 1 kHz and set the scope so that at least two pulses are displayed on the screen. Ort Plot 1, sketch in the trace you observed on
PLOT 1
Copyright © 1994 by Menill Publishing Company, an imprint of Macmillan Publishing Company. All rights reserved.
5. Now change the clock frequency to 100 kHz, and on Plot 2, sketch the waveform observed on the scope. The scope should be adjusted to make at least two cycles of the clock pulse visible. Record the deflections.
Vertical deflection
= =
_ _
OFF and the negative pulse LED is normally ON. You also can use the scope to observe the pulse output. Because only a single pulse will be produced, you will have to adjust the trigger level carefully, using positive-edge triggering to see the pulse. Operate the pulser switch repeatedly until you have the scope adjusted properly. On Plot 3, draw the trace you observe, and record the scope settings in the space provided. Move the scope probe to the negative-pulse output, and change your trigger control for negative-edge triggering. Also draw the observed signal on Plot 3. Compare the two traces; note the pulse widths, amplitudes, and inactive (no signal) voltage level. Vertical deflection
=
=
_ ------
PLOT 2
Pulser 6. Now refer to Figure 1-3(b), which shows the connections for measuring the pulser outputs. Actuate the switch, and observe the displays. If your unit trainer produces a very short pulse (say, 10 us), you will not be able to notice the LEDs blink. You should have noticed that the positive-pulse LED is normally
PLOT 3
~()I"O
EXERCISES
1. For TTL logic levels, what is the peak-to-peak amplitude of the largest AC signal that could be added to a DC level of 0.4 V and remain a "legal" logical O? What is the peak-to-peak amplitude of the largest AC signal that could be added to a DC level of 2.0 V and remain a "legal" logicall?
2. If neither display is ON in Step 1 [Figure 1-2(a)], what are several possible problems?
Publishing
Company.
3. Consider the test for measuring clock pulses in Figure 1-3(a). If you have the scope input switch selected to AC instead of DC, what change will occur in the displayed trace?
4. If the pulse width of a single clock pulse is measured at 4.5 I-LS, what is the frequency of the clock? Assume that the clock signal is a square wave.
TABLE 1-1 Required integrated circuits and other components. Quantity 2 I 2 I I I I I I I I 2 I 2 I I I I I I I I 2 2 2 I 2 2 I Type 7400 7402 7404 7405 7408 7432 7442A 7446 7474 7475 7476 74LS76A 7483 7485 7486 7490 7493A 74111 74123 74125 74132 74147 74151A 74170 74180 74184 74193 74LSI94 74S81 Description Quad 2-input NAND gate Quad 2-input NOR gate Hex inverter Hex open-collector inverter Quad 2-input AND gate Quad 2-input OR gate BCD-to-decimal decoder BCD-to-7 -segment decoder / dri ver Dual D-type flip-flop 4-bit gated 0 latch Master-slave J-K flip-flop (pulse-triggered) Master-slave J-K flip-flop (edge-triggered) 4-bit full-adder 4-bit magnitude comparator Quad 2-input exclusive-OR gate Decade counter 4-bit binary counter Dual master-slave J-K (data-lockout) Dual retriggerable monostable multi vibrator Quad 3-state buffer Quad 2-input Schmitt trigger gate BCD priority encoder 8-channel data selector / multiplexer 4 x 4 register file 9-bit parity generator / checker BCD-to-binary converter Binary synchronous up/ down counter 4-bit bidirectional universal shift register Arithmetic logic unit (ALU) Quantity 2 I 1 2 1 1 1 1 1 Type 2112-2 HP5082-7750 C0400lAE C04016 C04017B 741 DAC0806LCN ADC0804LCN 555 Description 256 x 4-bit memory 7-segment CA LEO display CMOS NOR gate CMOS bilateral switch CMOS decade counter Operational amplifier (opamp) 8-bit digital-to-analog converter 8-bit analog-to-digital converter Timer
Fixed resistors 2 I I 2 3 1 I 1 3 I I 47 n 270n 330 n 1.0kn 4.7 kn S.O kn 6.0 kn 8.2 kn 10 kn 27 kn 100 kn
d watt):
Adjustable resistors: I Ikn 10k{} I Capacitors: 1 100 pF 150 pF I 2 1000 pF I 0.01 IlF I 0.1 IlF 4 0.2 IlF I 471lF Diodes: IN4149 2
2
Logic Probe and Logic Pulser
OBJECTIVES
The logic probe and logic pulser are instruments designed as aids in troubleshooting digital circuits. After completion of this experiment, you will be able to: D Use the logic probe. D Use the logic pulser.
Logic Probe
The logic probe provides an LED display of the logic state of the point to which the probe is connected. The exact type of display varies with the logic probe manufacturer. The logic probe should have the capabilities of detecting the following conditions: 1. HIGH logic level: For TTL> 2.0 V; for CMOS> 70% of voltage supply. 2. LOW logic level: For TTL < 0.8 V; for CMOS < 30% of voltage supply. 3. Bad logic level: Invalid voltages between a "legal" HIGH or LOW. (Note: The voltage levels specified above are normally accurate only within approximately 0.2 V.) 4. Pulse memory: The pulse indicator remains lighted after the first pulse transition until it is reset. 5. Pulse stretch: The pulse indicator will provide an easily seen "flash" even for a single 20 ns pulse. 6. Clock pulses: Continuous pulse trains up to 40 MHz will cause the indicator to blink (approximately 10 Hz). The logic probe is ideal for detecting short-duration and low-repetition-rate pulses that are difficult to observe with the oscilloscope. Positive pulses only 20 ns in width trigger the indicator on for approximately 50 ms or more. This 50-ms "stretched" pulse is easily observed. Negative pulses cause the indicator to go off momentarily. You will find the logic probe very useful in
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REFERENCE READING
Floyd, Digital Fundamentals, 5th ed., Section 1-6, Digital and Troubleshooting Instruments
MATERIALS NEEDED
Logic trainer Logic pulser Logic probe Oscilloscope DVM 1 kfl potentiometer (pot) Two 47-fl resistors Two l-kf] resistors
DISCUSSION
In the previous experiment you measured the output of the trainer pulse generator with the oscilloscope. This measurement was difficult because only a single narrow pulse was generated, and the pulse was difficult to trigger and observe on the oscilloscope. For this type of measurement, and also for other digital signals, the logic probe is extremely useful.
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monitoring various control signals such as reset, start, stop, clocks, and so forth. (These terms will be discussed in later experiments.) You can also quickly determine pulse activity in a circuit by noting if the probe indicator is flashing ON and OFF.
current pulse is produced when CMOS is selected. Some models of logic pulsers automatically adjust the pulse width by detecting the amount of current required in the pulse. Examples of logic probes and logic pulsers are shown in Figures 2-I(a) and (b).
Logic Pulser
A companion unit to the logic probe is the logic pulser. With the logic pulser you can stimulate digital ICs in-circuit. That is, you can drive a logic LOW to a logic HIGH and a HIGH to LOW without damaging the IC and without changing any connections. You can place the pulser's tip on an input or output (node) of an IC and drive the node to the opposite state. The logic pulser obtains its power from the circuit under test and self-adjusts the amplitude of the output pulse to match the circuit under test. The logic pulser prevents damage to the IC by producing a very narrow pulse. Even though the pulse is of sufficient current to override the existing logic level, it is narrow enough to keep the energy level LOW. If the logic pulser switch is depressed for less than 1 second, then a single output pulse is produced. Holding the switch down produces a continuous IOO-Hz pulse train. Because CMOS devices operate at slower rates than TTL, a longer pulse but lower
Current Tracer
The current tracer is used to locate the precise point of a short after the logic probe and pulser have located the fault to a certain node. The current tracer is traced along the circuit path of the printed wiring board while the logic pulser connected to the node is actuated. When the tracer passes over the short, its indicator light comes on. The tracer detects the magnetic field generated by the high current pulses at the point of the short.
Logic Clip
The logic clip [Figure 2-1 (b)] is an instrument that clips onto a DIP IC package and contacts all the pins simultaneously, displaying the state on each pin by a set of LEOs along the top of the clip. Logic clips are useful only for static checks, because rapidly changing data cannot be read from the clip.
(a)
(b)
FIGURE 2-1
Examples of logic probes and pulsers. [Photo (a) courtesy Inc.; photo (b) courtesy of Hewlett-Packard Co.] of O.K. Industries,
PROCEDURE
Logic Probe Test 1. Connect the logic probe as shown in Figure 2-2(a). Because the threshold voltages of each logic probe vary, this test will determine the actual threshold voltages for a logic 1, a logic 0, and a bad level for your logic probe. You should refer to the manufacturer's specifications to determine what levels to expect. Logic 0 Test 2. Switch the TTL/CMOS switch to TTL. Adjust the pot until the LOW indication is made. In some models the indicator LED will be off. Your measurement should be in the range of 0.5 to 1.0 V. Logic 1 Test 3. Adjust the pot until the HIGH indication comes on. The voltage should range from 1.8 to 2.4 V. Floating Level Test 4. The bad level will be the range between your logic 0 and logic 1 readings. As you will see in later
experiments, an external unconnected input to an IC will fall in the floating level range, so-called because all inputs would normally be connected to the output of another IC, and IC outputs should be at a logic 1 or O. When you detect a bad level while troubleshooting a circuit, it usually indicates an open output of the IC that is driving that point. CMOS Tests 5. Now switch the TTL/CMOS switch to CMOS. Repeat the three tests above (logic 0, logic 1, bad level). The LOW logic voltage should be in the range of 1.0 to 1.7 V. The HIGH logic voltage should be in the range of 3.1 to 4.0 V. The bad level is the range between the HIGH and LOW logic levels. The logic probe TTL levels are fixed, and CMOS levels track the power supply voltage to which the probe is connected. Single Pulse Test 6. Switch the TTL/CMOS switch to TTL. Set the logic probe to the memory mode. Connect the logic probe as shown in Figure 2-2(b). Press the positive-pulse output, and observe with the logic probe. The memory indicator should come on. Clear
+5 V
Logic probe
(a) Setup for measuring logic level threshold
Trainer Pulse output
_r!
L..J
jI
Positive pulse
A >------Cf
Negative pulse
A
Clock ouput
>------0'
Pulse mode
A>------Cf I kHz
Note:
FIGURE 2-2
Power and ground leads of probe are not shown.
(b) Setup for measuring pulse and clock
Copyright
© 1994 by Merrill Publishing Company,
Publishing Company.
+5
v
Pulser power and ground leads are
r-----~------L_~~
c o
E
_~L.__L~~
not shown
Pulser
Move scope. probe. and pulser together to all five positions.
(a) Functional test of pulser
Trainer Logic switch
o
FIGURE 2-3
Measure for both logic and logic I.
(b) Functional test of logic switches
the indication. Next, apply a negative-pulse output to the logic probe. Again, the memory indicator should come on. You should find this means of detecting single pulses much more convenient than using the scope. You should have noticed that the indicator came on for either a HIGH or a LOW level change.
Logic Pulser
9. The purpose of the next part of the experiment is to point out some of the key features of the logic probe and logic pulser. Refer to Figure 2-3(a) for this discussion. First connect the logic probe, logic pulser, and scope to point C. Remember to connect power and ground to the logic pulser and logic probe. The measurements you make at this point will give you the best idea of how the logic pulser operates. Press the logic pulser pushbutton for continuous pulses while observing the scope, and plot the waveform in Plot 1. On the plot, be sure to mark where your O-V level is, and record your scope settings in the space provided. You should note that the logic pulser is able to pull the DC level down to a logic 0 and up to a logic 1. Each pulse should have a width of approximately 10 u.s. Also, you should note that the logic probe changes from a bad level to a logic LOW. (The response to a pulser on a bad level will vary from probe type to probe type.)
Pulse Test
7. Set the logic probe back to normal or nonmemory mode. Press the positive-pulse output, and observe the logic probe. You should see the logic probe indicator flash on (approximately 50 to 100 ms). Next, apply a negative-pulse output to the logic probe. In this case the negative pulse will cause the LED to switch off.
Clock Test
8. Move the logic probe to the I-kHz clock output, and observe the indication. Pulsating inputs should cause the LED to flash at approximately a IO-Hz rate.
10
Vertical deflection
= =
_ _
Vertical deflection
=
=
PLOTt Point c.
PLOT 3 PointB.
Vertical deflection
= =
_ _
Vertical deflection
= =
_ _
PLOT 4 Points A and E.
PLOT 2 PointD.
1 momentarily. With this capability you can test for both states (0 and 1) of the circuit. Draw the scope waveform on Plot 2, and record your scope readings.
Pulser Test on Logic 0

10. Next measure point D, and repeat the same steps. Here you should have seen that the logic pulser will pull up the logic 0 to a logic HIGH and cause the logic probe to flash on. This feature is a very important one, because you can pull up a 0 and force it to a
Pulser Test on Logic 1

11. Repeat the above tests on point B. In this test, the logic pulser will pull the logic 1 down and the logic probe will blink off. Again, you have been able to force a logic level to the opposite state and at
11
the same time observe this change with the logic probe. Plot the scope waveform on Plot 3. and record your readings.
Tests for Shorts

12. Next repeat the measurements on points A and E. If the logic pulser and logic probe are connected to a line that is direct to Vee or ground, then the logic pulser cannot cause the level to change to
the opposite state. This troubleshooting feature is very important, because you can tell immediately if a circuit point is shorted to Vee or ground. You would then begin looking for shorts (e.g., solder bridges) instead of looking for defective ICs. Draw the scope waveforms of the measurements of points A and Eon Plot 4. Label each trace accordingly, and record the deflections.
EXERCISES
1. Place the switch in Figure 2-3(b) in the logic 1 position. Using the logic probe and logic pulser, determine if the logic switch output of your logic trainer is connected directly to Vee or the logic 1 output of an IC. Do the same for a logic 0, and determine if the switch output is connected to ground or the logic output of an K'.
2. For the logic probe you are using, what type of indication should you get for a nonsymmetrical pulse train with a duty cycle that is more positive than negative? Also, describe the indication when the duty cycle is more negative than positive.
3. Some power supplies have an "overcurrent" protection feature that causes the output voltage to be reduced if the output current exceeds the rated amount. Explain how a power supply with this feature is similar to the logic pulser when it is connected to Vee or ground.
12
Copyright © 1994 by Merrill Publishing Company. an imprint of Macmillan Publishing Company.
3
Logic Inverter
OBJECTIVES
The logic inverter is a digital device that enables you to convert active-HIGH signals to active-LOW signals and vice versa. After performing this experiment, you will be able to: o Describe the function of the inverter. o Troubleshoot the inverter.
REFERENCE READING
Floyd, Digital Fundamentals, The Inverter 5th ed., Section 3-1,
MATERIALS NEEDED
7404 hex inverter Logic trainer Logic probe Logic pulser
DISCUSSION
In this experiment you will be using a typical TTL IC to demonstrate the functions of the logic inverter. This IC and others in this manual are housed in a DIP. Refer to your data book to determine the pin assignments for each logical element. The mechanical section of the data book indicates the way the pins are numbered. Pin I is indexed in several different ways, such as a dot, indentation, or notch. Figure 3-1(a) shows the logic diagram and the physical pin connections for the 7404 hex inverter.
This IC contains six identical and independent logic inverters. The circuit drawings for the experiments in this manual will give only the logic symbol and not the pin numbers. You will have to look up the pin numbers in your data book and mark them on the schematic. However, you will find this a useful exercise, because you will become more familiar with the data sheets. Figure 3-1 (b) shows a logic diagram with the pin numbers given. Warning: When you are making pin assignments on a schematic, be sure to keep track of which logical elements (such as an inverter) you have used. It is very easy to assign seven or more inverters in an IC that contains only six to begin with. Figure 3-1 (c) shows the input and output relationships for the inverter. Notice the use of the bubble (the small circle). The bubble indicates an activeLOW, and the absence of the bubble indicates an active-HIGH. Also, because the inputs and outputs of an inverter are opposite logic levels, the inverter is said to complement a variable. Observe in Figure 3-I(c) that the "bar" over the variable name (A) is used to indicate the variable's complement form (A). The inverter is also called a NOT circuit. Therefore the inverter can be used to convert an active-LOW signal to an active-HIGH signal and vice versa.
PROCEDURE
1. Install the 7404 inverter IC on the breadboard in the logic trainer. Connect pin 14 to + 5 V and pin 7 to ground (GND) as indicated in Figure 3-2(a). When the IC is installed in the breadboard,
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13
FIGURE 3-1
Inverter.
3. Apply the logic levels to the input as shown in the truth table of Figure 3-1; verify each output condition against the table. Notice what the output is before connecting the input. You should notice that the open connection has the same effect as a logic 1. 4. Repeat Step 3 for all six inverters. 5. To determine the effect of one inverter driving another, connect two inverters in cascade as shown in Figure 3-2(b), then complete Table 3-1.
TABLE 3-1 Switch A
1
(a) Top view of Hex inverter showing pin assignments
GN[
Display LJ
0
12
'--
....:5--1G,
C>o...:::6 __
(b) Typical circuit with pin assignments
Input
A
(I)
Output _
A
(0)
(0)
A--{>-A
(I)
(HIGH)
(LOW)
(LOW)
(HIGH)
A ">, NOT symbol
A-V--Y
Input A
Y=A
Truth table for inverter Output Y
A is active - HIGH.
A is active - LOW.
A LOW output should have been measured when the switch input was LOW. 6. This step produces a result that may surprise you. Connect the output from the second inverter G2 to the input of inverter G1 as shown in Figure 3-2(c). Set switch A to 0 (LOW), and connect it to point X momentarily as shown. LI should be OFF. Now move the switch A output to point Y momentarily; LI should now be ON. Notice that the circuit remains in the state in which it was last set and that a LOW must be applied to the output that is HIGH to make it change its state. This circuit, called a latch, will be discussed in detail later; it is the basis for the memory devices covered later in this manual.
(c) Input-output relationships
TROUBLESHOOTING
One of the ways you can verify the proper operation of an inverter is to perform Steps 1 through 4 in the preceding Procedure. This method is called static testing . You will now demonstrate how the logic pulser and logic probe can be used to troubleshoot an inverter circuit. 1. Connect the circuit shown in Figure 3-3(a). With data switch A in the LOW position, use the logic probe to measure points A through E. You should verify that the output state of each inverter is opposite the input state. 2. Repeat Step 1 with data switch A in the HIGH position. 3. Keep data switch A in the HIGH position. Now connect the probe and pulser to point A. Monitor the probe as the pulser is activated. (Note: Some models of logic trainers have switches that connect directly to ground or + 5 V.
(LOW) I (HIGH)
I (HIGH) (LOW)
there will be four remaining holes in the row next to each pin in which to place a wire. It will make troubleshooting easier if the two holes next to the Ie pin are left empty. 2. Connect one of the inverters as shown in Figure 3-2(a). The input will come from data switch A, and the output will be displayed on indicator LJ of the logic trainer. In the logic trainer used in this manual, a logic HIGH will tum ON the indicator LED, and a logic LOW will turn OFF the LED.
14
Copyright © 1994 by Menill Publishing Company. an imprint of Macmillan Publishing Company. All rights reserved.
HIGH = I LOW - 0 Data switch
Display G, L,
Note: Logic I (HIGH) turns display L, ON. Logic 0 (LOW) turns display L, OFF.
(a) Inverter test
Data switch
L,
(b) Double inversion
r-
_ X_
Data switch
",~~~~ILL_, ~
A
G,. G, = 7404
A momentary LOW at point Y keeps L, ON. A momentary LOW at point X keeps L, OFF. A = 0 (LOW)
FIGURE 3--2
(c) Latch circuit using inverters
The logic pulser will not be able to pull direct connections up or down. You should recall from an earlier experiment that the logic probe will not blink when the logic pulser injects a signal directly to a + 5-V power or ground connection. In fact, direct connections are detected by this method.) If the probe does blink, then move it to the other points B through E. 4. Now move the pulser and probe to point B. The pulser should be able to force the logic level of the inverter output to the opposite state. You will be able to observe this logic level change by noticing that the logic probe will blink at points B through E. Now move the probe to points B through E while you inject a signal at point B with the pulser. Notice that this technique will allow you to check out the entire circuit without changing the state of data switch A. This capability is important because many times it will be inconvenient or impossible to alter the state of the circuit. You should begin to see how valuable the logic pulser and probe are as a troubleshooting team. 5. Repeat Steps 3 and 4 with data switch A in the LOW position. 6. There are two inverters not used in Figure 3-3. Use the logic probe to monitor their inputs. The probe should produce a DIM indication. (This indication varies with different models of logic probes.) This DIM indication means that this input is open.
Now read the outputs of these inverters. The LOW output means. that the open input will act effectively as a HIGH input. 7. The next step is to introduce a fault in Figure 3-3 and then use the logic probe and pulser to detect this fault. First, put data switch A in the HIGH position, and observe displays LI and L2• You should note that LI is OFF and L2 is ON. Now at point C remove the jumper that connects the output of G2 to the input of G 3; observe the state of the displays. You should notice that the displays do not change when the jumper is removed. Because the open input has the effect of a HIGH, no error condition has been detected yet. 8. Next, put data switch A in the LOW position (with the jumper still removed), and again observe the displays. You should now observe that the LI display is in the wrong state (LOW); LI should be HIGH for a properly wired circuit. Because the L2 display is still correct, you do not need to troubleshoot this part of the circuit. Now place the logic probe on the input of G3• It should be DIM, indicating that an open connection has been located. Next, measure the output of G2• The output of G2 should indicate LOW. Because the output of G2 is LOW and the input of G3 indicates an open input, the measurements indicate that there is an open connection between G2 and G3•
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15
Data switch
Display A f-L-----'-r--I
(a) Troubleshooting
inverters G,-G, 7404

=
Input
o _j
II
t
U
I
I
linn U L____j
I
I
I
I
II
II
L __Time
II
II
(b) Timing diagram for Exercise 4

I
Output
FIGURE 3-3
Complete the waveforms.
Notes To emphasize the operation of the inverter, we bypassed some of the usual steps in troubleshooting. Of course, one of the main objectives of these experiments is to develop a systematic procedure for locating a problem. Refer to Appendix A, "Systematic Approach to Troubleshooting Digital and Microcomputer Systems." As this Appendix points out, one of
the first steps you should perform is to verify that the power is properly connected. You do so by measuring the voltage directly on the power pins. Do not depend on a visual check. Then measure the outputs of each gate to determine if the outputs are correct based on the inputs being applied. Also, remember that all combinations must be tested (whenever this is feasible) to ensure that the fault will be detected.
EXERCISES
1. In Figure 3-3 (a) , G, is shown driving two other inverters. What is the maximum number of inverters that can be driven by one inverter? The maximum number of similar gates that a gate can drive and maintain its output is calledfan-out. (Refer to the TTL data sheets.)
2. Would there ever be a logical reason for two inverters to be cascaded (such as shown in Figure 3-3)? When would you cascade two inverters? Consider Exercise 1 in your answer.
16
3. If in Figure 3-3 we give point B the variable name UP, what will be the names of the other points in the circuit? (Note: The complement of a variable is represented by a "bar" over the name.) Also, if point B is LOW, what will be the states of the other points?
4. Draw the output waveform of an inverter with the signal of Figure 3-3(b) applied to the input.
5. In Figure 3-3, neither L, nor L2 reads correctly. Which inverter (G1 through G 4) or other possible problem do you suspect?
Notes In the space remaining, respond to the following: 1. Results that differed from expected. 2. Possible explanations.
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17
4
AND/NAND LogicGates
OBJECTIVES
In digital electronics, the AND gate provides an active-HIGH output only when ALL of the inputs are active-HIGH. After performing this experiment, you will be able to: D Explain how the AND gate works. D Explain how the NAND gate works. D Troubleshoot both the AND and the NAND gates.
REFERENCE READING
Floyd, Digital Fundamentals, 5th ed., Section 3-2, The AND Gate; Section 3-4, The NAND Gate
MATERIALS NEEDED
Logic trainer 7408 AND gate 7400 NAND gate 7404 inverter Logic pulser Logic probe
The same logic applies for AND gates with more than two inputs. For example, Figure 4-1(b) is a 3-input AND gate; the timing diagram, truth table, and logic expression are shown. Notice that the number of entries for a truth table doubles with each additional input. The NAND gate is equivalent to an AND gate followed by an inverter, as shown in Figure 4-1(c); the timing diagram, truth table, and logic expression are shown for a 2-input NAND gate. Therefore, the NAND gate can be used whenever an active-LOW output is required. The NAND gate provides an active-LOW output only when ALL of the inputs are active-HIGH. This statement necessarily implies that the NAND gate will provide an active-HIGH output when ANY of the inputs are active-LOW. It also follows that the truth table for a 3-input NAND gate is the same as the truth table for a 3-input AND gate but with all outputs inverted.
PROCEDURE
1. Install the 7408 two-input AND gate on the logic trainer breadboard. Refer to your data book to determine the pin connections for each of the four AND gates. Connect +5 V to pin 14 and GND to pin 7. 2. Select one of the four gates in the IC, and write the pin numbers on Figure 4-2(a). Now connect the circuit as shown. 3. Operate data switch A and data switch B as shown in the truth table of Figure 4-1(a), and note the indications. Do the results agree with the truth table?
DISCUSSION
The AND gate provides an active-HIGH output only when ALL of the inputs are active-HIGH. This statement necessarily implies that the AND gate will provide an active-LOW output when ANY of the inputs are active-LOW. Figure 4-1 (a) shows the logic symbol, sample timing diagram, truth table, and logic expression for a 2-input AND gate.
19
Timing diagram A
------I\____
Truth table Inputs A 0 0 I I B 0 I 0
I
B~ymbol B
Output X 0 0 0 I
Period when ALL inputs are HIGH
Logic expression: X = AB reads "X equals A AND B." (a) 2-input AND gate
Timing diagram A~ B~X C Logic symbol Truth table Inputs A 0 0 0 0 I I I I I B 0 0 I I 0 0 0 I I C 0 I 0 I 0 0 I 0 I Output X 0 0 0 0 0 0 0 0 I X
Jpr
I
I
I I
I I
I I
I I
I I
I I
iod when ANY input is LQ~ I ! L i I I
T
Logic expression: X
Period when ALL inputs are HfGH
ABC reads "X
A AND BAND
C"
(b) 3-input AND gate
~==D'::~bol
Truth table Inputs A 0 0
I
Bubble indicates inverted output.
Timing diagram
L
B X
Output X I I I 0
B 0 I 0 I
Logic expression: X
7VJ reads
"X
NOT (A AND B)."
FIGURE 4-1
(c) 2-input NAND gate
4. Connect the circuit as shown in Figure 4-2(b). Again, make your own pin assignments, and write them in the figure. This experiment illustrates the gating action of the AND gate. Note the condition of the display before the button is depressed (OFF), and enter the condition of LI in Table 4-1. Also, note the
condition of the display when the button is depressed (ON), and record the condition in Table 4-1. Compare your results with the timing diagram of Figure 4-2(b). S. Next, install the 7400 two-input NAND gate on the breadboard, and again refer to the data book
20
Data switches A B
Display )-'X":"___---1L, G, = 7408 A I indicates that display L, is ON. ~ A 0 indicates that L, IS OFF. Display Clock
A
(a) 2-input AND gate
x
(b) AND gating action Timing diagram
G, = 7400 Data switches A f---_' B

b-----I
Truth table for AND/NAND Display

L, A
Inputs B 0
I
AND X 0 0 0
I
NAND X
I I I
= AB
0 0
I I
0
I
(c) 2-input NAND
Clock Display L,
Timing diagram
FIGURE 4-2
(d) NAND gating action
for the pin connections. Connect the circuit as shown in Figure 4-2( c). Did you remember + 5 V and ground? 6. 0 rate data switch A and data switch B as shown in able 4-2, and record the indications. You should no ice that the logic function being performed is the NA D function. 7. 0 serve from Table 4-2 that when both inputs are IGH (ON), the output is LOW. Also, observe tha when both inputs are LOW (OFF), the output is IGH. Therefore, you could use the NAND
TABLE 4Display LI Condition
as an inverter by tying both inputs together . You might do this when you have a spare NAND gate but not an inverter. 8. Now connect the 7400 NAND gate as shown in Figure 4-2(d). Perform the operations in Table 4-3, and record your results. You should notice that
TABLE 4-2
Data Switches A
Display LI Condition
OFF
Pushbutton A
OFF ON OFF ON
(ON/OFF) OFF ON
OFF ON ON
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21
TABLE 4-3
Display LI Condition
TABLE 4-4
Pushbutton
Inputs A B LI before Short LI after Short
(ON/OFF) OFF
0 ON 0
1
0
1
0
1
the output of the NAND gate is an exact inversion of the output of the AND gate.
TROUBLESHOOTING
You will now apply your knowledge about AND/ NAND gates and the logic probe and pulser to troubleshoot several types of faults. 1. First, connect the circuit as shown in Figure 4-3. Notice that the fault is a jumper between the two input pins. As you might expect, shorts between adjacent pins are a common occurrence. For example, in printed circuit (PC) boards, a short of this type happens when there is a solder bridge between pins. Other causes of shorts between pins are conductive materials or other foreign particles. 2. Before you install the fault (jumper), make your entries in Table 4-4. Then install the jumper and complete the table. Notes With the fault-jumper installed, the outputs of G1 and G2 are connected together. Normally, outputs of ICs should never be connected together unless the IC is specifically designed for that purpose. Such devices are covered in a later experiment. You may have wondered what the purpose of inverters G1 and G2 is. These inverters prevent the outputs of the switches from being connected together when the fault-jumper is installed. Because the short between inputs also connects the inverter outputs together, you will see what the outcome is when one of the outputs is trying to produce a HIGH and other other output is trying to pro-
duce a LOW. The result of two outputs driving in opposite directions (for example, one HIGH and one LOW) is that the LOW output will usually override the HIGH output. This information should help you explain why the truth table is still satisfied with the fault installed. Even though the truth table is satisfied, a serious problem can result when the outputs of G1 and G2 are tied together: if the outputs of either G1 or G2 are connected to other circuits, then this fault will appear in these other circuits. The point is that even though the output of the AND gate appears normal, you should also check the inputs. To check the inputs, apply the pulser to one of the inputs of G3 and move the probe to the other input. Now you can see that there is interaction between the two inputs (which should not happen). This interaction is the error indication, and therefore you have now isolated the problem. 3. To demonstrate the next fault, reconnect the circuit as shown in Figure 4-2(b). Before proceeding, verify that the circuit is operating normally. Now continue with Figure 4-2(b) , and create the next fault by removing the jumper between pushbutton A and the AND gate (G1) input. Now you should notice that the switch has no effect on the operation of the circuit. You should also notice that display L, is still blinking. Thus, the other input is always a 1. Keep in mind that a 1 on an input of a 2-input AND (or NAND) gate will cause the output state of the AND to be the same as the other input state (inverted for the NAND).
Sholt
Data switches
Display L, G, = 7408 G G, = 7404 "
FIGURE 4-3
Troubleshooting.
22
+5 V R
A
B
(a)
y=----
You should be able to isolate the problem of an open connection by using the logic probe only. When you check the input of G3, you should get a DIM indication from the probe, which means an open connection. You should next verify that the output of pushbutton switch A is good. When you have done this, your problem is isolated.
A__ i L9.ESer
u
B~
L_~ (b)
'
Sketch
the logic element.
. Inputs
I:
X
=
Output
-----"0
_ (c)
Inputs
B= X=
°
(d)
Complete the waveforms.
Output
FIGURE 4-4
EXERCISES
1. Given that you have only inverters and NAND gates, draw a circuit showing how you would create the AND function.
2. How many entries are there in a truth table for a 4-input AND gate?
3. What logical function does the circuit of Figure 4-4(a) perform?
23
4. The Ie shown in Figure 4-4(b) requires an active-LOW RESET signal when two other signals (called A and B) are active-HIGH. Sketch the logic element that will perform this function.
5. Using only 2-input AND gates, draw a circuit that will perform the function X = ABeD.
6. Draw the output for the two inputs shown in Figure 4-4(c) if an AND gate is used.
7. Draw the B input that will produce the X output shown in Figure 4-4(d) if a NAND gate is used.
24
5
OR/NOR Logic Gates
OBJECTIVES
In digital electronics, the OR gate performs the function of providing an active-HIGH output when one or more of the inputs are active-HIGH. After performing this experiment, you will be able to: o Describe how the OR gate works. o Describe how the NOR gate works. o Troubleshoot both the OR and the NOR gates.
REFERENCE READING
Floyd, Digital Fundamentals, 5th ed., Section 3-3, The OR Gate; Section 3-5, The NOR Gate; Section 3-7, IC Logic Families
MATERIALS NEEDED
Logic trainer 7432 OR gate 7402 NOR gate Logic pulser Logic probe
This logic can be extended for OR gates with more than two inputs. For example, Figure 5-1(b) illustrates a 3-input OR gate and its truth table. Notice that twice as many entries are required for the 3-input gate as for the 2-input gate. For every additional input, the number of entries doubles. Thus, the number of possible combinations at the inputs of the gate doubles with each additional input. The NOR gate is equivalent to an OR gate with its output inverted, as shown in Figure 5-l(c). Therefore the NOR gate can be used whenever an activeLOW output is required. The NOR gate provides an active-LOW output when one or more of the inputs are active-HIGH. This statement necessarily implies that the NOR gate will provide an active-HIGH output only when ALL of the inputs are active-LOW. Again, you should verify these statements by checking the entries in the truth table. The logic symbol, truth table, timing diagram, and logic expression for the 2-input NOR gate are shown in Figure 5-1 (c).
DISCUSSION
The OR gate provides an active-HIGH output when one or more of the inputs are active-HIGH. This statement necessarily implies that the OR gate will provide an active-LOW output when ALL of the inputs are active-LOW. Verify these statements by checking each entry in the truth table shown in Figure 5-1(a), which also shows the logic symbol, logic expression, and timing diagram for the 2-input OR gate.
PROCEDURE OR Gate
1. Install the 7432 two-input OR gate on the breadboard. Refer to your data book to determine the pin connections for each of the four OR gates. Connect +5 V to pin 14 and GND to pin 7. 2. Select one of the four OR gates in the K'. Write these pin numbers on Figure 5-2(a), and connect the circuit as shown.
25
Timing diagram
A~X
=i.>
= =
A Logic symbol A + Breads A OR B." B
L
o o
Logic expression: X "X
X Truth table Inputs A 0 0 I I B 0 I 0 I Output X 0 I I I
IJ'-
_
ALL inputs LOW ANY input HIGH
(a) 2-input OR gate
Timing diagram
B A~
C
X
Logic symbol
Logic expression: X = A + B + C reads "X = A OR B OR C."
Truth table Inputs ABC 000 O0I 0I0 0II I00 I0I II0 III Output X 0-
J
/'
t- ALL inputs LOW
l-
ANY input HIGH
(b) 3-input OR gate
Timing diagram A ~ndicates B Logic expression: X = inversion X . Logic sym bo I
L
B
·x =
A+7i
reads NOT (A OR B)."
Truth Table Inputs A 0 0 I I B 0 I 0 I Output X I 0 0 0
x~l~, ~~~
(C) 2-input NOR gate
ALL inputs LOW ANY input HIGH
FIGURE5-!
26
Data switches
Display A B (a) 2-input OR

)-X __ ---1 L,
G, = 7432
Display X L,
it
X
(b) OR gating action
Data switches
Display L,
G, = 7402
B X=A+B
(c) 2-input NOR
Display
)o-----1L,
(d) NOR gating action
D
~
Period when ANY input is HIGH Period when ALL inputs are LOW
FIGURES-2
3. Operate data switch A and data switch B as shown in the truth table, and record the indication. The results should agree with the truth table in Figure
5-1(a).
NOR Gate 5. Next, install the 7402 two-input NOR gate on the breadboard, and again, get the pin numbers from your data book. Connect the circuit as shown in Figure 5-2(c). Did you remember +5 V and GND? 6. Operate data switch A and data switch B as shown in the truth table of Figure 5-l(c), and record the indications. You should note that the logical NOR function is being performed. 7. In the previous step, you should have noted that the output was LOW when both inputs were HIGH and that the output was HIGH when both inputs were LOW. Therefore if necessary, you could use the 2-input NOR as an inverter if you connected both inputs together. 8. Now connect the 7402 NOR gate as shown in Figure 5-2(d). Notice the condition of the display
4. Now connect the circuit as shown in Figure 5-2(b). Again, make your own pin assignments, and write them in the figure. This experiment illustrates the gating action of the OR gate. Notice that the active-LOW (pushbutton A) is used; thus, the condition of pushbutton A is HIGH before the button is depressed. You should have noted that the display (the output of the OR gate) was ON before the button was depressed. As you can see from the truth table, a HIGH input on an OR gate always forces the output HIGH. When used as a gate, the OR gate is disabled in this condition. Then you should have noted that the display was blinking when the pushbutton was depressed, indicating that the gate was enabled.
27
(output of the NOR gate) before the button is depressed and while the button is depressed. You should note that the clock signal is inverted after going through the NOR gate. If the output of the NOR gate is used to drive the input of another IC, then this input must be active-LOW.
Internal Input Open

5. For the next situation, assume that the open connection is internal to Gland therefore the measurement on the input pin will not indicate a floating line (open). Because this is a NOR, the internal open (which acts like a 1) will force the output LOW. (Refer to the truth table to confirm this.) Therefore action on the input, even with the pulser, will not cause the output to change. Remember that in the previous experiment you were able to detect an internal open input on the AND/NAND gate. For the OR or the NOR gate, however, there is no single test that determines if the input of the gate is open. A LOW output that cannot be changed by any combination of input conditions is said to be stuck at zero. The internal open input on an OR or a NOR gate cannot be distinguished from an internal output shorted to ground. Therefore if the fault is an internal open input on an OR or a NOR gate, we must first prove that no other faults are causing the output node to be stuck at zero. In other words, the Type 4 fault, as indicated in Figure 5-3, cannot be isolated by a single test. A node can be stuck LOW by anyone of the four types of faults; however, there are only tests for Types 1, 2, and 3. These three types of faults must be tested for and eliminated before a Type 4 fault in G 1 can be assumed. To illustrate the procedure, you will use the circuit shown in Figure 5-3. 6. How do you proceed from here? You are now aware that several different faults could cause the output to stay LOW. To simplify the explanation, we will assume that power and ground voltages have been checked at the proper pins and that all displays and switches are known to be good. The four remaining types of faults are as follows: Type 1. A direct external short to ground on some point of the connection node. Type 2. An internal-input short to ground in any of the gates that are connected to the node. Type 3. A short to an adjacent node that is LOW. Type 4. An internal-output short to ground in the gate dri ving this node. Recall that an internal open input will also cause the output of a NOR gate to be LOW. These four failure types are marked on Figure 5-3. It is important to test for each failure type in the sequence that follows. In the example shown in Figure 5-3, the only fault that is to be installed is Type 3. The other faults that are shown are for purposes of illustration and discussion only!
TROUBLESHOOTING
You will now use the logic probe and pulser along with your knowledge of logic gates to troubleshoot several types of faults. When troubleshooting, always keep in mind that there are usually a number of faults that can cause the same error condition. You will see this illustrated in the steps that follow. You should refer to the "Troubleshooting Flow Chart" Digital and Microcomputing Systems in the Appendix while performing the following steps.
External Input Open

1. First, reconnect the NOR gate circuit exactly as you did in Figure 5-2(c), and verify that it is functioning correctly. Now remove the jumper from data switch A to the input of G l' and repeat the checkout as before. You should note that the L, display did not come on. 2. You must assume that your troubleshooting begins at this point and forget that everything worked before you removed the jumper. The first thing you must do is to place the switches in the condition that should cause the display to come on. You should recall that both data switch A and data switch B must be LOW to cause L I to come ON. Because you will normally be starting from the incorrect output and working back toward the inputs, you should first check the output of G1; it should be HIGH. 3. Verify that the signals are getting to G1 by measuring with the logic probe right on the input pins of G1. What is the indication on the logic probe? The logic probe indicates an open condition, so you have quickly found the fault as the logic probe can detect an external open connection between gates. You should recall that a DIM indication (or floater) is caused by an open connection between the driver gate or switch output and the point of measurement. (Note: The indication for an OPEN will vary with each logic probe manufacturer. Always refer to the operating instructions for the probe you are using.) 4. Now check the output of data switch A. What indication do you get? Because the logic probe indicates a definite LOW, you know that the fault is an open connection between the switch and the G1 input. This is so because the switch output is good and the logic probe indicates an open connection.
28
Data switches
A 1-..::0_--1 B 1-"0_---1
ground
FIGURES-3 Logic probe and pulser positions to detect different failures for a node stuck LOW.
Short to adjacent node
+--' To other inputs G,-G. = 7402
Type 1: External Short to Ground

7. Connect the logic probe to the output pin of G1• What is the indication on the logic probe? Because both inputs of the NOR gate G1 are LOW, the output should be HIGH. If it is LOW, then you call this condition stuck at zero. The first thing you would like to find out is if this LOW is a direct connection to ground or one of the other failure types. 8. Next, connect the logic probe and pulser as shown in the Type I test in Figure 5-3. What is the indication this time? If there had been a direct connection to GND, then the pulser would not have been able to pull the line (node) up and cause the probe to blink. Therefore you conclude that the failure is not a Type I failure.
indicating that G2 is good. If there had been a real internal short to ground on the input of G2, then the output would not have responded. Because the node is still LOW, the problem must be another failure type.
Type 3: Short to Adjacent Node

11. For the next failure type, observe the connection of the output of G) to the node being tested. This connection is the real fault you have installed in this example. Because the inputs to the NOR gate G) are open, the output will be driven LOW. It is this LOW that is causing the problem in your circuit. You have also seen that the logic pulser can pull up an output that is in the LOW state. For illustration, the G) output connection to the node can be considered as the short-to-adjacent-node fault (which, in fact, it is). A method of detection for this fault is to apply the pulser to the stuck LOW node, move the logic probe to adjacent pins, and observe if any pulse activity is occurring on them. See the Type 3 test setup shown in Figure 5-3. When you find an adjacent pin that is pulsing at the rate of the logic pulser, you will have "discovered" the short.
Type 2: Internal-Input Short to Ground

9. Observe the internal fault (short to ground) illustrated in NOR gate G2. Notice that a resistance is shown between the input and ground. This resistor represents the amount of resistance that is present when an input shorts to ground (usually approximately 50 0). The logic pulser will be able to pull up this type of failure, whereas it would not be able to pull up the previous direct short-to-ground failure type. 10. To detect this type of failure, arrange the logic probe and pulser as shown in Figure 5-3 for the Type 2 failure. Notice that the other input of the NOR gate G2 must be LOW. Now when the pulser is activated, the logic probe on the output of G2 will blink,
Type 4: Internal-Output Short to Ground

12. It is very important to understand that you should test for the first three types of faults before assuming that G1 is bad. If there are any other gates (such as G 2) connected to the output of G I' then they
29
also must be tested before G1 is replaced. In brief, a failure in G1 can be determined only by a process of elimination when its output is stuck LOW. (A similar procedure is used if the node is stuck HIGH). There are, in fact, several internal faults that could cause the NOR gate G1 to hold the output down. Because we have to replace the IC in any case, the actual fault
does not matter to you. You have seen now that there are several faults that can cause the same indications but that you can use a systematic method for determining which fault it is. The "Troubleshooting Flow Chart" in the Appendix should help you follow this sequence.
EXERCISES
1. Given that you have only 2-input, 7402 NOR gates, draw a circuit that will perform a 3-input NOR gate function. Use a truth table to verify your answer.
2. Using the input signals A and B, complete the output waveforms for each gate shown in Figure 5-4(a).
-A
-----
;=G>~=G>(a)
-8
X=
I 0 Complete the waveforms,
X=
X=
___J
:--------~,
I I I
I
~
Complete the circuit.
___J 'I
I I
I
..JI
(c)
FIGURE 5-4
30
3. What logic function does the circuit of Figure 5-4(b) perform?
4. In Figure 5-4(c), complete the circuit that will provide an active-LOW reset signal for Figure 5-4(c) when any of two signals are active-HIGH.
5. Assume that you need to use a 2-input OR gate in a circuit but that you have only a 3-input OR gate available. Show how you would connect the 3-input OR gate, and indicate how the unused input should be connected.
Publishing Company.
31
6
CMOS Logic Gates
OBJECTIVES
Another widely used logic family that has major advantages in low-power, low-speed applications is the CMOS (complementary metal-oxide semiconductor). After completion of this experiment, you will be able to: D Use a typical CMOS NOR gate. D Handle CMOS devices in a proper manner. D Interface CMOS and TTL devices. D Troubleshoot these devices.
ment, the CMOS logic is finding wide use. The speed of operation is approximately 1/3 that of standard TTL, but power consumption is approximately '/1000. With the introduction of the S4174C line, most of the functions available in TTL are duplicated in CMOS. Thus, in certain cases a TTL AND gate IC is pin-for-pin compatible with a CMOS AND gate IC. Special Precautions Because the oxide layer in the CMOS device is so thin, special precautions in handling are required to prevent static discharge through the gates of the device. Although all gates have internal protection, the following rules should be observed: I. Leads of the CMOS device should remain in contact with conductive foam until the device is ready to be used. 2. Ground both yourself and your tools before making contact with the CMOS parts. 3. Never insert or remove CMOS parts with the power on. 4. Never apply signals to an unpowered device. S. Always connect unused inputs to + Vee or GND (depending on the logic type). Interfacing The CMOS logic operates over a wide range of power supply voltages, from 3 V to IS V. Therefore CMOS can use the same + Vee (S V) as TTL. As shown in Figure 6-1, interfacing between CMOS and TTL can be direct when both are operated from a +S V supply. The 740S TTL device used is an open-collector inPublishing Company. All rights reserved.
REFERENCE READING
Floyd, Digital Fundamentals, Sth ed., Section 3-7, Integrated Circuit Logic Families
MATERIALS NEEDED
Logic trainer CD400IAE CMOS NOR gate 740S open-collector TTL inverter Two lO-kfl resistors Logic probe Logic pulser
DISCUSSION
The only logic family that we have discussed up to this point is TTL, which has great popularity because of its excellent tradeoff between speed and power consumption. However, where power consumption is critical and speed less so, as in certain portable equipCopyright © 1994 by Merrill Publishing Company.
33
FIGURE 6-1
(a) CMOS to TTL
(b) TTL to CMOS
verter that allows an external resistor to be connected from the open-collector output to Vcc- (This device will be covered in Experiment 27 on register files.) The HIGH output voltage level available from the open-collector will now exceed 4 V, a level necessary to drive the input of the CMOS device; a standard TTL HIGH output voltage is typically only 3.5 V. The output drive (current) of a typical CMOS device is less than that of a TTL device, so if more than one TTL gate must be driven, a special CMOS driver must be used. The logic probe and pulser will work equally well with CMOS devices. When testing CMOS, place the TTL-CMOS device-type switch on the logic pulser or probe to the CMOS position. Because of the slower switching speeds of the CMOS devices, the pulse widths are greater in the CMOS mode.
PROCEDURE
1. Install the CD4001AE and 7405 on the breadboard, observing the precautions described earlier. Refer to your data book for pin assignments, and mark them in Figure 6-2(a). Connect +5 V and GND to both ICs.
CMOS Driving TTL 2. With data switch A and data switch B, apply the inputs as shown in truth Table 6-1 , and record the indications. Notice that the combination of the G1 NOR gate followed by the G2 inverter produces the OR function.
+5 V Data switches 10 kG
A
Displays L,
(a) CMOS "toTTL
G, G,
= =
CD4001 7405
Data switches
~
___n_n_r
Displays L,
B f-------q
FIGURE 6-2
(b) TTL to CMOS
G, = CD4001 G,. G, = 7405
34
TABLE 6-1
Truth table for Figure 6-2(a).
TABLE 6-2
Truth table for Figure 6-2(b).
Data Switches A
Display Condition
Data Switches A
Display Condition
LI
LI
OFF OFF ON ON
OFF ON OFF ON
OFF OFF ON ON
OFF ON OFF ON
TTL Device Driving a CMOS Device 3. Next connect the circuit as shown in Figure 6-2(b). With data switch A and data switch B, apply the inputs as shown in truth Table 6-2, and record the indications of L1. What logic function is being performed? Recall that an AND gate will provide an active-LOW output for ANY active-LOW input. Therefore a 2-input AND gate would produce the same outputs for this truth table.
TROUBLESHOOTING
You will now use the logic probe and pulser to test the circuit of Figure 6-2(b). 1. Connect the pulser to the input of G2 and the probe to the output of G2• Did you recall that the pulser and probe TTL-CMOS switch should be in the TTL position? Notice that here the input and output are both TTL. Now move the probe to the output of G1, and put both the pulser and the probe in the
CMOS position. Observe the indication on the logic probe. Remember to place the data switches in a position so that the input of the NOR gate that is not being pulsed is LOW. Also, remember that a HIGH on any input of a NOR will keep the output LOW regardless of the other inputs. In a 2-input NOR gate, if one of the inputs is LOW, then the gate is considered enabled. Keep in mind that the pulser will not exercise a gate unless the other inputs are enabled. (There is a jumper accessory available with the pulser to permit it to drive several pins at a time.) One way to pulse both input pins simultaneously is to press the tip of the pulser between the adjacent input pins (e.g., pins 1 and 2). Now put data switch A and data switch B through all of the combinations, and verify that the output of G1 will blink for any of these combinations. 2. Next, move the pulser and probe to the output of G1• Observe the indication of the logic probe when the pulser is actuated. You should notice that the pulser is able to drive the output of a CMOS device to the state opposite its present output state.
EXERCISES
1. In the Discussion, it was stated that the CMOS inputs required a higher input
voltage (> 3.5 V) than is required by TTL (> 2.0 V). Would you consider this requirement an advantage or a disadvantage? Why?
2. Notice that in Figure 6-2(b) all of the inputs and outputs were active-LOW and the total circuit performed the AND function. If all the inputs and outputs of an AND gate were inverted, what function would be performed?
Copyright
© 1994 by Merrill Publishing
Company,
Publishing
Company.
35
3. What advantage would the wide power supply range (3 V to 15 V) of CMOS have in battery-operated equipment?
Notes In the remaining space, respond to the following: 1. Observations different from expected. 2. Possible explanations.
36
Copyright © 1994 by Merrill Publishing Company, an imprint of Macmillan Publishing Company. AU rights reserved.
7
Logic Gate Cha.racteristics
OBJECTIVES
In this experiment, the mechanical, electrical, and timing characteristics of the standard TIL logic family will be discussed. After completing this experiment, you will be able to: o Determine TIL power supply requirements. o Measure the input and output voltages for logiclevel signals. o Estimate propagation delays.
REFERENCE READING
Floyd, Digital Fundamentals, 5th ed., Section 1-2, Logic Levels and Digital Waveforms; Section 1-5, Digital Integrated Circuits
ment, the mechanical, electrical, and timing characteristics will be studied. Although only the TIL logic family will be covered, you will find that data sheets for other logic families are organized in a similar way. All of the experiments in this manual use the dual-in-line package (DIP). The number of pins in each package depends on the function performed. Most SSI (small-scale integration) is in a 14- or 16pin package. The spacing between pins is 0.1 inch regardless of the total number of pins. Refer to your data book for other mechanical details and an explanation of part number identification.
TTL DESIGNATIONS
IC manufacturers use a standardized numbering system that identifies the device type and the package type. A specific example illustrates the scheme. In SN 54LS75 J the following holds: SN = manufacturer's prefix 54 temperature range (74 [commercial] = 0 to 70°C; 54 [military] = -55 to 125°C) LS TIL family (LS = low-power Schottky; no letters = standard) 75 = logic function (75 = 4-bit latch) J package type (J = ceramic DIP; N = plastic DIP) Each of the families has specific characteristics that suit it for particular applications. The tradeoffs
MATERIALS NEEDED
Logic trainer 7408 Two-input AND gate 7404 inverter l-kf] potentiometer (pot) 270-fi resistor 6-kfi resistor Silicon diode Oscilloscope Digital voltmeter Logic probe
DISCUSSION
In the previous experiments, you used the basic logic gates to perform logical functions. In this experiCopyright © 1994 by Merrill Publishing Company,
37
Sink 1.6 rnA per connected input (a) Output sink and source currents
Source 40 fJ.A per connected input
Input pulse Rise time

(I,) 1---
Fall time (tf)
50% ------+I
1-----
Propagation delay (I,,,f)
Output pulse
o
FIGURE 7-1
level----
Time (b) Pulse parameters
are usually between switching speeds and power consumption. In general, the higher operating speeds require more power. However, the low-power Schottky series is functionally equivalent to the standard TTL, even in switching speed, while consuming less power. The digits following the family type specify the logic function. The range of these numbers is from 00 to over 300, with new numbers being continually added. Normally, the prefix and package identifiers are not included in a general discussion when a standard DIP is implied. For example, in this manual a device is called a 7408. Of course, this would not be complete enough when ordering from a manufacturer.
ELECTRICAL CHARACTERISTICS
Your data book also provides information about the electrical characteristics. In most cases, the characteristics of all of the logic functions are the same. For this reason, your data book provides one set of electrical characteristics that represents the entire family; however, the pin-outs for each device are given. A standard 7400 TTL gate requires a power supply voltage between 4.75 V and 5.25 V and a supply current of approximately 2 rnA.
A voltage of 0.8 V or less will pull a TTL input LOW. The driver IC must be able to sink as much as 1.6 rnA for each input that is pulled LOW. A voltage of 2.0 V or greater will force a TTL input HIGH. The driver IC must be able to deliver or source as much as 40 !-LA each input that is forced for HIGH. The voltages specified (0.8 V for a LOW and 2.0 V for a HIGH) are the input voltages applied to the gates when they are tested. Therefore any voltage above 0.8 V (for a LOW) and below 2.0 V (for a HIGH) will produce unpredictable results. Also, notice that the sink current (16 rnA) is much greater than the source current (400 !-LA).This difference indicates that the LOW -output condition can handle much greater currents than a HIGH output. A standard TTL output can drive up to 10 other standard TTL inputs, and the gate is said to have ajan-out of 10. To provide a margin of safety called noise margin, every gate must actually produce a LOW output of no more than 0.4 V and a HIGH output of at least 2.4 V when tested at the manufacturer. This gives a O.4-V noise margin between the output of a driving gate and the input of the receiving gate. The output sink and source currents are shown in Figure 7-1(a). The characteristic or parameter that determines speed (number of operations per second) is called
38
propagation delay, which is the time that it takes the output to respond to a change on the input. Figure 7-I(b) shows how propagation delay and some of the other important pulse measurements are defined. In the data sheets, the propagation delay is determined from the switching characteristics. Two measurements are usually given: the turn-on delay, and the turn-off delay. It takes approximately 10 to 25 ns for a change on the input to propagate to the output for standard TTL. This time determines the number of operations per second a computer or other digital system is able to perform.
V. This voltage is called voltage input LOW (V1L). Now connect the DVM to the output of G1, and record the voltage in the blank provided in the figure. This output voltage, called voltage output HIGH (V OH)' should be greater than 2.4 V. The 6-kO load resistor represents the load that 10 gates would require: 10 gates x 40 f.1A = 400 f.1A R = 2.4 V/400 f.1A = 6000 0 3. Connect the circuit as shown in Figure 7-2(b). Now connect the DVM to the input of G1, and adjust the pot to 2.0 V. This voltage is called voltage input HIGH (VlH). Next, connect the DVM to the output of G1, and record the output voltage in the blank provided in the figure. This output voltage, called voltage output LOW (VOL), should be less than 0.4 V. The 270-0 resistor approximates the load that 10 gates would require:
PROCEDURE
1. Connect the circuit as shown in Figure 7-2(a). Refer to your data book for pin connections. 2. Connect the digital voltmeter (DVM) to the input of G1, and adjust the potentiometer (pot) to 0.8
(a) Output HIGH test +5 V +5 V 270
>o--r--~
16 rnA
Must be less than 0.4 V

VOL
= _
DVM voltage = (b) Output LOW test
0.8 V 0.4V
--~-A-~-A-A--}
~. LOW output
____
Unacceptable noise
~~:;Ptable
2.4 V 2.0 V
-----~T-}
"/'0'1).
A.
--
Acceptable noise Unacceptable noise
L HIGH output
FIGURE 7-2
(c) Noise immunity
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Publishing Company.
39
Figure 7-3
-:
To external
trigger
(a) Circuit
G,-G, G"
= =
7404 7408
input
A B
I
I
:
I I I I ' I
--:
I I
:-I I
Total
propagation
delay
for 5 inverters
_ll
(b) Timing diagram
n_
I"
----
FIGURE 7-3
10 gates x 1.6 rnA 5.0 V - 0.7 V - 0.4 V R
16mA 3.9V 3.9 V/16 rnA
244
4. Notice that the tests described are made with a full load and with the worst-case input voltage. If the ICs do not pass all of these tests conducted by the manufacturer, they are rejected. Also, notice that for a logic LOW, the outputs must be less than 0.4 V, but a LOW input must work with 0.8 V applied. This 0.4- V difference is called LOW level noise immunity. Also, a logic HIGH output must produce more than 2.4 V, but a HIGH input must work with only 2.0 V applied. Again, this 0.4- V difference is called HIGH level noise immunity. Noise immunity is shown in Figure 7-2(c). The unacceptable noise spikes shown in Figure 7-2(c) become "glitches" on the output. The harm that these brief glitches might cause may not be apparent at this time, but if you recall, it only required a brief or momentary LOW at Point Y of Figure 3-2(c) to cause that circuit to change state. Thus, you can see that a single noise spike can cause a circuit to be switched to the wrong state. 5. What would happen if an intermediate voltage such as 1.4 V were applied to the input? To find out, adjust the pot to 1.4 V, and disconnect the load from the previous step. Place the logic probe on the output, and note the indication. If no pulse activity is observed, then readjust the pot while observing the logic probe. When activity is observed, record the DVM voltage where noted on the figure. This voltage is called the threshold voltage.
6. In the following steps of the Procedure, we will demonstrate the effects of propagation delay rather than try to measure it directly. The proper measurement of propagation delay requires equipment normally not available to educational laboratories. Connect the circuit as shown in Figure 7-3(a) using your data book to obtain the pin assignments. 7. Connect the loo-kHz clock to the external trigger input of the oscilloscope as shown. Now connect the scope probe directly to the clock, and adjust the scope until a stable and clear trace is obtained. You will normally be using the fastest sweep time available on your scope (approximately 0.1 us/em). At this sweep time, you are normally able to see only the leading edge of the clock signal. 8. Move the scope probe to each inverter output. You should observe the clock signal shifting to the right. Compare your results with the turn-on and turn-off times given in your data book. Notice that after an even number of inverters, the output of the inverter has the same polarity as does the clock, and after an odd number of inverters the polarity is reversed. The signal that you measure at point B should be similar to the one in the timing diagram of Figure 7-3(b). What is your estimate of the delay? You should get approximately 50 ns. 9. Next, connect the scope probe to point C of the diagram. Your indication should agree with the diagram. Such narrow pulses are called glitches. (Actually, this same type of circuit will be used in Experiment 20 when edge-triggered flip-flops are discussed.) Estimate and record the pulse width (tw) of this narrow pulse on the diagram. Now connect the
40
(a) Oscillator circuit
G,-G,
= 7404
_fU1__f1flfl__f
--I I- 5 gate delays
=
5 x 10 ns
I I f=-=--=IOMHz . T 100 ns
50 ns
Period = Frequency =
_ _
FIGURE 7-4
(b) Oscilloscope trace
logic probe to the output of G6 (point C). The pulse indication on the logic probe should come on. Notice that if you need to determine only whether a pulse is present, the logic probe is much easier to use than the oscilloscope. 10. Connect the circuit as shown in Figure 7-4(a). Use your data book to determine pin assignments. Set the scope to internal trigger and an approximately O.I-J.Lssweep time. Connect the scope probe to point A. Refer to Figure A-2 of the Appendix for examples of a good and some bad pulses. One of the causes of apparent bad pulses is improper test equipment connections. For example, to measure the pulses in Figure A-2, the oscilloscope must be in the DC mode and the ground lead connected to the circuit ground. 11. What are the period and the frequency of
this signal? Record your results on Figure 7-4(b). This type of circuit is called an oscillator. It is so named because the phase relationship of the output and input is such that when the output is connected to the input, the circuit continues to operate with no external input. You should get a period of approximately 100 ns (assuming 10 ns per inverter and remembering that the period consists of the time between identical points of successive pulses). Your scope indication may appear sinusoidal if the scope does not have an adequate bandwidth. 12. Now connect the logic probe to pointA, and observe the indication. As you can see, you can use the logic probe to detect high-frequency signals. The logic probe should indicate a blinking LED display for pulse trains.
EXERCISES
1. What is the difference between 74oo-series TTL and 54oo-series TTL?
2. DefineJan-out. What is the fan-out for a 5400 TTL gate?
3. What maximum current would be required for a standard TTL gate driving five TTL-inputs LOW? What would happen if 15 inputs were connected to the driver gate?
4. Repeat Exercise 3 for a logic HIGH.
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Company.
41
5. Define the following: (a) Turn-on delay (b) Turn-off delay (c) HIGH level noise margin
(d) LOW level noise margin
6. What should be done with the unused pins of gates?
7. Redraw the output signal (point C) of Figure 7-3 if four inverters are used instead of five.
8. If two outputs were accidentally connected together, what voltage would you expect to measure with one output driving HIGH and the other driving LOW?
9. Calculate the maximum current requirements for a 7404 inverter and a 7408 AND gate.
10. What would the estimated power requirement be for a circuit board with 25 TIL ICs mounted on it?
42
Copyright © 1994 by Merrill Publishing Company.
8
Logic Gate Applications
OBJECTIVES
Logic gates are used in circuits to perform logic functions. After completing this experiment, you will be able to: D Implement simple logic functions using gates. D Use clock and enable functions. D Use timing diagrams to determine timing relationships of variables. D Troubleshoot a short-between-nodes type of failure.
2. Both data lines are to be enabled by a single switch. 3. The data lines are to be clocked. 4. The circuit will be redrawn using the simplest logic form. 5. The circuit will be redrawn and then built using only NAND gates and inverters. First, you need to understand the new terms used in the problem. Data lines (when grouped) are signal lines that can represent information such as letters and numbers. Another type of signal line is a control line, such as the enable line required in this problem. A third type of signal line (also used in this problem) is the clock line. The purpose of the clock in this example is to gate the data only during the clock pulse time. One possible logic diagram to accomplish this requirement is shown in Figure 8-1 (a). Because only NAND gates and inverters can be used, the circuit is redrawn in Figure 8-I(b). The AND gates are built by using a NAND with the output inverted. Notice in Figure 8-1 (a) that when the enable line is LOW, the data displays will be off regardless of any other condition. Consider the operation when the enable line is HIGH. Gates G2 and G3 will be enabled only when the clock line is HIGH. At this time, the data are said to be valid and are gated to the displays. This is an example of using clocked data with an enable line. Verify that Figures 8-I(a) and (b) perform exactly the same function. Refer to the timing diagram in the figure to visualize how all of the signals relate to each other. In particular, notice that the clock pulses are positioned so that they occur only
REFERENCE READING
Floyd, Digital Fundamentals, 5th ed., Section 3-8, Troubleshooting; Section 3-9, Digital System Applications
MATERIALS NEEDED
Logic trainer 7400 TTL 2-input NAND gate 7404 hex inverter Logic probe Logic pulser
DISCUSSION
In this experiment you will continue to examine the logic properties of gates. To illustrate the application of gates to perform a logic function, you will consider the following problems: I. Two data lines are to be gated to two displays.
43
Timing diagram clocillJLIUULnJUUl
Data A
---
Data A ------+-------1
L, Data B -------(a) Logic diagram using ANDs
~Il___fl_
Display Data switches C L,
G,-G, = 7400 G.-Go = 7404
L,
(b) Logic diagram using NANDs and inverters
These 2 nodes are tied together.
FIGURE 8-1
Combinationaiiogic circuit. (c) Short-between-nodes type of failure
before or after the A and B data lines change (from LOW to HIGH or HIGH or LOW).
your results with those of the timing diagram in Figure 8-1(a). The results should agree.
PROCEDURE 1. Connect the circuit as shown in Figure 8-1 (b). Refer to your data book for pin connections, and mark them on the drawing. Label the switches as shown. Use a clock frequency of approximately 1 Hz. The low frequency should allow you to follow the blinking of the displays. 2. Place the enable switch in the LOW or OFF position. 3. Operate switches A and B in all positions, and note if the display comes on. This step requires the four tests shown in Table 8-1; complete the table. 4. Put the enable switch in the ON position, and repeat Step 3 by completing Table 8-2. Compare
44
TROUBLESHOOTING
This troubleshooting section will illustrate the failure that occurs when two nodes in a circuit are shorted together. For example, see Figure 8-l(c) , which shows a short between the inputs of G3 that connects two nodes together. Refer to the Appendix to see how the short-between-nodes problem relates to other possible problems. Warning
1. You should verify that the data switches do NOT provide direct connections to + 5 V and GND for their HIGH and LOW outputs. These outputs
Copyright © 1994 by Merrill Publishing Company, an imprint of Macmillan Publishing Company, All rights reserved.
TABLE 8-1 Data Switches A OFF OFF ON ON B OFF ON OFF ON L, Displays L2
TABLE 8-3 Data Switches A LOW LOW

HIGH HIGH
Displays B L, L2
LOW
HIGH
LOW
HIGH
TABLE 8-2 Data Switches A OFF OFF ON ON B OFF ON OFF ON L, Displays L2
should be current-limited as described in Experiment 1. If the short is installed as shown and no current limiting is provided in the data switches, then G will be overloaded. 2. If data switch B is LOW, it will place a LOW not only on the input of G3 but also on G2, causing improper operation. Next, install the short as shown in Figure 8-l(c), and record the indication of the displays for the four tests in Table 8-3. A number of points must be made about this particular fault (the inputs of NAND gate G3 shorted). First, note that some modes of operation remain normal. For this reason, it is necessary to test all of the combinations. See Step 3 in the preceding Procedure. Another interesting point about this fault is that the output of the NAND will produce the correct response even with its inputs shorted. Therefore it is necessary to read the inputs and outputs at the same time when exercising the truth table. You do not know if a HIGH applied to an input stays HIGH unless you measure it! Recall from Experiment 4 (AND/NAND Logic Gates) that a short on the inputs of a gate could not be detected by checking the output only.
4
3. We find this particular fault by first placing the switches in a mode to cause a malfunction. For example, with switch B OFF and switch A ON, the L1 display does not blink. Using the logic probe and tracing back from the A display (L1), you will find that the output of inverter G 4 is LOW. It should have been pulsing. You next need to determine if this node is stuck. (You will find the troubleshooting flowchart in the Appendix helpful with the following discussion.) 4. Remember that the input of inverter G 4 might be open and cause the output to be LOW. You should recall that the open input of inverter G 4 cannot be detected with the logic probe and pulser. Put the pulser on the input of inverter G 4 and the probe on inverter G4 output. See if it responds, and note the indication. You should not have been able to get a response from inverter G4. Recall that an open input on an inverter causes the output to drive LOW. Unfortunately, this failure cannot be distinguished from grounded inputs on NAND gate G2 and NAND gate G3• However, you can test NAND gate G2 and NAND gate G3 with the logic probe and pulser and determine if they are all right. After using the pulser to drive both inputs of NAND gate G2, note the probe indication on the NAND gate G2 output. It should be all right. Do the same for NAND gate G3• The outputs of both G2 and G3 should have pulsed. 5. At this point, you have good reason to suspect inverter G4, because NAND gate G2 ar.d NAND gate G3 check all right. But before you replace inverter G4, place data switch B in the HIGH position, and read the inverter G4 output with the probe. You should observe that the node is now pulsing as it should. This means inverter G4 is all right. 6. You should now realize that there is interaction between the two nodes. You would have seen this earlier if you had been monitoring both nodes with the probe while changing the data switches. Now that you know there is interaction between nodes,
45
you must perform a careful visual inspection of both nodes. Every point on both nodes must be checked for solder bridges, bent pins, and so on. A careful
check will finally reveal the short between the input pins of NAND gate G3•
EXERCISES
1. Redraw the circuit using only NOR gates and inverters.
2. How many separate tests are required to completely test this circuit? If an additional display and data switch were added, how many tests would be required?
3. In Figure 8-1, if the data are gated to the displays by the switches but the enable control has no effect, what are some possible causes?
4. If no power is connected to inverter G 4 in Figure 8-1 (b), what voltage will be measured on the input pins of G2?
46
9
Universal Property of NAND/NOR Gates
OBJECTIVES
In this experiment we introduce the universal property, which states that any logic function can be implemented by use of either NAND or NOR gates. At the end of this experiment, you will be able to: D Use NAND gates to perform functions described by ANDs and ORs. D Use NOR gates to perform functions described by ANDs and ORs. D Use the logic probe and pulser to troubleshoot a typical combinational logic circuit.
verify that the positive-NAND and the negative-OR produce the same output as shown in the timing diagram. Then do the same for the positive-NOR and the negative-AND. . Often, it is simpler to troubleshoot those lOgIC gates if you have to remember only a single fact about each one. A set of statements that is useful for this purpose is shown below. As used below, the word ANY means "anyone or more." AND NANDA LOW on ANY input will always produce a LOW output. A LOW on ANY input will always produce a HIGH output. A HIGH on ANY input will always produce a HIGH output. A HIGH on ANY input will always produce a LOW output.
REFERENCE READING
Floyd, Digital Fundamentals, 5th ed., Section 5-3, The Universal Property of NAND and NOR Gates; Section 5--4, Combinational Logic using Universal Gates; Section 5-6, Troubleshooting
OR NOR
MATERIALS NEEDED
Logic trainer 7400 two-input NAND gate 7402 two-input NOR gate Logic probe Logic pulser
For example, if you are troubleshooting a NAND gate and the output is HIGH, then at least one of the inputs should be LOW. You should verify the statements above by comparing them with the timing diagrams of Figure 9-1.
PROCEDURE DISCUSSION
Timing diagrams for the AND, NAND, OR, and NOR gates are shown in Figure 9-1. You should
1. The logic diagram in Figure 9-2(a) shows a circuit implemented with ANDs and ORs. Fill in the XI column in truth Table 9-1 based on the logic diagram shown.
Publishing Company.r/vll rights reserved.
47
Inputs A B
~~
I
0 __________
B
A
X=
~ 0___fjfff~4_ I
:
I
=[>-Negative - OR
X=
B A B
A
=8>-OR
=EY-AND
X=
~ ~ffiW1W'4-- , , I
:
I
Outputs ,',
:
!
:
:
,
:
'
, ~
I~ X = 0____rw"~~4-----r~ I I :
I
FIGURE 9-1
Logic gate timing diagram.
=[)Negative - AND
::i
:
::::
X=
~ B~
-X=I
0~A.__
NOR Equivalent
2. Construct the equivalent circuit shown in Figure 9-2(b). Here, only 7402 NORs are used. Although G2 is a positive-NOR gate, in this application it is more meaningful to use the negative-AND logic symbol. Use your data book for pin connections, and mark them on the drawing. Notice that you use NOR gate G3 as an inverter by tying both inputs together. 3. Now, apply the switch inputs according to truth Table 9-1, and fill in the X2 column from the display readings. The Xl and X2 columns should agree. This step shows that the AND/OR circuit could
be replaced by a NOR equivalent circuit. In general, any logic circuit can be implemented by using only NORs. 4. The logic diagram in Figure 9-3(a) shows a circuit implemented with ANDs and ORs. First, fill out the X I column in truth Table 9-2 based on the logic diagram.
NAND Equivalent
s. Next, construct the equivalent circuit shown in Figure 9-3(b). Notice that only 7400 NANDs are used. Although G2 is a positive-NAND gate, in this
X,
(A
B)C
(a) Logic diagram using ANDs and ORs
<. )
X,
Equivalent
Data switches
B Display G,-G,
= 7402
(A
B)C
FIGURE 9-2
Universal property of NORs. (b) Logic diagram using only NORs
48
Copyright © 1994 by Merrill Publishing Company. an imprint of Macmillan Publishing Company. All rights reserved,
TABLE 9-1 Truth table for Figure 9-2. Inputs

A
Outputs C 0
I XI . X2
B 0 0
I I
0 0 0 0
I I I I
0
I
0 0
I I
0
I
a short between adjacent nodes. Add the 2-input NAND (G4) as shown in Figure 9-4, and connect its output to the output of NAND gate G,. This connection will simulate a short-between-adjacent-nodes fault, which you will "find" by following the remaining steps of this Troubleshooting section. Normally, outputs should not be tied together unless they are designed for that purpose. Notice that the inputs of G4 are left open, causing the G4 output to be LOW. The output of NAND gate G, should be HIGH, because only one of the inputs is a 1. However, the LOW output of G 4 will pull down the HIGH output of G,. This set of conditions will cause the error to appear. 2. Complete truth Table 9-3. With the fault installed as shown in Figure 9-4, the following lines of the truth table will have the incorrect outputs as follows: A
0
I
o
application it is more meaningful to use the negative-OR logic symbol. Use your data book for pin connections, and mark them on the drawing. Notice that NAND gate G3 is used as an inverter to produce the active-LOW input for the negative-OR gate G2• 6. Now, apply the switch inputs according to truth Table 9-2, and fill out the X2 column from the display readings. The X, and X2 columns should agree. This step shows that the AND/OR circuit could be replaced by a NAND equivalent circuit. In general, any logic circuit can be implemented by using only NANDs. Do not tear down this circuit; it will be used in the next step (in the Troubleshooting section).
o o
o o o
t.,
1 1 1
3. Apply one of the three combinations above, and make the measurements in Table 9-4. Your first step is to find out which node is the cause (or source) of the error. 4. Use the logic probe to verify the measurements in Table 9-4. Because the inputs of G, were correct, the source faulty node is the output of NAND gate G,. It is stuck LOW when it should be HIGH. Even though the faulty node has been located, however, the actual failure has not yet been determined. 5. In general, five possible failures can cause a node to be stuck LOW: 1. 2. 3. 4. +5 V open to GI. Direct short to ground. Internal short to ground on Short to another node that between nodes causes both 5. Internal short to ground on
TROUBLESHOOTING
This section will demonstrate troubleshooting techniques using the logic probe and pulser. Because the input/output electrical characteristics of most devices are similar, the troubleshooting techniques used for gates will apply to almost all other deivces that are covered in this manual. Node Stuck Low 1. Figure 9-4 is functionally identical to Figure 9-3. For purposes of illustration only one fault, such as a short between adjacent nodes, will be installed at a time. It is possible, of course, for more than one fault to be present at a time. This fault is produced by connecting the output of NAND gate G4 to the output of NAND gate G I' This fault represents
G2 input. is LOW. A short nodes to be bad. G I output.
These failures are shown in Figure 9-4. All five possible failures are shown in Figure 9-4, but in the example only one is physically installed. The first four are indicated by Tests 1 through 4. You should recall that the fifth failure (the output of G, internally shorted to ground) cannot be detected by measurement. The other four failures must be tested for and eliminated before GI can be assumed to be bad. 6. Figure 9-4 provides a pictorial aid for using the logic probe and pulser. It is important to follow the test numbers in sequence, because the decision to
49
A B
X,
AB
+C
(a) Logic diagram using ANDs and ORs
<; )
X, = AB + C
Equivalent
Data switches
A B Display C L, G,-G,
= 7400
FIGURE 9-3 Universal property of NANDs.
(b) Logic diagram using only NAND
replace G1 is not made until the other tests have been completed. The reason is that the other faults can be tested directly, but an output fault must be determined by a process of elimination. Perform the five tests as shown in Figure 9-4. Note the following comments about the five tests: 1. Check the + 5 V connection to pin 14 of G I with the logic probe.
TABLE 9-2 Truth table for Figure 9-3.
Inputs
Outputs
A 0 0 0 0
1 1 1 1
C 0
1
Xl
X2
0 0
1 1
2. Apply the pulser to the bad node, and monitor with the probe. The pulser will not pull up a direct short to ground; this is how a short to ground is detected. However, the pulser should pull up the LOW output of G4. 3. Apply the pulser to the bad node, and monitor the output of G2 with the logic probe. If the output of G2 pulses when the input of G2 is pulsed, then G2 is good. 4. Move the probe around to adjacent pins and signal paths to detect shorts between nodes. An ohmmeter could also be used to find a short between nodes. A malfunction in another portion of the circuit would also indicate a short between nodes. A close visual inspection is required. At this point, you should "discover" the fault. 5. If none of these tests had detected a failure, then G1 would probably have been bad. 7. Remove the jumper that connected the output of G4 to the output of G1. After any repair is made, it is necessary to completely retest the circuit. Node Stuck IDGH
0
1
0 0
1 I
0
1
0
I
8. To simulate a node stuck HIGH, modify the circuit as shown in Figure 9-5(a). For this simulation, assume that you do not have access to the G1 output or to the G4 inputs. The G4 output therefore will simulate a defective G1 with its output stuck at I. 9. Retest the circuit with the full truth Table 9-5.
50
Pulser Data
switches A
~ ~
B
Probe
(No test possible)
FIGURE 9-4 Troubleshooting node stuck LOW.
short
Only the following test should have failed:
A
1
B 1
c
o
t., (G2
o (should
output)
be 1)
bad node is the output of GI. It is stuck at 1. However, the actual failure has not yet been determined, 11. In general, five possible failures can cause a node to be stuck HIGH: 1. 2. 3. 4. Open power ground on GI. Direct short to + 5 V. Internal short to +5 V in G2 input. Short to another node that is HIGH. However, this fault is unlikely to show up on this test, because in TTL logic, a LOW will usually pull down a HIGH from another node. The problem will also show up in a test of the adjacent circuit. 5. Internal short to + 5 V in G I output.
10. Apply the test pattern above and make the

measurements shown in Table 9-6. Because the inputs of G I were correct, the source
TABLE 9-3 Truth table for Figure 9-4. Inputs A 0 0 0 0 I I I I B 0 0 I I 0 0
I
Output C 0 I 0 I 0 I 0
1
L,
12. Figure 9-5(a) provides a pictorial aid for using the logic probe and pulser. It is important to follow the numbered sequence, because if GI is bad, the decision to replace it cannot be made until the other tests have been completed. Note the following comments about the tests:
TABLE 9-4 Measurements Output G2 is HIGH. Bottom input pin of G2 is HIGH. Top input pin of G2 is LOW. Output pin of G, is LOW. One of the inputs to G, is LOW. Remarks Should be LOW. Correct. Should be HIGH. Should be HIGH. Correct.
'Indicates combinations that will produce an incorrect output.
51
Data switches
(a) Troubleshooting tests for node stuck HIGH
Data A switches B open
Display
L,
FIGURE 9-5
(b) Troubleshooting tests for floating node
1. Check the ground pin of G 1. 2. The pulser will not pull down a direct short to +5 V; this is how a short to + 5 V is detected if one is present. 3. If the output of G2 pulses when the input of G2 is pulsed, then G2 is good. 4. Move the logic probe around while pulsing the stuck HIGH node. Pulses that appear on another node that is not part of this circuit indicate a short between nodes. 5. If none of the above tests detect a failure, then replace G1• In this simulation, no other tests failed; therefore you must assume that G1 is defective. After a suspected IC has been removed from an actual circuit, you should verify that the node is no longer stuck HIGH by measuring the node with a logic probe. 13. After any repairs are made, the entire circuit must be retested.
Floating or Open Node 14. We must test for one additional failure type:
afloating or open node. You can simulate it by opening up a connection between the output of G 1 to the input of G2• This type of open is one of the failure modes. This particular fault will cause the circuit to fail the same test as in the previous stuck HIGH example. 15. Restore and retest the circuit as in Figure 9-3(b). Now remove the jumper between the output of Gland the input of G 2. Complete truth Table 9-7, and note which test(s) fail. The same test as in Step 8 should have failed. 16. Apply the pattern (A = 1, B = 1, C = 0) in Figure 9-5(b), and use the logic probe to make the measurements in Table 9-8. The faulty node is the top input of G 2. Figure 9-5(b) indicates four possible fault locations. The pulser is not required for these measurements. Use the probe to measure the four locations, and compare your indications with the following comments:
52
TABLE 9-5 Truth table for Figure 9-5(a). Inputs

A B
TABLE 9-7 Truth table for Figure 9-5(b). Output C 0

I
Inputs
A
Output C 0
I
LI
B 0 0
I I
LI
0 0 0 0
I I I I 'Indicates
0 0
I I
0 0 0 0
I I
0
I
0
I
0 0
I I combinations
0
I
0 0
I I
0
I
0
I that will produce an incorrect output.
I I 'Indicates
0
I
combinations that will produce an incorrect output.
TABLE 9-6 Measurements Output pin of G2 is LOW. Bottom input pin of G2 is HIGH. Top input of G2 is HIGH. Output of G4 (G1) is HIGH. Both input pins of G1 are HIGH. Remarks Should be I. Correct. Should be O. Should be O. Correct. TABLE 9-8 Measurements G2 output is O. G2 bottom pin is I. G2 top input is bad (float). Remarks Should be I. Correct. Should be O.
1. If the output pin of G2 is LOW, then there is an open between this pin and the input pin of G2• This, of course, is the fault you should have "discovered." 2. If the output pin of G1 had been "floating,"
you would have checked for + 5 V and ground to G1. If these checks were good, then there must have been an internal open in the output of G1• Therefore you would have had to replace G1 and then retest.
S3
EXERCISES
1. In Figure 9--3(b), if the input from switch A to G, is open (no connection) and B = I, C = I, what will the indication of the display be? If there is a short between the input pins of G" will the circuit perform properly? Try this experimentally.
2. In Figure 9-3, when the display is ON and C
0, what are A and B (0 or I)?
3. In Figure 9-3(b), the display is OFF and A = I, B = 0, and C = 1. If the output of G, is HIGH and the output of G3 is LOW, what do you suspect?
4. Refer to the data sheet for a 540017400 quad 2-input NAND. How much current can the device deliver when the output is HIGH? How much current can the device "sink" when the output is LOW?
s.
In Figure 9-4, if it has been confirmed that there is an internal short either in G, or in G2, what tests do you make to determine which fault it is?
6. In Figure 9-5, if the node is stuck HIGH as indicated, can any additional information be determined by pulsing the inputs of G, ? Why?
7. Given the information in Figure 9-5(b), is it likely that this problem could be caused by a defect in G2? Why or why not?
8. Draw the appropriate logic symbol for each of the AND, NAND, OR, and NOR gates.
9. Implement the circuit of Figure 9-3 using only NORs.
54
Notes
In the remaining space, respond to the following: 1. Observations different from expected. 2. Possible explanations.
55
10
Exclusive-OR Gates
OBJECTIVES
The exclusive-OR (XOR) is frequently used in applications such as adders, parity checkers, code converters, and many others. After completion of this experiment, you will be able to: o Use exclusive-OR gates. o Troubleshoot these devices.
REFERENCE READING
Floyd, Digital Fundamentals, 5th ed., Section 3-6, The Exclusive-OR and Exclusive-NOR Gates; Section 6-4, Comparators
ever, a more economical method is to use the 7486 gate, which provides four exclusive-OR gates in one 14-pin package. The XOR can also be used to complement (invert) a variable such as A by using the B input as a control. Examine the truth table in Figure 10-1(a) and you will notice that when B = 1, the output X = A. Also notice that when B = 0, the output X = A. You will use this feature as part of the Procedure below.
PROCEDURE
Programmable Inverter
1. To illustrate the programmable inverter, you will use four data switches to represent a value that you want to complement. That is, if A = I, B = 0, C = 0, and D = 1, then you want the circuit to produce four outputs: L] = 0, L2 = 1, L3 = 1, and L4 = 0. You will use another switch as the "control" switch, which will determine if the input value will be displayed complemented or noncomplemented. Before proceeding, draw a circuit that you think will perform this function.
MATERIALS NEEDED
Logic trainer Logic probe Logic pulser 7486 exclusive-OR gate
DISCUSSION
The XOR gate is distinctly different from the 2-input OR gate. The output of the XOR gate is HIGH when one and only one of its inputs is HIGH. A simple but important observation is that the output will be HIGH when the number of HIGH inputs is ODD. In Figure IO-l(a), the logic symbol, truth table, timing diagram, and logical expression of an XOR gate are shown. One method of building the XOR from the other logic gates is shown in Figure 10-1(b). HowCopyright © 1994 by Merrill Publishing Company,
CIRCUlI
FOR STEP 1
57
Timing diagram A~X=AEIlB B Logic expression: Logic symbol X = AB + AB = A EllBreads "X = A exclusive-OR B." ~ Truth Table
A 0 0
A7"BorAEIlB A=B
B
0
X
0
I
0 I
I I
I I
0
(a) XOR gate
B X
AB + AB
A EllB
FIGURE 10-1
(b) Exclusive-OR circuit 4 data lines Data switches Display

A
1-----+---+1
)-----'
L,
)---L2
G,-G4
}---L,
= 7486
E 1--
-r-r-r-'
Control__j (a) Programmable inverter
Data switches
Display
A 1----\-\ B 1----+1
G,-G,
7486
C I---~
DI---H X=AEIlBEIlCEIlD
FIGURE 10-2
(b) Odd detector
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TABLE 10-1 Data table for programmable mode). Data Switches

A
inverter: E = 0 (noncomplement
To place a numerical value for the data switches, use the following "weights" for each switch and its corresponding display: A = 8, B L, = 8, L2
= =
Displays
E
4, 4,
C = 2, D = I L3 = 2, L4 = I
B 0 0
I
C
I I
D I
Ll
L2
L3
L4
0
I
0 0 0 0 0 0
0 0
I I I
0
I
0
I I I
0
I I
0
I
For example, when switch A is a I, it represents 8. When switch A is a 0, it represents O. Also, if L3 is ON, it represents a value of 2; when it is OFF, it represents O. 4. Read the switches and displays, and calculate and record the weighted values in the last columns of Table 10--2. Notice that the sum ofthese two readings is always 15. A 4-bit number added to its complement equals 15. This function is called complementation. This type of circuit is used in the addition and subtraction operations in a computer. Odd Detector 5. For the next step, connect the XOR gates as shown in Figure 10--2(b). Study data Table 10--3, which is provided for you to record the output of the circuit in Figure 10--2(b), for all combinations of the four input variables. Recall that 16 lines are required in a truth table with four variables. 6. Next fill in the output for each of the 16 lines. To analyze how the odd detector works, you should determine the output of XOR gates G1 and G2 and then determine the output of XOR gate G3 by taking the XOR of these two inputs. Calculate each line, and then verify your outcome by applying the inputs for each line. Now examine your data. You will notice that you obtained a 1 output whenever the number of
2. Install the 7486 XOR gates on the trainer, and connect the circuit as shown in Figure 1O-2(a) using your data book for pin assignments. In Table 10-1, record the states of the displays with switch E = 0 for several combinations as shown. The displays should agree with the four data switch inputs. 3. Now put the control switch to E = 1, and record your readings in data Table 10-2. In this mode, the XOR gates should invert each of the data inputs A, B, C, and D. Use the different values of data provided, and confirm that the data are complemented for each value.
TABLE 10-2 Data table for programmable inverter: E = 1 (complement mode). Weighted Sums: Data Switches
A
Displays
E 1 1 1 1 1 1
Data Switches
Displays
E
B 0 0
I
C
1 1
D 1
Ll
L2
L3
L4
Ll
L2
L3
L4
0
1
0 0
I 1 I
0
I
0
1 I 1
0
1 1
0
1
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TABLE 10-3
Odd-detector data table.
Data Switches A
Display
B 0 0 0 0
1 1 1 1
C 0 0
1 1
Ll
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
0
1
0
1
0 0
1 1
0
1
0
1
0 0 0 0
1 1 1 1
0 0
1 1
0
1
0
1
HIGH on an input does not force the output. Refer to the XOR truth table in Figure lO-l(a) if this concept is unclear to you. If you check this truth table for the XOR gate, you will also notice that a single logic HIGH on an input will not force the output to a particular state. In other words, if one of the inputs of an XOR gate is HIGH, the output will depend on the logic state of the other input. 2. To simulate the external open fault, connect the circuit as shown in Figure 10-3(a). Notice that the jumper between data switch A and the input of XOR gate G. is removed. Next, place the switches in the A = 0 and B = 1 positions. You should note that the L. indication is incorrect. Because the display is incorrect, you should next place the logic probe directly on the output pin of XOR gate G. to verify that the output pin is in the same state as the display. They should both be LOW in this simulation. 3. Next, measure the inputs of G t- You should find that the input pin of G. coming from switch B is a l , which is correct. However, the input pin of G. coming from switch A produces an "open" indication. Next, place the logic probe directly on the switch A output connection. Because you should read a LOW (which is correct) at this point, the fault is between the switch and the input pin of G i- Note that there is no jumper between the switch and the input pin, and therefore you have located the fault. Internal Open Input 4. An internal open in an IC cannot be easily simulated. However, you can assume that an internal open input exists, and then you can perform the tests using an external open input. First, recall that the same error indication will result from either an external or an internal open on an input pin. Therefore the output of G. will also be LOW (incorrect) for an internal open input. With this in mind, assume that a LOW is measured directly on the switch A input pin of G i- Assume this in spite of the fact that the jumper is not installed. You can actually measure a HIGH on the other input, and therefore both inputs are correct (A = 0, B = 1). Remember that a LOW output can be caused by a fault on the G. output (e.g., short to ground) or an internal open input. You can use the logic probe and pulser to determine which of these two faults it is. S. Connect the probe and pulser as shown in Figure l0-3(a), and make a note of your indications on the diagram. Next, move the logic pulser to the switch side of the simulated-open input on the top pin, and observe the output of G. with the logic probe. You should notice that the output does not respond to the top input. Also note that the output will
0 0
1 1
0
1
0
1
1's in the four inputs was odd. Versions of this circuit are used in parity checkers, which are covered in Experiment 14.
TROUBLESHOOTING
External Open Input 1. The first troubleshooting situation for the XOR gate is to determine how the output will be affected by an external open input. Recall that an open input in any TIL device assumes a logic HIGH. Therefore in an OR gate a single logic HIGH input will force the output HIGH. In a NOR, of course, the output will be LOW with a HIGH input. However, for the AND or NAND gate, remember the output is not forced, because a single logic
60
Copyright © 1994 by MerriIJ Publishing Company, an imprint of Macmillan Publishing Company. All rights reserved.
Data switches
A !---,O::..__
Simulated open input tI
G, = 7486
Fill in Step 5 of Troubleshooting: (a) Simulation of external and internal open inputs
__
Data switches
Short
FlGUREl~3
(b) Troubleshooting
shorted inputs
TABLE 10-4 Troubleshooting
chart for figure 10--3. Symptom Cause Possible Solution Force one input HIGH, measure other input, then force one input LOW and measure both. Closely inspect input wiring Check A input for external open connection or a stuck HIGH. An internal open can be tested for by use of logic pulser and probe Test A input with logic pulser and probe for stuck LOW condition.
Output always LOW
Inputs shorted to each other
Output is always complement of B input. (for example)
A input OPEN (' 'I ") or stuck HIGH.
Output is always same as B input (for example)
A input stuck LOW
respond from one input but not the other; hence, the fault must be an internal open input. Shorted Inputs 6. If the inputs of an XOR gate are shorted together, then the output will always be LOW. To understand this concept, first recall from previous experiments that a LOW output will pull down a HIGH output. Therefore if either input is driven LOW, it will pull the other input LOW. From the truth table in Figure 10-1(a) you can see that the XOR gate produces a LOW when both inputs are LOW. The
only other case to consider is when both inputs are driven HIGH, and this condition also produces a LOW output. 7. To illustrate the shorted input failure, connect the circuit as shown in Figure 10-3(b). Install the fault (a jumper between the inputs as shown). Place the switches so that A = 1 and B = o. You should note that the L, display is LOW, whereas the correct indication is HIGH. Begin your troubleshooting by measuring the output of the XOR gate G 1 directly on the output pin. Because it is also incorrect, next measure the input pins with the logic probe.
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You will observe that both input pins are LOW, which disagrees with the state of the switches that you selected (A = 1, B = 0). Of course, several possible causes could bring switch A LOW (e.g., a short to ground). To determine the cause of the problem, you might operate switch B and, at the same time, monitor switch A with the logic probe. When you do this, you will notice that there is interaction between the two pins. Now that you have noticed that both inputs
go LOW when either input is LOW, you have "discovered" the short connecting the two inputs.
Other XOR Gate Failures

8. To troubleshoot other types of XOR gate failures, such as grounded outputs and inputs or open outputs, use the same procedures as for the other gates covered in previous experiments. Also, see Table 10-4, which illustrates some of the possible faults in the circuit of Figure 10-3.
EXERCISES
1. Write out the truth table for an XOR gate with an inverter on one of the inputs. Will a different result occur if the inverter is placed on the output?
2. Design an XOR function using two 2-input NORs and one 2-input AND.
3. In Figure 10-2(a), what fault would be likely if you had the following indications when using the circuit? (a) If A = 0, B = 1, C = 0, D = 1, E = 0; and LJ = 1, L2 = 0, L3 == 0, L4 == 1.
(b) If A = 1, B = 0, C == 1, D == 0, E = 0; and LJ = 0, L2 == 1, L3 == 1, L4 == O.
4. In Figure 10-2(b), what fault would you suspect if you took the following data from Table 10-3? A 1 B
C
000 000 010
5. How would you modify the circuit of Figure 10-2(b) if you wanted to detect an even number of Is on the four inputs?
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Copyright © 1994 by Merrill Publishing Company.
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11
Implementation of Logic Networks
OBJECTIVES
In this experiment, you will use your knowledge of gates and truth tables along with a new device called a data selector to implement a typical logic function. At the end of this experiment, you will be able to: D Build a typical logic function. D Use the data selector to build a logic function. D Troubleshoot logic networks.
REFERENCE READING
Floyd, Digital Fundamentals, 5th ed., Section 4-8, The Karnaugh Map; Section 5-2, Implementation of Combinational Logic; Section 6-8, Multiplexers (Data Selectors)
MATERIALS NEEDED
Logic trainer 7408 two-input AND gate 7432 two-input OR gate 7404 inverter 74151A data selector Logic probe Logic pulser
DISCUSSION
The previous experiments discussed basic gate functions and some applications of these gates. In this experiment, you will be given a word statement of a problem and then implement the required function
with gates or the data selector. Because these circuits use combinations of gates, they are called combinationallogic circuits. For example, suppose that you need a circuit that will provide an active-HIGH output when two variables (A and B) are the same. Your first step is to fill in the truth table. As shown in Table 11-1, a 1or a is entered in the output column as required by the statement of the problem. A logic diagram solution for this problem is shown in Figure 11-I(a). Notice that no simplification was necessary and that you could build the circuit directly from the Boolean expression or the Karnaugh map. The Karnaugh map method is systematic and avoids the trials and errors often encountered using the laws and rules of Boolean algebra. When there are three or more variables, however, the work involved becomes tedious although the procedure is much the same. The main drawback is that any change in the problem statement requires a new solution, and this change may also require different gates, wiring, and so on. Fortunately, manufacturers of ICs have produced a device called a data selector that can be used for solving many combinational logic problems. It does so without the use of Karnaugh maps or Boolean algebra. Also, the data selector will usually reduce the number of IC packages required and make any changes much easier to make. In general, a data selector has inputs that act as address lines to select and transfer one of the data inputs to the output. For example, a 2-input data selector requires one address line, a 4-input data se-
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65
Karnaugh map A
B
0
I
0
I
0
I
(a) Logic diagram for Y = AS + AB Truth table

A
A 0 00
I
Y 00
0,
Block diagram
0, Y = A(Oo) (A)
A(O,)
(0) (1)
(b) 2-input data selector
Block diagram
(A) (0)
B
-~'_"'I
(1)
FIGURE 11-1
(c) Data selector used to implement Y = AS + AB
lector requires two address lines, an 8-input selector requires three address lines, and so on. A 2-input (Do and D1) data selector is shown in Figure 11-I(b). Note that when A is LOW, the Do input is "selected" and that when A is HIGH, DI is "selected." You can see that the block diagram along with the accompanying truth table in Figure 11-1 (b) describes this operation. For the first example using the data selector, you will implement the same problem of Figure 11-I(a). Refer to truth Table 11-1 and the table in Figure 11-I(b). By examining these truth tables, you can
TABLE 11-1 Truth table for Figures II-I(a) and (c). Inputs
A B
determine how to use the data selector. First, notice that when A is 0 (Do selected), the Y output is always the opposite value of B. Therefore you invert Band then connect it to the Do input. Next, notice that when A is 1 (D1 selected), the Y output is the same value as B. Therefore you connect B directly to the DI input. These connections are shown in Figure II-I( c). Now compare the logic diagrams of Figure 11-I(a) and (c). One more example of using a data selector for a two-variable problem is provided. Begin by examining truth Table 11-2 and Figure 11-2(a). Notice that
TABLE 11-2 Truth table for Figure 11-2 (a).
Output
Y A
Inputs
B
Output
Y
0 0
I
0 I 0 I
I 0 0 I
0 0
I I
0 I 0
I
0 0
I
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Selector input
A
A
(A) Do (0) (I)
~ ~
Selector inputs
A
D,
y = (O)A + BA = AB
(a) 2-variable/2-input
data selector
B
(A B)
(A B C)
D" D,
y Data inputs
(0 0 0) (0 0 (0 (0 (I (I (I (I I I I) 0) I) 0) I) 0) I)
Dn
(00) (0 I) (10) (I I)
D, D, D,
D, D, D4 D, Dh D,
Y output
o
0 I I
(b) 3-variable/4-input data selector
FIGURE 11-2
(c) 4-variable/8-input
data selector
when A is a 0 (Do selected), the Y output is always a O. Therefore connect the Do input to a 0 as shown in the block diagram of the data selector in Figure 11-1(b). Now notice that when A is a 1 (DI selected), the Y output is always opposite to B. Therefore you invert B and connect it to the DI input. In the next example, a three-variable problem will be implemented with a data selector. A threevariable problem requires a 4-input (Do, D1, D2, D3) data selector. Two of the variables (A and B) are used to select each of the four inputs, as shown in the data selector block diagram of Figure 11-2(b) and in Table 11-3. The third variable (C) is connected to one of the data inputs as will be explained below. The truth table for the three-variable example problem to be implemented is shown in Table 11-4. Notice that for the two cases when A is 0 AND B is 0 (Do selected), the Youtput is the same value as the variable C. Therefore you connect C directly to the Do input.
TABLf; 11-3 Truth table for Figure l1-2(b): Inputs
A B
Keep in mind (and this is very important) that

A = 0 and B = 0 for two of the eight lines of the
truth table on Table 11-4. Now, the Youtput for any pair (e.g., A = 0, B = 1) can be: LOW both times HIGH both times Same as variable C both times Opposite to variable C both times
TABLE 11-4 Three-variable example. Data Input Selected Inputs
A B
C 0
I
Output y 0 1
I
Do Do DI DI D2 D2 DJ DJ
TABLE 11-5
0 0 0 0
I I
0 0
I
1 0 0
I I
0 1 0
I
0 0 0
I I
1
1
0
I
4-input data selector. Output Y 0 1 0 1
Number of Variables 2 3 4 5
Data Inputs Required 2 4 8 16
0 0 1 1
Do DI D2 DJ
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TABLE 11-6
Truth table for Figure ll-2(c): Inputs A 8-input data selector. Output
B 0 0
1 1
C 0
1
0 0 0 0
1 1 1 1
0
1
0 0
1 1
0
1
0
1
Do D1 D2 D3 D4 Ds D6 D7
Next notice that for the two cases when A is 0 AND B is 1 (D1 selected), the Y output is always opposite to the value of C. Therefore invert C and connect it to the D 1 input. When A is 1 AND B is 0 (Dz selected), the Y output is always O. Therefore you
Data switches A
connect a 0 to the o, input. When A is 1 AND B is 1 (D3 selected), the Youtput is always 1. Therefore you connect a 1 to the D3 input. You have probably noticed that no Boolean algebra or Karnaugh map was required in these exampIes, which used the data selector. Second, note that if a change is made to the truth table, it is easy to revise the inputs of the data selector. Also, as you will see in the Procedure below, a four-variable problem can be implemented with only one data selector IC, as opposed to nearly two ICs if logic gates are used. Table 11-5 shows the number of data inputs required for the data selector for different numbers of variables. You can see that if a four-variable function is to be implemented, then an 8-input data selector will be required. Figure 11-2(c) shows the block diagram for an 8-input data selector; the truth table is given in Table 11-6. The device (IC) that is used for the 8-input data selector is the 74151A.
G,.G,
= 7408 G, = 7432 G4.G, = 7404
(a) Circuit for Y = AB + AB
Data switches
A Display
G,.G, = 7408
Dor--+---_...J
0, f------~
L,
G, = 7432 G4 = 7404
(b) 2-input data selector
Data switches
A --------
B -----
-------
-FIGURE 11-3
2-input data Y Do selector from 0, Fig. ll-3(b)

A
Display L,
Com p lete the circuit. (c) Circuit for Step 3
Y = AB + AB
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Notes
The format of the block diagram shown in Figures 11-3 and 11-4 is not a standard format for the data selector. However, this format is used because it is more compatible with the Discussion presented in this experiment. A 16-input data selector is manufactured that could be used for five-variable functions. However, for more than five variables, designers use a read-only memory (ROM) or programmable logic array (PLA).
TABLE 11-7
Truth table for Figure 11-4 football game. Data Input Selected
Inputs A 0 0 0 0 0 0 0 0 1 1 1 1
1 1 B
Output C 0 0 1 1 0 0 1 1 0 0 1
1
D
0 1 0 1 0 1 0 1 0 1 0
1
Y 0 1 0 1 1 0 1 0 1 1
(}'
PROCEDURE
1. Construct the circuit shown in Figure 113(a). Use your data book to find the pin connections, and mark them on the drawing. Apply the inputs from the switches as required by truth Table 11-1, and compare the table with the indications on your display. The display should come on when the switches are in the same position. You should recall that the name for this type of circuit is the exclusive-NOR (XNOR) or the comparator. 2. Construct the circuit shown in Figure 113(b). Use your data book to find the pin connections, and mark them on the drawing. When switch A is in the 0 position, note the effect of moving Do from 0 to 1. With A still a 0, note the effect of moving DJ from o to 1. Now put A in the 1 position, and note the effect of moving Do from 0 to 1. With A still in the 1 position, note the effect of moving DJ from 0 to 1. This circuit is performing the function of selecting data input Do or DJ• 3. Next, modify the circuit of Step 2 to perform truth Table 11-1. Use the steps as detailed in the Discussion to make the data selector from Figure 11-3(b) perform the required truth table. Draw your changes or additions in Figure 11-3(c). Verify that the modified circuit display agrees with truth Table
Do Do Dl Dl D2 D2 D3 D3 D4 D4 Ds Ds D6 D6 D7 D7
0 0 0 0 1 1 1 1 0 0 0 0
1 1
1
1
1
1
0 0 1 1
0 1 0
1
0 1
1
0 0
.--
Definitions of variables: A = offensive pass B = offense to right side C = defense for pass D = defense to right side
A= Ii = C= 15 =
offensive run offense to left side defense for run defense to left side
11-1.
4. In this step, you are given a word statement of a problem and are then asked to build the solution and test it. The problem is to build a "football game" with the following criteria: 1. There are two players: one player is offense, and one player is defense. 2. Each player has two switches: one switch is for pass/run, and the other switch is for left! right. 3. The game is played by the offensive player selecting a pass or run play and also selecting a direction of left or right. At the same time, the defensive player sets his defense for pass or run and also sets his defense for either the left or the right side of the field. A display will indicate if the play worked or not.
4. Design the logic to work as follows: (a) If the offense selects a pass, the play works unless the defense is set for pass (regardless of which direction either chooses). (b) If the offense selects run to the left, the play works unless the defense is set for left. (c) If the offense selects run to the right, the play works unless the defense is set for right. On a separate sheet of paper, draw out your solution before referring to truth Table 11-7 and Figure 11-4(a), which show a solution using a single 74151A data selector. If you had used conventional gate logic, several ICs would have been required. Refer to your data book for pin connections. Notice that an active-LOW strobe (enable) is used. It must be tied LOW to enable the outputs.
TROUBLESHOOTING
1. The logic probe and pulser can be used effectively to test the data selector in-circuit. The procedure outlined here is not an exhaustive test. It would require thousands of tests to check every possible combination of inputs.
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Data switches
C B A
I
A
C (ABC)
ICI
0"
(000) (001) (0 I 0) (0 I I) (100) (10 I) G, ~ 7404 ICI ~ 74151
,
~
V
0, 0,
OJ
Display y L,
,___ 0,
0,
O.
07
(J J 0)
(I I I)
-==To data switches
5 (strobe)
(a) Football game using data selector
--------,
------,
A .rtrt,
0" 0, 0, 0, 04 0, y
O.
To data switch
I-----..q
07
FIGURE 11-4
(b) Testing the data selector
2. Refer to Figure 11-4(b). First, select the Do input (A = 0, B = 0, C = 0), and enable the strobe (S = 0). Connect the logic pulser to the Do input, and monitor the Y output with the logic probe. You should notice that the Do input is selected to the output. Next, move the pulser to all other inputs, and monitor the logic probe. Because the other inputs are not selected, the output should remain LOW. 3. Repeat Step 2, but select the next input D. (A = 0, B = 0, C = 1), move the pulser to all inputs,
and monitor the output Y. Continue the sequence until all eight inputs have been tested. This series of tests verifies that all inputs can be selected to the output and that only one input is selected at a time. 4. Next, disable the strobe line by selecting S = 1. Move the pulser through all inputs, and verify that the Y output remains LOW. 5. The Woutput is the inversion of the Youtput. Repeat Step 2, except monitor the Woutput. Verify that the W output is opposite to the Y output.
EXERCISES
1. If there were no output for any selection of addresses on the data selector, what checks would you make first?
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2. Write the Boolean expression for output Y in Figure 11-2(b).
3. You could implement a five-variable expression with one 16-input data selector or with two 8-input data selectors. What are the advantages of each approach? (Refer to your data book for a comparison of number of pins and so forth. Also, consider how you would select each 8-input data selector.)
4. Draw the mechanical switch equivalent for a 4-input data selector.
s.
Draw the Karnaugh map and the logic circuit using conventional gates for the "football game."
6. What is another name for the data selector?
7. You are troubleshooting a 74151A data selector that is known to be good. However, when the Do input is selected, the output also responds to D4• The same is true for Dl and Dj, D2 and Dg, and D, and Dv. You suspect one of the selector inputs (A, B, or C). Which one do you suspect and why?
Notes In the space remaining, respond to the following: I. Results that differed from expected. 2. Possible explanations.
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12
Comparators
OBJECTIVES
A comparator is a device that compares the magnitudes of two digital quantities and produces an output indicating the relationship of the quantities. After completion of this experiment, you will be able to: o Use the 7485 magnitude comparator. o Build a simple IC tester. o Cascade the 7485. o Troubleshoot the 7485.
A block diagram for a magnitude comparator designed to compare two 4-bit binary numbers is shown in Figure 12-1(b). Three outputs are provided: P < Q, P = Q, and P > Q. It is important to notice that when two numbers are unequal, you determine the greater number by examining the most significant unequal bit; for example, the number 11010 is greater than 11001. The internal logic of the magnitude comparator uses this order to prevent an incorrect comparison.
REFERENCE READING
Floyd, Digital Fundamentals, Comparators 5th ed., Section 6-4,
PROCEDURE
7485 Four-Bit Magnitude Comparator 1. Refer to your data book for the pin assignments and for the function table. Notice that afunction table is used instead of a truth table. The reason is that a device of this type requires a large number of bit patterns, or lines in the truth table, to completely describe all of the combinations; thus, a function table is much more practical. Figure 12-1(b) shows the block diagram for the 7485 magnitude comparator. Notice that it has three cascading inputs that permit the comparators to be cascaded so that any number of bits can be compared. Cascading is done by connecting the outputs of a less significant comparator to the cascade inputs of a more significant comparator. (MSB means most significant bit; "LSB" means least significant bit.) When there is no "less significant" comparator, the cascade inputs are connected as shown in Figure 12-1(b). Notice that the active-HIGH P = Q input is tied HIGH, and the active-HIGH P < Q and P > Q
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MATERIALS NEEDED
Logic trainer Logic probe Logic pulser Two 7485 magnitude comparators 7404 inverter Two 7400 NANDs
DISCUSSION
In Experiment 10, you used the XOR gate, which produced a HIGH output when the two inputs were unequal. It follows that the XNOR will produce a HIGH output when the two inputs are equal. The logic symbol and Boolean expression for the XNOR are shown in Figure 12-1 (a).
73
7486 XNOR
7404
Equivalent
XNOR
Logic expression:
= AB
+ AB:
(A = B)
(a) Exclusive-NOR
(comparator)
7485 Data switches
P, r---------j ,----_----\
MSB P,
for P for Q
Q, ~_..,.--P,
MSB
Q,f---....J
P,f----_J
Q,
P,
LSB for P LSB for Q Displays
Q,
Po Qo P <Q P
Out
P <Q P
L, L, L,
P>Q
(P>Q
(b) Test circuit
for 7485
magnitude
comparator
Inputs:
P,
Q,
P,
Q,
P=Q P>Q
FIGURE 12-1
(c) Timi ng diagram
for 7485
inputs are tied LOW! The reasons for these connections are as follows: When only one 4-bit comparator is used, it is considered the least significant comparator for purposes of cascading. Logically, it should not be affected by the absence of a less significant comparator. It follows that the P = Q cascade input should be active-HIGH, because the "absent four bits of P" could not be considered either more or less than the "absent four bits of Q." Also, keep in mind that the cascaded inputs are not even examined unless the two 4-bit numbers being compared are equal. In this case, the only condition of the cascaded inputs that will not disturb this equality is that the cascaded input P = Q is tied HIGH and the P < Q and P > Q inputs are tied LOW.
2. Now connect the 7485 as shown in Figure 12-1(b). Notice that some of the input pins are not assigned. For simplicity, only the two most significant bits of each binary number are illustrated. The use of only two bits does not alter the explanation, but it makes the experiment less cumbersome. 3. Next, refer to the timing diagram of Figure 12-1(c). Carefully study each of the 16 steps of the timing diagram. The diagram should help clarify the operation of the 7485 comparator. Notice that when the MSBs are the same, the comparator outputs are determined by the LSBs. In general, the comparison is determined by the relationship of the most significant unequal bits. 4. Complete data Table 12-1 by setting the input switches as shown and reading the outputs on the
74
displays. Leave the PI' Po, QI' and Qo inputs open. You should have observed that on the second entry and last three entries, the outputs depended on the cascaded inputs.
Simple IC Tester
5. As an application experiment, you will use the 7485 comparator in a simple IC tester. Figure 12-2(a) shows the block diagram of a simple IC tester. Connect the circuit as shown in Figure 12-2(b). A 7400 NAND gate is used to demonstrate how the comparator is used in this type of tester. From your data book you will notice that the 7400 NAND gate contains four 2-input NAND gates. One position is assigned for the IC under test, and the other position contains a known good 7400. Other devices could be tested by changing the wiring and installing a known good device of the type desired. Notice that the inverters are used to "buffer," or provide an electrical separation between, the inputs of the device under test and the known good device. Consider what would happen if you grounded an input of the IC under test when the inverters were not there. In this case, the inputs of the good IC would also be directly connected to the inputs of the IC under test. Because both ICs would have the same input condition, an input fault would not cause the test to fail as it should. Therefore we put the inverters in the circuit to act as buffers to isolate the IC under test from the known good IC.
TABLE 12-1
Data table for Figure 12-I(b).
6. Before creating any faults, first verify that the circuit is functioning properly. Exercise the ICs by using the truth table inputs for a 2-input device (four tests). Although you could monitor the outputs for each test, the good IC and the comparator circuit do the job for you. You must only watch the pass/fail light. 7. You should now create several faults to simulate IC failures, such as opens and shorts. Recall that for each fault the IC is tested for, you must apply all four possible input patterns (because the node on which you create the fault may already be in that state), and you need to test all four possible input conditions. In Experiments 23-25, we introduce a device called a counter that could be used to generate these test patterns for you ...._'--__ 8. If you did not t shorting two input pfus together on the NAND gate do ·..;6w. Notice that this failure is not detected by this simple IC tester. You may recall from Experiment 4 (AND/ NAND Logic Gates) that you must also monitor the inputs when performing a complete test. As you can see, this tester does not compare the inputs.
Cascaded 7485 Comparators

9. To make comparisons for numbers greater than four bits, the 7485 can be connected in cascade. Figure 12-3 shows the connections for two 7485s connected in cascade. Because 16 switches would be required to connect the eight inputs for each number,
Inputs
Outputs
P3
I I I I I
Q3
I I I
P2
I
Q2 0 0
I
P<Q
0 0 0 0 0 0 0
I
P=Q
I I I I I I I
P>Q
0 0 0 0 0 0 0 0 0
I
P<Q
P=Q
P>Q
0 0
I
0 0
I I I
0 0
I
0 0
I
0 0
I
0 0
I
0
I
0
I
0
I
0
I
0 0
Copyright
© 1994 by Merrill Publishing
Company,
Publishing
Company.
75
Ie under test Test patterns Known good Ie (a) Block diagram of simple Ie tester
G,-G, = 7400
Ie under test
G,-G, = 7400
Known good Ie Data switches 7485

L__-----J ~-----l L._+------1 ~--___1Q, P,
Q,
P,
Gy-G" Inverter 7404
L._---1-+------l P, ~-___1Q,
FIGURE 12-2
(b) Wiring diagram for simple Ie tester
you may use jumpers to + 5 V for HIGH inputs and ground for the LOW inputs. When wiring in the test numbers, make sure you observe the MSB and the LSB assignments. Connect the P and Q inputs with the test numbers in Table 12-2, and record the indications of the comparator outputs in the columns provided. The indicated outputs should agree with your own calculations.
TROUBLESHOOTING
1. Refer again to Figure 12-1(b), which shows a test circuit for the 7485. You will need to use your knowledge of the functions of the comparator to trou-
bleshoot it efficiently. For example, if the P < Q output is HIGH incorrectly for a large number of test patterns, you should suspect that the Q3 input is open or stuck HIGH. Likewise, if the P> Q output is HIGH incorrectly for a large number of test patterns, then you should suspect that the P 3 input is open or stuck HIGH. You should begin checking inputs by starting with the MSB and working toward the LSB. 2. If the P = Q equality output indicates HIGH when it should be LOW, then you might suspect adjacent inputs shorted together. If the P > Q, P = Q, and P < Q outputs ever produce more than one HIGH output at a time or no HIGH outputs, then the problem may be that the cascaded inputs (P > Q, P = Q, and P < Q) are connected incorrectly.
76
TABLE 12-2
Inputs Outputs
P
10010011 01001100 01110101 10010011 01001100 01110111
Q
01101011 10000000 01110101 10011011 01001101 01111000
P<Q
P=Q
P>Q
Jumper inputs to +5 V or GND to compare numbers PandO +5 V IC2
OJ P, 0, P, 0, P" 0" P<O p=o p>o

Out
PJ
/\::1
p<O
ICI
OJ
r,
P,
ICI. 1C2
7485
0, P,
0,
P" o. P=O { p>o P<O p=o p>o
FIGURE 12-3 8-bit comparator using two 7485s.
Lowest-order 4 bits
Highest-order 4 bits Highest-order 4 bits
r"------'
~{
p<o p=o P>O
Display
L, L,
LJ
EXERCISES
1. If a magnitude comparator did not have a P < Q output available, how would you generate this comparison? Draw the logic diagram using the P = Q and the P > Q outputs from the magnitude comparator as the inputs for your logic circuit.
2. Refer to the IC tester diagram (Figure 12-2) and name several possible faults that this tester will not detect in an IC.
Copyright
e 1994 by Merrill Publishinl Company. an imprint of MacmiDIII PublisbiDI Company. AU riPtI. reserved.
77
3. In the timing diagram of Figure 12-1 (c), 16 steps were shown for the comparison of the two MSBs of each number. How many steps would be required if all four bits of each number were displayed?
4. Draw a circuit that will produce an active-HIGH output when P = Q OR when P > Q (when P is equal to or greater than Q). Assume that you have all three outputs available from the 7485 magnitude comparator. (Hint: One possible solution requires only a single inverter.)
78
Copyright © 1994 by M~I
Publishing Company, an imprint of Macmillan Publishing Company. All rights reserved.
13
Parallel Binary AdderlSubtractor
OBJECTIVES
The adder, the basic arithmetic circuit, performs the addition of numbers. In this experiment, we work on a circuit that performs both addition and subtraction. After completion of this experiment, you will be able to: D Describe how the basic adder unit works. D Use the 7483 four-bit binary adder. D Cascade two or more 7483s. D Build a 4-bit adderlsubtractor. D Troubleshoot these circuits.
REFERENCE READIN
Floyd, Digital Fundamentals Decimal Numbers; Section Section 2-4, Binary Arithmet 2's Complements; Section tion 6-2, Parallel Binary Add 5th ed., Section 2-1, -2, Binary Numbers; c; Section 2-5, l's and 1, Basic Adders; Secrs
MATERIALS NEEDED
Logic trainer Logic probe Logic pulser 7486 exclusive-OR 7483 four-bit adder
DISCUSSION
The 4-bit adder consists of fo r full-adders cascaded together. The truth table for full-adder is shown in
Copyright © 1994 by Merrill Publishin Company,
Table 13-1. An inspection of the sum (S) output shows that the sum is a 1 when the number of 1s in the three inputs (A, B, CI) is odd. Therefore you use the XOR of these three inputs to produce the sum output. [Recall from Experiment 10 (Exclusive-OR Gates) that you used the XOR as an odd detector.] The carry output is a 1 when two or more of the three inputs (A, B, CI) are Is. Figure 13-1 shows the block diagram of the full-adder and also the Boolean expressions for the sum and carry outputs. The rules for binary arithmetic are similar to those for decimal arithmetic. All operations depend on positional values. In a binary number, the rightmost position (the LSB) has a value of 1, and each position to the left doubles in value. Figure 13-2(a) shows a 4-bit adder. Using the rules of arithmetic, the sums and carries for the values of A and B are shown. All of the four adder circuits (called full-adders) are identical. The carry input (CI) bit of the LSB is used as the cascade input from the carry output (CO) ofthe next lower significant adder, but it is tied LOW when there is no lower-order adder. The 7483 is a 4-bit adder that accepts two 4-bit numbers (A and B) and a carry input as inputs. It provides a 4-bit sum output and a carry output. Figure 13-2(b) shows the logic symbol of the 7483. Figure 13-2(c) shows how an adder for values greater than four bits can be cascaded by connecting the carry output of the least significant four bits of the number to the carry input of the next most significant four bits. To demonstrate the operation of the 4-bit adder, use the following format of the bits to be added:
79
TABLE 13-1 Truth table for fuJI-adder. Inputs CI 0 0 0 0

I I I I A B
Example 2:
Outputs' S 0 I
1
o
CO 0 0 0
I
0 0
1 1
0
I
1001 +9 +1100+12 10101 +2 1 Example 2 shows a condition in which the carry output bit is a 1. Example 3: 1 +1 01 1 1 +7 + 001 1 +3 01011 +11
0
1
0
1
0 0
1 1
0
1
0
1 1 I
0
1
0 0
I
CI
Full-
Block
Example 3 shows a case with a carry input bit of 1.
adder
diagram
2's Complement
co
or ~
Is
+
= A Ell B Ell CI
co
= AB
CI(A Ell B) = AB
A(Cl)
B(CI)
FIGURE 13... 1
CI A4A3A2A) + B4B3B2B) S5 S4 S3 S2 SI [S5 is the same as the carry output (CO) bit.] We will consider three examples. Example 1:
o
01 1 1 +7 +1000 +8 01111 +15 Example 1 shows a decimal sum of 15, which is the maximum value that a 4-bit adder can represent without the carry. An "overflow" condition results when the sum exceeds 15, and the maximum number of bits that can be handled (stored) is only four. If the number of bits in the system exceeds four, then additional adders can be cascaded by connecting the carry output to the carry input of the next most significant adder.
Only positive numbers have been used in the previous examples. Of course, both positive and negative numbers must be represented in digital systems. The use of both positives and negatives can be accomplished by the 2' s complement method, the most widely used number system in computer arithmetic. A table for the 4-bit combinations in 2's complement, representing -8 to +7, is shown in Table 13-2. Notice that the MSB is a 0 for positive numbers and a 1 for negative numbers. Also, notice that the numbers increase from bottom to top until -1 is reached. At this point, when 1 is added to binary 1111, it becomes 0000 with the carry ignored. Keep in mind that the 2's complement method works only if "legal" numbers are used. Legal numbers for a 4-bit system are those from - 8 to + 7. It is important to keep in mind that positive numbers are not converted but are used as is; for example, +7 = 0111. To convert a negative decimal number to a 2' s complement binary number: 1. Represent the decimal number as a positive binary number. 2. Complement this binary number (invert each bit). 3. Add 1. 4. Ignore carries (if any) from the MSB. With this procedure, zero (0) is the only value that will generate a carry. Now we will consider some examples of decimal-to-binary and binary-to-decimal conversion.
80
CI A,A)A,A,
+B, B) B, B, L, L, L) I,L,
A, B,
CI
CI
A, B,
CI
A, B,
CI
Fulladder (FA) 8's
FA 4's
FA 2's
FA I's
(I indicates sum.) (a) 4-bit binary adder with carry input and carry output
7483 CI Data Bit value 5, 5, 5) 5, I's 2 4 8

= 16
Data
A, A, A) A, B, B, B) B,
C,
(CO)
(b) 7483 4-bit binary adder
(c) 8-bit adder, cascading 7483's
FIGURE 13-2
Example 4: Step Step Step Step Step 0: Decimal number 1: Positive binary 2: Complement 3: Add 1 4: Ignore carry
=
= = = =
Example 5: Step Step Step Step Step 0: 1: 2: 3: 4: Decimal number Positive binary Complement Add 1 Ignore carry
=
-5 0101 1010 1011 1011 (2's complement of -5) -9
To reverse the process, simply complement the binary number and add 1_ The result is a positive binary number whose magnitude, when converted to decimal, is the value of the negative decimal number. Try several conversions in both directions, using Table 13-2 to verify your results.
Example 6: Step Step Step Step 0: 1: 2: 3: 2' s complement Complement Add 1 Decimal number = 1011 =0100 = 0101 = -5 (Decimal value of 1011)
= 1001
=0110 = 0111 = 0111 (Error: -9 illegal)

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81
TABLE 13-2 2's complement representation of positive and negative numbers. Binary Value MSBs
Decimal +7 +6 +5 +4 +3 +2 +1 0 -1 -2 -3 -4 -5 -6 -7
o o
-8
III I 10 010 1 0100 00 I I 0010 0001 0000 I1I I I I 10 1 10 1 I 100 10 I I I0 I0 100 1 1000
Positive numbers (unchanged)
addition, because a 0 into the XOR causes the data not to be inverted and, also, a 0 is placed on the carry input. You should notice that with only four bits available, only the number values shown in Table 13-2 can be used. In other words, it is not permissible to add +7 and +6 using four bits in 2's complement arithmetic, because the value of + 13 does not fall within the range of the table. In this case, the sum overflows the table.
2's Complement Arithmetic 3. The following rules apply when the 2' s complement system is used. (Note: The results referred to
2's complement
in the following rules are the 4-bit sums or differences and do not include the carry output bit. The carry output bit is ignored in 2's complement arithmetic. Also, the carry input is always 0.)
Rule 1: When two numbers of unlike sign are

Example 7: Step Step Step Step 0: 1: 2: 3: 2's complement = 1001 Complement = 0110 Add 1 = 0111 Decimal number = -7 (Decimal value of 1001) added, the result will always be in the "legal" range. +0 +7 +(-8) +1000 1111 +1
o111
Rule 2: When two positive numbers are added,

overflow occurs if the result is negative.
When a negative 2's complement number is added to a positive number, the process of subtraction takes place. It other words, to subtract, take the 2' s complement of the number and add. Prove this rule to yourself by trying several values from Table 13-2.
o o111
+ 0011 01010
+0 +7 +(+3) +10 (overflow)
PROCEDURE
Four-Bit AdderlSubtractor 1. A 4-bit adderlsubtractor is shown in Figure
13-3. The programmable inverter circuit used in this figure is the same one used previously in Experiment 10 (Exclusive-OR Gates). When the subtract mode is selected (a logical HIGH or 1), the complement of the B number is performed by the XORs, and at the same time, a I is placed on the carry input of the 4-bit adder. This 1 on the carry input performs the "Add 1" of Step 3 in the previous examples. 2. Refer to your data book for pin connections, and connect the circuit as shown in Figure 13-3. Do you agree that the circuit performs the exact steps as stated in the Discussion? When the add mode is selected (a logical LOW or 0), the 4-bit adder performs
Rule 3: When two negative numbers are added,

underflow occurs if the result is positive.
o +0 1010 -6 + 1 101 +(-3) 10 1 1 1 -9 (underflow)

Rule 4: When two numbers of like sign are
subtracted, the result will always be in the "legal" range. Remember that in 2's complement arithmetic, subtraction is done by taking the 2' s complement and then adding. 2' s Complementation
82
Copyright © 1994 by Merrill Publishing Company, an imprint of Macmillan Publishing Company. AlI rights reserved.
Programmable inverters Adds + I when 74113 Data switches CI I's LSB 2's
A, G,-G, = 7486
A, B, A2 B2
A, B,
Displays S,
L,
B,
A,
B,
.5,
2's
L,
4's
A, S, B,
4's
L.
A4 B4
8's
A,
.5,
B,
S's NC
L,
SUB = I ADD = 0
(CO)
Co
FIGURE 13-3 2's complement adderl subtractor.
+ /_
B4 B, B2 B,
A4 A, A2A,
--.54-.5,
.5, .5,
I Sum/difference
Numbers in 2's complement form in 2's complement form
Step 0: Decimal number Step 1: 2's complement Step 2: Complement Step 3: Add 1
= -3
= 1101 =0010 (2's complement = 0011 of -( -3) = +3)
o +0 0100 +4 + 0 11 0 -(-6) 01010 + 10 (overflow)

Rule 6: When a positive number is subtracted from a negative number, underflow occurs if the result is positive. This case is effectively the same as that in Rule 3. 2's Complementation Step 0: Decimal number Step 1: 2's complement Step 2: Complement Step 3: Add 1
+0
-4 1100 + 00 11 -(-3) o 1 1 1 1 -1
Rule 5: When a negative number is subtracted from a positive number, overflow occurs if the result is negative. This is effectively the same case as in Rule 2. 2's Complementation Step 0: Decimal number Step 1: 2's complement Step 2: Complement Step 3: Add 1
+7
=0111 = 1000
(2's complement 1001 of +7)
-6
o +0 -2 1 1 10 -(+7) +1001 -9 (underflow) 10111

Keep in mind that all numbers ,sums and differences as well as inputs, must be represented in 2's arithmetic form.
= 1010 = 0101 (2's complement = 0110 of -( -6)= +6)
83
4. Using the circuit of Figure 13-3, try several numbers in each of the six groups described to test the rules for yourself. In each group, try some numbers that stay in the table and some that overjlow or underflow. You should use at least 12 sets of numbers to test for both valid and invalid data. In a computer system, underjlow and overjlow detection circuits are provided to prevent any illegal values from being used as valid data. Do not tear down the circuit yet; it will be used in the Troubleshooting section below.
The carry output bit is discarded in 2's complement arithmetic. If the carry input for the 4's bit were always HIGH, the errors described would result. Note that the fault only caused errors in the last two sums. Determine what error in the adder could generate the incorrect sums for the following three addition examples: 10110101 1011 0110 1001 1101 -----0001 1100 0110 If the carry input for the 2's bit were always LOW, the errors above would result. Logic Probe and Pulser 2. The logic probe and pulser can be used effectively to troubleshoot functional devices such as the 4-bit adder. For the two faults illustrated earlier, the pulser should be placed on the suspected node and the probe placed on the output of the adder bit (Figure 13-3). If the probe indicates pulse activity, then the Ie is probably good. Therefore the input node should be checked carefully for a fault using the methods developed for logic gates in earlier experiments.
TROUBLESHOOTING
Logic Analysis 1. When troubleshooting a circuit such as the adderlsubtractor described, you should take into account the weighting Jactor of each bit. For example, if an error of Jour results for several test values, then check the inputs and outputs of the 4's adder for a stuck HIGH or a stuck LOW line. To illustrate this idea, note the following three additions using 2' s complement arithmetic. 1011 1001 0101 0110 0110 1001 -----0001 0011 0010
EXERCISES
1. Design an overflow detector for the situation described in Rule 2 in the Procedure.
2. What range of positive and negative integers can be represented in a 16-bit computer?
3. Use 2's complement arithmetic to add the following 4-bit 2's complement numbers. Also indicate the sum as a signed decimal number. (a) 0011
+ 0001
(b) 1101
1010 =
84
(c) 0101
1101 =
4. Use 2's complement arithmetic to subtract the following 4-bit 2's complement numbers. Also indicate the difference as a signed decimal number.
(a) OlIO - 0001 = _
(b) 1101 - 0011
(c) 1001 - 1110
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85
14
Parity Generator/Checker
OBJECTIVES
The term parity refers to the oddness or evenness of the number of Is in a specified group of bits. Parity generation and checking are means of detecting data errors during transmission or processing. After completion of this experiment, you will be able to: o Describe how the parity function works. o Use the 74180 parity generator/checker. o Cascade the 74180. o Troubleshoot the 74180.
REFERENCE READING
Floyd, Digital Fundamentals, 5th ed., Section 6-10, Parity Generators/Checkers
MATERIALS NEEDED
Logic trainer Logic probe Logic pulser Two 74180 nine-bit parity generators/checkers Two 7404 inverters
To provide a means of error detection, a parity bit is added to "data words." Either ODD or EVEN parity can be used. In ODD parity, the number of Is in the data word plus the parity bit should always be ODD before storage or transmission. For example, if the number of 1s in the data word is EVEN, then the added parity bit will be made a I. If the number of 1s in the data word is already ODD, then the parity bit will be a O. This process is called parity generation. After retrieval or reception of data using ODD parity, the number of Is in the data plus the parity bit should still be ODD. If the number of bits is not ODD, then an error has occurred, and the parity checker will cause an alarm or error message to be generated. The simple parity-type error-detection system is, in general, effective only when there is a single error, not multiple errors. If the number of multiple errors is EVEN, then an error will not be detected. The reason is that an EVEN number of errors does not cause the number of Is in the data word to change from ODD to EVEN or from EVEN to ODD. There are other systems available (e.g., error detection and correction) that are designed to detect multiple errors. 74180 Parity Generator/Checker
DISCUSSION
Parity Checking and Generation Although the reliability of most digital systems quite high, in certain instances errors are likely occur. Two such examples are (l) transmission data over long distances and (2) storage of data magnetic media.
is to of on
A circuit that will determine if the data are ODD or EVEN was discussed in Experiment 10 (Exclusive-OR Gates). You will not have to build this circuit, however, because there is available a universal 9-bit (8 data bits plus I parity bit) MSI (medium-scale integration) chip designated the 74180. Figure 14-1(a) shows the block diagram of the 74180, and Table 14-1 shows the truth table. The
87

Digital Experiments Emphasizing Troubleshooting

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NOTICE TO THE READER

'(lI8qmo:J anirfailduq IUIl1im:lllM

tEi),O lYI ,anil:J boowslan3 ,~unsvA IUIvl'(2 Ell

MERRILL'S INTERNATIONAL SERIES IN ENGINEERING TECHNOLOGY

Pond, Introduction to Engineering Edition, 0-02-396031-0 ELECTRONICS Electronics TECHNOLOGY

1 Familiarization with Laboratory

Po wer sup ply +5 V

Part of electrically connected power bus terminals on breadboard /Jumper

Part of a second bus

Copyright © 1994 by Merrill Publishing Company,

All rights reserved.

(b) Setup for measuring pulser outputs

Copyright © 1994 by Merrill Publishing Company,

All rights reserved.

an imprint of Macmillan Publishing

(a) Setup for measuring logic level threshold

Trainer Pulse output

Power and ground leads of probe are not shown.

(b) Setup for measuring pulse and clock

© 1994 by Merrill Publishing Company,

All rights reserved.

Move scope. probe. and pulser together to all five positions.

(a) Functional test of pulser

Trainer Logic switch

Measure for both logic and logic I.

(b) Functional test of logic switches

PLOT 4 Points A and E.

Pulser Test on Logic 0

Pulser Test on Logic 1

Tests for Shorts

Copyright © 1994 by Merrill Publishing Company. an imprint of Macmillan Publishing Company.

All rights reserved.

an imprint of Macmillan Publishing Company.

(a) Top view of Hex inverter showing pin assignments

(b) Typical circuit with pin assignments

A ">, NOT symbol

(c) Input-output relationships

HIGH = I LOW - 0 Data switch

(a) Inverter test

(b) Double inversion

(c) Latch circuit using inverters

inverters G,-G, 7404

(b) Timing diagram for Exercise 4

Complete the waveforms.

© 1994 by Merrill Publishing Company,

All rights reserved.

Period when ALL inputs are HIGH

Timing diagram A~ B~X C Logic symbol Truth table Inputs A 0 0 0 0 I I I I I B 0 0 I I 0 0 0 I I C 0 I 0 I 0 0 I 0 I Output X 0 0 0 0 0 0 0 0 I X

iod when ANY input is LQ~ I ! L i I I

Period when ALL inputs are HfGH

ABC reads "X

(b) 3-input AND gate

Bubble indicates inverted output.

NOT (A AND B)."

(c) 2-input NAND gate

(a) 2-input AND gate

G, = 7400 Data switches A f---_' B

Truth table for AND/NAND Display

(c) 2-input NAND

(d) NAND gating action