CXA2074Q/S

US Audio Multiplexing Decoder

Description
CXA2074Q CXA2074S
The CXA2074Q/S is an IC designed as a decoder
48 pin QFP (Plastic) 42 pin SDIP (Plastic)
for the Zenith TV Multi-channel System and also
corresponds with I2C BUS. Functions include stereo
demodulation, SAP (Separate Audio Program)
demodulation, dbx noise reduction and sound
processor. Various kinds of filters are built in while
adjustment, mode control and sound processor
control are all executed through I2C BUS.

Absolute Maximum Ratings (Ta = 25°C)

Features
• Supply voltage VCC 11 V
• Audio multiplexing decoder, dbx noise reduction
• Operating temperature Topr –20 to +75 °C
decoder and sound processor are all included in a
• Storage temperature Tstg –65 to +150 °C
single chip. Almost any sort of signal processing is
• Allowable power dissipation
possible through this IC.
PD 0.6 (48 pin QFP) W
• All adjustments are possible through I2C BUS to
2.2 (42 pin SDIP) W
allow for automatic adjustment.
• Various built-in filter circuits greatly reduce external
Range of Operating Supply Voltage
parts.
9 ± 0.5 V
• There are three systems for inputs and two
systems for outputs, and each mode control is
Applications
possible.
TV, VCR and other decoding systems for US audio
multiplexing TV broadcasting
Standard I/O Level
[( ) is the pin No. for the CXA2074S.]
Structure
• Input level
Bipolar silicon monolithic IC
COMPIN (Pin 17) 245mVrms
AUX1-L/R (Pins 36 and 35) 490mVrms
∗ A license of the dbx-TV noise reduction system is
AUX2-L/R (Pins 38 and 37) 490mVrms
required for the use of this device.
• Output level
LPOUT-L/R (Pins 40 and 39) 490mVrms
LSOUT-L/R (Pins 8 and 7) 490mVrms

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

–1–
E96843B86
 CXA2074Q/S

Pin Configuration (Top View)

CXA2074Q

VCAWGT

VEWGT
AUX1-R
AUX1-L

VEOUT
VCATC

VCAIN

SAPIN
VETC
NC

NC

VE
36 35 34 33 32 31 30 29 28 27 26 25

AUX2-R 37 24 SAPOUT

AUX2-L 38 23 NOISETC

LPOUT-R 39 22 STIN

LPOUT-L 40 21 SUBOUT

LPIN-R 41 20 NC

LPIN-L 42 19 VCC

NC 43 18 SAPTC

BASSR1 44 17 GND
BASSR2 45 16 IREF
BASSL1 46 15 VGR
BASSL2 47 14 COMPIN
TRER 48 13 PLINT

1 2 3 4 5 6 7 8 9 10 11 12
SDA

NC

NC
LSOUT-R

SCL

MAININ

PCINT1
LSOUT-L

DGND

MAINOUT

PCINT2
TREL

CXA2074S
LPOUT-R

NOISETC
VCAWGT

SUBOUT
LPOUT-L

SAPOUT
VEWGT
AUX1-R
AUX2-R

AUX1-L
AUX2-L

VCATC

VEOUT
LPIN-R
LPIN-L

VCAIN

SAPIN
VETC

STIN

VCC
VE

42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
LSOUT-L

DGND
BASSR2

LSOUT-R

SDA
TRER
BASSL1

PCINT2
MAINOUT
TREL

PCINT1
MAININ
BASSL2

COMPIN
PLINT

SAPTC
SCL

VGR
BASSR1

IREF

GND

–2–
 Block Diagram

CXA2074Q

AUX1-R

MAINOUT

PCINT1
MAININ

PCINT2
PLINT
SUBOUT
AUX1-L
11 12 13 21 9 8 36 35
STLPF

"FILTER"

FEXT1
LFLT VCO 1/4 1/2
38 AUX2-L
MATRIX TVSW
37 AUX2-R
FLT LPF VCA
FEXT2
40 LPOUT-L
"STEREO" WIDEBAND
COMPIN 14 VCA LPF DeEm LPF 39 LPOUT-R
NRSW/FOMO/SAPC
TVSW/EXT/M1
(+6dB) 42 LPIN-L
ATT PASSSW
STIND
PSW

41 LPIN-R
VCC 19
LOGIC

GND 17

–3–
VOL-L

SAPVCO
VOL-L

BPF LPF
VOL-R

VOL-R

46 BASSL1
DeEm VE VCA
NOISETC 23 NOISE 47 BASSL2
DET "NOISE"

HPF 44 BASSR1
RMSDET
"SAP"
BASS

BASS

BASS

SAPTC 18 SAPIND 45 BASSR2

VCO FILTER SPECTRAL

AMP 1 TREL
LPF LPF RMSDET
(+4dB)

IREF I2C BUS I/F 48 TRER

TREB
TREB

SW
M2 TREBLE

"PONRES"

15 16 6 5 4 24 25 22 26 27 28 30 31 33 32 3 2
VE

SCL
SDA

VGR
IREF
STIN
VETC

SAPIN
VCAIN

DGND
VCATC

VEOUT

VEWGT

SAPOUT
LSOUT-L

VCAWGT
LSOUT-R
CXA2074Q/S
 CXA2074S

AUX1-L
AUX1-R

MAINOUT

PCINT1
MAININ

PCINT2
PLINT
SUBOUT
14 15 16 23 13 12 36 35

STLPF

"FILTER"

FEXT1
LFLT VCO 1/4 1/2
38 AUX2-L
MATRIX TVSW
37 AUX2-R
FLT LPF VCA
FEXT2
40 LPOUT-L
"STEREO" WIDEBAND
COMPIN 17 VCA LPF DeEm LPF 39 LPOUT-R
TVSW/EXT/M1
NRSW/FOMO/SAPC
(+6dB) 42 LPIN-L
PASSSW
PSW

ATT STIND 41 LPIN-R

VCC 22
LOGIC

GND 20

–4–
VOL-L
VOL-L
VOL-R

SAPVCO
VOL-R

BPF LPF

3 BASSL1
DeEm VE VCA
NOISETC 25 NOISE 4 BASSL2
DET "NOISE"
1 BASSR1
HPF RMSDET
"SAP"
BASS
BASS

BASS

SAPTC 21 SAPIND 2 BASSR2

VCO FILTER SPECTRAL

AMP 6 TREL
(+4dB) LPF LPF RMSDET

IREF I2C BUS I/F 5 TRER

TREB
TREB

SW
M2 TREBLE

"PONRES"

18 19 11 10 9 26 27 24 28 29 30 31 32 34 33 8 7
VE

SCL
SDA

VGR
IREF
STIN
VETC

DGND
SAPIN
VCAIN
VCATC

VEOUT

VEWGT
LSOUT-R

SAPOUT
LSOUT-L

VCAWGT
CXA2074Q/S
 CXA2074Q/S

Pin Description

Pin No. Pin

Symbol Equivalent circuit Description
QFP SDIP voltage

BASS filter pin. (Right channel)

44 1 BASSR1 4.0V VCC (Connect a 47nF capacitor
3k between Pins 1 and 2 (44
and 45).)
(45) 2
The cutoff frequency is
190
(47) 4 determined by the built-in
45 2 BASSR2 4.0V 4.2k 190 resistor and the external
3.4k capacitance.
2.7k

2.2k BASS filter pin. (Left channel)

46 3 BASSL1 4.0V (Connect a 47nF capacitor
1.8k VCC
between Pins 3 and 4 (46
1.4k
and 47).)
1 (44)
1.2k The cutoff frequency is
3 (46)
4.9k determined by the built-in
47 4 BASSL2 4.0V 4V resistor and the external
capacitance.

VCC
3k

TREBLE filter pin.

48 5 TRER 4.0V (Right channel)
580 (Connect a 6.8nF capacitor
4.2k 580 between this pin and GND.)
3.4k

2.7k

2.2k

1.8k

1.4k
VCC
TREBLE filter pin.
1.2k
1 6 TREL (Left channel)
4.0V 4.9k (Connect a 6.8nF capacitor
(48) 5
between this pin and GND.)
(1) 6

VCC
3k
LSOUT right channel output
2 7 LSOUT-R 4.0V VCC pin.

580
(2) 7
(3) 8 580

3 8 LSOUT-L 4.0V LSOUT left channel output

pin.

–5–
 CXA2074Q/S

Pin No. Pin

Symbol Equivalent circuit Description
QFP SDIP voltage

VCC
7.5k

↓ 35µ
2.1V
4k
×2
Serial data I/O pin.
4 9 SDA — ×5 VIH > 0V
4.5k 3k
7.5k VIL < 1.5V

9
(4)

VCC
7.5k

↓ 35µ

2.1V
4k Serial clock input pin.
×4
VIH > 3.0V
5 10 SCL — 10.5k 3k VIL < 1.5V

10
(5)

11
6 11 DGND — Digital block GND.
(6)

VCC
10k

VCC Input the (L + R) signal from

8 12 MAININ 4.0V
MAINOUT (Pin 13 (9)).
147
12
(8) 53k

4V

VCC
15k
×4
VCC

9 13 MAINOUT 4.0V 147 (L + R) signal output pin.

13
(9)

↓ 1k
200µ

–6–
 CXA2074Q/S

Pin No. Pin

Symbol Equivalent circuit Description
QFP SDIP voltage

VCC

147
14
(11) 30k
11 14 PCINT1 4.0V

22k

Stereo block PLL loop filter

integrating pin.
VCC

147
15
(12) 10k 10k
12 15 PCINT2 4.0V
2k

×2
4k

VCC
20k 20k

Pilot cancel circuit loop filter

147 integrating pin.
13 16 PLINT 5.1V 16
(Connect a 1µF capacitor
(13)
between this pin and GND.)
20k 20k

↓ 20k ↓ 10k
26µ 50µ

VCC

50k 147
17
(14)
Audio multiplexing signal
14 17 COMPIN 4.0V 22k 20k
3k input pin.
3V

4k 4k 4k 16k 24k

–7–
 CXA2074Q/S

Pin No. Pin

Symbol Equivalent circuit Description
QFP SDIP voltage

3k 147 Band gap reference output

pin.
15 18 VGR 1.3V 9.7k 19.4k VCC
11k (Connect a 10µF capacitor
between this pin and GND.)
×4 11k 11k
18
2.06k (15)

VCC
40k 40k 30k 30k 15k 30k

×2
Set the filter and VCO
reference current. The
reference current is adjusted
VCC
with the BUS DATA based
16 19 IREF 1.3V on the current which flows to
30p 1.8k this pin.
19 (Connect a 62kΩ (±1%)
147 (16) resistor between this pin and
GND.)
6.3k
16k

20
17 20 GND — Analog block GND.
(17)

VCC
8k

10k

3k 1k
Set the time constant for the
VCC SAP carrier detection circuit.
18 21 SAPTC 4.5V 4k (Connect a 4.7µF capacitor
↓ 50µ between this pin and GND.)
21
(18)

22 Supply voltage pin.

19 22 VCC —
(19)

–8–
 CXA2074Q/S

Pin No. Pin

Symbol Equivalent circuit Description
QFP SDIP voltage

Vcc
2k 2k

10P
4k

580
21 23 SUBOUT 4.0V 23 (L – R) signal output pin.
14.4k 580 147
2k 2k (21)

2k 4k 1k

VCC
23k 23k Input the (L – R) signal from
22 24 STIN 4.0V
SUBOUT (Pin 23 (21)).
11.7k

147 147
24 27

SAPIN (22) 18k 18k (25) Input the (SAP) signal from
25 27 4.0V
SAPOUT (Pin 26 (24)).
4V 20k 4V

Vcc
8k 3.3k

10k
1k
Set the time constant for the
2k
4k noise detection circuit.
23 25 NOISETC 3.0V ×2 (Connect a 4.7µF capacitor
4V between this pin and GND.)
3k Vcc 3k

200k

25
(23)

Vcc
5P

580

SAPOUT 4.0V
580 10k SAP FM detector output pin.
24 26
26
147 (24)

24k 4k
↓ 10µ ↓ 50µ

–9–
 CXA2074Q/S

Pin No. Pin

Symbol Equivalent circuit Description
QFP SDIP voltage

VCC
7.5k

Variable de-emphasis
147 integrating pin.
26 28 VE 4.0V 28 (Connect a 2700pF capacitor
(26) and a 3.3kΩ resistor in series
between this pin and GND.)

Vcc

Weight the variable

de-emphasis control
2.9V effective value detection
580 4V
29
circuit.
27 29 VEWGT 4.0V 147 36k (Connect a 0.047µF
(27)
580 capacitor and a 3kΩ resistor
in series between this pin
and GND.)
8k 30k 4k
↓ 8µ ↓ 50µ

Vcc
Determine the restoration
time constant of the variable
de-emphasis control
effective value detection
30
×4 ×4 circuit.
28 30 VETC 1.7V (28)
(The specified restoration
time constant can be
20k obtained by connecting a
4k ↓ 7.5µ 3.3µF capacitor between this
↓ 50µ pin and GND.)

Vcc

5P
Variable de-emphasis output
580
pin.
30 31 VEOUT 4.0V 31 (Connect a 4.7µF non-polar
(30) 10k capacitor between Pins 31
580
(30) and 32 (31).)

– 10 –
 CXA2074Q/S

Pin No. Pin

Symbol Equivalent circuit Description
QFP SDIP voltage

VCC

47k 47k
VCA input pin.
20k Input the variable
31 32 VCAIN 4.0V VCC de-emphasis output signal
from Pin 31 (30) via a
32
coupling capacitor.
(31)

VCC
Determine the restoration
time constant of the VCA
×4 33 control effective value
×4
(32) detection circuit.
32 33 VCATC 1.7V (The specified restoration
time constant can be
obtained by connecting a
10µF capacitor between this
4k 20k
↓ ↓ pin and GND.)
50µ 7.5µ

VCC
40k 40k 3p

Weight the VCA control

580 effective value detection
34 circuit.
33 34 VCAWGT 4.0V 2.9V 580 147
36k (33) (Connect a 1µF capacitor
and a 3.9kΩ resistor in series
between this pin and GND.)
↓ 4k ↓ 30k 8k
50µ 8µ

35 35 AUX1-R 4.0V Right channel external input

VCC 1 pin.
10k
36 36 AUX1-L 4.0V Left channel external input
147 1 pin.
35
27.5k 36
37 37 AUX2-R 4.0V Right channel external input
37 2 pin.
47k
38
4V Left channel external input
38 38 AUX2-L 4.0V
2 pin.

– 11 –
 CXA2074Q/S

Pin No. Pin

Symbol Equivalent circuit Description
QFP SDIP voltage

VCC
3k
LPOUT right channel output
39 39 LPOUT-R 4.0V
pin.

147 580
39
580
40
LPOUT left channel output
40 40 LPOUT-L 4.0V
pin.

VCC
41 41 LPIN-R 4.0V Right channel loop input pin.
10k

147
41
42

47k
42 42 LPIN-L 4.0V Left channel loop input pin.
4V

7 — NC — (7)
10 — NC — (10)
20 — NC — (20)
29 — NC — (29)
34 — NC — (34)
43 — NC — (43)

– 12 –
 Electrical Characteristics
COMPIN input level
(100% modulation level)
Main (L + R) (Pre-Emphasis: OFF) = 245mVrms
SUB (L – R) (dbx-TV: OFF) = 490mVrms
Pilot = 49mVrms
The pin numbers in parenthesis are for the CXA2074Q.
SAP Carrier = 147mVrms
fH = 15.734kHz (Ta = 25°C, VCC = 9V)

Measurement Output
No. Item Signal Mode Input pin Input signal Filter Min. Typ. Max. Unit
conditions pin

1 Current consumption 17 No signal 30 40 50 mA

Icc
(14)
17 Mono 1kHz 100% mod.
2 Main output level Vmain MONO 39/40 440 490 540 mVrms
(14) Pre-em. ON
Main de-emphasis 17 Mono 5kHz 30% mod. 20 log
3 FCdeem MONO 39/40 –1.2 0 1.0 dB
frequency characteristic (14) Pre-em. ON ('5k'/'1k')
Main LPF frequency 17 Mono 12kHz 30% mod. 20 log
4 FCmain MONO 39/40 –3.0 –1.0 1.0 dB
characteristic (14) Pre-em. ON ('12k'/'1k')
17 Mono 1kHz 100% mod.
5 Main distortion THDm MONO 15kLPF 39/40 – 0.1 0.5 %
(14) Pre-em. ON

17 Mono 1kHz 200% mod.

6 Main overload distortion THDmmax MONO 15kLPF 39/40 – 0.15 0.5 %
(14) Pre-em. OFF

17 Mono 1kHz, 20 log

7 Main S/N SNmain MONO 15kLPF 39/40 61 69 – dB

– 13 –
(14) Pre-em. ON ('100%'/'0%')
17 SUB (L-R), 1kHz, 23
8 Sub output level Vsub ST 150 190 230 mVrms
(14) 100% mod., NR OFF (21)
Sub LPF frequency 17 SUB (L-R) 12kHz, 20 log 23
9 FCsub ST –3.0 –0.5 1.0 dB
characteristic (14) 30% mod., NR OFF ('12k'/'1k') (21)
17 SUB (L-R) 1kHz, 23
10 Sub distortion THDsub ST 15kLPF – 0.1 1.0 %
(14) 100% mod., NR OFF (21)
17 SUB (L-R), 1kHz, 23
11 Sub overload distortion THDsmax ST 15kLPF – 0.2 2.0 %
(14) 200% mod., NR OFF (21)
17 SUB (L-R) 1kHz, 20 log 23
12 Sub S/N SNsub ST 15kLPF 56 64 – dB
(14) NR OFF ('100%'/'0%') (21)
SUB (L-R), 1kHz, 20 log
ST → SAP 17 1kBPF
13 CTst SAP 100% mod., NR ON, ('NRSW = 0'/ 40 60 70 – dB
Crosstalk (14) SAP Carrier (5fH) 'NRSW = 1')

14 Sub pilot leak 17 PILOT (fH) 0dB 0dB = 49mVrms fH BPF 23 –27 dB
PCsub ST – –35
(14) (21)

15 Stereo ON level THst 0dB = 49mVrms –9.0 –6.0 –3.0 dB

17 Change BUS
ST
Stereo ON/OFF (14) PILOT (fH) Level 20 log (‘on RETURN
8.5
CXA2074Q/S

16 HYst 3.5 6.0 dB

hysteresis level'/'off level')
 Input pin Measurement Output Min. Typ. Max.
No. Item Symbol Mode Input signal Filter Unit
conditions pin
17 SAP 1kHz 100% mod. 26
17 SAP output level Vsap SAP (14) (24) 150 190 230 mVrms
NR OFF
SAP LPF frequency 17 SAP 10kHz, 30% mod. 20 log 26
18 FCsap SAP (14) –3.0 0 2.5 dB
characteristic NR OFF ('10k'/'1k') (24)
17 SAP 1kHz 100% mod. 26
19 SAP distortion THDsap SAP 15kLPF – 2.5 6.0 %
(14) NR OFF (24)
17 20 log 26
20 SAP S/N SNsap SAP SAP 1kHz, NR OFF ('100%'/'0%') 15kLPF 46 55 – dB
(14) (24)
SAP → ST 17 SAP 1kHz 100% mod. 20 log ('NRSW –
21 CTsap ST 1kBPF 40 60 70 dB
Cross talk (14) NR ON, Pilot (fH) = 1'/'NRSW = 0')

22 SAP ON level THsap Change 0dB = 147mVrms –12.0 –9.0 –6.5 dB

17 BUS
SAP SAP Carrier (5fH)
(14) 20 log (‘on RETURN
23 Level dB
SAP ON/OFF hysteresis HYsap level’/’off level’) 2.0 4.0 6.0

24 17 ST-L 300Hz 30% mod.

ST separation 1 L → R STLsep1 ST 15kLPF 39/40 23 35 – dB
(14) NR ON

25 17 ST-R 300Hz 30% mod. –

ST separation 1 R → L STRsep1 ST 15kLPF 39/40 23 35 dB
(14) NR ON
26 17 ST-L 3kHz 30% mod.
ST separation 2 L → R STLsep2 ST 15kLPF 39/40 23 35 – dB

– 14 –
(14) NR ON
17 ST-R 3kHz 30% mod.
27 ST separation 2 R → L STRsep2 ST 15kLPF 39/40 23 35 – dB
(14) NR ON
28 35/36 Sine wave 1kHz,
LPOUT output level Vtp EXT 0dB = 490mVrms 39/40 –0.5 0 0.5 dB
37/38 490mVrms

29 17 MONO 1kHz, 100%, 20 log (M1 =

MUlp1 INT (14) – –85 –70 dB
LPOUT Pre-em. on "0"/M1 = "1")
muted amount 1kBPF 39/40
30 MUlp2 35/36 Sine wave 1kHz, 20 log (M1 =
EXT "0"/M1 = "1") – –90 –75 dB
37/38 490mVrms
17 MONO 1kHz
INT 0dB = 490mVrms
(14) 100%, Pre-em. on 7/8
31 LSOUT output level Vls (2/3) –0.9 dB
0 0.9
35/36 Sine wave 1kHz, 0dB = 490mVrms
EXT
37/38 490mVrms
35/36 Sine wave 1kHz, 0dB = 490mVrms 7/8
INT 1kBPF (2/3) – –75 –60 dB
37/38 490mVrms EXT → INT
32 LSOUT cross talk CTls
17 MONO 1kHz 0dB=490mVrms 7/8 –
EXT 1kBPF –90 –80 dB
(14) 100%, Pre-em. on INT → EXT (2/3)
35/36 Sine wave 1kHz, 20 log (M2 = 7/8 – –90 –75 dB
33 LSOUT muted amount MUls EXT 1kBPF
37/38 490mVrms "0"/M2 = "1") (2/3)
CXA2074Q/S
 Measurement Output Min. Typ. Max. Unit
No. Item Symbol Mode Input pin Input signal Filter
conditions pin

Mute (M2 = 0)/

INT — DC difference 7/8 –25 0 25 mV
34 LSOUT DC offset OSls No signal when there is (2/3)
EXT
no signal

35/36 Sine wave 1kHz, 7/8 –

35 LSOUT distortion THDls EXT 37/38 15kLPF 0.01 0.5 %
490mVrms (2/3)
20 log 7/8
35/36 Sine wave 1kHz, 75 dB
36 LSOUT S/N SNls EXT ('490mVrms'/ 15kLPF (2/3) 88 –
37/38 490mVrms
'No signal')
35/36 Sine wave 1kHz, 7/8
37 LSOUT overload distortion THDlsmax EXT 15kLPF – 0.1 1.0 %
37/38 2Vrms (2/3)

35/36 Sine wave 100Hz, BASS = "F" 7/8

38 BASS maximum value TBmax EXT 11 12 13 dB
37/38 245mVrms 0dB = 245mVrms (2/3)

35/36 Sine wave 100Hz, BASS = "0" 7/8

39 BASS minimum value TBmin EXT –13 –12 –11 dB
37/38 245mVrms 0dB = 245mVrms (2/3)

35/36 Sine wave 10kHz, TREBLE = "F" 7/8

40 TREBLE maximum value TTmax EXT 11 12 13 dB

– 15 –
37/38 245mVrms 0dB = 245mVrms (2/3)

35/36 Sine wave 10kHz, TREBLE = "0" 7/8

41 TREBLE minimum value TTmin EXT 245mVrms –13 –12 –11 dB
37/38 0dB = 245mVrms (2/3)

35/36 Sine wave 1kHz, VOL-L = "0", 7/8

42 Volume minimum value VOLmin EXT 490mVrms VOL-R = "0" 1kBPF – –90 –75 dB
37/38 (2/3)
0dB = 490mVrms
CXA2074Q/S
 CXA2074Q/S

I2C BUS block items (SDA, SCL)

No. Item Symbol Min. Typ. Max. Unit
1 High level input voltage VIH 3.0 — 5.0
2 Low level input voltage VIL 0 — 1.5 V

3 High level input current IIH — — 10

µA
4 Low level input current IIL — — 10
5 Low level output voltage SDA (Pin 9) during 3mA inflow VOL 0 — 0.4 V
6 Maximum inflow current IOL 3 — — mA
7 Input capacitance CI — — 10 pF
8 Maximum clock frequency fSCL 0 — 100 kHz
9 Minimum waiting time for data change tBUF 4.7 — —
10 Minimum waiting time for start of data transfer tHD: STA 4.0 — —
11 Low level clock pulse width tLOW 4.7 — —
µs
12 High level clock pulse width tHIGH 4.0 — —
13 Minimum waiting time for start preparation tSU: STA 4.7 — —
14 Minimum data hold time tHD: DAT 0 — —
15 Minimum data preparation time tSU: DAT 250 — — ns
16 Rise time tR — — 1 µs
17 Fall time tF — — 300 ns
18 Minimum waiting time for stop preparation tSU: STO 4.7 — — µs

I2C BUS load conditions: Pull-up resistor 4kΩ (Connect to +5V)

Load capacity 200pF (Connect to GND)

I2C BUS Control Signal

SDA

tBUF tR tF tHD: STA

SCL

tSU: STA tSU: STO

P S tHD: STA tLOW tHD: DAT tHIGH tSU: DAT Sr P

– 16 –
 CXA2074Q/S

Electrical Characteristics Measurement Circuit

CXA2074Q

S6
S5
S4
BUFF
S3
FILTERS MEASURES
SIGNAL SIGNAL SIGNAL SIGNAL S2
GENE- GENE- GENE- GENE- S1 15kHz LPF
RATOR RATOR RATOR RATOR
fH BPF
V2 V4 V5 V6 1kHz BPF
AC AC AC AC

TANTALUM
TANTALUM
R1 C15 R4 R6
3.9k 4.7µ 3k 3.3k
C10 C12 C13 C14 C17 C18 C19
4.7µ 4.7µ 1µ 10µ 3.3µ 0.047µ 2700p
36 35 34 33 32 31 30 29 28 27 26 25
C28

VETC
VCAIN
NC

VE
NC
VCATC
AUX1-R

VEWGT
VEOUT
VCAWGT
AUX1-L

SAPIN
4.7µ
C2
37 24
4.7µ SAPOUT
AUX2-R

38 AUX2-L NOISETC 23
C3
C22
4.7µ
4.7µ
39 LPOUT-R STIN 22
C4
4.7µ
C29
40 LPOUT-L SUBOUT 21
C5 4.7µ
SIGNAL
4.7µ
GENERATOR
41 LPIN-R NC 20
C6
4.7µ
V1
AC
42 LPIN-L VCC 19
C7 C23 VCC
V3
4.7µ 100µ
AC V8
43 NC SAPTC 18 9V
SIGNAL C24 GND
GENERATOR 4.7µ
44 BASSR1 GND 17
GND
C8 R8
45 BASSR2 IREF 16
47n 62k METAL ± 1%

46 BASSL1 VGR 15
C25 SIGNAL
10µ GENERATOR
C9
47n
47 BASSL2 COMPIN 14
C26 V7
MAINOUT
LSOUT-R

4.7µ AC
LSOUT-L

PCINT1

PCINT2
MAININ

48 TRER PLINT 13
DGND

GND
TREL

C27
SDA

SCL

C1
NC
NC

6.8n 1µ
1 2 3 4 5 6 7 8 9 10 11 12
R7
C11 R2 R3 C20 1MEG
6.8n 220 220 C16 5600P
4.7µ
R5 C21
I2C BUS DATA 100k 0.012µ

DGND

– 17 –
 CXA2074S

S
6
S
5
S
4 BUFF
S
3 FILTER MEASURE
S S S
SIGNAL SIGNAL SIGNAL SIGNAL
GENERATOR GENERATOR SIGNAL
2
GENERATOR GENERATOR S
GENERATOR 15kHz LPF
SIGNAL 1
V1 V2 V3 V4 V5 V6 fH BPF
GENERATOR
1kHz BPF
AC AC AC AC AC AC

R2 R5 R7
C1 C3 C4 C6 C8 C10 C12 C14 3.9k 3k 3.3k C28 C31
4.7µ 4.7µ 4.7µ 4.7µ 4.7µ 4.7µ 4.7µ 4.7µ C17 C25 4.7µ C29 100µ
C15 4.7µ C21 C23

C16 10µ
4.7µ 4.7µ

C19 3.3µ
1µ 0.047µ 2700p

TANTALUM
TANTALUM
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22

VE
VCC
VCC

STIN

V8

VETC

VCAIN
SAPIN

LPIN-L
LPIN-R
VCATC
VEOUT

AUX1-L

AUX2-L
AUX1-R

AUX2-R
9V

VEWGT
SAPOUT

LPOUT-L
SUBOUT

VCAWGT

LPOUT-R
NOISETC

– 18 –
GND

MAININ

DGND

SCL

SDA

LSOUT-L

LSOUT-R

BASSL2

BASSL1

BASSR2

BASSR1
TREL

TRER
SAPTC

GND

IREF

VGR

COMPIN

PLINT

PCINT2

PCINT1

MAINOUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
R6
1MEG
C24 C26 C27 C30
C7 C9 C11 C13 R1 R3 C20 5600p 1µ 4.7µ 10µ
C2 C5 C18 4.7µ
R8 62k

6.8n 6.8n 4.7µ 4.7µ 220 220

47n 47n 4.7µ
METAL ± 1%

R4 C22
100k 0.012µ
SIGNAL
GENERATO
R GND
V7
I2C BUS DATA
AC
GND

DGND
CXA2074Q/S
 CXA2074Q/S

I2C BUS Register Data Standard Setting Values

Number Classifi- Standard Setting value when electrical

Register Contents
of bits cation setting characteristics are measured
ATT 4 A 9
VCO 6 A 1F
FILTER 6 A 1F Center point Adjustment point

SPECTRAL 6 A 1F
WIDEBAND 6 A 1F
TEST-DA 1 T 0
Normal mode Standard setting value
TEST1 1 T 0
FST 1 T 0 Normal mode FST = 0
VOL-L 6 U 3F 3F = 0dB
VOL-R 6 U 3F 3F = 0dB
BASS 4 U 8 7 or 8 = 0dB
TREBLE 4 U 8 7 or 8 = 0dB
NRSW 1 U —
According to the mode control table
FOMO 1 U —
TVSW 1 U 0
TV decoder output selection Standard setting value
EXT 1 U 0
FEXT1 1 U 0 External input 1 forced MONO Standard setting value
FEXT2 1 U 0 External input 2 forced MONO Standard setting value
PSW 1 U 0 TVSW output selection Standard setting value
M1 1 U 1
Mute OFF
M2 1 U 1
ATTSW 1 S —
Fixed by the set specifications
SAPC 1 S —

Classification A: Adjustment
U: User control
S: Proper to set
T: Test

– 19 –
 List of Adjustment Contents The pin numbers in parenthesis are for the CXA2074Q.

Adjustment Input signal Test mode

Adjustment item Input pin Measurement Adjustment contents
data data setting
COMPIN
100Hz LPOUT-L output Adjust as close to 490mVrms
1 MAIN VCA ATT Pin 17
245mVrms level as possible
(Pin 14)
ST & SAP LPOUT-R output Adjust as close to 62.936kHz
2 VCO None None TEST-DA = 1
VCO frequency as possible
COMPIN
ST & SAP 9.4kHz STA5 Adjust to the center of the
3 FILTER Pin 17 TEST1 = 1
& dbx FILTER 600mVrms (FILADJ) FILADJ = 1 condition
(Pin 14)
COMPIN
Low frequency ST-L 30% LPOUT-R output
WIDEBAND Pin 17 Minimize the output level
ST separation 300Hz level
(Pin 14)
4
COMPIN
High frequency ST-L 30% LPOUT-R output
SPECTRAL Pin 17 Minimize the output level
ST separation 3kHz level
(Pin 14)

– 20 –
CXA2074Q/S
 CXA2074Q/S

Adjustment Method (Adjust this IC through Tuner and IF when this IC is mounted on the set.)
1. ATT adjustment
1) TEST BIT is set to “TEST1 = 0” and “TEST-DA = 0”.
2) Input a 100Hz, 245mVrms sine wave signal to COMPIN and monitor the LPOUT-L output level. Then,
adjust the “ATT” data for ATT adjustment so that the LPOUT-L output goes to the standard value
(490mVrms).
3) Adjustment range: ±30%
Adjustment bits: 4 bits

2. Stereo, SAPVCO adjustment

1) TEST BIT is set to “TEST1 = 0” and “TEST-DA = 1”.
2) Monitor the LPOUT-R output (4fH free running) frequency in a no input state, and adjust “VCO”
adjustment data so that this frequency is as close to 4fH (62.936kHz) as possible.
3) Adjustment range: ±20%
Adjustment bits: 6 bits

3. Stereo, SAP block, dbx filter adjustment

1) TEST BIT is set to “TEST1 = 1” and “TEST-DA = 0”.
2) Input a 9.4kHz, 600mVrms sine wave signal to COMPIN. While monitoring the STATUS FLAG (STA5)
condition, adjust the “FILTER” adjustment data.
3) Adjustment range: ±20%
Adjustment bits: 6 bits
Align “FILTER” with the center of the STA5 = 1 (adjustment OK) condition range.

Adjustment point

Control data
"FILTER"
0 3F

1
Measurement data
0 STA5 "FILADJ"

4.Separation adjustment
1) TEST BIT is set to “TEST1 = 0” and “TEST-DA = 0”.
2) Set the unit to stereo mode and input the left channel only signal (modulation factor 30%, frequency 300Hz
NR-ON) to COMPIN. At this time, adjust the “WIDEBAND” adjustment data to reduce LPOUT-R output to
the minimum.
3) Next, set the frequency only of the input signal to 3kHz and adjust the “SPECTRAL” adjustment data to
reduce LPOUT-R output to the minimum.
4) The adjustments in 2 and 3 above are performed to optimize the separation.
5) “WIDEBAND” “SPECTRAL”
Adjustment range: ±30% Adjustment range: ±15%
Adjustment bits: 6 bits Adjustment bits: 6 bits

– 21 –
 CXA2074Q/S

Description of Operation [The pin numbers in parenthesis are for the CXA2074Q.]

The US audio multiplexing system possesses the base band spectrum shown in Fig. 1.
PEAK DEV
kHz AM-DSB-SC
50 50

L-R
dbx-TV
25 25 NR
PILOT

15
SAP
dbx-TV NR TELEMETRY
L+R 5 FM 10kHz FM 3kHz
50 – 15kHz 50 – 10kHz 3

fH 2fH 3fH 4fH 5fH 6fH 6.5fH f

fH = 15.734kHz
Fig. 1. Base band spectrum

I2C BUS
2fHL0° DECODER
PLL PILOT
fHL90° MODE
(VCO 8fH) DET
fHL0° CONTROL

STEREO LPF MAIN LPF DE.EM (MAIN OUT)

(COMPIN) (MAIN IN)
17 MVCA PILOT 13 12
CANCEL
(14) (9) 4.7µ (8)
L+R
SUB LPF WIDEBAND
(SUBOUT) (ST IN) MATRIX
L-R (DSB) SUBVCA
DET
23 24 (Lch)
(21) 4.7µ (22)
NR SW to
L–R
SAP(FM) A B TVSW
dbx-TV (Rch)
SAP BPF DET SAP LPF BLOCK
(SAP OUT)
INJ.
LOCK 26
(24) (SAP IN)

NOISE I2C BUS 27

DET DECODER 4.7µ (25) MODE
CONTROL
I2C BUS
SAP DECODER
DET MODE
CONTROL

Fig. 2. Overall block diagram (See Fig. 3 for the dbx-TV block)

(ST IN) FIXED VARIABLE

NR SW DEEMPHASIS DEEMPHASIS
(22) 24 (VE OUT) (VCA IN)
A B
to
(SAP IN) 31 32 VCA
MATRIX
(25) 27 (30) 4.7µ (31)
HPF
LPF RMS
DET
LPF
RMS
DET

Fig 3. dbx-TV block

– 22 –
 CXA2074Q/S

(AUX2-L) (AUX2-R) (LPIN-L) (LPIN-R)

38 37 42 41
(LPOUT-L) (LPOUT-R)

40 39 (LSOUT-L)
(AUX1-L) BASS TREBLE
VOL-L
36 8 (3)
TVSW PASSSW
35 7 (2)
VOL-R
(AUX1-R) (LSOUT-R)

(Lch) (Rch)

from MATRIX

Fig. 4. Sound processor block

(1) L + R (MAIN)
After the audio multiplexing signal input from COMPIN (Pin 17 (Pin 14)) passes through MVCA, the
SAP signal and telemetry signal are suppressed by STEREO LPF. Next, the pilot signals are
canceled. Finally, the L – R signal and SAP signal are removed by MAIN LPF, and frequency
characteristics are flattened (de-emphasized) and input to the matrix.

(2) L – R (SUB)
The L – R signal follows the same course as L + R before the pilot signal is canceled. L – R has no
carrier signal, as it is a suppressed-carrier double-sideband amplitude modulated signal (DSB-AM
modulated). For this reason, the pilot signal is used to regenerate the carrier signal (quasi-sine wave)
to be used for the demodulation of the L – R signal. In the last stage, the residual high frequency
components are removed by SUB LPF and the L – R signal is input to the dbx-TV block via the NRSW
circuit after passing through SUBVCA.

(3) SAP
SAP is an FM signal using 5fH as a carrier as shown in the Fig. 1. First, the SAP signal only is
extracted using SAP BPF. Then, this is subjected to FM detection. Finally, residual high frequency
components are removed and frequency characteristics flattened using SAP LPF, and the SAP signal
is input to the dbx-TV block via the NRSW circuit. When there is no SAP signal, the Pin 26 output is
soft muted.

(4) Mode discrimination

Stereo discrimination is performed by detecting the pilot signal amplitude. SAP discrimination is
performed by detecting the 5fH carrier amplitude. NOISE discrimination is performed by detecting the
noise near 25kHz after FM detection of SAP signal.

(5) dbx-TV block

Either the L – R signal or SAP signal input respectively from ST IN (Pin 24 (Pin 22)) or SAP IN (Pin 27
(Pin 25)) is selected by the mode control and input to the dbx-TV block.
The input signal then passes through the fixed de-emphasis circuit and is applied to the variable de-
emphasis circuit. The signal output from the variable de-emphasis circuit passes through an external
capacitor and is applied to VCA (voltage control amplifier). Finally, the VCA output is converted from a
current to a voltage using an operational amplifier and then input to the matrix.

– 23 –
 CXA2074Q/S

The variable de-emphasis circuit transmittance and VCA gain are respectively controlled by Each of
effective value detection circuits. Each of the effective value detection circuits passes the input signal
through a predetermined filter for weighting before the effective value of the weighted signal is
detected to provide the control signal.

(6) Matrix, TVSW, PASSSW

The signals (L + R, L – R, SAP) input to “MATRIX” become the outputs for the ST-L, ST-R, MONO and
SAP signals according to the BUS data and whether there is ST / SAP discrimination.
“TVSW” switches the “MATRIX” output signal, external input signal (input to AUX1-L, R), external input
signal (input to AUX2-L, R) and external forced MONO.
“PASSSW” switches the “TVSW” output signal and external input signal (input to LPIN-L, R).

(7) Sound processor block

The sound processor block contains, “BASS/TREBLE” tone control functions, and “VOLUME”.
BASS: ±12dB (±1.7dB/STEP at 100Hz)
TREBLE: ±12dB (±1.7dB/STEP at 10kHz)
VOLUME: 0 to –80dB (–1.25dB/STEP)

(8) Others
“MVCA” is a VCA which adjusts the input signal level to the standard level of this IC.
“Bias” supplies the reference voltage and reference current to the other blocks. The current flowing to
the resistor connecting IREF (Pin 19 (Pin 16)) with GND become the reference current.

Standard input and output levels

Input pin Pin No. Input level LPOUT output level LSOUT output level∗3
17
COMPIN 245mVrms∗1 490mVrms∗2 490mVrms∗2
(14)
AUX1-L/AUX1-R 36/35 490mVrms 490mVrms 490mVrms
AUX2-L/AUX2-R 38/37 490mVrms 490mVrms 490mVrms
LPIN-L/LPIN-R 42/41 490mVrms — 490mVrms
∗1 MONO, 25kHz Deviation, Pre-Em. off
∗2 MONO, 25kHz Deviation, Pre-Em. on
∗3 VOLUME MAX, BASS & TREBLE CENTER

– 24 –
 CXA2074Q/S

Register Specifications

Slave address

SLAVE RECEIVER SLAVE TRANSMITTER

80H (1000 0000) 81H (1000 0001)

Register table

SUB ADDRESS DATA

MSB LSB BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
∗∗∗∗0000 ∗ TEST-DA TEST1 ATT (4)
∗∗∗∗0001 ∗ VCO (6)
∗∗∗∗0010 ∗ FILTER (6)
∗∗∗∗0011 ∗ SPECTRAL (6)
∗∗∗∗0100 ∗ WIDEBAND (6)
∗∗∗∗0101 ∗ ATTSW FST NRSW FOMO SAPC M1
∗∗∗∗0110 ∗ PSW FEXT1 FEXT2 TVSW EXT M2
∗∗∗∗0111 ∗ VOL-L (6)
∗∗∗∗1000 ∗ VOL-R (6)
∗∗∗∗1001 ∗ BASS (4)
∗∗∗∗1010 ∗ TREBLE (4)
∗ : Don't Care

Status Registers

when TEST1 = 0

STA1 STA2 STA3 STA4 STA5 STA6 STA7 STA8

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
POWER
STEREO SAP NOISE — — — —
ON RESET

when TEST1 = 1

STA1 STA2 STA3 STA4 STA5 STA6 STA7 STA8

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
POWER
STEREO SAP NOISE FILADJ — — —
ON RESET

– 25 –
 CXA2074Q/S

Description of Registers

Control registers

Register Number of bits Classification∗1 Contents

ATT 4 A Input level adjustment
VCO 6 A STEREO VCO & SAP VCO free running frequency adjustment
FILTER 6 A STEREO and SAP and dbx filter adjustment
SPECTRAL 6 A Adjustment of stereo separation (3kHz)
WIDEBAND 6 A Adjustment of stereo separation (300Hz)
Turn to DAC test mode and VCO adjustment mode by means
TEST-DA 1 T
of TEST-DA = 1.
Turn to test mode by means of TEST = 1.
TEST1 1 T
(Adjustment of FILTER)
FST 1 T Turn to forced stereo by means of FST = 1.
VOL-L 6 U LSOUT-L output signal level control
VOL-R 6 U LSOUT-R output signal level control
BASS 4 U LSOUT output bass control
TREBLE 4 U LSOUT output treble control
NRSW 1 U Selection of the output signal (Stereo mode, SAP mode)
Turn to forced MONO by means of FOMO = 1.
FOMO 1 U
(Left channel only is MONO during SAP output.)
Selection of TV mode or external input mode for LPOUT
TVSW 1 U
output
Selection of external input 1 mode or external input 2 mode
EXT 1 U
for LPOUT output. (TVSW = 1)
FEXT1 1 U External input 1 forced MONO (1: forced MONO ON)
FEXT2 1 U External input 2 forced MONO (1: forced MONO ON)
PSW 1 U Selection of internal mode or LPIN mode for LSOUT output.
Selection of LPOUT mute ON/OFF
M1 1 U
(0: mute ON, 1: mute OFF)
Selection of LSOUT mute ON/OFF
M2 1 U
(0: mute ON, 1: mute OFF)
ATTSW 1 S Turn the input stage MVCA off when ATTSW = 1.
Selection of SAP mode or L + R mode according to the
SAPC 1 S
presence of SAP broadcasting
∗1 Classification U: User control
A: Adjustment
S: Proper to set
T: Test

– 26 –
 CXA2074Q/S

Status registers

Register Number of bits Contents

PONRES 1 POWER ON RESET detection; 1: RESET
STEREO 1 Stereo discrimination of the COMPIN input signal; 1: Stereo
SAP 1 SAP discrimination of the COMPIN input signal; 1: SAP
NOISE 1 Noise level discrimination of the SAP signal; 1: Noise
FILADJ 1 Status of FILTER adjustment; 1: OK range

Description of Control Registers

ATT (4): Adjust the signal level input to COMPIN (Pin 17 (Pin 14)) to the standard input level (245mVrms).
Variable range of the input signal: 245mVrms –5.0dB to +3.0dB
0 = Level min.
F = Level max.

VCO (6): Adjust STEREO & SAP VCO free running frequency (fo).
Variable range: fo ±20%
0 = Free running frequency min.
3F = Free running frequency max.

FILTER (6): Adjust the filter fo of the ST, SAP and dbx blocks.
Variable range: fo ±20%
0 = Frequency min.
3F= Frequency max.

SPECTRAL (6): Perform high frequency (fs = 3kHz) separation adjustment.

0 = Level max.
3F = Level min.

WIDEBAND (6): Perform low frequency (fs = 300Hz) separation adjustment.

0 = Level min.
3F = Level max.

TEST-DA (1): Set DAC output test mode and VCO adjustment mode.
0 = Normal mode
1 = DAC output test mode and VCO adjustment mode
In addition, the following outputs are present at Pins 40 and 39.
LPOUT-L (Pin 40): DA control DC level
LPOUT-R (Pin 39): STEREO VCO oscillation frequency (4fH)

– 27 –
 CXA2074Q/S

TEST1 (1): Set filter adjustment mode.

0 = Normal mode
1 = FILTER (STA5) adjustment mode
In addition, the following outputs are present at Pins 40 and 39.
LPOUT-L (Pin 40): SAP BPF OUT
LPOUT-R (Pin 39): NR BPF OUT

FST (1): Select forced STEREO mode

0 = Normal mode
1 = Forced stereo mode

VOL-L (6): LSOUT-L output signal level control

0 = Volume Min. (–80dB)
3F= Volume Max. (0dB)
–1.25 dB/STEP

VOL-R (6): LSOUT-R output signal level control

0 = Volume Min. (–80dB)
3F= Volume Max. (0dB)
–1.25 dB/STEP

BASS (4): LSOUT output bass control

0 = Bass Min.
7 & 8 = Bass Center (0dB)
F = Bass Max.

TREBLE (4): LSOUT output treble control

0 = Treble Min.
7 & 8 = Treble Center (0dB)
F = Treble Max.

NRSW (1): Select stereo mode or SAP mode

0 = Stereo mode
1 = SAP mode

FOMO (1): Select forced MONO mode

0 = Normal mode
1 = Forced MONO mode

TVSW (1): Select TV mode or external input mode for LPOUT output.
0 = TV mode
1 = External input mode

EXT (1): Select external input [1] mode or external input [2] mode for LPOUT output. (TVSW = 1)
0 = External input [1] mode
1 = External input [2] mode

– 28 –
 CXA2074Q/S

FEXT1 (1): Turn external input [1] to forced MONO.

0 = Normal mode
1 = External input [1] is forced MONO.
Input the same signal to both AUX1-L and AUX1-R.

FEXT2 (1): Turn external input [2] to forced MONO

0 = Normal mode
1 = External input [2] is forced MONO
Input the same signal to both AUX2-L and AUX2-R.

PSW (1) Select INT mode or LPIN mode for LSOUT output.
0 = INT mode
1 = LPIN mode

M1 (1): Mute the LPOUT-L and LPOUT-R output.

0 = Mute ON
1 = Mute OFF

M2 (1): Mute the LSOUT-L and LSOUT-R output.

0 = Mute ON
1 = Mute OFF

ATTSW (1) Select BYPASS SW of MVCA

0 = Normal mode
1 = MVCA is passed

SAPC (1): Select the SAP signal output mode

When there is no SAP signal, the conditions for selecting SAP output are selected by
SAPC.
0 = L + R output is selected
1 = SAP output is selected

– 29 –
 CXA2074Q/S

Description of Mode Control

Priority ranking: M1/M2 > TVSW/EXT > TEST-DA > TEST1 > (NRSW & FOMO & SAPC)

Mode control SAPC = 0 SAPC = 1

“Select dbx input and TV decoder output” “Select dbx input and TV decoder output”
Conditions: FOMO = 0 Conditions: FOMO = 0
NRSW = 0 (MONO or ST output) NRSW = 0 (MONO or ST output)
• During ST input: left channel: L, As on the left
right channel: R
• During other input: left channel: L + R,
NRSW right channel: L + R
NRSW = 1 (SAP output) NRSW = 1 (SAP output)
• When there is “SAP” during SAP • Regardless of the presence of SAP
discrimination discrimination,
– left channel: SAP, right channel: SAP dbx input: “SAP”
• When there is “No SAP”, output is the left channel: SAP, right channel: SAP
same as when NRSW = 0. However, when there is no SAP, SAPOUT
output is soft muted (–7dB)

“Forced MONO”

FOMO FOMO = 1
• During SAP output: left channel: L + R, right channel: SAP
• During ST or MONO output: left channel: L + R, right channel: L + R

Change the selection conditions for “MONO or ST output” and “SAP output”.
SAPC = 0: Switch to SAP output when there is SAP discrimination.
SAPC
Do not switch to SAP output when there is no SAP discrimination.
SAPC = 1: Switch to SAP output regardless of whether there is SAP discrimination.

“MUTE”
M1/M2 M1 = 0: LPOUT output is muted.
M2 = 0: LSOUT output is muted.

“TV mode/external input mode selection”

TVSW = 0: Set LPOUT output to TV mode.
TVSW/EXT TVSW = 1: Set LPOUT output to external input mode.
EXT = 0: Set LPOUT output to external input [1] mode. (TVSW = 1)
EXT = 1: Set LPOUT output to external input [2] mode. (TVSW = 1)

“TEST1”
TEST1 = 1
Return adjustment data with STATUS REGISTER as an adjustment mode.
TEST1
In addition, outputs are as follows.
left channel: SAP BPF OUT
right channel: NR BPF OUT

“TEST-DA”
TEST-DA = 1
TEST-DA Used to adjust the D/A TEST and VCO.
left channel: D/A output
right channel: STVCO oscillation frequency (4fH)

– 30 –
 CXA2074Q/S

Decoder Output and Mode Control Table 1 (SAPC = 1)

Mode detection Mode control Output

Input signal mode dbx
ST SAP NOISE NRSW FOMO SAPC input Lch Rch
0 0 0 0 ∗ 1 MUTE L+R L+R
0 0 0 1 0 1 SAP SAP SAP
0 0 0 1 1 1 SAP L+R SAP
MONO ∗1
0 ∗ 1 0 ∗ 1 MUTE L+R L+R
0 ∗ 1 1 0 1 (SAP) (SAP) (SAP)
0 ∗ 1 1 1 1 (SAP) L+R (SAP)
1 0 ∗ 0 0 1 L–R L R
1 0 ∗ 0 1 1 MUTE L+R L+R
1 1 1 0 0 1 L–R L R
1 1 1 0 1 1 MUTE L+R L+R
STEREO ∗1
1 0 0 1 0 1 SAP SAP SAP
1 0 0 1 1 1 SAP L+R SAP
1 ∗ 1 1 0 1 (SAP) (SAP) (SAP)
1 ∗ 1 1 1 1 (SAP) L+R (SAP)
0 1 ∗ 0 0 1 MUTE L+R L+R
0 1 ∗ 0 1 1 MUTE L+R L+R
0 1 0 1 0 1 SAP SAP SAP
MONO & SAP
0 1 0 1 1 1 SAP L+R SAP
0 1 1 1 0 1 (SAP) (SAP) (SAP)
0 1 1 1 1 1 (SAP) L+R (SAP)
1 1 ∗ 0 0 1 L–R L R
1 1 ∗ 0 1 1 MUTE L+R L+R
1 1 0 1 0 1 SAP SAP SAP
STEREO & SAP
1 1 0 1 1 1 SAP L+R SAP
1 1 1 1 0 1 (SAP) (SAP) (SAP)
1 1 1 1 1 1 (SAP) L+R (SAP)

Note
(SAP) : The SAPOUT output signal is soft muted (approximately –7dB).
The signal is soft muted when NOISE = 1.
∗ : Don’t care.
∗1 SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is
inputted in the weak electric field.
"NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN.

– 31 –
 CXA2074Q/S

Decoder Output and Mode Control Table 2 (SAPC = 0)

Mode detection Mode control Output

Input signal mode dbx
ST SAP NOISE NRSW FOMO SAPC input Lch Rch
0 0 ∗ ∗ ∗ 0 MUTE L+R L+R
0 1 1 0 0 0 MUTE L+R L+R
MONO ∗1 0 1 1 0 1 0 MUTE L+R L+R
0 1 1 1 0 0 (SAP) (SAP) (SAP)
0 1 1 1 1 0 (SAP) L+R (SAP)
1 0 ∗ 0 0 0 L–R L R
1 0 ∗ 0 1 0 MUTE L+R L+R
1 0 ∗ 1 0 0 L–R L R
1 0 ∗ 1 1 0 MUTE L+R L+R
STEREO ∗1
1 1 1 0 0 0 L–R L R
1 1 1 0 1 0 MUTE L+R L+R
1 1 1 1 0 0 (SAP) (SAP) (SAP)
1 1 1 1 1 0 (SAP) L+R (SAP)
0 1 0 0 0 0 MUTE L+R L+R
0 1 0 0 1 0 MUTE L+R L+R
0 1 0 1 0 0 SAP SAP SAP
0 1 0 1 1 0 SAP L+R SAP
MONO & SAP
0 1 1 0 0 0 MUTE L+R L+R
0 1 1 0 1 0 MUTE L+R L+R
0 1 1 1 0 0 (SAP) (SAP) (SAP)
0 1 1 1 1 0 (SAP) L+R (SAP)
1 1 0 0 0 0 L–R L R
1 1 0 0 1 0 MUTE L+R L+R
1 1 0 1 0 0 SAP SAP SAP
1 1 0 1 1 0 SAP L+R SAP
STEREO & SAP
1 1 1 0 0 0 L–R L R
1 1 1 0 1 0 MUTE L+R L+R
1 1 1 1 0 0 (SAP) (SAP) (SAP)
1 1 1 1 1 0 (SAP) L+R (SAP)

Note
(SAP) : The SAPOUT output signal is soft muted (approximately –7dB).
The signal is soft muted when NOISE = 1.
∗ : Don’t care.
∗1 SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is
inputted in the weak electric field.
"NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN.

– 32 –
 CXA2074Q/S

Mode Control Table 3

M1 TVSW EXT FEXT1 FEXT2 LPOUT-L LPOUT-R

1 0 – – – – MUTE MUTE
2 1 0 – – – TV (L) TV (R)
3 1 1 0 0 – AUX1-L AUX1-R
4 1 1 0 1 – AUX1-L AUX1-L
5 1 1 1 – 0 AUX2-L AUX2-R
6 1 1 1 – 1 AUX2-L AUX2-L

TV (L) / TV (R) are selected in MATRIX

TV (L): MONO, ST-L, SAP, (SAPBPFout, D/Aout)
TV (R): MONO, ST-R, SAP, (NRBPFout, STVCO freerun (4fH))

I2C BUS Signal

There are two I2C signals, SDA (Serial DATA) and SCL (Serial CLOCK) signals. SDA is a bidirectional signal.
• Accordingly there are 3 values outputs, H, L and HIZ.

H L HIZ L

• I2C transfer begins with Start Condition and ends with Stop Condition.

Start Condition S Stop Condition P

SDA

SCL

– 33 –
 CXA2074Q/S

• I2C data Write (Write from I2C controller to the IC)

L during Write
MSB MSB LSB
HIZ HIZ
SDA

SCL 1 2 3 4 5 6 7 8 9 1 8 9

S
Address ACK Sub Address ACK

MSB LSB
HIZ HIZ

1 8 9 1 8 9

DATA (n) ACK DATA (n + 1) ACK DATA (n + 2)

HIZ HIZ

8 9 1 8 9 ∗ Data can be transferred in 8-bit units to be

P set as required.
DATA ACK DATA ACK Sub address is incremented automatically.

• I2C data Read (Read from the IC to I2C controller)

H during Read

HIZ
SDA

SCL 1 6 7 8 9 1 7 8 9

S P
Address ACK DATA ACK

• Read timing

MSB LSB
IC output SDA

SCL 9 1 2 3 4 5 6 7 8 9

Read timing
ACK DATA ACK

∗ Data Read is performed during SCL rise.

– 34 –
 CXA2074Q/S

Input level vs. Distortion characteristics 1 (MONO) Input level vs. Distortion characteristics 2 (Stereo)

Input signal: Stereo L = –R

Input signal: MONO (Pre-emphasis on), 1kHz
(dbx-TVNR ON), 1kHz
0dB = 100% modulation level
10 0dB = 100% modulation level
1.0 VCC = 9V, 30kHz using LPF
VCC = 9V, 30kHz using LPF, ST mode
Measurement point: LPOUT-L/R
Measurement point: LPOUT-L/R
Distortion [%]

Distortion [%]
0.1 1.0

Standard level (100%)

–10 0 10
Input level [dB] Standard level (100%)

–10 0 10
Input level [dB]

Input level vs. Distortion characteristics 3 (SAP)

Input signal: SAP (dbx-TVNR ON)

1kHz, 0dB = 100% modulation
10 level
VCC = 9V, 30kHz using LPF, SAP mode
Measurement point: LPOUT-L/R
Distortion [%]

1.0

Standard level (100%)

–10 0 10
Input level [dB]

– 35 –
 CXA2074Q/S

Stereo LPF frequency characteristics

10

Gain [dB] 0

–5

–10

0 20 40 60 80 100
Frequency [kHz]

Main LPF and Sub LPF frequency characteristics

30

20
Gain (FC main and FC sub) [dB]

10

–10

–20

–30

–40

–50
1 2 5 7 10 20 50 70 100
Frequency [kHz]

SAP frequency characteristics and group delay

100

20 90
5fH
80
Gain
10 70
Group delay [µs]

60
Gain [dB]

0 50

40

–10 30

20
Group delay
–20 3.8fH 10
6.2fH
0
20 40 60 80 100 120

Frequency [kHz]

– 36 –
 CXA2074Q/S

BASS-TREBLE characteristics

BASS. MAX TREBLE. MAX

+12

+8
Boost amount [dB]

+4

–4

–8

–12

BASS. MIN TREBLE. MIN

20 100 1k 10k 20k

Frequency [Hz]

Input: AUX1, 2
245mVrms
Output: LSOUT

Volume characteristics

–20
LSOUT output level [dB]

–40

–60

–80
Input: AUX1, 2
1kHz, 490mVrms
Output: LSOUT

–100
0 F 1F 2F 3F
Control data VOL-L, VOL-R

– 37 –
 CXA2074Q/S

Package Outline Unit: mm

CXA2074Q 48PIN QFP (PLASTIC)

15.3 ± 0.4

+ 0.4 + 0.1
12.0 – 0.1 0.15 – 0.05

36 25
0.15

37 24

13.5
48 13 + 0.2
0.1 – 0.1

1 12

0.9 ± 0.2
+ 0.15
0.8 0.3 – 0.1
± 0.12 M
+ 0.35
2.2 – 0.15

PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN

SONY CODE LEAD TREATMENT SOLDER / PALLADIUM

QFP-48P-L04 PLATING
EIAJ CODE ∗QFP048-P-1212-B LEAD MATERIAL COPPER / 42 ALLOY

JEDEC CODE PACKAGE WEIGHT 0.7g

CXA2074S
42PIN SDIP (PLASTIC) 600mil
– 0.05
+ 0.1

+ 0.4
37.8 – 0.1
0.25

42 22
15.24 ± 0.25
+ 0.3
13.0 – 0.1

0° to 15°

1 21
1.778 ± 0.25
+ 0.4
4.6 – 0.1
0.5 MIN
3.0 MIN

0.5 ± 0.1
0.9 ± 0.15

PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN

SONY CODE SDIP-42P-02 LEAD TREATMENT SOLDER PLATING

EIAJ CODE SDIP042-P-0600-A LEAD MATERIAL COPPER / 42 ALLOY

JEDEC CODE PACKAGE WEIGHT 4.4g

– 38 –