Power Factor Correction using an

Enhancement-mode SiC JFET

Robin Kelley1,2, Michael Mazzola1, Shane Morrison2, Igor Sankin2,
David Sheridan2, and Jeff Casady2
1Center for Advanced Vehicular Systems (CAVS)

at Mississippi State University

2SemiSouth Laboratories, Inc.

mazzola@ece.msstate.edu
 Outline
• SiC switch selection issues.
• The three-terminal (non-cascoded)
enhancement-mode (Normally OFF) SiC JFET.
• Design for drop-in replacement in applications
using standard PWM ICs or MOSFET drivers.
• Results with a commercially available PFC
evaluation board (Fairchild FEB-109).
• Examination of the compression of the gate
drive voltage swing, is this the “Achilles' heel?”
SiC Switch Selection – pros & cons
1200-V SiC DMOSFET
Pros Cons
• Normally OFF • SiC MOS reliability
• Lower specific Rds(on) than Si • SiC pn body diode reliability
MOSFET (1/5 to 1/10) • Cost $$$$
• Marginally lower Rds(on)Qg
than Si MOSFET
• Modestly higher junction temp
• “Drop-in replacement” – can
go in existing sockets

1200-V SiC BJT

Pros
• Normally OFF
• Lower loss than Si MOSFET
• Much higher junction temp
Cons
• SiC base-emitter reliability
• Very low current gain
• Socket replacement?
• Cost $$$
 SiC Switch Selection – pros & cons
1200-V SiC DM Lateral Channel JFET
Pros Cons
• Lower specific Rds(on) than Si • Normally ON
MOSFET (1/10 to 1/20) • Not a socket replacement w/o
• Marginally lower Rds(on)Qg cascoded Si MOSFET
than Si • SiC pn body diode reliability
• Much higher junction temp • Cost $$ / cascode: Cost $$$

1200-V SiC EM Vertical Channel JFET

Pros Cons
• Normally OFF • Gate drive voltage swing?
Known to the • Much Lower specific Rds(on) • Cost $ / IDSS comp.: Cost $$
power than Si MOSFET (1/20 to 1/30)
semiconductor • Lower Rds(on)Qg than Si
community. • Much higher junction temp
• No body diode
Purpose • “Drop-in replacement” – can
of this go in existing sockets
work
 Range of Deliveries in Commercial Packaging
Multi-Die 600-V Rated Half-
Example list of SiC Vertical-Channel, Bridge Power Module
• With SBD in anti-parallel
JFET deliveries in commercial • With gate drive circuit
• 0.003 Ω Rds(on)
packaging by SemiSouth or CAVS • >600 A IDSS
within the last three months
Multi-Die 600-V Rated Solid-
State Power Controller
• With SBD in chopper circuit
• Pure Enhancement Mode
• 0.015 Ω Rds(on)
• 150 A IDSS

Single-Die 1200-V Rated TO-247

• 1500-V Avalanche
• 0.1 Ω Rds(on)
• 40 A IDSS

Aircraft or Ground Vehicle Power

Management & Distribution System

High-frequency AC Link Matrix Permanent-Magnet Motor Drive for

Converter Battery Electric Vehicle
 SiC Unipolar Power Switches: JFETs
600 V ~ 1200 V, 20 A ~ 50 A 4H-SiC Power JFET
Unipolar device with SiC P-N
junction gate ¾Schematic cross sections of half cells
9 Fast switching for two different power JFET concepts.
a) LC/VJFET, b) VC/VJFET:
9 Easy to parallel
9 No bipolar degradation / gate oxide (a) (b)
problems
9 High breakdown field / avalanche
rated
Vertical channel
9High channel packing density / High
electron mobility (║ to c-axis)
9VTH defined by layout
9Simple self-aligned process - Low cost
9More gate area exposed to drain: Coss
dominated by Miller capacitance
Ronald Green, Aderinto Ogunniyi, Dimeji Ibitayo, Gail Koebke1, Mark Morgenstern, Aivars Lelis, and Corey Dickens, “Evaluation of 4H-SiC DMOSFET’s for High-Power
Electronics Applications”, ICSCRM 2007, in press, Oct. 15-19, Otsu, Japan.
 SiC Unipolar Power Switches: JFETs
600 V ~ 1200 V 4H-SiC E-mode Power VJFET
¾ Drain families of curves measured at RT and 200 ºC:
8 3 Normally-Off SiC VJFET module
VGS = 3.0 V VGS = 3.0 V
2.2 mΩ•cm2
6.6 mΩ•cm2 VGS = 2.5 V ID = 150 A @ VDS = 3 V
6
ID @ 25ºC, A

ID @ 200ºC, A
200
2.9 mΩ•cm2 2 VGS = 2.5 V
VGS = 2.5 V

ID @ 25ºC, A
4 VGS = 2.0 V 150
VGS = 2.0 V
1 100
2 VGS = 2.0 V
VGS = 1.5 V VGS = 1.5 V
VGS = 1.5 V 50
0 0 VGS = 1.0 V
0 1 2 3 0 1 2 3 0
VDS, V VDS, V 0 1 2 3 4 5
VDS, V
¾ Blocking characteristics of 800 V & 1800 V normally-off VJFET:
Avalanche @ 895 V
500
1000
25˚C VDS=1800 V, 400
VGS = 0 V
VDS @ IDS = 1 mA, V

ID @ 25ºC, µA
800 100˚C VGS
GD=0 V,
150˚C ID=1.05 mA ID = 64 µA
300
600 200˚C @ VDS = 600 V
200
400
100
200
0
0
I. Sankin, D.C. Sheridan, W. Draper, V. Bondarenko, R. Kelley, 0 200 400 600
0.5 0.75 1 1.25 1.5
M.S. Mazzola, and J.B. Casady, “Normally-Off SiC VJFETs for VDS, V
VGS, V 800 V and 1200 V Power Switching Applications”, ISPSD 2008,
May. 18-22, Orlanda, FL, USA.
 Selected VJFET SiC Switch
• Blocks dielectric-limited voltage
at VGS = 0 V
• ~ +1.25 V threshold
• Single die in TO257 metal-can
Package
– Rds(on) = 80 mΩ @ T = 25°C
– IDSS = 18 A
– IG(leakage) = 8 mA @ VGS = 2.5 V
– Negligible bipolar mode (minimal
hole injection)
– “Effective beta” > 2000
• Get your own at:
– www.semisouth.com
– brice.moore@semisouth.com
 Gate Drive Level Shifting
• Typical COTS MOSFET
Controller/Driver IC’s
– Grounded unipolar supply,
VCC = 15 V.
– DC coupled, 1 to 5 A source
or sink.
• Only modification to *MOSFET or IGBT
accommodate EM VJFET:
– BJT-like drive with current
limiting resistor and parallel
dynamic bypass capacitor.
– Very high “effective beta”
preserves “insulated gate”
feature.
 Selecting the “base” drive
• RC design requirements:
– Selected VGS = +2.5V to minimize Rds(on) and maximize IDSS.
– Resistor selected to limit forward gate current at VGS = +2.5V & VGG = 15 V.
– Capacitor sized larger than Ciss for charge/discharge of Miller capacitance.

• Initially selected Cg =
10x input capacitance
of the switch; adjusted
for best performance.
• Rg = (VGG – VGS ) / IG
 “Drop-In” Demo Board Description
• FEB-109 Evaluation Board manufact. by Fairchild Semiconductor
• 300-W Off-line CCM PFC SMPS
• ML4821 PFC controller (average current mode control w/ CVR)
• 100 kHz
Boost IGBT

Boost
Diode

Rectifier PFC
Controller
FEB-109 Evaluation Board Schematic
 PFC Benchmark
• PFC demo board
specifications:
– VIN = 85 – 265 VAC
– VOUT = 400 V
– POUT = 300 W
– Fs = 100 kHz
– 600-V, 34-A IGBT as
main power switch
– Exchanged original
freewheeling diode for
comparable SiC SBD to
match current research
– Precision power
analyzer (Yokagawa IGBT switching waveforms.
PZ4000) used to VIN - rectified input voltage (purple, 100 V/div)
determine benchmark VOUT - output voltage (green, 200 V/div)
system efficiency VDS - IGBT collector-emitter voltage (blue, 200 V/div)
VGE - gate-emitter voltage (brown, 20 V/div)
 PFC Benchmark
• Precision power analyzer was used to evaluate the
system efficiency through out the universal input voltage
and the specified load range.
FEB-109 Evaluation Board Modifications

1. Replace w/ SiC SBD

2. Replace with SiC JFET

RCL
CBP

3. Change resistor value

4. Add Capacitor
Demo Board After “Drop-In” of SiC
SBD & JFET

EM SiC
JFET

SiC SBD
PFC Demo
PCB
Operating Waveforms with EM SiC JFET

• Prior to start-up, device

safely blocking at VGS = 0 V.
• After start-up, RC gate drive
level shifts driver IC output
to expected bias voltages on
JFET gate.
• Bypass capacitor in gate
driver pulls gate negative for
fast turn-off.
Efficiency after Drop-In of JFET
• Max switch current experienced at low line.
• Max efficiency experienced at full load.
• 1.25% efficiency improvement measured at low line and
max power.
91

89

87

85
Efficiency (%)

83

81

79

77

75

73
0 20 40 60 80 100
Total Load (% )
Benchmark @ 87V JFET @ 87V
 EM SiC JFET vs Si IGBT
•600-V, 34-A Si IGBT
replaced with an
800-V, 11A EM SiC
JFET.
•Ohmic region prior to
saturation leads to
significant reduction
in conduction losses
(est. 50% less)
*Red Box highlights operating
•2.5x faster turn-on region of PFC drain currents
speed (turn-off
limited by
commutation to
FWD)
 What about gate-drive voltage
compression between 0-2.5 V?
Residual
Residual charge
charge on
on bypass
bypass capacitor
capacitor
•• Negative
Negative “bounce”
“bounce” caused
caused by
by level
level shift
shift
•• Shoot
Shoot through
through prevented
prevented for
for dV
dVDG /dt ≤ 24 V/ns
DG/dt ≤ 24 V/ns

SiC JFET Drain Voltage →

SiC JFET Gate Voltage →

-6 V

PWM Controller Output →

 Conclusion
• Please moderate the impulse to say “but a JFET is a
Normally ON device.” They don’t have to be in SiC.
• Please ask your SiC switch vendor about Normally OFF
SiC JFETs. If they don’t have one, find one who does.
• Drop-in replacement of a Si IGBT with an EM SiC JFET
produced a 1.25% efficiency improvement at low-line
with no circuit optimization in a COTS PFC AC-DC
reference design.
• Counter-intuitively, following the approach reported here
for matching COTS MOSFET/IGBT gate-drives to the
EM JFET maintains full dV/dt without false operation due
to compression of the gate-voltage swing.