54 CHAPTER 1 SEMICONDUCTOR ELECTRONICS

TABLE 1.4 Additional Properties of Silicon (Lightly Doped, at 300 K Unless

Otherwise Noted)

Property Symbol Units Values

Tetrahedral radius nm 0.117

Pressure coefficient of
energy gap tlEg! tlp eV (atm)-1 -1.5 X 10-6

Intrinsic carrier densitya nj (Tin K) 3.87 X 10 16 T 3 / 2 exp [ -7~14]

4.73 x 10- 4 T2 2.1 THE SILICON PLANAR PROCESS
Bandgap 1.17- T -
+ 651 2.2 CRYSTAL GROWTH
Temperature coefficient
of lattice mobility 2.3 THERMAL OXIDATION
Electron tlJ.Ln/ tl T cm 2 (V s K)-1 -11.6 Oxidation Kinetics
Hole tlJ.Lp/ tl T cm 2 (V s K)-1 -4.3
2.4 LITHOGRAPHY AND PATTERN TRANSFER
Diffusion coefficient
Electron On cm 2 5- 1 34.6 2.5 DOPANT ADDITION AND DIFFUSION
Hole Op cm 2 5- 1 12.3 Ion Implantation
Hardness H Mohs 7.0
Diffusion
Elastic constants C 11 dyne cm 2 1.656 X 10 12 2.6 CHEMICAL VAPOR DEPOSITION
C12 0.639 X 10 12 Epitaxy
C 44 0.796 x 10 12
Nonepitaxial Films
Young's modulus
«111> direction) Y dyne cm- 2 1.9 X 10 12 2.7 INTERCONNECTION AND PACKAGING
Surface tension Interconnections
(at 1412°C) dyne cm- 2 720 Testing and Packaging
Latent heat of fusion eV 0.41
2.8 COMPOUND-SEMICONDUCTOR PROCESSING
Expansion on freezing % 9.0
Cut-off frequency of 2.9 NUMERICAL SIMULATION
lattice vibrations Vo Hz 1.39 X 1013 Basic Concept of Simulation
Grids
Main Source: H. F. Wolf, Semiconductors, Wiley, New York (1971), p. 45. Process Models
Device Simulation
Energy Levels of Elemental Impurities in Sib Simulation Challenges
Li Sb P As Bi Ni S Mn Ag Pt Hg 2.10 DEVICE: INTEGRATED-CIRCUIT RESISTOR
0~033 (f039 0.044 SUMMARY
0.049 0.069 0.18
PROBLEMS
0.35 0.33
0.37 0.33 0.37
A
0.54
Gap center - 0-,-5i5 0.53
Si -------------- -----------------------------------------------------------A -------------------------------------------------------------------- Successful engineering rests on two foundations. One is a mastery of
0.55 0.52 D
0.40 0.34
0.36 underlying physical concepts; a second foundation, at least of equal importance, is a
0.39 0.31 0.37 -0.35 D perfected technology-a means to translate engineering concepts into useful structures.
D
0.26 0.24 0.22 In Chapter 1 we reviewed the physical principles needed for integrated-circuit electron-
0.16 ics. In this chapter we discuss the technology to produce devices in silicon, a technol-
0.065
0.057 0.03
ogy now so powerful that the entire modem world has felt its impact. In addition to de-
0.045
scribing IC technology as it is now practiced, we attempt to provide a perspective on
B AI Ga In TI Co Zn Cu Au Fe 0 continuing developments in this fast-moving area.
aa plot of n; versus T at higher temperatures is given in Figure 2.10.
bThe levels below the gap center are measured from the top of the valence band and are acceptor levels unless Technological evolution toward integrated circuits began with development of an
indicated by 0 for donor level. The levels above the gap center are measured from the bottom of the conduction
understanding of diode action and the invention of the transistor in the late 1940s. At
band and are donor levels unless indicated by A for acceptor level [10J.

55
 p
56 CHAPTER 2 SILICON TECHNOLOGY
that time the semiconductor of greatest interest was germanium. Experiments with ger-
manium produced important knowledge about the growth of large single crystals having
chemical purity and crystalline perfection that were previously unachievable.
Gennanium is an element that crystallizes in a diamond-like lattice structure, in
which each atom forms covalent bonds with its four nearest neighbors. The crystal
structure is shown in Figure 1.8. Germanium has a band gap of 0.67 eV and an intrinsic
carrier density equal to 2.5 X 1013 cm- 3 at 300 K. Because of the relatively small band
gap in germanium, its intrinsic-carrier density increases rapidly with increasing temper-
ature, growing roughly to lOIS cm- 3 at 400 K (see Figure 1.9).
Because most devices are no longer useful when the intrinsic-carrier concentra-
tion becomes comparable to the dopant density, germanium devices are limited to
operating temperatures below about 70°C (343 K). As early as 1950, the temperature
limitations of germanium devices motivated research on several other semiconductors
that crystallize with similar lattice structures but can be used at higher temperatures. In
the intervening decades technological development for integrated circuits has focused
on the elemental semiconductor silicon (Eg = 1.12 eV) and the compound semiconduc-
tor gallium arsenide (Eg = 1.42 eV). Silicon is used in the overwhelming majority of
integrated circuits, while compound semiconductors, such as gallium arsenide, find
application in specialized, high-performance circuits. Compound semiconductors are
especially useful in optical devices that rely on the efficient light emission from direct-
bandgap compound semiconductors.
Most of this chapter deals with silicon technology, but the technology associated
with compound semiconductors will be briefly discussed later in this chapter. Properties
of germanium, silicon, gallium arsenide, and several other useful electronic materials
are summarized in Table 1.3 (page 52-53). Table 1.4 (page 54) lists some additional
properties of silicon.
2.1 THE SILICON PLANAR PROCESS
In addition to the good semiconducting properties of silicon, the major reason for its
widespread use is the ability to form on it a stable, controllable oxide film (silicon
dioxide Si02 ) that has excellent insulating properties. This capability, which is not
matched by any other semiconductor-insulator combination, makes it possible to intro-
duce controlled amounts of dopant impurities into small, selected areas of a silicon sam-
ple while the oxide blocks the impurities from the remainder of the silicon. The ability
to dope small regions of the silicon is the key to producing dense arrays of devices in
integrated circuits.
Two chemical properties of the Si-Si02 system are of basic importance to silicon
technology. First, selective etching is possible using liquid or gaseous etchants that attack
only one of the two materials. For example, hydrofluoric acid dissolves silicon dioxide
but not silicon. Second, silicon dioxide can be used to shield an underlying silicon crys-
tal from dopant impurity atoms brought to the surface either by high-energy ion beams
or from a high-temperature gaseous diffusion source.
b
2.1 THE SILICON PLANAR PROCESS 57
Using these features, dopant atoms can be introduced into areas on the silicon that
are not shielded by thick silicon dioxide. The shielded regions can be accurately defined
by using photosensitive polymer films exposed with photographic masks. The polymer
pattern protects selected oxide regions on the silicon surface when it is immersed in a
hydrofluoric-acid bath, or exposed to a gas-phase etchant, forming a surface consisting of
bare silicon windows in a silicon-dioxide layer. This selective etching process, originally
developed for lithographic printing applications, permits delineation of very small pat-
terns. When the silicon sample is placed in an ambient that deposits dopant atoms on the
surface, these atoms enter the silicon only at the exposed silicon windows.
Proper sequencing and repetition of the oxidation, patterning, and dopant-addition
operations just described can be used to introduce p- and n-type dopant atoms selectively
into regions having dimensions ranging down to the few hundred nanometer range. These
steps are the basic elements of the silicon planar process, so called because it is a process
that produces device structures through a sequence of steps carried out near the surface
plane of the silicon crystal.
In addition to providing a means of limiting the area of dopant introduction, a well-
formed oxide on silicon improves the electrical properties at the surface of the silicon substrate.
Because of the termination of the crystal lattice of the silicon substrate, uncompleted or dang-
ling bonds exist at an ideal free surface. As we will see in Chapter 4, these broken bonds can
introduce allowed states into the energy gap of the silicon substrate at its surface and degrade
the electrical behavior of device regions near the surface. However, a well-formed silicon-
dioxide layer on the silicon surface electrically passivates almost all of these surface states,
allowing nearly ideal behavior of the surface region of the silicon. Although the area density
of bonds at the silicon surface is about 10 15 cm- 2, the number of electrically active bonds
can be reduced to less than lOll cm- 2 by properly growing a silicon-dioxide layer on the sur-
face. The ability to remove virtually all the electrically active states at the silicon surface al-
lows the successful operation of the ubiquitous silicon metal-oxide-semiconductor (MOS)
transistor, which is the basis of most large-scale integrated circuits today.
The silicon crystals used for the planar process consist of slices (called wafers) that
are made from a large single crystal of silicon. Dopant atoms are typically added to the
silicon by depositing them in selected regions on or near the wafer surface, and then diff-
using them into the silicon. Because dopant atoms are introduced from the surface and
typical diffusion dimensions are very small, the active regions of the planar-processed de-
vices are themselves within a few micrometers* of the wafer surface. The remaining thick-
ness (generally several hundred micrometers) serves simply as a mechanical support for
the important surface region.
A major advantage of the planar process is that each fabrication step (prior to pack-
aging) is typically applied to the entire wafer. Hence, it is possible to make and inter-
connect many devices with high precision to build an integrated circuit (1C). At present,
individual ICs typically measure up to 20 mm on a side, so that a wafer (most often
20-30 em in diameter) can contain many ICs. There is clear economic advantage to in-
creasing the area of each wafer and, at the same time, reducing the area of each integrated
circuit built on the wafer.
The most important steps in the planar process, shown in Figure 2.1, include (a)
formation of a masking oxide layer, (b) its selective removal, (c) deposition of dopant
atoms on or near the wafer surface, and (d) their diffusion into the exposed silicon re-
gions. These processes determine the location of the dopants which, in tum, detennines
the electrical characteristics of the devices and ICs.
* 1 micrometer = 1 [Lm. sometimes called a micron, equals 10- 4 em = 103 nm = 104 A (angstrom).
 ----------------------------------------,. .. ----------------------------------------------~

58 CHAPTER 2 SILICON TECHNOLOGY 2.1 THE SILICON PLANAR PROCESS 59

(a)

Si0 2 selectively removed

(b)

Dopant atoms deposited

on exposed surfaces

(e)

FIGURE 2.1 Basic fabrica-

tion steps in the silicon
planar process: (a) oxide
formation, (b) selective oxide
removal, (c) deposition of
dopant atoms on wafer,
(d) diffusion of dopant
atoms into exposed regions
(d) of silicon.
FIGURE 2.2 Evolution of Ie technology. (a) First commercial silicon planar transistor (1959)
(outer diameter 0.87 mm). (b) Diode-transistor logic (DTL) circuit (1964) (chip size 1.9 mm
Refinements of the planar process and, along with it, the growth of silicon-based square). (c) 256-bit bipolar random access memory (RAM) circuit (1970) (chip size 2.8 x 3.6
electronics has been amazingly rapid and continuous. Figure 2.2 gives some perspective mm). (d) VLSI central-processor computer chip containing 450,000 transistors (1981). The dif-
to the development of silicon integrated-circuit technology over the past 40 years. ferent functions carried out by the IC are labeled on the figure (chip size 6.3 mm square).
[(a), (b)' (c) courtesy of B.E. Deal-Fairchild Semiconductor, (d) Courtesy of Hewlett-Packard
The minimum feature size on an integrated circuit has continued to evolve at a rapid
Co.l (e) Block diagram of Pentium 4 processor with 42 million transistors (2000); the corre-
rate, decreasing from 8 /-Lm in 1969 to 130 nm* today. The rate of evolution can be ap-
sponding chips photo is shown on the book cover. (Courtesy of Intel Corporation.) (f) Mini-
preciated by plotting the minimum feature size (on a logarithmic scale) versus year of first mum feature size versus year of first commercial production. (g) Another embodiment of
commercial production, as shown in Figure 2.2j. The straight line on this plot indicates Moore's law shows that the number of transistors per chip has doubled every 18-24 months
the exponential decrease in the minimum feature size. The exponential change was first for approximately 30 years. (h) Along with decreasing feature size, the number of electrons
quantified by Gordon Moore of Intel Corporation and is known as "Moore's Law." in each device decreases. [(f}-(h) adapted from Mark Bohr, Intel; Howard Huff, Sematech;
(Moore's law is so well recognized and frequently cited that it has even been mentioned Joel Birnbaum, Hewlett-Packard; Motorola.l
in the cartoon "Dilbert" [1]. Along with the rapid decrease in minimum feature size, the
size of the IC chip continues to increase, although less rapidly than the minimum feature
size decreases. Because of the combination of smaller features and larger chips, the number

* 1 nanometer (nm) = 10- 9 m = 10- 7 cm = 10- 1 fLm.

hr
 60 CHAPTER 2 SILICON TECHNOLOGY 2.1 THE SILICON PLANAR PROCESS 61

109~-----------------------------------------------=~

.~ 107~-------------------------------.~--------------~
-5
g,
~ 106
.~
§
~ 105~------------~~--------------------------------~

lif~----~~----------------------------------------~

1972 1976 1980 1984 1988 1992 1996 2000 2004 2008
Year
(g)

-
104

(e)
~ .
. I per Ch'lp
T ranslstors

~6M~
-
103
256M

~ ...IG
<l)
10 11m .;;:u
OJ

"''"" 102
OJ
N
OJ
0..
l!l
~
~~
t'I ;; 'u;
~ 111m g
u
10 1 =--- -
~ .... .... ....
'1, '~ ~
"
;;;
cll .... .... .,.
II"
E 10°
.5"c
::§
100nm
10- 1
1988 1992 1996
:1
2000 2004 2008 2012 2016 2020
Year
10nmL-____L __ _ _ _L __ _ _ _L __ _ ~_ _ _ _ _ _L __ _ _ _L __ _ _ _ _ _ _ _~
(h)
1964 1970 1976 1982 1988 1994 2000 2006 2012
FIGURE 2.2 (continued)
Year
(j)
FIGURE 2.2 (continued)
Once Moore's law was well accepted, it became almost a self-fulfilling prophecy.
of transistors on an Ie chip increases even more rapidly--doubling every 18-24 months By extrapolating from the past evolution of feature size shown in Figure 2.2f, a target
(Figure 2.2g). This rapid increase is made possible by continuing technological develop- value for minimum feature size is determined for each future year. Projections for feature
ment, while the basic physics of the transistors remains relatively constant. (However, sec- size and other physical and electrical characteristics have been quantified in an
ondary effects that were less important in large transistors can dominate the behavior of "International Technology Roadmap for Semiconductors" (ITRS) [3], which is updated
smaller transistors.) frequently. Semiconductor manufacturers then devote the resources needed to develop the
Because different manufacturing equipment is often needed to produce circuits technology required to produce features of the predetermined size. In fact, the changes
with smaller features, the decrease of feature size is not continuous. Rather, the area of can sometimes exceed the predicted rate of improvement. If the predetermined size is typ-
a transistor for each device "generation" decreases by a ratio that provides enough ben- ical for the industry, then each company tries to develop the technology more rapidly than
efit to justify the cost of new equipment. Typically the area decreases by a factor of predicted to give it a competitive advantage in the market.
two, so the linear dimension decreases by a factor of 1.4 (i.e., the dimension "scales" Device scaling cannot continue indefinitely, however. It will be limited by two fac-
by 0.7). Device features of 60 nm are produced today. and features of 20-30 nm have tors. First, as the device features scale to smaller dimensions, the number of electrons
been demonstrated [2]. within each transistor decreases, as shown in Figure 2.2h. As the number of electrons n

hn
62 CHAPTER 2 SILICON TECHNOLOGY
2.2 CRYSTAL GROWTH 63

decreases, the statistical fluctuations in the number (~vn) becomes an increasing frac-
tion of the total, limiting circuit performance and making circuit design more difficult.
Several years ago, these statistical fluctuations began to impact the performance of ana-
log circuits. Within a few years, similar fluctuations will influence digital circuit design.
Considerably after statistical fluctuations become important, we will reach the time
at which each transistor contains only one electron (perhaps about 2015). At that point,
the entire concept of electronic devices must change. A number of different alternatives
are being investigated in advanced research laboratories, but no favored approach has
yet emerged.
Second, even in the shorter term with conventional devices, each generation of tech-
nology becomes more difficult and more expensive. The lithography needed to define
increasingly small dimensions is often limiting. Eventually, the cost of technology devel-
opment and manufacturing equipment is likely to limit the further evolution of IC tech-
nology. A modern IC manufacturing facility can cost several billion U.S. dollars today,
and the cost is continuing to increase. The high cost of the manufacturing facilities limits
the number of companies that can afford to manufacture ICs. In fact, many companies
have the circuits they design manufactured by "foundries" that specialize in high-volume
manufacturing of ICs for other companies.
However, even with these future limitations, the planar process will continue to dom-
inate electronics for a number of years. The benefits it has provided for computers,
communications, and consumer products have led to the continuing huge investment in
research and development and manufacturing facilities. The planar process is the founda-
tion for the production of silicon integrated circuits and continually evolves to allow
production of increasingly complex circuits. Making the best use of its many degrees of
freedom in understanding and designing devices requires a fairly thorough understanding
of the basic elements of silicon technology. Much of the remainder of this chapter is di-
rected toward providing such an understanding and a basis for the discussion of devices
in the following chapters.
trichlorosilane from any other chloride complexes. The purified trichlorosilane is then re-
duced by hydrogen to form high-purity, semiconductor-grade, solid silicon. At this point,
the silicon is polycrystalline, composed of many small crystals with random orientations.
This elemental poly crystalline silicon, also called polysilicon, is usually deposited on a
high-purity rod of semiconductor-grade silicon to avoid contamination.
The silicon is then formed into a large (about 20-30 cm diameter), nearly perfect,
single crystal because grain boundaries and other crystalline defects degrade device
performance. Sophisticated techniques are needed to obtain single crystals of such high
qUality. These crystals can be formed-by either the Czochralski (CZ) technique or the
float-zone (FZ) method.
Czochralski Silicon. In the Czochralski technique, which is most widely used to
form the starting material for integrated circuits, pieces of the polysilicon rod are first
melted in a fused-silica crucible in an inert atmosphere (typically argon) and held at a
temperature just above 1412°C, the melting temperature of silicon (Figure 2.3).
A high-quality seed crystal with the desired crystalline orientation is then lowered
into the melt while being rotated, as indicated in Figure 2.3a. The crucible is simultane-
ously turned in the opposite direction to induce mixing in the melt and to minimize
temperature nonunifornlities. A portion of the seed crystal is dissolved in the molten sil-
icon to remove the strained outer portions and to expose fresh crystal surfaces. The seed
is then slowly raised (or pulled) from the melt. As it is raised, it cools, and material from
the melt solidifies on the seed, forming a larger crystal, as shown in Figure 2.3b. Under
the carefully controlled conditions maintained during growth, the new silicon atoms con-
tinue the crystal structure of the already solidified material. The desired crystal diameter
is obtained by controlling the pull rate and temperature with automatic feedback mecha-
nisms. In this manner cylindrical, single-crystal ingots of silicon can be fabricated. As
crystal-growing technology has developed, the diameter of the cylindrical crystals has
increased progressively from a few mm to the 20 or 30 cm common today.

2.2 CRYSTAL GROWTH

Silicon used for the production of integrated circuits consists of large, high-quality, sin-
gle crystals [4]. What is meant by "high quality" can be better understood from a brief
consideration of the ultimate requirements placed on the silicon.
Typical IC applications require dopant concentrations ranging from roughly 10 15 to
10 atoms cm - 3 • To control device properties, any unintentional or background concen-
20
Solid
trations of electrically active impurity atoms should be at least two orders of magnitude silk:on
lower than the minimum intentional dopant concentration-that is, about 1013 cm- 3 or 0 o 0 o
lower. Because silicon contains roughly 5 X 10 22 atoms cm- 3 , the presence of only about 0 Seed o 0 o
one unintentional, electrically active, impurity atom per billion silicon atoms can be tol- 0
crystal
o Heating 0 o
erated. This high purity is well beyond that required for the raw material in virtually any coils
0 o 0 o
other industry; the routine production of material of this quality for the manufacture of
Molten Molten Solid-liquid
integrated circuits demonstrates the extraordinary refinement of silicon technology. 0 o 0 o
silicon silicon interface
High-purity silicon is obtained from two common materials: silicon dioxide (found 0 o 0 o
in common sand) and elemental carbon. In a high-temperature (~2000°C) electric-arc fur-
nace, the carbon reduces the silicon dioxide to elemental silicon, which condenses as about (al (b)
90% pure, metallurgical-grade silicon-still not pure enough for use in semiconductor de- FIGURE 2.3 Formation of a single-crystal semiconductor ingot by the Czochralski
vices. The metallurgical-grade silicon is purified by converting it into liquid trichlorosi- process: (a) initiation of the crystal by a seed held at the melt surface, (b) withdrawal
lane (SiHCI 3), which can be purified. Selective distillation (fractionation) separates the of the seed "pulls" a single crystal.

...
 f
64 CHAPTER 2 SILICON TECHNOLOGY
For many integrated-circuit processes, an initial dopant density of about 10 15 cm - 3
is desired in the silicon. This dopant concentration is obtained by incorporating a small,
carefully controlled quantity of the desired dopant element, such as boron or phos-
phorus, into the melt. Typically, dopant impurities weighing about one-tenth milligram
must be added to each kilogram of silicon. For accurate control, small quantities of
heavily doped silicon, rather than the elemental dopant, are usually added to the un-
doped melt. The dopant concentration in the pulled crystal of silicon is always less
than that in the melt because dopant is rejected from the growing crystal into the melt
as the silicon solidifies. This segregation causes the dopant concentration in the melt
to increase as the crystal grows, and the seed end of the crystal is less heavily doped
than is the tail end. Slight dopant-concentration gradients can also exist along the crystal
radius in Czochralski silicon.
Czochralski silicon contains a substantial quantity of oxygen, resulting from the
slow dissolution of the fused-silica (silicon dioxide) crucible that holds the molten sili-
con. Oxygen does not contribute significantly to the net dopant density in the moderately
doped wafers used for silicon integrated circuits. However, the typical inclusion of about
10 18 cm- 3 oxygen atoms (the solid solubility of oxygen in silicon at the solidification tem-
perature) in silicon crystals produced by the Czochralski process can be used to control
the movement of unintentional impurities (typically metals) in IC wafers. At the temper-
atures used in integrated-circuit processing, oxygen can precipitate, forming sites on which
other impurities tend to accumulate. If the oxygen precipitates are located within an ac-
tive device, they degrade its performance. However, if they are remote from active de-
vices, precipitates can function as gettering sites for unwanted impurities, attracting them
away from electrically active regions and improving device properties. Control of the lo-
cation and size of the oxygen precipitates is important in determining the uniformity of
device properties in high-density integrated circuits.
Convective flow of the molten silicon accelerates erosion of the crucible, increas-
ing the oxygen content in the melt and in the solidifying crystal. The convective flow can
also contribute to instabilities in the crystal growth process, degrading the structure of the
growing crystal. The convective flow can be suppressed by superposing magnetic fields
on the melt. This magnetically confined Czochralski growth technique offers the possibility
of improved control over the crystal-growth process and increased purity of the resulting
crystal.
A small fraction of the included oxygen, about 0.01 % of the total, can act as donors
after moderate-temperature heat treatments. This small concentration (about 10 14 cm- 3)
does not appreciably alter the resistivity of most integrated-circuit silicon. However, for
the high-resistivity (20-100 O-cm) silicon used to produce power devices and for other
specialized applications, oxygen can become a problem. For this reason, high-resistivity
silicon is usually formed by the float-zone process.
Float-Zone Silicon. In the float-zone process, a rod of cast polycrystalline silicon
is held in a vertical position and rotated while a melted zone (between I and 2 cm long)
is slowly passed from the bottom of the rod to the top, as shown in Figure 2.4. The melted
region is heated [usually by a radio-frequency (RF) induction heater] and moved through
the rod starting from a seed crystal that initiates crystallization. The impurities tend to
segregate in the molten portion so that the solidifying silicon is purified. In contrast to
Czochralski-processed silicon, oxygen is not introduced into float-zone silicon because
the silicon is not held in an oxygen-containing crucible. Although it is a more costly
process and limited to smaller-diameter ingots, the silicon produced by the float-zone
process typically contains about 1% as much oxygen as that produced by the Czochralski
b
2.2 CRYSTAL GROWTH 65
Holder
Polycrystalline
cast rod --+--
Heating coil
Single-crystal silicon
Molten zone
Seed crystal
Holder
FIGURE 2.4 The float-zone
process. A molten zone passes
through a polycrystalline-silicon
rod, and a single crystal grows
from a seed at the bottom end.
method, and other impurity concentrations are also reduced. Multiple passes of the molten
zone can be used to produce silicon with resistivities above 104 O-cm.
Wafer Production. Once the single-crystal ingot is grown and ground to a precise
diameter, it is sliced with a diamond saw into thin, circular wafers. The wafers are chem-
ically etched to remove sawing damage and then polished with successively finer polish-
ing grits and chemical etchants until a defect-free, mirror-like surface is obtained. The
wafers are then ready for device fabrication.
Before slicing, index marks are placed on the wafer to facilitate the orientation of
processed circuits along specific crystal directions. In particular, edges of an area on the
wafer called a die or a chip are typically aligned in directions along which the wafer read-
ily breaks so that the dice can be separated from one another after planar processing is
completed. This separation is often accomplished by scribing between them with a sharp
stylus and breaking them apart, so the orientation of the easy cleavage planes is impor-
tant. On smaller wafers the crystal directions are indicated by grinding aflat on the wafer,
usually perpendicular to an easy cleavage direction. In most cases, the primary flat is
formed along a (110) direction. A smaller secondary flat is sometimes added to identify
the orientation and conductivity type of the wafer, as shown in Table 2.1. On larger wafers,
using wafer flats would appreciably decrease the wafer area and the number of chips on
the wafer. Therefore, the wafer flats are omitted on larger wafers, and the crystal axes are
indicated by a small notch placed at the edge of the wafer.
66 CHAPTER 2 SILICON TECHNOLOGY 2.3 THERMAL OXIDATION 67

TABLE 2.1 Location of Secondary

Wafer Flat

Secondary Flat ~~--~~-------------------------------

Crystal (Relative to Silicon wafers I
Conductivity I

lJJJJJJ))}
I
Orientation Type Primary Flat) J
J
\
(100) n 180 0 \
\
(100) P 90° ~-~-----------------------/------- Quartz
tube
(111 ) n 45° Quartz carrier
(111 ) P No secondary flat

Furnace
FIGURE 2.5 An insulating layer of silicon dioxide is grown on silicon wafers by
After slicing, a unique wafer number is often marked on the wafer surface by va- exposing them to oxidizing gases in a high-temperature furnace.
porizing small spots of silicon with a laser. The marks identify the manufacturer, ingot,
dopant species, and crystal orientation. Other digits are unique to a wafer, allowing each
wafer to be identified at any point in the wafer-fabrication process. The laser marks can hydrogen in the furnace. A steam environment can also be formed by passing high-purity,
be read both manually by equipment operators and also by automated process equipment. dry oxygen or nitrogen through water heated almost to its boiling point. The overall ox-
The laser marks are added before the wafer is etched and polished so that strain from the idation reactions are
marking process can be removed by chemical etching and stray spattered material does
not contaminate the fine surface finish after polishing. (2.3.1 a)
and

2.3 THERMAL OXIDATION (2.3.lb)

Oxidation proceeds much more rapidly in a steam ambient, which is consequently
An oxide layer about 2 nm thick quickly forms on the surface of a bare silicon wafer in used for the formation of thicker protective layers of silicon dioxide. Growth of a thick
room-temperature air. The thicker (typically 8 nm to 1 ,um) silicon dioxide layers used to oxide in the slower, dry-oxygen environment can lead to undesirable movement (redist-
protect the silicon surface during dopant incorporation can be formed either by thermal ribution) of impurities introduced into the wafer during previous processing.
oxidation or by deposition. When silicon dioxide is formed by deposition, both silicon Oxidation takes place at the Si-Si02 interface so that oxidizing species must dif-
and oxygen are conveyed to the wafer surface and reacted there (Sec. 2.6). In thermal ox- fuse through any previously formed oxide and then react with silicon at this interface
idation, however, there is a direct reaction between atoms near the surface of the wafer (Figure 2.6). At lower temperatures and for thinner oxides, the surface reaction rate at the
and oxygen supplied in a high-temperature furnace. Thermally grown oxides are gener- Si-Si02 interface limits the growth rate, and the thickness of the oxide layer increases
ally of a higher quality than deposited oxides. Although their structure is amorphous, they linearly with increasing oxidation time.
typically have an exact stoichiometric ratio (Si0 2), and they are strongly bonded to the At higher temperatures and for thicker oxides, the oxidation process is limited by
silicon surface. The interface between silicon and thermally grown Si02 has stable and diffusion of the oxidizing species through the previously formed oxide. In this case the
controllable electrical properties. As we will see in Chapter 8, the quality of this excel- grown oxide thickness is approximately proportional to the square root of the oxidation
lent semiconductor-insulator interface is fundamental to the successful production of time. This square-root dependence is characteristic of diffusion processes and sets a
metal-ox ide-semiconductor (MaS) transistors. practical upper limit on the thickness that can be conveniently obtained.
To form a thermal oxide, the wafer is placed inside a quartz tube that is set within
the cylindrical opening of a resistance-heated furnace. This furnace can be oriented
horizontally, as shown in Figure 2.5, or vertically. The wafer surface is usually perpendi-
cular to the main gas tlow. Temperatures in the range of 850 to 1100°C are typical, the
Gas stream I FIGURE 2.6 Three fluxes that
.F(l) characterize the oxidation rate: F{ 1)
reaction proceeding more rapidly at higher temperatures. Silicon itself does not melt until
the flow from the gas stream to the
the temperature reaches 1412°C, but oxidation temperatures are kept considerably lower
surface, F(2) the diffusion of oxidiz-
to reduce the generation of crystalline defects and the movement of previously introduced
dopant atoms. In addition, the quartz furnace tube and other fixtures start to soften and
t F (2) Silicon dioxide film ing species through the already
formed oxide, and F(3) the reaction
degrade above 1150°C. Silicon wafer at the Si-Si0 2 interface. The concen-
The oxidizing ambient can be dry oxygen, or it can contain water vapor, which is tration of the oxidizing species
generally produced by reaction of oxygen and hydrogen in the high-temperature furnace. varies in the film from Co near the
Use of such pyrogenic steam requires careful safety procedures to handle explosive hy- gas interface to Ci near the silicon
drogen gas, and a slight excess of oxygen is generally introduced to avoid having unreacted interface.

Chapter
3 8. Describe the benefits in the wafer fab process that come from flat
Crystal Growth and
Silicon Wafer Preparation
Overview
In this chapter, the preparation of semiconductor-grade silicon from
sand, its conversion into crystals and wafers (material preparation
stage), and the processes required to produce polished wafers (crystal
growth and wafer preparation) are explained.
Objectives
Upon completion of this chapter, you should be able to:
1. Explain the difference between crystalline and noncrystalline ma-
terials.
2. Explain the differences between a polycrystalline and a single
crystalline material.
3. Draw a diagram of the two major wafer crystal orientations used
in semiconductor processing.
4. Explain the Czochralski, float zone and liquid crystal encapsulated
Czochralski methods of crystal growing.
5. Draw a flow diagram of the wafer preparation process.
6. Explain the use and meaning of the flats or notches ground on wa-
fers.
7. Describe the benefits in the wafer fab process that come from edge-
rounded wafers.
51
52 Chapter 3
and damage-free wafer surfaces.
Introduction
The evolution of higher-density and larger-size chips has required
the delivery of larger diameter wafers. Starting with 1-in diameter
wafers in the 1960s, the industry is now introducing 300-mm (12-in)
diameter wafers into production lines. According the International
Technology Roadmap for Semiconductors, 300-mm wafers will be the
standard diameter until about 2007, and 400- or 450-mm diameter
wafers are predicted for the far future (Figure 3.1). Larger-diameter
wafers are necessary to accommodate increasing chip sizes with cost
effective wafer fabrication processes (see Chaps. 6 and 15). The chal-
lenges in wafer preparation are formidable. In crystal growth, the is-
sues of structural and electrical uniformity and contamination
become challenges. In wafer preparation, flatness, diameter control,
and crystal integrity are issues. Larger diameters are heavier, which
requires more substantial process tools and, ultimately, full automa-
tion. A production lot of 300-mm diameter wafers weighs about 20 lb
(7.5 kg) and can have a production value of half a million dollars or
more.1 These challenges coexist with ever tightening specifications
for almost every parameter. Keeping abreast of these challenges and
providing ever larger diameter wafers is a key to continued micro-
chip evolution.
Semiconductor Silicon Preparation
Semiconductor devices and circuits are formed in and on the surface of
wafers of a semiconductor material, usually silicon. Those wafers
must have very low levels of contaminants, be doped to a specified re-
sistivity level, have a specific crystal structure, be optically flat, and
meet a host of other mechanical and cleanliness specifications. Manu-
facture of IC grade silicon wafers proceeds in four stages.
Year of
production 2001 2006 2012
Wafer
diameter (mm) 300 300 450
Figure 3.1 Wafer diameters. (Courtesy of
SIA.)
 Crystal Growth and Silicon Wafer Preparation 53 54 Chapter 3

Silicon wafer preparation stages Another term used to reference crystal structures is lattice. A crys-
talline material is said to have a specific lattice structure and that the
■
Conversion of ore to a high-purity gas atoms are located at specific points in the lattice structure.
The number of atoms, relative positions, and binding energies be-
■
Conversion of gas to polysilicon silicon
tween the atoms in the unit cell gives rise to many of the characteris-
■
Conversion of polysilicon silicon to a single crystalline, doped crystal tics of the material. Each crystalline material has a unique unit cell.
ingot Silicon atoms have 16 atoms arranged into a diamond structure
(Fig. 3.3). GaAs crystals have 18 atoms in a unit cell configuration
■
Preparation of wafers from the crystal ingot
called a zincblend (Fig. 3.4).
The first stage of semiconductor manufacturing is the extraction and
purification of the raw semiconductor material(s) from the earth. Puri- Poly and single crystals
fication starts with a chemical reaction. For silicon, it is the conver-
sion of the ore to a silicon-bearing gas such as silicon tetrachloride or The second level of organization within a crystal is related to the orga-
trichlorosilane. Contaminants, such as other metals, are left behind in nization of the unit cells. In intrinsic semiconductors, the unit cells
the ore remains. The silicon bearing gas is then reacted with hydrogen are not in a regular arrangement to each other. The situation is simi-
(Fig. 3.2) to produce semiconductor grade silicon. The silicon produced lar to a disorderly pile of sugar cubes, with each cube representing a
is 99.9999999 percent pure, one of the purist materials on Earth.2 It unit cell. A material with such an arrangement has a polycrystalline
has a crystal structure known as polycrystalline or polysilicon. structure.
The second level of organization occurs when the unit cells (sugar
cubes) are all neatly and regularly arranged relative to each of the
Crystalline Materials others (Fig. 3.5). Materials thus arranged have a single (or mono-)
crystalline structure.
One way that materials differ is in the organization of their atoms. In
some materials, such as silicon and germanium, the atoms are ar-
ranged into a very definite structure that repeats throughout the ma-
terial. These materials are called crystals.
Materials without a definite periodic arrangement of their atoms
are called noncrystalline or amorphous. Plastics are examples of
amorphous materials.

Unit cells

There are actually two levels of atomic organization possible for crys- Figure 3.3 Unit cell of silicon.

talline materials. First is the organization of the individual atoms.

The atoms in a crystal arrange themselves at specific points in a
structure known as a unit cell. The unit cell is the first level of orga-
nization in a crystal. The unit cell structure is repeated everywhere
in the crystal.

Figure 3.4 GaAs crystal struc-

ture.

Figure 3.2 Hydrogen reduction of trichlorosilane.

 Crystal Growth and Silicon Wafer Preparation 55 56 Chapter 3

Figure 3.5 Poly- and single-crystal structures.

Figure 3.6 Crystal planes.

Single-crystal materials have more uniform and predictable proper-

ties than polycrystalline materials. The structure allows a uniform
and predictable electron flow in semiconductors. At the end of the fab
process, crystal uniformity is essential for separating the wafer into
die with non-ragged edges (see Chapter 18).

Crystal Orientation

In addition to the requirement of a single-crystal structure for a wafer,

there is the requirement of a specific crystal orientation. This concept
can be visualized by considering slicing the single crystalline block in
shown in Fig. 3.5. Slicing it in the vertical plane would expose one set
of planes, while slicing it corner-to-corner would expose a different Figure 3.7 Wafer orientation in-
plane. Each plane is unique, differing in atom count and binding ener- dicators.
gies between the atoms. Each has different chemical, electrical, and
physical properties that are imparted to the wafers. Specific crystal
orientations are required for the wafers.
Crystal planes are identified by a series of three numbers known as into quarters or with right angle (90°) breaks. The 〈111〉 wafers break
Miller Indices. Two simple cubic unit cells nestled into the origin of a into triangular pieces.
XYZ coordinate system are shown in Fig. 3.6. The two most common
orientations used for silicon wafers are the 〈100〉 and the 〈111〉 planes.
Crystal Growth
The plane designations are verbalized as the one-oh-oh plane and the
one-one-one plane. The brackets indicate that the three numbers are Semiconductor wafers are cut from large crystals of the semiconduct-
Miller indices. ing material. These crystals, also called ingots, are grown from chunks
〈100〉 oriented wafers are used for fabricating MOS devices and cir- of the intrinsic material, which have a polycrystalline structure and
cuits, while the 〈111〉 oriented wafers are used for bipolar devices and are undoped. The process of converting the polycrystalline chunks to a
circuits. GaAs wafers are also cut along the 〈100〉 planes of the crystal. large crystal of single-crystal structure, with the correct orientation
Note that the 〈100〉 plane in Fig. 3.6 has a square shape, while the and the proper amount of N- or P-type, is called crystal growing.
〈111〉 plane is triangular in shape. These orientations are revealed Three different methods are used to grow crystals: the Czochralski,
when wafers are broken as shown in Fig. 3.7. The 〈100〉 wafers break liquid encapsulated Czochralski, and float zone techniques.
 Crystal Growth and Silicon Wafer Preparation
Czochralski (CZ) method
The majority of silicon crystals are grown by the CZ method (Fig. 3.8).
The equipment consists of a quartz (silica) crucible that is heated by
surrounding coils that carry radio frequency (RF) waves or by electric
heaters. The crucible is loaded with chunks of polycrystalline of the
semiconductor material and small amounts of dopant. The dopant ma-
terial is selected to create either an N-type or P-type crystal. First, the
poly and dopants are heated to the liquid state at 1415°C (Fig. 3.9).
Next, a seed crystal is positioned to just touch the surface of the liquid
material (called the melt). The seed is a small crystal that has the
same crystal orientation required in the finished crystal. Seeds can be
Figure 3.8 Czochralski crystal-growing system.
Figure 3.9 Crystal growth from a seed.
57 58 Chapter 3
produced by chemical vapor techniques. In practice, they are pieces of
previously grown crystals and are reused.
Crystal growth starts as the seed is slowly raised above the melt.
The surface tension between the seed and the melt causes a thin film
of the melt to adhere to the seed and then to cool. During the cooling,
the atoms in the melted semiconductor material orient themselves to
the crystal structure of the seed. The net effect is that the crystal ori-
entation of the seed is propagated in the growing crystal. The dopant
atoms in the melt become incorporated into the growing crystal, creat-
ing an N- or P-type crystal.
To achieve doping uniformity, crystal perfection, and diameter con-
trol, the seed and crucible (along with the pull rate) are rotated in op-
posite directions during the entire crystal-growing process. Process
control requires a complicated feedback system integrating the pa-
rameters of rotational speed, pull speeds, and melt temperature.
The crystal is pulled in three sections. First a thin neck is formed,
followed by the body of the crystal ending with a blunt tail. The CZ
method is capable of producing crystals several feet in length and with
diameters up to 12 or more inches. A crystal for 200-mm wafers will
weigh some 450 lb (168 kg) and take three days to grow.
Liquid encapsulated Czochralski (LEC)
LEC crystal growing3 is used for the growing of gallium arsenide crys-
tals. It is essentially the same as the standard CZ process but with a
major modification for gallium arsenide. The modification is required
because of the evaporative property of the arsenic in the melt. At the
crystal growing temperature, the gallium and arsenic react, and the
arsenic can evaporate, resulting in a nonuniform crystal.
Two solutions to the problem are available. One is to pressurize the
crystal growing chamber to suppress the evaporation of the arsenic.
The other is the LEC process (Fig. 3.10). LEC uses a layer of boron tri-
oxide (B2O3) floating on top of the melt to suppress the arsenic evapo-
ration. In this method, a pressure of about one atmosphere is required
in the chamber.
Float zone
Float zone crystal growth is one of several processes explained in this
text that were developed early in the history of the technology and are
still used for special needs. A drawback to the CZ method is the inclu-
sion of oxygen from the crucible into the crystal. For some devices,
higher levels of oxygen are intolerable. For these special cases, the
 Crystal Growth and Silicon Wafer Preparation 59 60 Chapter 3

Figure 3.10 LEC system of crys-

tal growth.

crystal might be grown by the float zone technique, which produces a

lower oxygen content crystal.
Float zone crystal growth (Fig. 3.11) requires a bar of the polysilicon
and dopants that have been cast in a mold. The seed is fused to one
end of the bar and the assemblage placed in the crystal grower. Con-
version of the bar to a single-crystal orientation starts when an RF coil Figure 3.11 Float zone crystal-
growing system.
heats the interface region of the bar and seed. The coil is then moved
along the axis of the bar, heating it to the liquid point a small section
at a time. Within each molten region, the atoms align to the orienta-
tion started at the seed end. Thus, the entire bar is converted to a sin-
gle crystal with the orientation of the starting seed.
Float zone crystal growing cannot produce the large diameters that
are obtainable with the CZ process, and the crystals have a higher dis-
location density. But the absence of a silica (silicon) crucible yields
higher-purity crystals with lower oxygen content. Lower oxygen al-
lows crystals with higher that find use in semiconductor devices such Figure 3.12 Comparison of CZ
and float crystal-growing meth-
as power thyristors and rectifiers. The two methods are compared in ods.
Fig. 3.12.

Crystal and Wafer Quality

leakage and may prevent the devices from operating at required volt-
Semiconductor devices require a high degree of crystal perfection. But ages. There are three major categories of crystal defects:
even with the most sophisticated techniques, a perfect crystal is unob-
tainable. The imperfections, called crystal defects, result in process 1. Point defects
problems by causing uneven silicon dioxide film growth, poor epitaxial 2. Dislocations
film deposition, uneven doping layers in the wafer, and other prob-
lems. In finished devices, the crystal defects cause unwanted current 3. Growth defects
 Crystal Growth and Silicon Wafer Preparation
Point defects
Point defects come in two varieties. One comes when contaminants in
the crystal become jammed in the crystal structure, causing strain.
The second is known as a vacancy. In this situation, there is an atom
missing from a location in the structure (Fig. 3.13).
Vacancies are natural phenomena that occur in every crystal. Unfor-
tunately, vacancies occur whenever a crystal or wafer is heated and
cooled, such as in the fabrication process. The minimization of vacan-
cies is one of the driving forces behind the desire for low-temperature
processing.
Dislocations
Dislocations are misplacements of the unit cells in a single crystal.
They can be imagined as a orderly pile of sugar cubes with one of the
cubes slightly out of alignment with the others.
Dislocations occur from growth conditions and lattice strain in the
crystal. They also occur in wafers from physical abuse during the fab
process. A chip or abrasion of the wafer edge serves as a lattice strain
site that can generate a line of dislocations that progresses into the
wafer interior with each subsequent high-temperature processing of
the wafer. Wafer dislocations are revealed by a special etch of the sur-
face. A typical wafer has a density of 200 to 1000 dislocations per
square centimeter.
Etched dislocations appear on the surface of the wafer in shapes in-
dicative of their crystal orientation. 〈111〉 wafers etch into triangular
dislocations, and 〈100〉 wafers show “squarish” etch pits (Fig. 3.7).
Growth defects
During crystal growth, certain conditions can result in structural de-
fects. One is slip, which refers to the slippage of the crystal along
crystal planes (Fig. 3.14). Another problem is twinning. This is a sit-
uation in which the crystal grows in two different directions from the
same interface. Both of these defects are cause for rejection of the
crystal.
Figure 3.13 Vacancy crystal de-
fect.
61 62 Chapter 3
Figure 3.14 Crystal slip.
Wafer Preparation
End cropping
After removal from the crystal grower, the crystal goes through a se-
ries of steps that result in the finished wafer. First is the cropping off
of the crystal ends with a saw.
Diameter grinding
During crystal growth, there is a diameter variation over the length of
the crystal (Fig. 3.15). Wafer fabrication processing, with its variety of
wafer holders and automatic equipment, requires tight diameter con-
trol to minimize warped and broken wafers.
Diameter grinding is a mechanical operation performed in a center-
less grinder. This machine grinds the crystal to the correct diameter
without the necessity of clamping it into a lathe-type grinder with a
fixed center point—although lathe-type grinders are used.
Crystal orientation, conductivity, and resistivity check
Before the crystal is submitted to the wafer preparation steps, it is
necessary to determine whether it meets orientation and resistivity
specifications.
The crystal orientation (Fig. 3.16) is determined by either X-ray dif-
fraction or collimated light refraction. In both methods, an end of the
crystal is etched or polished to remove saw damage. Next, the crystal
is mounted in the refraction apparatus and the X-rays or collimated
light reflected off the crystal surface onto a photographic plate (X-
rays) or screen (collimated light). The pattern formed on the plate or
Figure 3.15 Crystal diameter
grinding.
 Crystal Growth and Silicon Wafer Preparation
Figure 3.16 Crystal orientation
determination.
screen is indicative of the crystal plane (orientation) of the grown crys-
tal. The pattern shown in Fig. 3.16 is representative of a 〈100〉 orienta-
tion.
Most crystals are purposely grown several degrees off the major
〈111〉 or 〈100〉 plane. This off-orientation provides several benefits in
wafer fabrication processing, particularly ion implantation. The rea-
sons are covered in the applicable process chapters.
The crystal is positioned on a slicing block to ensure that the wafers
will be cut from the crystal in the correct orientation.
Because each crystal is doped, an important electrical check is the
conductivity type (N or P) to ensure that the right dopant type was
used. A hot-point probe connected to a polarity meter is used to gener-
ate holes or electrons (depending on the type) in the crystal. The con-
ductivity type is displayed on the meter.
The amount of dopant put into the crystal is determined by a resis-
tivity measurement using a four-point probe. See Chapter 13 for a de-
scription of this measurement technique. The curves presented in
Chapter 2 (Fig. 2.7) show the relationship between resistivity and dop-
ing concentration for N- and P-type silicon.
The resistivity is checked along the axis of the crystal due to dopant
variation during the growing process. This variation results in wafers
that fall into several resistivity specification ranges. Later in the pro-
cess, the wafers will be grouped by resistivity range to meet customer
specifications.
Grinding orientation indicators
Once the crystal is oriented on the cutting block, a flat is ground along
the axis (Fig. 3.17). This flat will show up on each of the wafers and is
called the major flat. The position of the flat is along one of the major
crystal planes, as determined by the orientation check.
In the fabrication process, the flat functions as a visual reference to
the orientation of the wafer. It is used to place the first pattern mask
on the wafer so that the orientation of the chips is always to a major
crystal plane.
63 64 Chapter 3
Figure 3.17 Crystal flat grind-
ing.
On most crystals, there is a second, smaller, secondary flat
ground on the edge. The position of the secondary flat to the major
flat is a code that tells the wafer fabrication department both the
orientation and conductivity type of the wafer. The code is shown in
Fig. 3.18.
For larger wafer diameters, a notch is ground on the crystal to in-
dicate the wafer crystal orientation (Fig. 3.17). In some cases, a sim-
ple notch is ground into the crystal to act as a production orientation
locator.
Wafer Slicing
The wafers are sliced from the crystal with the use of diamond-coated
inside diameter saws (Fig. 3.19). These saws are thin circular sheets
of steel with a hole cut out of the center. The inside of the hole is the
cutting edge and is coated with diamonds. An inside diameter saw has
rigidity, but without being very thick. These factors reduce the kerf
(cutting width) size which in turn prevents sizable amounts of the
crystal being wasted by the slicing process.
For 300-mm diameter wafers, wire saws are used to ensure flat
surfaces with little tapering and with a minimal amount of “kerf”
loss.
Figure 3.18 Wafer flat locations.
 Crystal Growth and Silicon Wafer Preparation 65 66 Chapter 3

Wafer center

Solid alignment bar

0.88 ± 0.05
Reference Point 2.00 ± 0.05
3.88 ± 0.05
a. Inside Diameter Diamond Saw
Figure 3.20 Laser dot coding. (Reprinted from the Jan. 1998
edition of Solid State Technology, copyright 1998 by Penn-
Well Publishing Company.)
Crystal
Wire

Figure 3.21 Cross section of a MOS tran-

sistor.
Spools

Rollers
b. Wire Saw
Figure 3.19 Inside-diameter saw wafer slicing.
Wafer Marking
Large-area wafers represent a high value in the wafer fabrication pro-
cess. Identifying them is necessary to prevent misprocessing and to
maintain accurate tracking. Laser marking, using bar codes and a
data matrix code4 (Fig. 3.20), is used. Laser dots are the agreed upon
method for 300-mm wafers.
Rough Polish
The surface of a semiconductor wafer has to be free of irregularities
and saw damage and must be absolutely flat. The first requirement
comes from the very small dimensions of the surface and subsurface
layers making up the device. They have dimensions in the 0.5 to 2 mi-
cron range. To get an idea of the relative dimensions of a semiconduc-
tor device, imagine the cross section in Fig. 3.21 as tall as a house
wall, about 8 ft (2.4 m). On that scale, the working layers on the top
of the wafer would all exist within the top 1 or 2 in (25 or 50 mm) or
less.
Flatness is an absolute requirement for small dimension patterning
(see Chapter 11). The advanced patterning processes project the re-
quired pattern image onto the wafer surface. If the surface is not flat,
the projected image will be distorted just as a film image will be out of
focus on a non-flat screen.
The flatting and polishing process proceeds in two steps: rough
polish and chemical/mechanical polishing (Fig. 3.22). Rough polish-
ing is a conventional abrasive slurry lapping process, but it is fine
tuned to semiconductor requirements. A primary purpose of the
rough polish is to remove the surface damage left over from the wa-
fer slicing process.
Figure 3.22 Abrasive and chemi-
cal-mechanical surface polish-
ing.
 Crystal Growth and Silicon Wafer Preparation 67 68 Chapter 3

Chemical Mechanical Polishing (CMP) side is another standard technique. Other methods include the deposi-
tion of a polysilicon layer or silicon nitride layer on the back.
The final polishing step is a combination of chemical etching and me-
chanical buffing. The wafers are mounted on rotating holders and low-
ered onto a pad surface rotating in the opposite direction. The pad Double-Sided Polishing
material is generally a cast and sliced polyurethane with a filler or a
One of the many demands on larger diameter wafers is flat and paral-
urethane coated felt. A slurry of silica (glass) suspended in a mild
lel surfaces. Most manufacturers of 300-mm diameter wafers employ
etchant, such as potassium or ammonium hydroxide, is dropped onto
double-sided polishing to achieve flatness specifications of 0.25 to
the polishing pad.
0.18 μm over 25 × 25 mm sites.5 A downside is that all further process-
The alkaline slurry chemically grows a thin layer of silicon dioxide
ing must employ handling techniques that do not scratch or contami-
on the wafer surface. The buffing action of the pad mechanically re-
nate the backside.
moves the oxide in a continuous action. High points on the wafer sur-
face are removed until an extremely flat surface is achieved. If a
semiconductor wafer surface was extended to 10,000 ft (3,048 m—the Edge Grinding and Polishing
length of a typical airport runway), it would vary about plus or minus
Edge grinding is a mechanical process that leaves the wafer with a
2 in (50 mm) over its entire length.
rounded edge (Fig. 3.24). Chemical polishing is employed to further
Achieving the extreme flatness requires the specification and con-
create an edge that minimizes edge chipping and damage during fab-
trol of the polishing time, the pressure on the wafer and pad, the
rication that can result in wafer breakage or serve as the nucleus for
speed of rotation, the slurry particle size, the slurry feed rate, the
dislocation lines.
chemistry (pH) of the slurry, and the pad material and conditions.
Chemical/mechanical polishing is one of the techniques developed
by the industry that has allowed production of larger wafers. CMP is Wafer Evaluation
used in the wafer fabrication process to flatten wafer surfaces after Before packing, the wafers (or samples) are checked for a number of
the buildup of new layers creates uneven surfaces. In this application, parameters as specified by the customer. Figure 3.25 illustrates a typ-
CMP is the abbreviation for chemical mechanical planarization. A de- ical wafer specification.
tailed explanation of this use of CMP appears in Chapter 10. Primary concerns are surface problems such as particulates, stain,
and haze. These problems are detected with the use of high-intensity
Backside Processing lights or automated inspection machines.
In most cases, only the front side of the wafer goes through the exten-
sive chem/mech polishing. The backs may be left rough or etched to a
Figure 3.24 Wafer edge grinding.
bright appearance. For some device use, the backs may receive a spe-
cial process to induce crystal damage, called backside damage. Back-
side damage causes the growth of dislocations that radiate up into the
wafer. These dislocations can act as a trap of mobile ionic contamina-
tion introduced into the wafer during the fab process. The trapping
phenomenon is called gettering (Fig. 3.23). Sandblasting of the back-

Wafer

Figure 3.23 Trapping. Figure 3.25 Typical 200-mm wa-

fer specification.
= Contamination
= Dislocation line
 Crystal Growth and Silicon Wafer Preparation 69 70 Chapter 3

Oxidation 9. Draw a flow diagram of the wafer preparation process.

Silicon wafers may be oxidized before shipment to the customer. The 10. Give two reasons why semiconductor wafers require a flat surface.
silicon dioxide layer serves to protect the wafer surface from scratches
and contamination during shipping. Most companies start the wafer References
fabrication process with an oxidation step, and buying the wafers with
an oxide layer saves a manufacturing step. Oxidation processes are 1. Russ Arensman, “One-Stop Automation,” Electronic Business, July 2002, p. 54.
2. Sumitomo Sitix product brochure.
explained in Chapter 7. 3. R. E. Williams, Gallium Arsenide Processing Techniques, Artech House Inc.,
Dedham MA, 1984, p. 37.
4. S. J. Brunkhorst and D. W. Sloat, “The impact of the 300-mm transition on silicon
Packaging wafer suppliers,” Solid State Technology, January 1998, p. 87.
5. Ibid.
While much effort goes into producing a high-quality and clean wafer,
the quality can be lost during shipment to the customer or, worse,
from the packaging method itself. Therefore, there is a very stringent
requirement for clean and protective packaging. The packaging mate-
rials are of nonstatic, nonparticle-generating materials, and the
equipment and operators are grounded to drain off static charges that
attract small particles to the wafers. Wafer packaging takes place in
cleanrooms.

Engineered Wafers (Substrates)

Increasingly, wafer fabrication companies are asking for wafer manu-
facturers to supply wafers with deposited top-side layers, such as epi-
taxial silicon. Other wafer products include silicon deposited on
insulators (SOI and SOS) such as sapphire or diamond (Chapter 12).

Review Questions

1. In a polycrystalline structure, the atoms are not arranged (true or

false).
2. In a single-crystal structure, the unit cells are not arranged (true
or false).
3. Draw a cubic unit cell and identify the 〈100〉 plane.
4. 〈111〉 oriented wafers are used for (bipolar, MOS) devices.
5. What is the orientation of a semiconductor crystal if the seed has a
〈100〉 orientation.
6. Draw a diagram of a CZ crystal grower and identify all the major
parts.
7. During crystal growth, the molten material is changed from single
crystal structure to a polycrystal structure (true or false).
8. Why are wafers edge rounded?