EE-321 Spring 2021

Computer Architecture and Organization

Lecture # 2
Designing a Basic Microprocessor

Muhammad Imran
muhammad.imran1@seecs.edu.pk
Contents
▪ Background
▪ Designing a Simple Microprocessor
▪ Learning about
▪ Basic hardware/software interface!
▪ A simple instruction set architecture and
microarchitecture!
▪ Caches
▪ Program Counter
▪ Pipelining
▪ Instruction execution cycle
▪ Basic performance metrics

2
Review of Some Basic Concepts
Basic Logic Gates
▪ NOT, AND, OR, XOR, XNOR, NAND, NOR
▪ Universal gates: NAND, NOR
▪ Can implement any logic

4
Multiplexer
▪ Select one of many inputs!
▪ A combinational circuit!

S1 S0 Output
Input 0 0

Input 1 1
00 Input 0
Output
Input 3 2
01 Input 1
Input 4 3
10 Input 2
11 Input 3

S1 S0

5
Flip Flops / Registers
▪ Sequential Circuits
▪ Output depends on state!
▪ Have memory!
▪ Use a clock signal
▪ A simple D-type flip flop
▪ Basic 1-bit storage element!

Clock D Qnext
Rising edge 0 0
Rising edge 1 1
Non-rising X Q

6
Timing in Sequential Circuits

▪ Setup time tS – minimum time the input has to be stable before the rising edge of
the clock
▪ Hold time tH – minimum time the input has to be stable after the rising edge of
the clock
▪ Propagation delay tCLK2Q – time to propagate input to output after the rising
edge of the clock 7
Critical Path and Clock Rate

input output

TCLK2Q=0.5ns 2ns 2ns 2ns 2ns Ts=0.3ns

Minimum Clock Period = the critical path delay betwen two registers!
1
Maximum Clock Frequency =
critical path delay
1 1
Maximum Clock Frequency = = = 113.6𝑀𝐻𝑧
0.5𝑛𝑠 + 2𝑛𝑠 + 2𝑛𝑠 + 2𝑛𝑠 + 2𝑛𝑠 + 0.3𝑛𝑠 8.8𝑛𝑠

8
Critical Path and Clock Rate
▪ Reducing the critical path

2ns
Tclk2q=0.5ns Ts=0.3ns

1 1
Maximum Clock Frequency = = = 357.14𝑀𝐻𝑧
0.5𝑛𝑠 + 2𝑛𝑠 + 0.3𝑛𝑠 2.8𝑛𝑠

9
 Pipelining: A Laundry Analogy

▪ “place one dirty load of clothes in the washer” !

▪ “when the washer is finished, place the wet load in the dryer” !
▪ “when the dryer is finished, take out the dry load and fold” !
▪ “when folding is finished, ask your roommate to put the clothes away”

10
Onur Mutlu: Digital Design & Computer Architecture
 Pipelining: A Laundry Analogy

- 4 Loads in Parallel
- Throughput increase 4 times
- Latency per load is same

11
Onur Mutlu: Digital Design & Computer Architecture
 Pipelining in Microprocessor
▪ Multi-cycle: 4 cycles per instruction

▪ Pipelined: 4 cycles per 4 instructions (steady state)

12
Onur Mutlu: Digital Design & Computer Architecture
Let’s build a simple
microprocessor!
What a microprocessor does?
Executes simple instructions for
arithmetic and logical
operations …
Designing a Simple Microprocessor
▪ Let’s design an ‘oversimplified’ microprocessor
▪ Let’s call it
▪ CAx2021
▪ What it does?
▪ Performs
▪ Addition
▪ Subtraction
▪ AND operation
▪ OR operation
▪ Arithmetic and logical operation!

16
Designing a Simple Microprocessor
▪ Let’s design an ‘oversimplified’ microprocessor
▪ Let’s call it
▪ CAx2021
▪ What it does?
▪ Operates on two operands
▪ Say Op1 and Op2
▪ The two operands are chosen from available four operands
▪ Handles an interrupt signal
▪ This signal overrides the normal operation of process!

17
Designing a Simple Microprocessor
▪ Top View
Instruction A B C D

Interrupt
CAx2021 Microprocessor

Result
18
Designing a Simple Microprocessor
▪ Defining the Instruction for Microprocessor!
▪ Microprocessor performs 4 operations
ADD, SUB, AND, OR
▪ To select one operation, we need 2 bits
00: ADD
01: SUB
10: AND
11: OR
▪ Operation selection bits are usually referred as
‘OpCode’

19
Designing a Simple Microprocessor
▪ Defining the Instruction for Microprocessor!
▪ There are 4 available operands:
A, B, C, D
▪ To select one of the 4 operands, we need 2 bits
00: A
01: B
10:C
11:D
▪ To select two operands (Op1 and Op2), we need 4 bits

20
Designing a Simple Microprocessor
▪ Defining the Instruction for Microprocessor!
▪ Instruction size:
2 bits (To select operation)
+ 2bits (To select Op1)
+ 2bits (To select Op2)
= 6 bits
▪ So CAx2021 Processor operates on 6-bit
instructions!

21
Designing a Simple Microprocessor
▪ Instruction Breakdown (Bit-wise)
Instruction(5:0) Instruction(5:4)
OpCode Six instruction bits
Instruction(3:2) are represented as
Sel_Op1 bit 0 to bit 5!
Instruction(1:0) Instruction(5:0)
Sel_Op2 5: MSB
0: LSB
OpCode Interrupt Result
00 0 ADD (Op1+Op2)
01 0 SUB (Op1-Op2)
10 0 AND (Op1 & Op2)
11 0 OR (Op1 | Op2)
x 1 111… (All bits = 1)
x: don’t care (any value) 22
Designing a Simple Microprocessor
▪ Instruction Breakdown (Bit-wise)
We have just
Instruction(5:0) Instruction(5:4)
OpCode decoded the
instruction to see
Instruction(3:2)
Sel_Op1 what it really
Instruction(1:0) means!
Sel_Op2

Sel_Op1 Op1 Sel_Op2 Op2

00 A 00 A
01 B 01 B
10 C 10 C
11 D 11 D

23
 Instruction A B C D

Instruction(1:0)
ABCD ABCD

0
1
2
3
0
1
2
3
Instruction(3:2)
Instruction(5:4)

Op1 Op2

ADD SUB AND OR

Interrupt
Select Result

Result
Implementation 24
 Instruction(5:4)
ADD SUB AND OR

3
Interrupt

OR
Select Result Logic

Result

Implementation 25
Example Instruction
▪ Instruction: 000110
▪ 00 : ADD Operation
▪ 01 : Operand B
▪ 10 : Operand C
▪ Instruction 000110 means ADD B and C …
▪ 000110 is ‘Machine Language’
▪ ADD B, C is ‘Assembly Language’
▪ It’s that simple ☺
▪ That’s how and why software came into being!
▪ It simplifies the way we can communicate with the hardware!
▪ High-level languages are more human friendly than machine
code!

26
Key Points!
▪ We designed a microprocessor that has six-bit
instructions!
▪ Instruction set has following type of instructions:
▪ ADD A, B
▪ SUB C, D
▪ and so on …
▪ That’s the assembly language for our processor!
▪ Can easily convert into equivalent 6-bit machine code
instructions! (That’s the job of assembler)
▪ The operand size can be variable
▪ A, B, C, D can have any size!
▪ We can say, its an n-bit processor!
▪ Operands are simple constant values or inputs from an
external memory or another system!
27
Key Points!
▪ The implementation is simple!
▪ Pure combinational circuit!
▪ Output changes when input instruction changes!
▪ Performance
▪ If we add a register at input and one at output, each
instruction takes one cycle to execute!
▪ CPI (cycles per instruction) = 1
▪ IPC (instructions per cycle) = 1

28
Key Points!
ABCD
▪ What’s the clock rate of this processor?
▪ Depends on the critical path!

0
1
2
3
▪ Critical path consists of Op1
▪ Two multiplexers
▪ Subtractor (longest path in the ALU blocks!)
▪ OR gate!
▪ 𝑀𝑎𝑥 𝐶𝑙𝑜𝑐𝑘 = SUB
1
2 × 𝑀𝑢𝑙𝑖𝑝𝑙𝑒𝑥𝑒𝑟 𝐷𝑒𝑙𝑎𝑦 + 𝑆𝑢𝑏𝑡𝑟𝑎𝑐𝑡𝑜𝑟 𝐷𝑒𝑙𝑎𝑦 + 𝑂𝑅 𝐺𝑎𝑡𝑒 𝐷𝑒𝑙𝑎𝑦 + 𝑡𝑠 + 𝑡𝑐𝑙𝑘2𝑞

3
Result
29
Rest is all about just adding
more to our processor!
☺
Want to execute multiple
instructions?
Let’s add memory for multiple
instructions …
Adding Instruction Cache
▪ Instruction Cache can hold multiple instruction!

A B C D

Instruction

CAx2021 Interrupt
Instruction Cache
Microprocessor

Result

33
Adding Instruction Cache
▪ 6-bit Instructions require a simple memory where
each location may be 6-bit
▪ Practical memories are addressed in bytes (8 bits)
▪ Let’s add an instruction cache of size 8x6 bits
▪ 8 locations
▪ Each location is 6 bits in size!
▪ How many bits do we need for address?
▪ 3 bits
▪ Instruction Cache is addressed using “Program
Counter”
▪ Also called “Instruction Pointer Register”!
▪ Usually a register in actual microprocessors!

34
 Program Counter / Instruction Pointer

▪ Program Counter (PC)

▪ To address instruction cache!
▪ For 8x6 bit instruction cache, PC is 3-bit!
▪ PC can go from 000 to 111 to select 8 instructions!
A B C D

PC CAx2021 Interrupt
Instruction Cache
Microprocessor

Result
35
Executing Multiple Instructions
▪ PC is incremented to select successive instructions!

A B C D
PC = 0 First Instruction
Second Instruction
Third Instruction
. CAx2021 Interrupt
. Microprocessor
.
.
.
Result
Instruction
Cache
36
 Executing Multiple Instructions
▪ PC is incremented to select successive instructions!

A B C D
First Instruction
PC = 1 Second Instruction
Third Instruction
. CAx2021 Interrupt
. Microprocessor
.
.
.
Result
Instruction
Cache
37
 Executing Multiple Instructions
▪ PC is incremented to select successive instructions!

A B C D
First Instruction
Second Instruction
PC = 2 Third Instruction
. CAx2021 Interrupt
. Microprocessor
.
.
.
Result
Instruction
Cache
38
Just like Instruction Cache, we
have Data Cache …
 Adding Data Cache
▪ Can add two simple data cache memories to load
operands! (multiplexers will be removed)
▪ Each data cache memory can be (4 x n) bits
▪ 4 locations
▪ Each having an n-bit operand!
▪ 2-bit address to select one of the four operands!
Usually,
microprocessors
A load one operand at
B a time from memory
Sel_Op1 instead of two!
C
Sel_Op1 acts as
address of a variable D Operands are loaded
in memory! Data Cache into registers inside
CPU!
40
Can we improve our processor’s
performance?
 Why not!
Let’s pipeline our processor
design …
Pipelining a Simple Design

input output

Pipelining

43
Pipelining Processor
▪ Without Pipelining

ADD
Sel_Op1

A
Instruction Cache

0
B Op1
1 OpCode

SUB
C 2
D 3
A 0
Sel_Op2 B 1
C 2
AND

D 3
A 0
B Op2
1
C 2
D 3
OR

44
Pipelining Processor
▪ Adding pipeline registers

ADD
Sel_Op1

A
Instruction Cache

0
B Op1
1 OpCode

SUB
C 2
D 3
A 0
Sel_Op2 B 1
C 2
AND

D 3
A 0
B Op2
1
C 2
D 3
OR

45
 Instruction Cache
6-bit Instruction

B
B

C
C

A
A

D
D

3
2
1
0
3
2
1
0

Sel_Op2
Sel_Op1

Op2
Op1
▪ Register Sizes

n bits for Op2 n bits for Op1 2 bits for OpCode

OR AND SUB ADD

Pipelining Processor

(n × 4) bits for each result 2 bits for OpCode

B
C
A

D
2
1
0

3
OpCode

n bits for selected result!

46

n bits for final result

 What’s the critical path in
pipelined implementation?
Critical Path in Pipelined Design
▪ It’s reduced to that of subtractor
▪ Assuming subtractor path is longer than that of
multiplexer!
1
▪ 𝑀𝑎𝑥 𝐶𝑙𝑜𝑐𝑘 =
𝑆𝑢𝑏𝑡𝑟𝑎𝑐𝑡𝑜𝑟 𝐷𝑒𝑙𝑎𝑦+𝑡𝑠+𝑡𝑐𝑙𝑘2𝑞
▪ Much faster than the previous design!
▪ As first instruction result (OpCode+Operands) goes to
second pipelined register
▪ Can load new instruction from instruction cache in first
pipelined register!

48
 We will build simply a more
capable microprocessor in the
coming lectures …
In a similar manner …
Main Components in a Processor

Update Register File

Program
Control Unit
Counter

Decode
Instruction

ALU
Program Counter Instruction Register
Data Register
Address Instruction Address Register
Memory

Instructions Data

51
Key Concepts Learned!
▪ A simple processor Datapath and Control
▪ Hardware/Software Interface
▪ High-level language → Assembly → Machine Code →
Hardware Control Signals!
▪ Instruction Encoding & Decoding
▪ Instruction and Data Cache
▪ Program Counter / Instruction Pointer Register
▪ Register File
▪ Pipelining and Pipelining Registers
▪ Critical Path and Clock Rate
52
Questions … ?