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Figure 3: FPGAs Bridge the SDR Application Task Space.
Figure 5: Unused system gates and RAM available allows users to include
Figure 4: Evolving FPGA Generations. custom algorithms.
provide plenty of I/O pins to delays and suggest alternate FPGA memory can now be advantages of parallel hard-
support on-board gigabit se- routing strategies to minimize configured with the design ware to handle some of
rial transceivers and other them within the part. This can tool to implement just the the high process intensity
user-configurable system in- really save one hours of tedious right structure for tasks that functions like DDCs and the
terfaces. New announcements troubleshooting, not only dur- include dual port RAM, FIFOs, benefit of programmability
seem to be coming out every ing design verification but also shift registers and other to accommodate some of
day from chip vendors like for production testing. popular memory types. These the decoding and analysis
Xilinx and Altera in a never- In the last few years, a memories can be distributed functions of DSPs. These
ending game of outperform- new industry of third party along the signal path or inter- advantages may come at the
ing the competition. intellectual property (IP) core spersed with the multipliers expense of increased power
To support such powerful vendors now offers thou- and math blocks, so that the dissipation and increased
devices, new design tools are sands of application-specific whole signal processing task product costs. However,
appearing that now open up algorithms. These are ready operates in parallel in a sys- these considerations are
FPGAs to both hardware and to drop into the FPGA de- tolic pipelined fashion. often secondary to the per-
software engineers. Instead sign process to help beat the Again, this is dramatically formance and capabilities of
of just accepting logic equa- time-to-market crunch and different from sequential these remarkable devices.
tions and schematics, these to minimize risk. execution and data fetches Figure 4 shows represen-
new tools accept entire block from external memory as tative members from four
diagrams as well as VHDL and FPGAs for Software Radio in a programmable DSP. As generations of Xilinx de-
Verilog definitions. Like ASICs, all the logic ele- we said, FPGAs now have vices currently used in Pentek
Choosing the best FPGA ments in FPGAs can execute in specialized serial and paral- Products: the Virtex-E, Virtex-II,
vendor often hinges heavily on parallel. This includes the hard- lel interfaces to match re- Virtex-II Pro, and Virtex-4. The
the quality of the design tools ware multipliers, and you can quirements for high- speed Virtex-E family includes a mix
available to support the parts. now get over 500 of them on peripherals and buses. of configurable logic blocks,
To minimize some of the tricky a single FPGA. This is in sharp As a result, FPGAs have logic cells, system gates and
timing work for hardware engi- contrast to programmable significantly invaded the block memory.
neers, excellent simulation and DSPs, which normally have just application task space as The Virtex-II family added
modelling tools help to quickly a handful of multipliers that shown by the centre bubble built in hardware multipliers
analyze worst case propagation must be operated sequentially. in Figure 3. They offer the that support digital filters,
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averagers, demodulators and cally boost clock speeds and of FPGAs and various Pentek remain unused and available
FFTs, a major benefit for soft- reduce power dissipation over hardware products that use for customer use.
ware radio signal processing. previous generations. them. Each hardware prod- This chart shows the per-
The Virtex-II Pro family dramat- The Virtex-4 LX family uct uses some of the FPGA centage of unused system
ically increased the number of delivers maximum logic and resources to implement stan- gates and RAM available to
hardware multipliers and also I/O pins while the SX family dard factory functions of the the user for extending the
added embedded PowerPC boasts of 512 hardware mul- products such as interfaces, FPGA to include custom
microcontrollers. tipliers for maximum DSP per- data formatting, state ma- algorithms. To address this
The Virtex-II Pro is also the formance. The FX family is a chines, and operating modes. requirement, Pentek has de-
first family to incorporate generous mix of all resources However, since many of the veloped the GateFlow FPGA
RocketIO multigigabit serial and is the only family to of- newer FPGAs are so large, Design Resources.
transceivers to support the new fer RocketIO, PowerPC cores, even after all the standard
switched gigabit serial fabrics. and the newly added gigabit factory functions have been
The Virtex-4 family is offered as Ethernet ports. implemented, a significant
three subfamilies that dramati- Figure 5 shows a sampling percentage of FPGA resources
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