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Abstract— Due to the huge difference in performance between the computer memory and processor , the virtual
memory management plays a vital role in system performance .A Cache memory is the fast memory which is used to
compensate the speed difference between the memory and processor. This paper gives an adaptive replacement
policy over the traditional policy which has low overhead, better performance and is easy to implement. Simulations
show that our algorithm performs better than Least-Recently-Used (LRU), First-In-First-Out (FIFO) and Clock with
Adaptive Replacement (CAR).
Index Terms— Adaptive page replacement, CAR, FIFO, LRU, Memory management, Weight ranking.
—————————— ——————————
1 INTRODUCTION
The terminology used for cache efficiency is “Hit Rate” (Hit
n modern computer systems the efficiency of the Rate ‐ represents the rapport between the number of
I memory hierarchy is one of the most crucial issues. To addresses accessed from cache and the total number of
obtain a high‐performance memory system, caching is addresses accessed during that time). The antonym for “Hit
the best direction in terms of cost and effectiveness. The Rate” is named “Miss Rate” which can be determined by
performance of the cache memories to compensate the Miss Rate = 1 – Hit Rate formulas. [1,24]
speed gap between processors and main memory is
determined by the access time and hit rates. Caching is an Cache efficiency can be changed by implementing
old and well‐known performance enhancement technique different replacement policies. Cache and auxiliary
that is widely used in computer systems. Processor’s cache, memories use uniformly sized items which are called pages.
paged virtual memory and web caching are some instances When the cache is empty the first access will be always a
of using this technique. In all levels of storage hierarchy, miss. The misses may occur until the cache is filled with
performance of the system is related to cache mechanism. pages. After some cycles, when the cache is filled, this kind
The time access for cache is at least 10 times smaller than the of misses will not occur anymore. Another kind of miss
main memory. occurs when the cache is full of pages and there is an access
to a page that is not in the cache, in this case replacement
Increasing the cache size results in better performance, policy should specify conditions under which a new page
but resulting a very expensive technology. That’s why the will be replaced with an existing one. The main role of
size of cache memory is always smaller than the main replacement policy is to choose a page which has the lowest
memory in every system. According to cache memory probability of further usage in the cache to be replaced with
access time, fetching data from cache is a big advantage and the new one. Generally there are three ways of mapping
has a significant role in system performance. We must use memory into cache: 1) Direct Mapped in which each block
other techniques to make cache more efficient for systems from the main memory is mapped only to a unique cache
which make use of it in their memory hierarchy block, no matter whether that block is empty or not. This
model of cache organization doesn’t require a replacement
———————————————— policy. 2) Fully Associative in which each block from the
Debabala Swain is with CSE Dept, Centurion University of Technology main memory can be mapped to any of cache blocks. If the
and Management, Bhubaneswar Campus, Orissa, India. cache is full then a replacement policy needs to decide
which data will be invalidated from cache for making room
Debabrata Swain is with Dept of Computer Science, Berhampur University, of this new data block. 3) Set Associative in which the cache
Orissa, India. is split into many sets. The new data can be mapped only to
Bijay k Paikaray is with CSE Dept, Centurion University of Technology the blocks of a certain set, determined by some bits from
and Management, Bhubaneswar Campus, Orissa, India. address field. In practice it is used mostly because of a very
efficient ratio between implementation and efficiency. There
may be another kind of miss in the direct map caches which
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ARC (Adaptive Replacement Cache) combines the LRU 3 WEIGHT RANKING ALGORITHM
and LFU solutions and dynamically adjusts between them.
ARC like LRU is easy to implement and has low over‐head In this section we will use the standard replacement
on systems[9].LRU captures only recency and not frequency, policy terminologies. We assume that the size of the blocks
and can be easily “polluted” by a scan. A scan is a sequence is equal and the replacement algorithm is used to manage a
of one‐time use only page requests, and leads to lower memory that holds a finite number of these blocks. A hit will
performance. occur when there is a reference to a block in the buffer.
ARC overcomes these two downfalls by using four When we have a reference to a block not in the buffer, a miss
doubly linked lists. Lists T1 and T2 are what is actually in will occur and referenced block must be added to buffer.
the cache at any given time, while B1 and B2 act as a second When buffer is full and a miss occurs, an existing block must
level. B1 and B2 contain the pages that have been thrown be replaced to make room for a new one.
out of T1 and T2 respectively. The total number of pages
therefore needed to implement these lists is 2*C, where C is For ranking of the referenced blocks, we consider three
the number of pages in the cache. T2 and B2 contain only factors. Let Fi be the frequency index which holds the
pages that have been used more than once. The lists both frequency of each block i in the buffer and Ri be the recency
use LRU replacement, in which the page removed from T2 index which shows the clock of last access when buffer has
is placed into B2. T1 and B1 work similarly together, except been referenced and N is the total number of access to be
where there is a hit in T1 or B1 the page is moved to T2. The made. Then the weighting value of block i can be computed
part that makes this policy very adaptive is the sizes of the as:
lists change. List T1 size and T2 size always add up to the
total number of pages in the cache. However, if there is a hit
in B1, also known as a Phantom Hit (i.e. not real hit in
cache), it increases the size of T1 by one and decreases the
size of T2 by one. In the other direction, a hit in B2 (Phantom
Hit) will increase the size of T2 by one and decrease the size Initially all the indices of Ri , Fi , Wi are set to 0.
of T1 by one. This allows the cache to adapt to have either
more recency or more frequency depending on the 1) Whenever a page frame k is referenced, the hardware
workload [9]. increments corresponding Fi by 1.When a hit occurs the
respective Ri counter will hold the corresponding clock access
ARC has following two drawbacks: value. At any instant, the block whose weight index is lowest is
the least recently used block, the block with next higher weight
1) The overhead of moving a page to the most recently index is the next least recently used, and so forth.
used position on every page hit. 2) When a miss occurs i.e. a new object k is placed in the
2) Serialized, in the fact that when moving these i block then Fi and Ri for the new block will be updated
pages to the most recently used position the cache is locked .Because, it means that object k has been placed and once
so that it doesn’t change during this transition. referenced.
The CAR (Clock with Adaptive Replacement) combines In every access to buffer, if referenced block i is in the
the LRU and LFU solutions and dynamically adjusts buffer then a hit is occurred and our policy will work in this
between them. ARC like LRU is easy to implement and has way:
low over‐head on system.
CAR only overcomes the first downfall, the second still 1) Fi will be changed to Fi + 1 for every i and Ri will hold
has a presence. CAR uses two clocks instead of lists, a clock the corresponding clock access value.
is a circular buffer. The two circular buffers are similar in
nature to T1 and T2, and it contains a B1 and B2 as well. The But if referenced block i is not in the buffer then a miss
main difference is that each page in T1 and T2 contains a occurs and our policy will choose the block in buffer, by
reference bit. When a hit occurs this reference bit is set on. calculating the weight function i.e. searching for object with
T1 and T2 still vary in size the same way they do in ARC smallest weighting value. It will be evaluated as follows:
(i.e. Phantom Hits cause these changes). When the cache is
full the corresponding clock begins reading around itself 1) The Wi value has to be evaluated for each block i, for
(i.e. the buffer) and replaces the first page whose reference every N ≠ Ri.
bit is zero. It also sets the reference bits back to zero if they 2) Now the page i with lowest weight index Wi will be
are currently set to one. The clock will continue to travel replaced with k.
around until it finds a page with reference bit equal to zero Then the corresponding Rk will be the clock value, Fk =1
to replace [11]. and Wk will be set to 0.
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The weighting value of blocks that are in buffer will only be
updated when a miss occurs in the buffer because one of the 4.2 Simulation Results
important concepts in replacement policies is its overhead in the We executed simulation program for all 8 different cache
systems. When cache size is small our algorithm will all most sizes and compared it with LRU, FIFO, and CAR. As it is
work like LRU. But in larger cache size it works better than indicated in Figure1, our Adaptive weighting ranking policy
LRU, FIFO and CAR. performs clearly better than LRU, FIFO and CAR. The
average enhancement compare with LRU is about 1.22%,
We have only talked about how our replacement average enhancement for FIFO is about 0.95% and average
algorithm works, but we have not discussed how it can be enhancement for CAR is about 0.47%.In Table 1, we can see
implemented in real system. the accurate hit ratio for all page references for all four
schemes.
AWRP needs three elements to work and will add space
overhead to system: first, algorithm needs a space for For the other three cases we executed simulator program
counter Fi second, it needs a space for counter Ri and third it with same 8 cache sizes. The result shows that the maximum
needs a counter for Wi, which holds weighting value for gain of hit ratio of 17.47% from LRU, is attained for the
each object in the buffer. Calculating weighting function cache size of 90 from LRU, and minimum gain is 0.76% for
value for each object after every access to cache will cause a cache size of 30 from LRU case. The result shows that the
time overhead to system. We have to consider the Wi as maximum hit ratio for AWRP is about 75.42% for a cache
floating numbers. size of 210, and minimum hit ratio is 41.9% for cache size of
30.
4 PERFORMANCE ANALYSIS
If we will compare AWRP with individual algorithm
To evaluate our replacement algorithm experimentally, then maximum gain from LRU is 17.47 % at cache size 90
we simulated our policy and compared it with other policies and minimum gain is 0.77% at cache size 30, maximum gain
like LRU, FIFO and CAR. The simulator program was from FIFO is 11.47% at cache size 120 and minimum gain is
designed to run some traces of load instructions executed 1.88% at cache size of 210.Maximum gain from CAR is
for some real programs and implement different 8.75% at cache size 60 and minimum gain is 0.96% at cache
replacement policies with different cache sizes. The obtained size of 150.One exceptional case is at a cache size of 180 CAR
hit ratio depends on the replacement algorithm, cache size works 0.93% better than AWRP. Also at cache size of 210
and the locality of reference for cache requests. Modular CAR and AWRP give same hit ratio of 75.42%.
design of simulator program allows easy simulation and
optimization of the new algorithm. In the used trace the hit ratio of proposed algorithm is
always better than LRU, FIFO and CAR replacement
4.1 Input traces policies, and in the worse cases the result is equal to the
Our address trace is simply a list of one thousand maximum hit ratio of CAR. That is because of the
memory addresses produced by a real program running on considered weighting factors in AWRP which never let the
a processor. Generally address traces would include both result become worse than maximum hit ratio of these
instruction fetch addresses and data (load and store) replacement policies except the 210 cache size from CAR.
addresses, but we are simulating only a data cache, so these
traces only have data addresses. The mapping scheme is
considered and set to set associative mapping. According to
traces that have been used, we considered 8 cache sizes and
ran the simulation program to test the performance of our
proposed algorithm.
Table 1. A Comparison between hit ratio of LRU, FIFO, CAR and AWRP for 8 different frame sizes.
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75
70
65
Hit Ratio(%)
60
55 LRU
U
50 AW
WRP
FIFO
O
45 CAR
R
40
3
30 60 90 120 150 180 210
Cache size
e(# of Blocks)
Figurre1. Performancee Analysis of LRU
U, FIFO, CAR an
nd AWRP with d
different frame sizzes.
5 SUM
MMARY & CONCLUSIO
C ONS
In this paper we ha
ave introducced a new paage be simuulated with other
o policiess with bench
hmark
replacemeent policy and
a the sim
mulation resu ults traces and
a for diffeerent applicattions and theen the
shows thaat it is a modiification and iimprovementt of overall results may b be compared with the resu ults of
famous reeplacement policies
p like LRU,
L FIFO and
a recentlyy proposed reeplacement policies.
CAR. We attended to reference ratte of each objject
in the bufffer and claimmed that the pprobability of re‐ It can be conclluded that if the additional
accessing of the pages with higher w weighting vaalue parameeters and facttors which describe features of
is more th han the otherrs and simulaations confirm med objects in the buffeer be taken into
i account,, then
our claimm. We simulatted AWRP and compared d it AWRP can be suitaably used forr application ns like
with only y three famouss policies. Thiis algorithm ccan databasse servers, web cach hing and other
applicaations.
ENCES
REFERE
Measurin ng and Modeling oof Computer Systeems, May 1997, p pp. 115‐
[1]Kaveh Samiee,
S ”WRP: Weighting Rep
placement Policy
y to
12
Improve Caache Performa
ance”, Internation
nal Journal of Hyybrid hang and X. Zh
[8] S. Jih hang, “LIRS: An
A Efficient Low w Inter
Information T
Technology,Vol.2, No.2, April, 20099. Reference Recency Set Replacement
R Pollicy to Improve Buffer
[2]Q. Yang,, H. H. Zhang g and H. Zhang, “Taylor Seeries Cache Peerformance,” Prooc. ACM Sigmetriccs Conf., ACM Prres, pp.
Prediction: A A Cache Replaceement Policy Based on Second‐Orrder 31‐42, 2002.
Trend Analy ysis,” Proc. 34th HHawaii Conf. Systtem Science, 2001. [9] N. Megiddo
M and D. S.
S Modha, “ARC C: A Self‐Tunning, Low
[3]S. Hossseini‐khayat, “On “ Optimal Replacement of Overhead d Replacement C Cache,”Proc.Usen nix Conf. File and Storage
Nonuniform m Cache Objectss,” IEEE Trans. Computers, vol. 49, Technologgies (FAST 2003),, Usenix, 2003, pp p.115‐130
no.8, Aug. 2000. [10] Y. Zhou
Z and J. F. Ph
hilbin, “The Multi‐Queue Replacement
[4] L. A. Beelady, “A Study y of Replacemen nt Algorithms fo or a Algorithm m for Second fo or Second‐Levell Buffer Caches,,” Proc.
Virtual Storrage Computer,” ” IBM systems J.vol.
J 5, no.2, pp
p.78‐ Usenix Ann. Tech conf. (Ussenix 2001), Usen nix, 2001, pp. 91‐‐104.
101, 1966. [11] Soraav Bansal and Dh harmendra S. Mo odha, ʺCAR: Clocck with
[5]S. Irani, “Page Replaceement with Mu ulti‐Size Pages and Adaptivee Replacement.ʺ USENIX File and d Storage Techn nologies
Applicationss to Web Cachin ng,” Proc.29th Ann n, ACM symp. Theory (FAST), M March 31‐April 22, 2004, San Franccisco, CA.
of Computingg, pp. 701‐710, 19 997. [12] Moh hamed Zahran. “Cache
“ Replacem
ment Policy Revisited,”
[6] E. J. O’N
Neil, P. E. O’Neiil, and G. Weikuum, “an Optimaality In Proceedings of the 6th W Workshop on Duplicating Decon‐strructing,
Proof of thee LRU‐K page Reeplacement Algo orithm.” J.ACM, vol. and Debu ugging, San Diego o, CA, USA, Junee 2007.
46, no.1, pp. 92‐112, 1999. [13] J. L. Bentley, D. D. S Sleator, R. E. Tarrjan, and V. K. WWei, “A
[7] G. Glass and P. Cao, “Ad daptive Page Rep placement Based d on locally addaptive data com mpression schem me,” Comm. ACM M, vol.
Memory Refference Behaviorrʺ, proc ACM SIG GMETRICS Conf. 29, no. 4, pp. 320–330, 19886.
JOURNAL OF COMPUTING, VOLUME 3, ISSUE 2, FEBRUARY 2011, ISSN 2151‐9617
HTTPS://SITES.GOOGLE.COM/SITE/JOURNALOFCOMPUTING/
WWW.JOURNALOFCOMPUTING.ORG 214
[14] A. J. Smith, “Disk cache‐miss ratio analysis and design [20] Yannis Smaragdakis, Scott Kaplan, Paul Wilson, “The
considerations,” ACM Trans. Computer Systems, vol. 3, no. 3, pp. EELRU adaptive replacement algorithm”performance Evaluation,
161– 203, 1985. v.53 n.2, pp. 93‐123, July 2003.
[15] J. Ziv and A. Lempel, “A universal algorithm for sequential [21] D. Lee, J. Choi, J.‐H. Kim, S. H. Noh, S. L. Min, Y. Cho, and
data compression,” IEEE Trans. Inform Theory, vol. 23, no. 3, pp. C. S. Kim, “On the existence of a spectrum of policies that
337–343, 1977. subsumes the least recently used (lru) and least frequently used
[16] A. V. Aho, P. J. Denning, and J. D. Ullman, “Principles of (lfu) policies,” in Proc. ACM SIGMETRICS Conf., pp. 134–143,
optimal page replacement,” J. ACM, vol.18, no. 1, pp. 80–93, 1999.
1971. [22] T. Johnson and D. Shasha, “2Q: A low overhead high
[17] D. Lee, J. Choi, J.‐H. Kim, S. H. Noh, S. L. Min, Y. Cho, and performance buffer management replacement algorithm,” in
C. S. Kim, “LRFU: A spectrum of policies that subsumes the Proc. VLDB Conf., pp. 297–306, 1994.
least recently used and least frequently used policies,” IEEE [23] S. Albers, S. Arora, and S. Khanna, “Page replacement for
Trans.Computers, vol. 50, no. 12, pp. 1352–1360, 2001. general caching problems,” Proceedings of the 10th Annual ACM–
[18] S. A. Johnson, B. McNutt, and R. Reich, “The making of a SIAM Symposium on Discrete Algorithms, pp. 31–40, 1999.
standard benchmark for open system storage,” J. Comput. [24]A. S. Tanenbaum and A. S. Woodhull, Operating Systems:
Resource Management, no. 101, pp. 26–32, Winter 2001. Design and Implementation. Prentice‐Hall, 1997.
[19] C. Aggarwal, J. L. Wolf, and P. S. Yu. “Caching on the [25] J. E. G. Coffman and P. J. Denning, Operating Systems Theory
WorldWideWeb,” In IEEE Transactions on Knowledge and Data Englewood Cliffs, NJ: Prentice‐Hall, 1973.
Engineering, vol. 11, pp. 94‐107, 1999. [26]www.ecs.umass.edu/ece/koren/architecture, Computer
Architecture Educational Tools. c
Authors
Debabala Swain, received her BE in Electronics & Debabrata Swain received his BTech in Computer Science Engg
Telecommunication Engineering from SMIT, Berhampur, from RIT, Berhampur, India in June 2008.Presently pursuing his
India, in June 2005, and M.Tech in Computer Science from M.Tech in Computer Science under Berhampur University. His
Berhampur University , India in June 2008.Presently pursuing subject of interest includes Computer Architecture, Computer
her PhD in Computer Science under Utkal University, Networking.
Bhubaneswar, India. Currently she is working as an Asst.
Professor in Department Computer science at Centurion Bijay Paikaray received his MCA from Sambalpur University in
University of Technology and Management, Bhubaneswar, June 2010.Presently working as a Lab Instructor in the Dept. of
India .Her prime research interest includes signal processing, CSE in Centurion University of Technology and Management,
wireless networking, System architecture and performance Bhubaneswar, India. His subject of interest includes Computer
evaluation. Organization, Network Security.