DESIGN AUTOMATION

USE OF TOOLS FOR AUTOMATION OF DESIGN

Layered Design Abstractions
A set of interrelated representational levels that allow a
system to be represented by varying amounts of detail.
Structured Design Concepts
1. Structural Description
A Description in which component is described as an
interconnection of more primitive components.
2. Behavioral Description
A Description in which component is described by its
input/output response.
Behavioral Description Structural Description

Specs(English) SYSTEM Computer,Disk

Unit etc.
Algorithm CHIP LEVEL Microprocessor

Data Flow REGISTER LEVEL Regsters,ALU,

Counters
Boolean
GATE LEVEL
Expressions AND, OR, NOT

Differential
CIRCUIT LEVEL Transistor,R,L,C
Equations

None SILICON LEVEL Geometrical

Shapes
Six Level Design Hierarchy
PROF M R BHUJADE CSE IIT BOMBAY VHDL 1
 IBM PC
DISK

Keyboard

Monitor

SYSTEM LEVEL

Microprocessor
RAM

PORTS

CHIP LEVEL

Register
ALU Register
Register
REGISTER LEVEL GATE LEVEL

Geometric shapes

SILICON LEVEL

PROF M R BHUJADE CSE IIT BOMBAY VHDL 2

CAD TOOL: A software program that assists in performing or
automating a particular design function

CAD TOOLS

Editors Simulators Checkers/ Synthesizers

Analyzers Optimizers
1. Editors: Textual or Graphical
(a) Text Editors
Used in Design entry in a Hardware Description
languages(HDL)
(b) Graphical Editors
1. Schematic Editors
An editor which can be used to create and
display interconnected set of graphic tokens
2. State Diagram Editors
allows drawing/displaying and editing of a FSM
state diagram as design.
2. Simulators
• A program that models the response of the system to
stimuli, where a system is a set of interconnected net
of components (logical deices).
Device is modeled by a process
Process : A computational entity that models the
function and delay of digital device
• Simulator is a major tool that allows prototyping of
design in software and to see it design working

PROF M R BHUJADE CSE IIT BOMBAY VHDL 3

3. Checkers and Analyzers
Programs that check entries and analyses them for any
violation of syntactic rules. HDL compilers check syntax of the
designs in HDL. Similarly other Design entries are
checked by the respective tools.
Timing and other constraints are also checked by these
tools.
• Synthesis Tools
Translates the design into lower level description of
design including silicon.
• Silicon compilers
Translates the HDL description into fabrication file for
given technology.
• FPGA Translators
Translates the design into programmable gate arrays
designs. ASICs are designed using FPGAs for physical
prototyping and testing.
• Optimizers:
Optimize the design for given criteria area optimization
will produce the design that occupies minimum chip
area.
• Speed optimization
will produce the design that works with maximum speed.
These are based on higher level languages that are designed
to do the job.
VHDL and Verilog are tow very important languages used in
the industry to day. VHDL is based on ADA philosophy while
Verilog is based on language C philosophy.
VHDL is IEEE standard and we have VHDL 87 and VHDL 93
PROF M R BHUJADE CSE IIT BOMBAY VHDL 4
 INTRODUCTION TO VHDL
• Origin : US government’s Very High Speed Integrated
Circuits (VHSIC) program
• VHDL : VHSIC Hardware Description Language VHSIC
• Motivations for VHDL
1. DESIGN ASPECTS
• Standardization of Requirement specification,
Documentation
• Reduced ambiguity in design interfaces Specs and design
functionality.
• Reusability of existing designs
• Better Integration of Multi-vendor Designs
• Shared design databases become possible
standard cells, behavioral models
• Improved Understanding of Designs
2. TEST AND VERIFICATION ASPECTS
a. Simulation
• Highly developed tools
• Inherently behavioral (structural simulators consist of ordered calls
to primitive procedures to model corresponding primitives.
• Limited by the effectiveness of the design test program
developed
b. Verification Possible by automated reasoning systems
3. HARDWARE SYNTHESIS
• Stepwise refinement of design by architectural
decomposition
• transformations from behavioral models to
corresponding structural and physical models
1. FPGA synthesis,
2. Standard Design Entity creations and
3. Making synthesis from the design cells.
• Enforcement of design constraints
• Expression transformations for optimization
PROF M R BHUJADE CSE IIT BOMBAY VHDL 5
• Purpose : To specify design using structural and
behavioral aspects and simulate and verify the
design using compilers and simulators.
Generate the design data file to synthesize
and verify the design.
Program /fabricate the CHIP.
VHDL compiler translates the source hardware description
into structure that is interpreted by various tools directly or
through other tools

Logic Simulators : Tests the resulting logic for functionality

and timings.
Circuit Simulators : Employ the silicon models of the cells
and interconnection delays used in the
design and tests the simulated electrical
circuit for functionality and delays.
Silicon compilers :Generate silicon file that can be used by
the foundry to make the IC
Let us look at the simple circuit: A single NAND gate

NAND_GATE is the name of

Entity NAND_GATE is the block.
port (a,b: in bit; c: out bit) a c
end NAND_GATE; b

Port specifies
the input out put pins
a,b,c are signal names.
PROF M R BHUJADE CSE IIT BOMBAY VHDL 6
In VHDL an entity is declared by the entity statement.
What function the entity carries out is specified by an
Architecture statement.
Architecture NandArch of nand_gate is
begin
process (a,b)
begin
c<= a nand b after 10 ns;
end process;
end NandArch;
This defines the behavior of the block called Nand_Gate.
Both the program segments (entity and architecture)
completely defines the nand_gate.
Nand used in the expression (in process) is an operator
of the language.
Process body may have a number of sequential statements
that are executed in sequence of appearance. The behavior
of the nand_gate requires the computation in the body of the
process to be executed again and again continuously so
that it mimics the physical gate which computes the output
continuously. This will eat up all the CPU time on the
machine.
Note that the same effect can be obtained when we
execute the body of the process when any of input signal
changes.The signals listed in the heading of the process
does this. It links the execution of the process to the
changes of values on these signals. The list is called
sensitivity list of a process. It creates a wait statement at
the end of a process .
PROF M R BHUJADE CSE IIT BOMBAY VHDL 7
 L1: process -- this loops indefinitely
begin -- eating all CPU time
c<= a nand b after 10 ns;
end process;
L2: process
begin
c<= a nand b after 10 ns;
wait on a,b; -- waits before loops
end process; -- back to begin
L3: process (a,b) -- This is equivalent to L2: Process
begin
c<= a nand b after 10 ns;
-- waits(due to sensitivity list)
end process; -- before loops back to begins

Example
VHDL program to describe the following logic circuit
composed of the entity nand_gate defined earlier.

x f
y
z

Module named as ckt

It has input pins x,y,z and one out put named as f

Entity ckt is
port (x,y,z: in bit; f : out bit);
end ckt;
PROF M R BHUJADE CSE IIT BOMBAY VHDL 8
1 Structural architecture description
Use components and connect them as required by the
circuit. Following architecture description does that.
Architecture cktarch1 of ckt is
Component Ngate port (a,b: in bit; c: out bit);
End component;
label U!,U2,U3; -- in VHDL 87
Signal s1,s2: bit;
for U1,U2,U3: ngate use entity NAND_GATE (nandarch);
begin
U1: ngate port map (x,y,s1);
U2: nagate port map (y,z,s2);
U3: ngate port map (s1,s2,f);
end cktarch;
-- This structural description is equivalent to wired logic diagram
-- (schematic). We are just describing the circuit schematic in this
-- architecture describtion.
2. Behavioral Architecture Description
architecture cktarch2 of ckt is
signal s1,s2: bit;
begin
process (x,y,z)
begin
s1<= x nand y after 10 ns;
s2<= y nand z after 10 ns;
f<= s1 nand s2 after 10 ns;
end process;
end cktarch2;
• In a process we can use only statements that are called
sequential statements.
• The signal assignments statement here are executed in
the sequence in which they appear.
PROF M R BHUJADE CSE IIT BOMBAY VHDL 9
• Entire process from begin to end is executed in 0 time and
• then suspends for the next event(change on any signal in
the sensitivity list)
• All the assignments take effects at the time specified.
The event scheduler schedules the three assignments
in the order in which they occur in the process.
In this case
a) At 10 ns s1,s2 get the value,
b) f will be getting new value after 10 ns from the
event on s1 and s2 (ie., after 20 ns)
3. Data flow Architecture Description
In this behavioral description concurrent signal assignments are
written as per the data flow of the logic network.(Process
is not used)
Architecture cktarch3 of ckt is
Signal s1,s2: bit;
begin
s1<= x nand y after 10 ns; -- these are concurrent statements
s2<= y nand z after 10 ns;
f<= s1 nand s2 after 10 ns;
end cktarch3;
• All the statements are executed concurrently. Computing
the these endlessly will eat out CPU time.
• The same effect is obtained by executing the architecture
body when a change on any signal(called event on a signal)
in any of expressions occurs.
• Thus, for each signal assignment in the architecture body,
an event on any signal in the expressions cause the
architecture body to be executed
PROF M R BHUJADE CSE IIT BOMBAY VHDL 10
• Architecture body could be composed of all the three ways
of describing the architecture if required.
Compiling VHDL code on Everest Unix
1. Store the script file which will be mailed to you in a file
called VHDL (or any other name)
2. Execute chmod 700 VHDL
3. Include the paths in your profile for the paths
mailed through a separate mail.
4. Now execute the command
VHDL ckt.cktarch1 nands.vhdl

Entity name arch name vhdl source file

Compiler name is VCOMP. It is directory

/usr/labs/logiclab/vhdl/bin
The output generated is a C language code, followed by a
.ivf file which is used by the simulator. An executable file
vsim_xxx (xxx is the name of the source file without
extension) .By executing vsim_nands the simulator promt
appears.
Simulator Commands
Watch * -- puts all signals on the dispplay list
dl -- displays signals on display list
st k -- steps time by k/10 ns
lo x,y,z -- makes x,y,z = 0 (low)
hi x,y -- makes x,y = 1 (high)
You can give values to x, y, z (by hi lo) and step time( by st
100 for 10 ns) and the display the signals by dl.
PROF M R BHUJADE CSE IIT BOMBAY VHDL 11
Entity statement syntax:

Entity entity_id is
[ generic(generic_list);]
[ port (port _list);]
[ entity_declarative_part];-- not supported by synth tools
[ begin
[ entity_statement_part;] -- not supported by synth tools
end [entity] [entity_id] ; -- are optional in VHDL 93

Example
Entity adderN is
generic (n : integer range <> := 8); -- range is open
port (a,b : in bit_vector ( n - 1 downto 0);
s : out bit_vector ( n -1 downto 0);
Cin : in bit;
Cout : out bit);
end adderN; -- N bit adder declaration template

entity Gate is
generic (Delay : Time := 10 ns);
port (a,b : in Std_Logic;
c : out Std_Logic);
end Gate;

delay value can be given later also. It will override the value
10 ns. All references to delay will have this value.

PROF M R BHUJADE CSE IIT BOMBAY VHDL 12

 Design Abstraction levels
Abstraction level helps in concealing irrelevant details
Example
To Design a n – bit adder (A,B,C are n bit numbers)
• Using VHDL operator
A<= B + C; statement does the job
• Designing adder at gate level
• Designing Adder using components such FA and their
layout.
Abstraction levels
• Functional : Algorithms could be described by a language (Need
not have timing info)
• Behavioral : function and timing can be described
• RTL level describes state machines, data paths operators,
registers etc.,(VHDL synthesizer maps these into hardware using
synthesis tool
• Logic Level : Description with Boolean Algebra or gate network.
• Lower levels (such as transistor network).These are not
supported by VHDL but Analog VHDL is coming up)
Design Hierarchy: We always follow the Idea of Hierarchy when
we deal with complexity

COMPONENT 1 Components 1.2

Components 1.1
Component 1.1 Component 1.2
VHDL VHDL
code code

Component Component
1.1.1 1.1.2

(a) Abstraction (b) Actual Design

PROF M R BHUJADE CSE IIT BOMBAY VHDL 13
 Example : Hierarchical Design of 8-Bit Adder

Component 1( 8 bit adder )

Component 1.1(4 bit adder) Component 1.2(4 bit adder)

1.1.1 1.1.2 1.1.3 1.1.4 1.2.1 1.2.2 1.2.3 1.2.4

………
Full Adders at leaf level
Design of Component 1 directly
Example 1:
Entity adder8 is
port (A, B: in integer range 0 to 255;
S: out integer range 0 to 255;
Cin: in integer range 0 to 1;cout: out bit);
end adder8;
Architecture adder8arch1 of adder8 is -- top level component
signal s1: integer range 0 to 512 ;
begin
S1<= A + B + cin; --the adder is synthesized by synthesis tool.
S <= S1 mod 256 ;
process (A,B,Cin,S1)
begin
if s1 > 255 then cout<= '1';
else cout <= '0';
end if;
end process;
end adder8arch1 ;
PROF M R BHUJADE CSE IIT BOMBAY VHDL 14
 Example 2: Design Using Two components as below. The
Next design uses this entity as component . Note that the
component name, pin names etc must be same, when this
entity is used as component. (if the entity can also be
separately compiled and kept in the library.

4 bit adder 4 bit adder

Entity adder4 is
port (X, Y: in integer range 0 to 15;
S: out integer range 0 to 15;
Cin: in integer range 0 to 1;cout: out bit);
end adder4;
Architecture adder4arch1 of adder4 is -- top level component
signal s1: integer range 0 to 31 ;
begin
S1<= X + Y + cin; --the adder is synthesized by synthesis tool.
S <= S1 mod 16 ;
process (X,Y,Cin,S1)
begin
if s1 > 15 then cout<= '1';
else cout <= '0';
end if;
end process;
end adder4arch1 ;

PROF M R BHUJADE CSE IIT BOMBAY VHDL 15

 8 bit Adder design Using 4 bit adders described
earlier as components.
Entity adder8 is
port (A, B: in Bit_vector(7 downto 0);
S: out bit_vector (7 downto 0);
Cin: in bit; cout: out bit);
end adder8
Architecture adder8arch2 of adder8 is
component adder4 is
port map (x,y: in bit_vector(15 downto 0);
s: out bit_vector (15 downto 0);
cin : in bit; cout : out bit);
end adder4;
signal CY4 : bit;
begin
U1: adder4 port map
(A(3) ,A(2),A(1),A(0),B(3),B(2),B(1),B(0),
S(3),S(2),S(1),S(0), Cin;CY4);
U2: adder4 port map
(A(7) ,A(6) ,A(5),A(4),B(7),B(6),B(5),B(4),
S(7),S(6),S(5),S(4), ;CY4,cout);
end adder8arch2;
Example 3: 8 bit adder can also be designed using full
adders directly. Use of hierarchy is useful for complex
systems.
A(7) B(7) .. A(2) B(2) A(1) B(1) A(0) B(0)
Cout
FA FA FA FA Cin

S(7) … S(2) S(1) S(0)

PROF M R BHUJADE CSE IIT BOMBAY VHDL 16
 Full Adder Design
U1 e1 U2
A
B S
Entity Full_Adder is Cin U3
port (a,b: in bit; s: out bit; e2
Cout
cin: in bit; cout : out bit);
end Full_adder;
e3 U5
Full Adder Architecture Descriptions U4
We describe FA through data flow (Boolean equations) and
also composed of gates(structural description)
1. Data flow description
Architecture FAarch of full_adder is
begin --
s<= a xor b xor cin after 10 ns;
cout<= (a or b) and Cin or ab after 10ns ;
end FAarch;
2. Structural description OF FULL ADDER
Architecture FAstrucarch of Full_adder is
component xor port (a,b,: in bit; f: out bit);end component;
component AND port (a,b: in bit; f: out bit);end component
component OR port (a,b: in bit; out bit); end component
signal s1,s2: bit;
begin
U1: xor port map (a,b,e1);
U2: xor port map (e1.cin,s);
U3: AND port map (e1 and cin,e2);
U4: AND port map (a,b,e2);
U5: OR port map (e2,e5,Cout);
end FAstructarch;

PROF M R BHUJADE CSE IIT BOMBAY VHDL 17

3. Behavioral Description
Architecture FAarch3 of FA is
signal s1: bit;
begin
process(a,b,cin)
begin
s1 <= a xor b after 10 ns;
s <= s1 xor cin after 10 ns;
cout <= (a and b )or (s1 and Cin) after 10 ns;
end FAarch;
-- The three statements are executed in sequence, but the
time taken by a process is 0. and assignments takes
effect as per the timings,
Below is the structural description of 8 bit adder, where
only FA is used as component which is
Architecture adder8arch2 of adder8 is
component FA is port (a,b: in bit; s,c: out bit);
signal c1,c2,c3,c4,c5,c6,c7: bit;
begin
U7: FA port map (A(7),B(7),S(7), c6,c7);
U6: FA port map (A(6),B(6),S(6), c5,c6);
U5: FA port map (A5),B(5),S(5), c4,5);
U4: FA port map (A(4),B(4),S4), c3,c4);
U3: FA port map (A(3),B(3),S(3), c2,c3);
U2: FA port map (A95),B(5),S(5), c1,c2);
U1: FA port map (A(7),B(7),S7), c0,c1);
U0: FA port map (A(6),B(6),S(6), cin,c0);
end adder8arch2LH
PROF M R BHUJADE CSE IIT BOMBAY VHDL 18
 Generate Statement
It is useful mechanism when design has copies of hardware
arranged as regular array of basic components. Conditional
elaboration is also allowed.
Suppose we want to specify the 8-bit adder as an
array of 8 Full Adders and join them as below:

A(7) B(7) .. A(2) B(2) A(1) B(1) A(0) B(0)

Cout Cin
FA FA FA FA

S(3) S(2) S(1) S(0)

Entity FA is port(A,B,C: in bit; S,Co: out bit); end FA;
Architecture FAarch of FA is
begin -- can also use earlier descriptions of FA
S<= A XOR B XOR C;
Co<= ((A OR B) and C) OR (A and B);
end Faarch;

entity adderN is
generic(n: integer:=8);
port (A,B: in bit_vector(7 downto 0);
S : out bit_vector(7 downto 0);
cin: in bit; cout: out bit);
end adderN;

PROF M R BHUJADE CSE IIT BOMBAY VHDL 19

Architecture adderNarch1 of adderN is
component FA is port (a,b,c: in bit; s,co: out bit);
end component;
signal C : bit_vector ( 8 downto 0);
begin
C(0)<= cin; -- cin;
cout<= c(8);
U : for I in 0 to N-1 generate
FAS: FA port map (A(I),B(I), C(i),S(I),C(I+1));
end generate; -- replicates 8 FAs
end adderNarch1;
Architecture adderNarch2 of adderN is
component FA is port (a,b,c: in bit; s,co: out bit);
end component;
signal C : bit_vector ( 8 downto 0);
signal g,p: bit_vector (8 downto 0);
begin
C(0)<= cin; -- cin;
cout<= c(8);
U : for I in 0 to 7
generate L1: if i < 5 generate
FAS: FA port map (A(I),B(I), C(i),S(I),C(I+1));
end generate;
L2 : if I = 5 or i= 6 or i=7
generate
p(i) <= a(i) xor b(i);
g(i)<= a(i) and b(i);
s(i) <= p(i) xor c(i);
C(i+1) <= (p(i) and c(i) ) or g(i) ;
end generate;
end generate;
end adderNarch2;
PROF M R BHUJADE CSE IIT BOMBAY VHDL 20
Architecture Statement Syntax
Architecture Arch_name of entity_name is
architecture_declarative_part
begin
Concurrent_statement
end arch_name;
Architecture_Declarative_ part can have none or one or
more of the following:
subprogram_declaration
subprogram body
type declaration
subtype declaration
constant declaration
signal acceleration
shared variable declaration -- not supported for synthesis
file declaration -- not supported for synthesis
alias declaration -- not supported for synthesis
component declaration
attribute declaration
attribute specification -- not supported for synthesis
configuration specification -- not supported for synthesis
disconnection specification -- not supported for synthesis
use clause
group complete declaration -- not supported for synthesis
group declaration -- not supported for synthesis

PROF M R BHUJADE CSE IIT BOMBAY VHDL 21

The following statements can be used in the
architecture body
1. Concurrent Statements
Concurrent Assert statement
Block statement
Component instantiation
Generate statement
Process statement
Concurrent Signal assignment statement
When else statement
With select statement
Concurrent procedure call statement
2. Sequential Statements
Can be used in Processes, Functions and Procedures
Some can be used in both Concurrent and Sequential
parts. Following statements are allowed as sequential VHDL
descriptions.
1. Assert statement
2. Case statement
3. If statement
4. Loop statement
5. Exit statement
6. Next statement
7. Null statement
8. Return statement
9. Signal and variable assignment statements
10. procedure call statement
11. Wait statement

PROF M R BHUJADE CSE IIT BOMBAY VHDL 22

1. ASSERT STATEMENT (Concurrent and Sequential)
Assert condition report Expression
severity severity _level
Example
Assert a=1 report “a is not one “ severity note;
2. CASE STATEMENT (Sequential)
Case expression is case_alternative end case
Example 1
case k is
when 0 => code<= “00”;
When 2 to 5 => code <= “10”;
When 1|9|6 => code <= “11”;
When others => code <= “01”;
End case;
Example2
Entity MUX is
port (I3,I2,I1,I0 : in bit; address: in bit_vector(1 downto 0);
f: out bit);
end MUX;
Architecture MUXarch1 of MUX is
process(cs,addres,I3,I2,I1,I0)
begin
Synthesized circuit
if cs =‘0’ then
case address is CS
when ‘00’ => f<= I0; I0 4 To 1 MUX
when ‘01’=> f <=I1; I1
when ‘10’=> f <=I2; I2
when ‘11’=> f <=I3; I3 f
end case; a1
else f<= ‘x’ -- try state f a0
end process;
end architecture;

PROF M R BHUJADE CSE IIT BOMBAY VHDL 23

3. IF STATEMENT (sequential)
If <condition> then expression statements
[{Elsif <condition>
statements}]
[else <condition> statements
end if;
Example D Flip Flop using behavioral Description
entity dff is
port (clock,clear,preset : in bit;
D: in bit ;
qb,q: out bit );
end dff;
architecture dffarch of dff is
begin
process (preset,clear,clock,d,q)
begin
if clear='0' then --asynchronous RESET active low
q <= '0';
elsif preset = '0' then q <= '1';
elsif (ClocK'event and ClocK='0')
then q <= D;
end if; preset
qb<= not q;
end process; D Q
end dffarch;

CK Qb

clear
PROF M R BHUJADE CSE IIT BOMBAY VHDL 24
4. LOOP STATEMENTS (Sequential)
While Loop
[loop_label:] while condition loop
sequence_of_statements
end loop [loop_label] ;
Example
L1: while not baldy
loop
do haircut;
end loop;
For Loop
[loop_label:] for loop_parameter in range loop
sequence_of_statements
end loop[loop_label];
Example
L1: for I in 7 downto to 0
loop
S(I)<= A(I) XOR B(I);
end loop l1;
Simple loop
[loop_label: ]
Loop
sequence of statements;
end loop [loop_label];
Example
signal Clock : BIT := '0';
process (Clk) clock generator loop.
begin
L1: loop
Clk <= not Clk after 10 ns;
end loop L1;
end process;

PROF M R BHUJADE CSE IIT BOMBAY VHDL 25

5. EXIT STAEMENT (Sequential)
Exit [loop_label] [when condition];
Exit the loop named by loop_label(or current loop
when no label is present.
Exit becomes conditional when the condition is specified.

6. NEXT STATEMENT (Sequential)

is used to complete execution of one of the iterations of
enclosing loop statement. The completion is conditional if
the statement includes a condition.
Syntax
next [loop_label] [ when condition] ;
Description:
when executed it results in skipping the current loop and
going to the next enclosing loop. If label present, one can
specify the loop to which control can be transferred.
Example
L0: while K <> 6 loop
L1: for I in 1 to 8 loop
A(i) := '0';
k := 0;
L2: loop
B(k) := '0';
next L0 when k > 6 -- when k=7 the loop L0
B(k + 8) := '0'; -- starts again
k := k + 1;
end loop L1;
end loop L2;
end loop L3

PROF M R BHUJADE CSE IIT BOMBAY VHDL 26

7. Null Statement
null; does not perform any action.
Examples:
Case code is
when "01" => Data := RegX OR RegY;
when "10" => DATA:= REGX and REGY;
when others => null;
end case;

8. Subprograms
Function ADDER8(a,b: bit_vector;f: bit_vector) return
bit_vector;
begin
return (a + b);
end function;
Function DFF (signal clk,clear, Din) return bit;
begin
If clear= ‘0’ then return 1 else
If clk’event and clk = ‘1’ then return Din;
end;
Procedure add(a,b: in integer range 255 downto 0;
f: out integer range 512 downto o) ;
begin
f <= a + b;
end;

PROF M R BHUJADE CSE IIT BOMBAY VHDL 27

9. WAIT STATEMENT (Sequential VHDL)
1. [label:] wait [on signal_list] [until condition] [for time];
-- suspends the process or procedure in which it is executed
-- resumes when any signal in signal_ list changes and the
-- condition if specified is satisfied for the time specified.
Example1:
wait on a
wait until ck=‘1’;
wait on (cs,en) until ck=‘1’;
wait for 10 ns;
wait on (cs,en) until ck=‘1’ for 10 ns;

Example 1
signal CS1,EN : bit;
process
begin
--
wait on CS,EN;
end process;
the process will be suspended on the wait statement and will be
resumed when one of the signals CS or EN changes its value(An
event occurs on one of them). If wait on signal_list is the only wait
statement in the process, then it has the same effect with a process
having these signals on the sensitivity list.
Note: A process with sensitivity list may not have wait
statement.
Example 2
wait until CS = ’0';
-- this is equivalent to
loop
wait on not CS;
exit when CS = ’0';
end loop;
PROF M R BHUJADE CSE IIT BOMBAY VHDL 28
 10. Delay modeling and Signal Assignments
(Concurrent and Sequential VHDL)
signal_name <= { [Transport|Inertial ] val_expr
[after time_exp} ;
Inertial delay is default which means
• Spikes of less than half the size of time given in after
clause are not propagated.
• Often used for component delays
a1<= inertial b nand c after 10 ns;
a2<= transport b nand c after 10 ns;
• Default is inertial and the spikes of less than 5ns will not
reach output signal a. On the other hand transport delay
models the ideal delay line, thus passing the input spikes
to the output.
b 0 5 10 17 20 30 40
b a
c
c

a1 10 15 20 27 30 40
Inertial delay
transport delay
a2 10 15 20 27 30 40
We can also specify the spike of lengths not be visible
a3<= Reject 7 ns inertial b nand c after 10 ns;

Spikes of length 7 ns or
less are suppressed 10 15 20 30 40

PROF M R BHUJADE CSE IIT BOMBAY VHDL 29

Waveforms
a<= b + c after 10 ns; right hand side is called a waveform.
In general we may have many such clauses that assigning
the values to a signal.
a<= 0 after 10 ns, 1 after 20 ns, 0 after 30 ns;
delays specified must be in ascending order.
Note: that the after clause is not supported by synthesis
tools
11. When else Statement (Concurren VHDL)
signal_name <= val_exp when condition {[,else
val_exp when condition]};
Example
R<= a + b when opcode= “01” else
a - b when opcode = “10” else
null when opcode =“00” else
a;

12. With Select Statement (Concurrent VHDL)

Syntax
with selection select
signal_name <= [Guarded|del_mech]]
[waveform when choice,}
waveform when choices;
Example
with address select -- MUX implementation
R<= I0 when “ 00”
I1 when “01”,
I2 when “10”,
I3 when others;

PROF M R BHUJADE CSE IIT BOMBAY VHDL 30

Sequential Assignment (in Processes)
• Are executed in the sequence in which they appear.i.e., the
events are scheduled in that order.
• Multiple assignments to a signal are allowed but only the
last one has the effect. I.e., Only one driver.

• The assignment takes effect when a process suspends.

• If a signal which is assigned a value in a process is
on the sensitivity list, a change in value will reactivate a
process.

Example:
signal x,y,z : bit
process(x,y)
begin
z<= x+y;
x<= x XOR y;
z<= x + y;
end process;

PROF M R BHUJADE CSE IIT BOMBAY VHDL 31

TYPES IN VHDL
• Each object in VHDL must be of some type,
• It defines possible values and operations that can be
performed on objects.
Operations on a type consists of:
• Basic operations (assignments, allocators, selected
names, indexed names, slice names,wherever applicable)
• allowed literals (numeric, literal null, string literal, bit
string literals, aggregates or predefined attributes
depending on particular type.
• though subprograms (predefined in standard
packages or user defined.
We have various basic types supported as below:
scalar types
Type positive is integer range 0 to <> ; --Unconstrained range
subtype DIGITS is INTEGER range 0 to 9;
The Enumeration types
values are defined by listing (enumerating) them explicitly.
values are represented by enumeration literals
Type Logic is ( '0', '1', ‘X’);
type Bitnew is (‘L’, ‘H’);
type std_ulogic is ( 'U', -- Uninitialized
'X', -- Forcing Unknown
'0', -- Forcing 0
'1', -- Forcing 1
'Z', -- High Impedance
'W', -- Weak Unknown
'L', -- Weak 0
'H', -- Weak 1
'-’ -- Don't Care);

PROF M R BHUJADE CSE IIT BOMBAY VHDL 32

The package Standard contains declarations of several predefined
enumeration types along with the opeartions.
The package is impliciltely visible for all programs.
Type boolean is (false,true); -- Boolean definition
Predefined operators are:
Logical: and, or, nand, nor, xor, xnor, not,
Comparison: =, /=, <, <=, >, >=),
Type Character is ( the values of this type are the 256 characters of
the ISO 8859-1 (Latin 1).
Predefined operators =, /=, <, <=, >, >=),
Type Bit is (‘0’,’1’);
Operators: same as Boolean.
Type integer is [(lower_num to higher_num);
Type integer is (higher_num downto lower_num);
Operators =, /=, <, <=, >, >=, +, -, abs, *, /, mod, rem, **),
Floating point type provides an approximation of the
real number value
type type_name is real_number_left_bound downto
real_number_right_bound;
Description:
A floating point type is a numeric type consisting of real numbers
which values are constrained by a specified range.
Type real is range ( 2.0**N) - 1.0 downto -2.0**N);
Type REAL is ( .. )
Operators =, /=, <, <=, >, >=, +, -, abs, *, /, **),
type Bit_vector is array( natural range <>) of bit;
signal Opcode is array( 7 downto 0) of Bit;
opcoe(0)<= ‘1’;
opcode<= (7|6=> ‘0’);
opcode<= opcode(5 downto 1=> ‘1’);
opcode <= “00111111”

PROF M R BHUJADE CSE IIT BOMBAY VHDL 33

 Physical type is a numeric scalar representing some quantity.
Example
type CAPACITANCE is range 0 to 1E5
units
pF; -- picofarad
nF = 1000 pF; -- nanofarad
uF = 1000 nF; -- microfarad
mF = 1000 uF; -- milifarad
F = 1000 mF; -- farad
end units Capacitance
Type time range is <> is
units
ps -- picosecond
ns = 1000 ps;
ms = 1000 ns;
s = 1000 ms;
min = 60 s;
hours = 60 min;
days = 24 hour;
end Units time ;
usgae:
var A,B: time;
A:= 10 ns;
B:= A + 100 days;
Subtypes
Subtype DIGIT is INTEGER range 0 to 9;
Subtype Capitals is Character range ‘A’ to ‘Z’
There are two predefined subtypes specified in the package
STANDARD: natural and positive.
subtype RBIT is RESOLVE_VALUE BIT;
• Type conversion between subtype and its base type is not required.
• The set of operations allowed on operands of a subtype is
the same as the set of operations on its base type.
Use subtypes of enumerated and integer types for synthesis is good
since synthesis tools infer an appropriate number of bits in synthesized
registers

PROF M R BHUJADE CSE IIT BOMBAY VHDL 34

Composite Types
Arrays indexed collection of elements of same type
type Matrix is array (1 to 100,1 to 100 ) of REAL;
type Bit_VECTOR is array (0 to 7) of BIT;
type Vector is array (NATURAL range <>) of integer --
· Arrays composed of file types are illegal
type vector is array(1 to 10 ) of integer range 0 to 15;
use of types
variable x,y: vector:= (1=> 0, others => 1); -- initiallised
array
Records Group of heterogeneous related information

Type Register is (R0, R1,R2,R3);

Type Instruction is record
Mnemonic : Bit_Vector(7 down to 0);
Reg: Register;
Address : Bit_Vector(23 down to 0);
end record;
variable A,B: instruction:= (0,AX,others=> “0”);
Reference (use of record variables) to compoents is by
selected components below:
A.reg:= R0;
A.address:= 200;
A.opcode:= 40;
A:= B; -- record assignment;
• Records may have elements that are composite but Files
are not allowed as elements of records.
Notes: record whose elements are of not of composite
type are synthesizable.

PROF M R BHUJADE CSE IIT BOMBAY VHDL 35

Attributes allow retrieving information(properties) about
types, objects, subprograms etc.
• VHDL defines a set of predefined attributes.
• User defined attributes: in addition possible
for any type T the following is available
Attribute
T’Base base type of T
Attributes of Scalar type
For Type T which is scaler we have following predefined
Attribute
T’Left gives leftmost value of T
T’Right gives rightmost value of T
T’Low gives least value in T
T’High gives greatest value in T
T’Ascending gives true if T is an ascending range
false otherwise
T’Image(x) gives a textual representation of the value x
T’Value(s) gives value of s
Attributes of discrete or physical types and subtypes
T’Pos(s) gives universal integer position number of s
T’Val(x) gives value at positionx (x is integer)
T’Succ(s) gives value at position one greater than s
T’Pred(s) gives value at position one less than s
T’Leftof(s) gives value at position one to the left of s
T’Rightof(s) gives value at position one to the right of s

PROF M R BHUJADE CSE IIT BOMBAY VHDL 36

Signals attributes
S’Delayed(t) gives copy of signal S delayed by time t, but
S’Stable(t) gives True if no event has occurred on S for
t time units, False otherwise
S’Quiet(t) True if no transaction taken on S for t time
units, False otherwise
S’Transaction generates a signal of type Bit whose value is
changed in each simulation cycle in which a
transaction occurs on S (signal S becomes
active)
S’Event Gives True if an event has occurred on signal
S in the current simulation cycle, False
otherwise
S’Active True if a transaction has occurred on S in the
current simulation cycle, False otherwise
S’Last_event the amount of time since last event occurred
on S, if no event has yet occurred it returns
Time’High
S’Last_active the amount of time since last transaction
occurred on S, if no event has yet occurred it
returns Time’High
S’Last_value the previous value of S before last event
occurred on it
S’Driving True if the process is driving S or every
element of a composite S, False if the
current value of the driver for S or any
element of S in the process is determined
by the null transaction
Synthesis tools support very small set of necessary attributes.

PROF M R BHUJADE CSE IIT BOMBAY VHDL 37

Attributes of named entities
E’Simple_name a string giving the simple name(or character
literal or operator symbol) defined in the
declaration of the item E
E’Path_name a string describing the path through
the design hierarchy, from the root entity or
package to the item E
E’Instance_name a string describing the path through the
design hierarchy, from the root entity or
package to the item E, but including the names
of the entity and architecture bound to each
component instance in the path

Attributes of the array type (or objects of the array type)

X’Left(n) leftmost value in index range of dimension n
X’Right(n) rightmost value in index range of dimension n
X’Low(n) lower bound of index range of dimension n
X’High(n) upper bound of index range of dimension n
X’Range(n) index range of dimension n
X’Reverse_range(n) reversed index range of dimension n
X’Length (n) number of values in the n-th index range
X’Ascending(n) True if index range of dimension n is
ascending, False otherwise

PROF M R BHUJADE CSE IIT BOMBAY VHDL 38

PROF M R BHUJADE CSE IIT BOMBAY VHDL 39
PROF M R BHUJADE CSE IIT BOMBAY VHDL 40
FILES
A file is used to define objects representing files in the
host environment.
The value of a file object is the sequence of values
contained in the physical file
File Type and Operations
Type FT is file of T; -- FT is a file of elements of type T
procedure FILE_OPEN ( file_variable: FT;
External_Name: in STRING;
mode : in FILE_OPEN_KIND
:= READ_MODE );
procedure FILE_OPEN ( Status: out FILE_OPEN_STATUS;
file_variable: FT;
External_Name: in STRING;
mode: in FILE_OPEN_KIND
:= READ_MODE );
procedure FILE_CLOSE ( file_variable: FT );
procedure READ (file_variable : FT; Value: out SomeType );
procedure WRITE (file_variable : FT; Value: in SomeType );
function ENDFILE (file_variable : FT ) return BOOLEAN;

Examples
Type names is file of STRING;
Type rollnos is file of integer;

Files of all scaler types, arrays of one dimension

and records are supported.
File types may not be supported by synthesis tools.

PROF M R BHUJADE CSE IIT BOMBAY VHDL 41

procedure Register (D: in bit_vector(7 downto 0);
Q: bit_vector(7 downto 0);
Clear, Load: in bit);
begin
if clear=‘0’ then Q<= ‘00000000’
elsif load’event and load =‘0’ then q<= D;
end if;
end Register;

PROF M R BHUJADE CSE IIT BOMBAY VHDL 42

PROF M R BHUJADE CSE IIT BOMBAY VHDL 43
PACKAGES

• A package is a unit that groups various declarations,

• The items declared in a package can be shared
among several designs.
• Packages are stored in libraries for greater convenience.
• A package consists of package declaration and optionally
a body.
A package is used to implement abstract data types and
create application specific extensions. A package is used
declare shareable types subtypes, constants, signals, files,
aliases, component, attributes and groups and opeartions.
Once a package is defined, it can be
used in multiple independent designs.
VHDL has default packages called STANDARD and TEXTIO.
The former contains basic declarations of types, constants and
operators, while the latter defines operations for manipulating
text files. Both are located in the library STD. User defined
libraries can hold various user packages.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package mrb is
type MUX_input is array (INTEGER range<>) of
STD_LOGIC_VECTOR (0 to 7);
type operation_set is (SHIFT_LEFT, ADD);
subtype MUX_address is POSITIVE;
function Compute_Adress (IN1 : MUX_input) return
MUX_address;
constant Deferred_Con : Integer;
end mrb;

PROF M R BHUJADE CSE IIT BOMBAY VHDL 44

Constants
type Opcode is (add,sub,mul,xor,or, not);
constant firstopcode: opcode := add;
constant Ground: Bit := '0';
constant Data_width, stack_depth :integer:= 8;
constant clockcycle : Time := 10 ns;
constant maxdelay : Time := 15 * CLKPeriod;

type Passwd is array (7 downto 0) of Integer range 0 to 9;

constant mrbpasswd: passwd := (2,6,4,8,0,0,1,3);
constant zeros: Bit _Vector(7 downto 0) := "00000000";

package Inialisation is
constant global_reset: bit;
power_on: bit;
end package Timing;

package body Initialisation is

constant global_reset: bit: := '0';
constant poer_on: bit:=‘1’;
end package body Timing;

PROF M R BHUJADE CSE IIT BOMBAY VHDL 45

There exists only one predefined floating point type: REAL
The range of the values for the type REAL are implementation
dependent, but must covers the values from -1.0E38 to +1.0E38

;l.

PROF M R BHUJADE CSE IIT BOMBAY VHDL 46

How simulation proceeds
The simulation is supposed to give the view as per the
logic circuits actions. The are three important things to
be looked at.
Concurrent Statements execute in parallel. Since
machine on which we schedule the operations is
sequential, the effect to be same irrespective of the order

PROF M R BHUJADE CSE IIT BOMBAY VHDL 47

Configuration

PROF M R BHUJADE CSE IIT BOMBAY VHDL 48

A type conversion is restricted to closely related types.e.g,
1. Integers and floating point are closely related types.
When a floating-point number is converted into an integer,
the result is rounded to the nearest integer.
2. Two arrays of same dimensions are closely related
types provided both their elements of the same type and
for each range, the index types are the same or closely
related. (index positions could have different directions)
Type conversion is done by the conversioin function whose
name is the type name.
Example
variable X,Y : integer;
y:= Integer (3.14158* real(x));

PROF M R BHUJADE CSE IIT BOMBAY VHDL 49

Alias Declarations
alias alias_name : alias_type is object_name;
(A synthesis tool may not support aliases.)
Example: Instruction Format
31 24 23 20 19 0

Opcode GPR Address

Index Disp

signal : Instruction Bit_Vector(31 downto 0);

alias opcode : bit_vector (7 downto 0) is
instruction (31 downto 24);
alias GPR : bit_vector (3 downto 0) is
address (23 downto 20);
alias address : bit_vector (19 downto 0) is
instruction (19 downto 0)
alias Index : bit_vector (15 downto 0) is
address(19 downto 16)
• In the example, using alias facilitates the refer to the
sub-slices with meaning full names with associated types
• The reference to the aliase names allows us to refer to the
slice of the original object.
• If Opcode <= ”10101010" then.. -- will refer to the object
instruction (31 downto 24)

PROF M R BHUJADE CSE IIT BOMBAY VHDL 50

 Access types
Objects that are created dynamically during run time by
allocators. (Pointers)
type type_id is access type_id;
Example1
Type Byte_pointer is access integer range 255 downto 0;
Example 2

type Stack ; -- incomplete declaration.

type stackaccess is access stack;
type Stack is
record array(1 to 255) of address;
sp: integer range 0 to 255;
end record;

Allocators
Type stage is array(0 to 15) of bit;
type Reservation_table is array (1 to 8) of stage;
type TableAccess is access Reservation_Table;
variable y : TableAccess;
y := new Table; -- will be initialized with default value all 0;s

PROF M R BHUJADE CSE IIT BOMBAY VHDL 51

type Table is array (1 to 8) of Natural;
type TableAccess is access Table;
variable x : TableAccess;
...
X := new Table; -- will be initialized with
-- (0, 0, 0, 0, 0, 0, 0, 0).

Aggregates
Array aggregates
signal Data : Std_Logic_Vector (7 downto 0);
signal x,y : : Std_Logic_Vector ;
Data <= (7 downto 3 => '1',
4|5 => x and y, bits
others => '0'); -- last choice

Record Aggregates
type Status is record
Code : integer range 0 to 15;
Name : String (1 to 4);
end record;
variable A : Status := (Code => 12, Name => ”ADD");

PROF M R BHUJADE CSE IIT BOMBAY VHDL 52

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