Moving Message

DISPLAY
INTRODUCTION TO MICROCONTROLLER

Introduction:

A Microcontroller consists of a powerful CPU tightly coupled with memory

RAM, ROM or EPROM, various I/O features such as serial ports, parallel ports,
timer/counters, interrupt controller, data acquisition interfaces- analog to digital
converter, digital to analog converter every thing integrated on to a single silicon chip.

It does not mean that any microcontroller should have all the above said features
on a chip depending on the need and area of application for which it is designed. The
on chip features present in it may or may not include all the individual section said
above.

Any microcomputer system requires memory to store a sequence of instructions

making up a program from parallel port or serial port for communicating with an
external system timer, counter for control purposes like generating time delays, baud
rate for the serial port apart from the controlling unit or the central processing unit.

ADVANTAGES OF MICROCONTROLLER:

If a system developed with a microprocessor the designer has to go for external

memory such as RAM, ROM, EPROM and peripherals and hence the size of the PCB
will be large enough to hold all the required peripherals. But the Microcontroller has
got all these facilities on a single chip so development of a similar system with a
microcontroller reduced PCB size and the cost of the design.

One of the major differences between microcontroller and microprocessor is

that a controller often deals with bits, not bytes as in the real world application. For
example switch contacts can only be opened or closed, indictors should be lit or dark
and motors can be either tuned on or off and so forth.
 FEATURES:

• AT89C52 Central Processing Unit.

• On-chip Flash Program Memory with In-System Programming
(ISP) and In-Application Programming (IAP) capability.
• Boot ROM contains low level Flash programming routines for
Downloading via the UART.
• Can be programmed by the end-user application (IAP).
• 6 clocks per machine cycle operation (standard).
• 12 clocks per machine cycle operation (optional).
• Speed up to 20 MHz with 6 clock cycles per machine cycle.
(40 MHz equivalent performance); up to 33 MHz with 12 clocks
Per machine cycle.
• Fully static operation.
• RAM expandable externally to 64 KB.
• 4 level priority interrupt.
• 7 interrupt sources.
• Four 8-bit I/O ports.
• Full duplex enhanced UART.
o Framing error detection.
o Automatic address recognition.
• Power control modes.
o Clock can be stopped and resumed.
o Idle mode.
o Power down mode.
• Programmable clock out.
• Second DPTR register.
• Asynchronous port reset.
• Low EMI (inhibit ALE).
• Programmable Counter Array (PCA).
 BLOCK DIAGRAM OF MICROCONTROLLER

FIG 6.1 BLOCK DIAGRAM OF MICROCONTROLLER

PIN DIAGRAM OF MICROCONTROLLER AT89C52RD2BA

1 40
2 P1.0 VCC 39
3 P1.1 P0.0/AD0 38
4 P1.2 P0.1/AD1 37
5 P1.3 P0.2/AD2 36
6 P1.4 P0.3/AD3 35
7 P1.5 P0.4/AD4 34
8 P1.6 P0.5/AD5 33
9 P1.7 P0.6/AD6 32
RST P0.7/AD7
10 31
11 P3.0/RXD EA 30
12 P3.1/TXD ALE 29
13 P3.2/INT0 PSEN 28
14 P3.3/INT1 P2.7/A15 27
15 P3.4/T0 P2.6/A14 26
16 P3.5/T1 P2.5/A13 25
17 P3.6/WR P2.4/A12 24
18 P3.7/RD P2.3/A11 23
19 X2 P2.2/A10 22
20 X1 P2.1/A9 21
GND P2.0/A8

AT89C52RD2BA
FIG 6.2 PIN DIAGRAM OF AT89C52RD2BA
PIN DESCRIPTION:

Ground: 0V reference.

Power Supply: This is the power supply voltage for normal, idle, and power-down
operation.

Port 0: Port 0 is an open-drain, bi-directional I/O port. Port 0 pins that have 1s written to
them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-
order address and data bus during accesses to external program and data memory. In this
application, it uses strong internal pull-ups when emitting 1s.

Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pull-ups on all pins except
P1.6 and P1.7, which are open drain. Port 1 pins that have 1s written to them are pulled
high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are
externally pulled low will source current because of the internal pull-ups.

T2 (P1.0): Timer/Counter 2 external counts input/Clock out (see Programmable Clock-

Out).
T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control.
ECI (P1.2): External Clock Input to the PCA.
CEX0 (P1.3): Capture/Compare External I/O for PCA module 0.
CEX1 (P1.4): Capture/Compare External I/O for PCA module 1.
CEX2 (P1.5): Capture/Compare External I/O for PCA module 2.
CEX3 (P1.6): Capture/Compare External I/O for PCA module 3.
CEX4 (P1.7): Capture/Compare External I/O for PCA module 4.

Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as inputs.
As inputs, port 2 pins that are externally being pulled low will source current because of
the internal pull-ups. Port 2 emits the high-order address byte during fetches from
external program memory and during accesses to external data memory that use 16-bit
addresses (MOVX@DPTR).
In this application, it uses strong internal pull-ups when emitting 1s.During accesses to
external data memory that use 8-bit addresses (MOV @ Ri), port 2 emits the contents
of the P2 special function register.

Port 3: Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as inputs.
As inputs, port 3 pins that are externally being pulled low will source current because of
the pull-ups.
Port 3 also serves the special features of the 89C51RB2/RC2/RD2, as listed below:

RxD (P3.0): Serial input port.

TxD (P3.1): Serial output port.
INT0 (P3.2): External interrupts.
INT1 (P3.3): External interrupts.
T0 (P3.4): Timer 0 external input.
T1 (P3.5): Timer 1 external input.
WR (P3.6): External data memory writes strobe.
RD (P3.7): External data memory reads strobe

Reset: A high on this pin for two machine cycles while the oscillator is running, resets
the device. An internal resistor to VSS permits a power-on reset using only an external
capacitor to VCC.

Address Latch Enable: Output pulse for latching the low byte of the address during an
access to external memory. In normal operation, ALE is emitted twice every machine
cycle, and can be used for external timing or clocking. Note that one ALE pulse is
skipped during each access to external data memory. ALE can be disabled by setting SFR
auxiliary. With this bit set, ALE will be active only during a MOVX instruction.
Program Store Enable: The read strobe to external program memory. When executing
code from the external program memory, PSEN is activated twice each machine cycle,
except that two PSEN activations are skipped during each access to external data
memory. PSEN is not activated during fetches from internal program memory.

External Access Enable/Programming Supply Voltage: EA must be externally held

low to enable the device to fetch code from external program memory locations. If EA is
held high, the device executes from internal program memory. The value on the EA pin is
latched when RST is released and any subsequent changes have no effect. This pin also
receives the programming supply voltage (VPP) during Flash programming.

Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock
generator circuits.
Crystal 2: Output from the inverting oscillator amplifier.

MEMORY ORGANISATION:

All Atmel flash microcontrollers have separate address spaces for program and
data memory as shown in figure. The logical separation of program and data memory
allow data memory to be accessed by 8 bit addresses which can be more quickly stored,
manipulated by an 8 bit CPU nevertheless 16 bit Data memory addresses can also
generated through the DPTR register

Program memory can be read and not written. There can be upto 64KB of directly
accessible program memory. The read strobe for external program memory is the
program strobe enable signal PSEN.Data memory occupies a separate address space from
program memory. Upto 64KB of external memory can be directly accessed in the
external data memory space.
PROGRAM MEMORY:

Figure shows the map of the lower part of the program memory, after reset, the
CPU begins execution from location 0000h.As shown in figure each interrupt is assigned
a fixed location in program memory. The interrupt causes the CPU to jump to that
location, where it executes the service routine. External interrupt 0 for example, is
assigned to location 0003h.If external interrupt 0 is used, its service routine must begin at
location 0003h. If the first interrupt is not used, its service location is available as
general-purpose program memory.

TIMER 2 002BH
SERIAL PORT 0023H
TIMER 1 001BH
EXT INTERRUPT 1 0013H
TIMER 0 000BH
EXT INTERRUPT 0 0003H
RESET 0000H

FIG 6.3 PROGRAM MEMORY

The interrupt service locations are spaced at 8 bit intervals 0003h for EXT
interrupt 0, 000Bh for Timer 0, 0013h for Ext INT 1, 001Bh for Timer 1, and so on. If
the interrupt service routine is short enough it can reside entirely with in that 8-byte
interval. Longer service routines can use a jump instruction to skip over subsequent
interrupt locations. If other interrupts are in use the lowest address of program memory
can be either in the on chip flash or in external memory.

To make this selection strap the external access EA Pin to either Vcc or ground.
For example AT89C52RD2BA with 4KB of on chip flash, if the EA pin is strapped to
Vcc, the program fetches to addresses 0000h through 0FFFh are directed to internal
flash. Program fetches to addresses 1000h through FFFFh are directed to external
memory.

DATA MEMORY:

The Internal Data memory is divided is divided into three blocks namely,

 The lower 128 Bytes of internal RAM.

 The upper 128 Bytes of Internal RAM.
 Special Function Register.

7FH

GENERAL PURPOSE
RAM

2FH

BIT ADDRESSABLE
LOCATIONS

20H
1FH
BANK 3
17H
BANK 2 FOUR BANKS OF 8
0FH REGISTERS
BANK 1
(R0 - R7)
07H
BANK 0
00H
FIG 6.4 DATA MEMORY
 Internal Data memory Addresses are always 1 byte wide, which implies an address
space of only 256 bytes. However, the addressing modes for internal RAM can in fact
accommodate 384 bytes. Direct addresses higher than 7Fh access one memory space,
and indirect address higher than 7Fh access a different Memory Space.

The lowest 32 bytes are grouped into 4 banks of 8 registers. Program instructions call
out these registers as R0 through R7. Two bits in the Program Status Word (PSW)
Select, which register bank, is in use. This architecture allows more efficient use of
code space, since register instructions are shorter than instructions that use direct
addressing.

The next 16-bytes above the register banks form a block of bit addressable memory
space. The micro controller instruction set includes a wide selection of single – bit
instructions and this instruction can directly address the 128 bytes in this area. These
bit addresses are 00h through 7Fh either direct or indirect addressing can access the
upper 128. The upper 128 bytes of RAM are only in the devices with 256 bytes of
RAM.

The Special Function Register includes Port, latches, timers, peripheral controls
etc., Direct addressing can only access these register. In general, all Atmel micro
controllers have the same SFRs at the same addresses in SFR space as the
AT89c52RD2BA and other compatible micro controllers. However, upgrades to the
AT89c52RD2BA have additional SFRs. Sixteen addresses in SFR space are both byte
and bit Addressable. The bit Addressable SFRs are those whose address ends in
0000B. The bit addresses in this area are 80h through FFh.
ADDRESSING MODES:

DIRECT ADDRESSING:

In direct addressing, the operand specified by an 8-bit address field in the

instruction. Only internal data RAM and SFR’s can be directly addressed.

INDIRECT ADDRESSING:

In Indirect addressing, the instruction specifies a register that contains the address of
the operand. Both internal and external RAM can indirectly address.The address
register for 8-bit addresses can be either the stack pointer or R0 or R1 of the selected
register Bank. The address register for 16-bit addresses can be only the 16-biy data
pointer register, DPTR.

INDEXED ADDRESSING:

Program memory can only be accessed via indexed addressing this addressing
mode is intended for reading look up tables in program memory. A 16 bit base register
(Either DPTR or the Program Counter) points to the base of the table, and the
accumulator is set up with the table entry numbe5r. Adding the Accumulator data to
the base pointer forms the address of the table entry in program me memory.

Another type of indexed addressing is used in the “case jump” instructions is

computed as the sum of the base pointer and the Accumulator data.
REGISTER ADDRESSING:

The register banks, which contains registers R0 through R7, can be accessed by
instructions whose opcodes carry a 3-bit register specification. Instructions that access
the registers this way make efficient use of code, since this mode eliminates an address
byte. When the instruction is executed, one of four banks is selected at execution time by
the row bank select bits in PSW.
REGISTER-SPECIFIC ADDRESSING:

Some instructions are specific to a certain register. For example some instruction
always operates on the Accumulator. In these cases, the opcode itself points to the correct
register. Instructions that refer to Accumulator as A assemble as Accumulator- specific
Opcodes.

IMMEDIATE ADDRESSING:

The value of a constant can follow the opcode in program memory for example.
MOV A, #100 loads the Accumulator with the decimal number 100. The same number
could be specified in hex digit as 64h.

PROGRAM STATUS WORD:

PSW.7 PSW.6 PSW.5 PSW.4 PSW.3 PSW.2 PSW.1 PSW.0

CY AC F0 RS1 RS0 OV --- P

FIG 6.5 PROGRAM STATUS WORD

PSW.0:
Parity of Accumulator set by hardware to 1 if it contains an odd number of 1s,
otherwise it is reset to 0.
PSW.1:
User Definable flag.
PSW.2:
Overflow flag set by arithmetic operations.
PSW.3:
Register Bank Select 0.
PSW.4:
Register Bank Select 1.
PSW.5:
General Purpose flag.
PSW.6:
Auxiliary Carry Flag. Receives carry out from bit 1 of addition operands.

PSW.7:
Carry flag receives carry out from Bit 1 of ALU operands.
The PSW contains status bit that reflects the current state of the CPU.The PSW
shown in figure resides in SFR space. The PSW contains the carry bit, the Auxiliary carry
(for BCD operations). The two register bank select bits, the overflow flag, a parity bit and
two user definable status flag.
The carry bit, in addition to serving a carry bit in arithmetic operations also serves
as the Accumulator for a number of Boolean operations. The bits RS0 and RS1 select one
of the four register banks. A no. Of instruction registers to this Ram locations as R0
through R7.The status of RS0 and RS1 bits at execution time determines which of the
four banks is selected.
The parity bit reflects the no. of 1s in the Accumulator. P=1 if the accumulator
contains an odd number of 1s, and P=0 if the Accumulator contains an even no. of
1s.Thus, the no. of 1s in the Accumulator plus P is always even. The two bits in the PSW
are uncommitted and can be used as general-purpose status flag.

TIMERS AND COUNTERS:

The AT89c52RD2BA has two Timers. Timer 0 and Timer 1.They can be used
either as Timers or as Event Counters.

Timer 0 Registers:
The 16-bit Register of Timer 0 is accessed as low byte and high byte. The low
byte register is called TL0 and high byte register is referred to as TH0.This registers can
be accessed like any other register, such as A, B, R0, R1, R2, etc.
Timer 1 Registers:
Timer 1 is also 16 bits and its 16-bit register is split in two bytes, referred to, as
TL1 And TH1.These registers are accessible in same as the registers of Timer 0.

TMOD (Timer Mode) REGISTER:

Both Timer 0 and 1 use the same register, called TMOD, to set the various Timer
operation modes. TMOD is an 8 bit register in which the lower 4 bits are set aside for
Timer 0 and the upper 4 bits are set aside for Timer 1.In each case, the lower 2 bits are
used to set the Timer mode and the upper two bits to specify the operations.

TIMER 1 TIMER 0

GATE C/T M1 M0 GATE C/T M1 M0

FIG 6.6 TMOD REGISTER

GATE:
Gating control when set. Timer/Counter is enabled while the INT x pin is high
and TRx control pin is set. When cleared, the Timer is enabled whenever the TRx control
bit is set.

C/T:
Timer or Counter selected cleared for Timer operation. Set for Counter operation.
M1:
Mode bit 1.
M0:
Mode bit 0.
M1 M0 MODE OPERATION MODE

0 0 0 13 bit Timer Mode.

8 Bit Timer/Counter TH x with TL x as high bit

Prescalar

0 1 1 16 Bit Timer Mode.

16 Bit Timer/Counter TH x and TL x are

cascaded.

1 0 2 8 Bit Auto Reload.

8 BIT Auto Reload Timer/Counter’s x holds a value, which
is to be, reloaded into TLx each time it overflows.

1 1 3 Split Timer Mode.

TAB 6.1 DIFFERENT MODES TMOD REGISTER

INTERRUPTS:

The AT89c52RD2BA provides 5 interrupt sources. Two external Interrupts, two

Timer Interrupts and a serial port interrupt. The External Interrupts INT0 and INT1 can
each either level activated or transition activated, depending on bits IT0 and IT1 in
register TCON. The flags that actually generate these Interrupts are the IE0 and IE1 bits
in TCON.
TF0 and TF1 generate the Timer 0 and Timer 1 Interrupts, which are set by a roll over
in their respective Timer/Counter register (Except for Timer 0 in Mode 3). When the
Timer Interrupt is generated, the on chip hardware clears the flag that generated it when
the service routine is vectored to.

The logical OR of RI and TI generate the serial port Interrupt. Neither of these
flags is cleared by hardware when the service routine is vectored to. Infact, the service
routine normally must determine whether RI or TI generated the interrupt and the bit
must be cleared in software.

INTERRUPT ENABLE REGISTER:

IE.7 IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0

EA -- ET2 ES ET1 EX1 ET0 EX0

FIG 6.7 INTERRUPT ENABLE REGISTER

Enable Bit =1 enables the Interrupt.

Enable Bit =0 disables the Interrupt.

EA:
Global enable interrupts.

If EA=0,no interrupt.
If EA =1,each interrupt is source individually enabled.

ET2:
Timer 2interrupt enable bit.

ES:
Serial port interrupt enabled bit.

ET1:
Timer1 interrupt enable bit.

EX1:
External interrupt1 enable bit.

ET0:
Timer0 interrupt enable bit.

EX0:
External interrupt 0 enable bit.
POWER SUPPLY:

1
T1
1 5
2 - + 4
1N4007
230V A.C.

4 8

OUTPUT
C R1
1k
1000uF
3

FIG POWER SUPPLY

The power supply can be built using a transformer connected to the A.C.
supply line to step the A.C. Voltage to desired amplitude, rectifying that
A.C. voltage, filtering it to a ripple free D.C. voltage with a capacitor. It is
then regulated to a steady level. A voltage regulator, which converts the
input D.C. voltage to a required low D.C. voltage, which remains the same
even if the input D.C. voltage varies, usually does the regulation or the
output load connected to the D.C. voltage changes. It provides regulations
of either a fixed positive voltage, a fixed negative voltage, or an adjustably
set voltage.
SPECIFICATIONS:
 Input Voltage -230V, 50 Hz
 Output Voltage - 6V
 Diode 1N 4007
 Capacitor 1000 µF
SERIAL COMMUNICATION

DB9 PIN

P 1
FIG 10.1 DB9 PIN
5
9 DB-9 PIN
4 CONNECTOR:
8
RX/
3
7 PIN
TX/
2
6
1 DESCRIPTION

DB9
1
Data carrier detect (DCD)
2 Received data (RXD)
3 Transmitted data (TXD)
4 Data terminal ready (DTR)
5 Signal ground (GND)
6 Data set ready (DSR)
7 Request to send (RTS)
8 Clear to send (CTS)
9 Ring indicator (RI)
TAB 9.1 DB9 PIN DESCRIPTIONS

1.DTR (Data Terminal Ready):

When the terminal (or a PC COM port) is turned on, after going
through a self-test, it sends out signal DTR to indicate that it is ready for
communication. If there is something wrong with the COM port, this signal
will then be activated. This is an active-low signal and can be used to
inform the modem that the computer is alive and kicking. This is an active-
low signal and can be used to inform the modem that the computer is alive
and kicking. This is an output pin from DTE (PC COM port) and an input to
the modem.

2. DSR (Data Set Ready):

When DCE (modem) is turned on and has gone through the self-test,
it asserts DSR to indicate that it is ready to communicate. Thus, it is an
output to the pc (DTE). This is an active low signal. If for any reason the
modem cannot make connection to the telephone, this signal remains
inactive, indicating to the PC (or terminal) that it cannot accept or send data.

3. RTS (Request To Send.):

When the DTE device (such as a PC) has a byte to transmit, it asserts
TRS to signal the modem that it has a byte of data to transmit. RTS is an
active low output from the DTE and an input to the modem.

4.CTS (Clear To Send):

In response to RTS, when the modem has room for storing the data it
is to receive, it sends out signal CTS to the DTE (PC) to indicate that it can
receive the data now. This input signal to the DTE is used by the DTE to
start transmission.
5.DCD (Carrier Detect, or DCD, Data Carrier Detect):

The modem asserts signal DCD to inform the DTE (PC) that a valid
carrier has been detected and that contact between it and the other modem is
established. Therefore, DCD is an output from the modem and an input to
the PC (DTE).

6. RI (ring indicator):

An output from the modem (DCE) and an input to a PC (DTE)

indicates that the telephone is ringing. It goes on and off in synchronization
with the ringing sound. Of the 6 handshake signals, this is the least often
used, due to the fact that modems take care of answering the phone.
However, if in a given system the PC is in charge of answering the phone,
this signal can be used.

From the above description, PC and modem communication can be

summarized as follo0ws: While signals DTR and DSR are used by the PC
and modem. Respectively, to indicate that they are alive and well, it is RTS
and CTS that actually control the flow of data. When the PC wants to send
data it asserts RTS, and in response, if the modem is ready (has room) to
accept the data, it sends back CTS. If, for lack of room, the modem does not
activate CTS, the PC will desserts DTR and try again. RTS and CTS are
also referred to as hardware control flow signals.

DISPLAY LED DETAILS

 On this page we will find a scrolling LED sign based on the AT89c52
microcontroller, which we can build ourself (when finished) Other names for this device
can be: Moving message sign, Message crawler, Scrolling message, message display, etc.
The idea is to let a text scroll over the LED dot-matrix displays. A dot-matrix
display is a display which contains 5x7 dots (LEDs) in one case, the LEDs are connected
like a matrix, there are two types CC and CA, the LEDs are simply put the other way
around, here the drawings (inside and front):
 If we put 1.8 Volt e.g. at the lines 4 and 10, that LED (dot) will lit, the trick of
multiplexing is to scan the columns (5) and set the data on the rows (7) (or visa-versa),
the multiplex-frequency must be greater than approx. 40Hz else we will see the flickering
of the LEDs to much (take about 5 msec per column, thats about 25 msec for one frame)

The scanning goes as follows, first set the rows data on the 7 rows e.g. 1010010,
then activate (0 or 1 -> depends on which type CA = common cathode, or CC = common
anode) the first column, now these LEDs (dots) will lit, wait 5 msec, then switch the
column off, now load the next rows data, and set the second column on, wait 5 msecs
again, and switch it off again, if we repeat this sequence very fast, we will see the data
(character data) appear on the display (refresh frequency 40 - 70Hz is ok, don't take twice
or half the artificial light-frequency of 50/60 Hz)

The rows data comes e.g. from the EEPROM or flash memory of the Atmel 89c52, we
can also take an external EEPROM/flash IC, the ATtiny2313 has 128 bytes EEPROM
and 2k of flash memory, what we can do is put the character data (ASCII) into the flash
memory (read below for more details) Next the test-diagram:
 The 74HC595 is an 8-bit shift-register IC, with this IC we can shift 8 bits to the
outputs with only 3 wires, that are Data (Ds), and 2 shift inputs (SHcp, STcp), connect
like the diagram. How does the 74HC595 works? First shift the 8 bits into the stages with
SHcp, then shift the stages to the outputs with STcp, this causes the outputs to switch in
one go, with e.g. a 74HCT164 we can only shift the bits into the outputs, the advantage of
the 74HC595 is the storage register. Don't forget that multiplexing causes the LEDs only
lit up for a fraction, so if we want the same intensity we must put more current through
them, this diagram is for practice and programming, wants we have it working we can put
transistors and resistors on. Here we put the letter R on the display as we can see, using a
little breadboard:

How to scroll a character across the display? The trick is to build one character on
the display by scanning the columns very fast, and let say each 20 times (20 frames)
scroll it one position to the left, this will give the effect of a walking text accross the dot-
matrix display. So first build one frame, repeat this 20 times, and after that, read the data
one address later, if we do this 5 times (5 columns) the character scroll from right to left
from the display. (the refresh goes so fast that wer brain can't keep up, and what we see is
the R scrolling over the display) Btw, we will take five 74HC595's shiftregisters IC's, that
are 5 x 8 bit = 40 bits / 5 columns = 8 dot-matrix displays, making it a nice tiny message
sign.
 What we are going to do is putting ASCII data (thats 128 x 5 bytes = 640 bytes)
into the 2k flash memory of the ATMEL 89c52, then we have 704 words left for my
program, that can really be a huge program!, because we used only 69 lines (69
instructions) of program so far, and that scrolls characters fluently accross the dot-matrix
display. we made the program so that we can set the scroll-speed, from 0 - 255, so 256
speeds, 25 fps (frames/second) is a nice speed. On one of our pages (this page) we are
using a 2-bit Gray code rotary encoder, with this encoder we will make an edit function
in the software, so we can edit messages, without a keyboard, this save space, this type of
rotary encoder has a push-function in the shaft, so e.g. after we select a character we can
store that in memory.