Beruflich Dokumente
Kultur Dokumente
Cable Broadband
Controller Data Manual
Version 1.2
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Table of Contents
Chapter 1: Introduction.........................................................................................................1-1
1.1 Features ......................................................................................................................................................1-1
List of Figures
Figure 2-1. TNETC4401 Functional Block Diagram ......................................................................................................2-2
Figure 4-1. 4Kc Core Block Diagram ...............................................................................................................................4-2
Figure 4-2. 4Kc Core Pipeline...........................................................................................................................................4-3
Figure 4-3. Minimum Timing Requirements for External Interrupts ............................................................................4-5
Figure 5-1. Clock Management Module ..........................................................................................................................5-1
Figure 10-1. Crystal Oscillator ..........................................................................................................................................10-1
Figure 10-2. DAC Output Circuits.....................................................................................................................................10-3
Figure 10-3. ADC Circuits..................................................................................................................................................10-4
Figure 10-4. AGC Control Line Filtration Stage .............................................................................................................10-5
Figure 11-1. JTAG TEST ...................................................................................................................................................11-1
Figure 11-2. EJTAG Test...................................................................................................................................................11-2
Figure 11-3. MII_RX Port...................................................................................................................................................11-3
Figure 11-4. MII_TX Port ...................................................................................................................................................11-4
Figure 11-5. MII_DIO Data Input Port..............................................................................................................................11-4
Figure 11-6. MII_DIO Data Output Port...........................................................................................................................11-5
Figure 11-7. USB I/O Timing Requirements ...................................................................................................................11-5
Figure 11-8. USB I/O..........................................................................................................................................................11-6
Figure 11-9. IIC_SCL and IIC_SDA .................................................................................................................................11-7
Figure 11-10. Acknowledge ............................................................................................................................................11-7
Figure 11-11. Start and Stop Condition ........................................................................................................................11-8
Figure 11-12. VLYNQ Timing .........................................................................................................................................11-8
Figure 11-13. Synchronous DRAM Read .....................................................................................................................11-9
Figure 11-14. Synchronous DRAM Write ...................................................................................................................11-10
Figure 11-15. Asynchronous Memory Read (No Wait).............................................................................................11-11
Figure 11-16. Asynchronous Memory Read (Wait)...................................................................................................11-12
Figure 11-17. Asynchronous Memory Write (No Wait) .............................................................................................11-13
Figure 11-18. Asynchronous Memory Write (Wait) ...................................................................................................11-14
Figure 12-1. Tester-Pin Electronics..................................................................................................................................12-1
Figure 12-2. Input and Output Voltage Reference Levels for Timing Measurements ..............................................12-1
Figure 13-1. Mechanical Package Diagram....................................................................................................................13-1
List of Tables
Table 3-1. Memory Map................................................................................................................................................... 3-1
Table 7-1. Boot-Mode Settings ....................................................................................................................................... 7-2
Table 8-1. Terminal Descriptions by Interface.............................................................................................................. 8-1
Table 8-2. Pinout by Terminal Number ......................................................................................................................... 8-7
Table 9-1. TNETC4401 Absolute Maximum Ratings over Operating Case Temperature Range
†
(unless otherwise noted) ............................................................................................................................. 9-1
Table 9-2. Recommended Operating Conditions ........................................................................................................ 9-2
Table 9-3. Electrical Characteristics over Recommended Range of Supply Voltage and Operating
Case Temperature Range for USB Terminals USBDM and USBDP (unless otherwise
noted)............................................................................................................................................................... 9-2
Table 9-4. Electrical Characteristics over Recommended Range of Supply Voltage and Operating
Case Temperature (unless otherwise noted) ............................................................................................ 9-2
Table 9-5. Crystal Electrical Characteristics over Recommended Operating Conditions...................................... 9-2
Table 9-6. US DOCSIS Settings .................................................................................................................................... 9-3
Table 9-7. DAC Specifications, with US DOCSIS Configuration ............................................................................... 9-3
Table 9-8. ADC Specifications, with US DOCSIS Configuration ............................................................................... 9-4
Table 9-9. EuroDOCSIS Settings................................................................................................................................... 9-4
Table 9-10. DAC Specifications, with EuroDOCSIS Configuration ............................................................................. 9-5
Table 9-11. ADC Specifications, with EuroDOCSIS Configuration ............................................................................. 9-5
Table 10-1. Matching Values from US DAC, per Application..................................................................................... 10-3
Table 10-2. Matching Values to D/S ADC, per Application ........................................................................................ 10-4
Table 11-1. JTAG Test..................................................................................................................................................... 11-1
Table 11-2. JTAG Test..................................................................................................................................................... 11-1
Table 11-3. EJTAG Timing Requirements .................................................................................................................... 11-2
Table 11-4. EJTAG Test – Switching Characteristics over Recommended Operating Conditions ...................... 11-2
Table 11-5. RX Timing Requirements ........................................................................................................................... 11-3
Table 11-6. TX Timing Requirements............................................................................................................................ 11-4
Table 11-7. TX Port – Switching Characteristics over Recommended Operating Conditions .............................. 11-4
Table 11-8. MII_DIO Data Input Port ............................................................................................................................. 11-4
Table 11-9. MII_DIO Data Output Port .......................................................................................................................... 11-5
Table 11-10. USB I/O Timing Requirements .................................................................................................................. 11-5
Table 11-11. USB I/O – Switching Characteristics over Recommended Operating Free-Air
Temperature Range (Full Speed).............................................................................................................. 11-6
2
Table 11-12. I C Master – Switching Characteristics over Recommended Operating Conditions ......................... 11-7
Table 11-13. VLYNQ Timing Parameters........................................................................................................................ 11-8
Table 11-14. Synchronous DRAM Read – Switching Characteristics over Recommended Operating
Conditions ..................................................................................................................................................... 11-9
Table 11-15. Synchronous DRAM Write – Switching Characteristics over Recommended Operating
Conditions ................................................................................................................................................... 11-10
Table 11-16. Asynchronous Memory Read (No Wait)................................................................................................. 11-11
Table 11-17. Asynchronous Memory Read (Wait)....................................................................................................... 11-12
Table 11-18. Asynchronous Memory Write (No Wait) ................................................................................................. 11-13
Table 11-19. Asynchronous Memory Write (Wait) ....................................................................................................... 11-14
Revision History
The following major changes were made from Revision 1.1:
Section Description
Chapter 7, Boot option pins require pull-up/down resistors of 4.7 KΩ when
Initialization, DEFAULT mode is not selected.
Section 7.2
Chapter 9, The specification data were updated.
Electrical
Specifications
Sections 9.1 and
9.2
Chapter 10, The RSTEXT resistor value was changed from 20 KΩ to 19.1 KΩ.
System Design
Considerations,
Section 10.3.3
Chapter 11, The timing specifications were updated.
Switching
Characteristics
Introduction
1.1 Features
Description
The TNETC4401 is a system-on-a-chip, which consists of a Million-Instruction-Per-Second (MIPS) processor and
peripherals designed to serve as a broadband network controller for residential and small-office applications. The
TNETC4401 is the DOCSIS 2.0 enhancement of the TNETC4400, and is based on the TNETC4305 broadband
communications processor and the TNETC4042A integrated cable modem, which enables cable broadband
home access along with various interfaces for making local connections, such as Ethernet, WLAN and USB.
SDRAM
FLASH , SRAM
DMA
Icache Dcache 125Mhz -
8KB 4KB DMA 62.5Mhz
ROM RAM Engine Bridge
10/100Base-T
Ethernet MAC
MIPS JADE MII
RISC Proccesor
125Mhz
JTAG
Test & Configuration
Flexible
DES Full-Speed USB
Function
Timer
Timer
VBUS 62.5Mhz
+ PLLs WDT GPIOs
Interrupt
Controller I2C
UART
UART
PCM Clock
DOCSIS 2.0 PHY
A-TDMA DOCSIS 2.0 MAC DMA
S-CDMA
Memory Map
The following table defines the memory map for the TNETC4401. All addresses are physical addresses.
Functional Overview
This chapter provides a high-level overview of each module in the TNETC4401 design. Detailed descriptions of
each module can be found in the TNETC4400/4401 User’s Guide and TNETC4401 DOCSIS Cable Modem Block
User's Guide.
The RISC includes a 16KB four-way set-associative instruction cache and a 16KB four-way set-associative data
cache. On a cache miss, loads are blocked only until the first critical word becomes available. The pipeline
resumes execution while the remaining words are being written to the cache. Both caches are virtually indexed
and physically tagged. Virtual indexing allows the cache to be indexed in the same clock that the address is
translated.
An Enhanced JTAG (EJTAG) block allows for single-stepping of the processor, as well as instruction and data
virtual-address breakpoints.
Processor Core
Bus-Interface Unit
Interface
Memory-
Execution On-Chip
Thin
Management Cache Control
Core Unit Bus(es)
System Transition
Coprocessor Lookaside Data Cache Power
Control Buffer Management
Figure 4-2 shows the timing diagram of the 4Kc core pipeline.
Stage I E M A W
Bytes
Bytes
I-Cache RegRd ALU Op
I TLB I Dec DAC D-Cache Align RegW
I-A1 I-A2
Bypass
RegW
Bypass
RegW
RegW
Multiply - 16 × 16, 32 × 16
The 4Kc core supports three modes of operation: user mode, kernel mode, and debug mode. User mode is most
often used for applications programs. Kernel mode typically is used for handling exceptions and operating-system
kernel functions, including processor management and I/O device accesses. An additional debug mode is used
during system startup and software development.
The following table describes the assignment of chip selects to different types of memories:
The following parameters can be configured by software for each asynchronous memory:
•= Access waveform timings (wait states etc.)
•= Memory width (8, 16 for ASYNC memories and 16-bit for SDRAM)
The memory controller is limited to support only 16-bit data width for SDRAM and 8-/16-bit widths for
asynchronous memories. It is designed to run at either half the speed of the processor, or at the same speed as
the processor. The rate is selected at boot time via the EA12 address pin.
Note:
The memory controller does not support burst accesses across chip select boundaries.
Application programs must comprehend this and must set the memory buffers' (e.g.
buffers for the DMAs) range within a memory range controlled by a single chip select.
The TNETC4401 supports four external interrupts. These external interrupts go through two-stage synchronizers.
The external interrupts are programmable to be level sensitive or edge triggered. The polarity also is
programmable (i.e., high or low in case of level sensitive and positive edge or negative edge triggered in case of
edge triggered).
The logical OR of these 40 primary interrupts is connected to the interrupt0 of the CPU. In addition, the internal
CPU timer_out signal is connected back as interrupt5 to the CPU.
A B
A A
Rising Edge
In case of a pulsed-type interrupt (rising/falling edge), the INTH receives only one interrupt for each transition.
The interrupt signal must return to the inactive state before additional interrupts can be generated. In the case of
level-sensitive interrupt, the device receives interrupts continuously as long as the interrupt signal is in the active
state (low for active low and high for active high).
The secondary interrupts/exceptions can be managed similar to primary interrupts, using the registers dedicated
for secondary interrupts/exceptions.
The first timer (TIMER0) is configured for use as a watchdog. The two other timers (TIMER1 and TIMER2) are
configured for general-purpose use.
Data movement from the 2Kbyte buffer can be done via built-in DMA or through programmed I/O.
The following endpoints are supported:
•= BULK OUT endpoint for host write to V-bus address space
•= BULK IN endpoint for host read of V-bus address space
•= BULK OUT endpoint for raw data movement to V-bus space
•= BULK IN endpoint for raw data movement from V-bus space
•= BULK OUT endpoint for continuous write to V-bus address space
•= INT IN endpoint for host interrupts
The VLYNQ interface can use either an internal or an external clock source. For details, see the
TNETC4400/4401 User's Guide.
1
Texas Instruments Literature Number SPRU571, September 2002
1) To access the processor on-chip emulator (EJTAG port) with a pseudo-IEEE JTAG protocol for emulation
purposes.
Or,
2) To dialog with an embedded TAP controller whose instructions set supports all the IEEE 1149 BSCAN
modes, the programming of the chip I/O configuration (PMT modes, full-scan modes, BIST modes,
functional 1 or 2 modes), and the selection of the boundary-scan chain for FLASH EPROM programming.
Clock Management
The clock management module is shown in Figure 5-1.
VLYNQ clock
VLYNQ
latched at reset
POST
PRE PLL DIV
DIV x1 - x15 by 2 USB PLLs
POST
USB_CLK
PRE PLL DIV
USB clock
latched at reset DIV x1 - x15 by 2 48 MHz
XOSC
Ethernet clock
25 MHz
25 MHz
MAC clock
US clock
CPU clock
clock_x6x7
clock x6x7
PCM Clock
10.24 DIV
NCO by 1 to 2^14
Power Management
The TNETC4401 supports three global power-down modes, as well as peripheral local power-down modes. The
supported global power-down modes are Idle, Stand-By, and Halt modes.
In addition, the system clock frequency can be lowered by setting the clock divider to a value greater than one (up
to 16 times slower).
Note:
The power-down signals are synchronized to the internal VBUS/MIPS clocks. Hence it is
safer to switch the clock source to the internal clock (for the modules which support
external clock sources) and drive them into low-power mode.
Initialization
Watchdog reset is asserted whenever the programmable timer times out. A Watchdog reset resets all the internal
peripherals, including the MIPS core.
After reset, the MIPS program counter points to address 1FC0:0000, which is mapped to the internal ROM. The
ROM code should jump to the proper boot location to execute the boot sequence with the internal ROM,
depending on the BOOTS (boot select) setting latched at reset in the BOOT MODE Register.
Note:
Only the BOOTS register is implemented in the hardware to latch the value on the pins at
the rising edge of RESET_N. It is the ROM code's responsibility to implement the boot
from different locations, based on this register value.
In addition to the above global resets, the TNETC4401 supports a programmable reset bit for each peripheral. On
power-up, these bits are held in the reset state, so that all the peripherals are held in the reset state (except the
MIPS core, system infrastructure logic and memory interface module). The MIPS core, system infrastructure logic
and the memory controller logic can be reset via a pulsed reset (64 clock cycles) by writing 1 to the Software
Reset Control register bit 0. The Software Reset Control register bit 1 can be set to issue a reset to the MIPS core
and system infrastructure logic without resetting the external memory controller.
EuroDOCSIS
Description US DOCSIS
External Pin Function Default:
Default:
Manual Settings: EM_A[6]=0, EM_A[19]=0 EM_A[6] = 1 EM_A[6] = 0,
EM_A[19] = 1
System PLL input clock select:
0 – The input clock to the System PLL is driven by the
EM_A[9] SYSPLSEL USBCLKI oscillator input. 1 0
1 – The input clock to the System PLL is driven by the
XTAL_IN oscillator input.
USB PLL1 input clock select:
0 – The input clock to the USB PLL is driven by the
EM_A[8] USBPLSEL USBCLKI oscillator input. 1 0
1 – The input clock to the USB PLL is driven by the
XTAL_IN oscillator input.
Ethernet clock select:
0 – The Ethernet clock is driven by the USBCLKI oscillator
EM_A[7] ETHCLKSEL input. 1 0
1 – The Ethernet clock is driven by the XTAL_IN oscillator
input.
0 – Check EM_A[19] to determine whether to use the
EM_A[6] DEFAULT internal predefined EuroDOCSIS default values - -
1 – Use the internal predefined US DOCSIS default values
Power down non-DOCSIS PLLs:
EM_A[5] AV_NOPLL 0 – VCO is turned off. 1 1
1 – VCO is on.
Sampled only when EM_A[15] is 1:
USB0_PLL_BY
EM_A[3] 0 – Don’t bypass USB_PLL_0 0 0
PASS
1 – Bypass USB_PLL_0
Sampled only when EM_A[15] is 1:
USB1_PLL_BY
EM_A[1] 0 – Don’t bypass USB_PLL_1 0 0
PASS
1 – Bypass USB_PLL_1
Terminal Descriptions
Terminal Description
Name Direction No.
DEDICATED GPIOS (sixteen signals)
GPIO6 IN/OUT 40 GPIO6
GPIO7 IN/OUT 33 GPIO7
GPIO8 IN/OUT 34 GPIO8
GPIO9 IN/OUT 36 GPIO9
GPIO10 IN/OUT 39 GPIO10
GPIO11 IN/OUT 29 GPIO11
GPIO12 IN/OUT 30 GPIO12
GPIO13 IN/OUT 31 GPIO13
GPIO14 IN/OUT 32 GPIO14
GPIO20 IN/OUT 42 GPIO20
GPIO21 IN/OUT 43 GPIO21
GPIO22 IN/OUT 44 GPIO22
GPIO23 IN/OUT 45 GPIO23.
GPIO24 IN/OUT 46 GPIO24
GPIO25 IN/OUT 47 GPIO25
GPIO27 IN/OUT 48 GPIO27
2
I C (two signals)
IIC_SCL/GPIO5 IN/OUT 49 Serial clock link/GPIO5. ( ↑ ) An external 4.7 KΩ pull-up is needed.
IIC_SDA/GPIO4 IN/OUT 50 Serial clock link/GPIO4. ( ↑ ) An external 4.7 KΩ pull-up is needed.
MII INTERFACE (19 signals)
MII_COL IN 138 MII collision
MII_CRS IN 142 MII carrier sense
MII_TCLK IN 143 MII transmit data clock
MII_RCLK IN 144 MII receive data clock
MII_RD0 IN 148 MII receive data [0]
MII_RD1 IN 147 MII receive data [1]
MII_RD2 IN 146 MII receive data [2]
MII_RD3 IN 145 MII receive data [3]
MII_RDV IN 149 MII receive data valid
MII_RER IN 150 MII receive data error
MII_TEN OUT 154 MII transmit data enable
MII_TD0 OUT 158 MII transmit data [0]
MII_TD1 OUT 157 MII transmit data [1]
MII_TD2 OUT 156 MII transmit data [2]
MII_TD3 OUT 155 MII transmit data [3]
MII_LINK IN 162 MII PHY link status
MII_DIO IN/OUT 163 MI serial-port data
MII_DIOCLK OUT 164 MI serial-port clock
MII_PHYCLK OUT 165 Eth PHY clock source (25 MHz)
Terminal Description
Name Direction No.
USB INTERFACE (six signals)
USB XTAL GND 131 Should NOT connect to board GND; instead, connect to USB XTAL capacitors.
USBCLKI IN 133 USB XTAL In
USBCLKO OUT 134 USB XTAL Out
USB_PULLE OUT 135 Pull-up enable
USB_DN IN/OUT 136 Slave differential –
USB_DP IN/OUT 137 Slave differential +
VLYNQ INTERFACE (five signals)
VLYNQ_CLK IN/OUT 125 VLYNQ clock ( ↑ )
VLYNQ_TXD0 OUT 126 VLYNQ transmit data [0]
VLYNQ_TXD1 OUT 129 VLYNQ transmit data [1]
VLYNQ_RXD0 IN 127 VLYNQ receive data [0]
VLYNQ_RXD1/GPIO26 IN/OUT 128 VLYNQ receive data [1]/GPIO26
EXTERNAL MEMORY INTERFACE (54 signals)
EM_CS0_n OUT 57 Chip select (Flash)
EM_CS1_n OUT 116 Chip select (SDRAM)
EM_CS3_n OUT 56 Chip select (asynchronous memory)
EM_CS4_n OUT 55 Chip select (asynchronous memory)
SDRAM_WE_n OUT 121 SDRAM write enable
SDRAM_RAS_n OUT 122 SDRAM RAS
SDRAM_CAS_n OUT 123 SDRAM CAS
EM_WE_SDQM0 OUT 99 Write strobe and data mask for SDRAM
EM_WE_SDQM1 OUT 95 Write strobes and data mask for SDRAM
EM_OE_n OUT 54 Output enable
EM_WAIT_n IN 59 Wait-state extend signal
EM_RNW OUT 60 Read/write signal used in HPI interface
EM_SDCKE1 OUT 119 SDRAM clock enable1
EM_SDCLK OUT 120 SDRAM clock signal
Terminal Description
Name Direction No.
EM_A23 OUT 61 Address bus [23] Notes:
EM_A22 OUT 62 Address bus [22] EM_A[23:5,3,1] values from external pull-ups/downs are
latched when RESET_N goes high.
EM_A21 OUT 63 Address bus [21]
Note that although these pins have internal pull-ups/downs,
EM_A20 OUT 64 Address bus [20] they must be connected to external pull-ups/downs of 4.7 KΩ
EM_A19 OUT 65 Address bus [19] when defining the required boot-mode as anything other than
Default.
EM_A18 OUT 66 Address bus [18]
For more details, refer to section 7.2 in this manual and
EM_A17 OUT 67 Address bus [17] section 1.5 in the TNETC4400/4401 User’s Guide.
EM_A16 OUT 70 Address bus [16]
EM_A15 OUT 71 Address bus [15]
EM_A14 OUT 73 Address bus [14]
EM_A13 OUT 74 Address bus [13]
EM_A12 OUT 100 Address bus [12]
EM_A11 OUT 101 Address bus [11]
EM_A10 OUT 102 Address bus [10]
EM_A9 OUT 103 Address bus [9]
EM_A8 OUT 107 Address bus [8]
EM_A7 OUT 108 Address bus [7]
EM_A6 OUT 109 Address bus [6]
EM_A5 OUT 110 Address bus [5]
EM_A4 OUT 111 Address bus [4]
EM_A3 OUT 112 Address bus [3]
EM_A2 OUT 113 Address bus [2]
EM_A1 OUT 114 Address bus [1]
EM_A0 OUT 115 Address bus [0]
EM_D15 IN/OUT 75 Data bus [15]
EM_D14 IN/OUT 76 Data bus [14]
EM_D13 IN/OUT 77 Data bus [13]
EM_D12 IN/OUT 78 Data bus [12]
EM_D11 IN/OUT 79 Data bus [11]
EM_D10 IN/OUT 80 Data bus [10]
EM_D9 IN/OUT 81 Data bus [9]
EM_D8 IN/OUT 82 Data bus [8]
EM_D7 IN/OUT 86 Data bus [7]
EM_D6 IN/OUT 87 Data bus [6]
EM_D5 IN/OUT 88 Data bus [5]
EM_D4 IN/OUT 89 Data bus [4]
EM_D3 IN/OUT 91 Data bus [3]
EM_D2 IN/OUT 92 Data bus [2]
EM_D1 IN/OUT 93 Data bus [1]
EM_D0 OUT 94 Data bus [0]
Terminal Description
Name Direction No.
DOCSIS INTERFACE (16 signals)
AINP A 2 ADC analog input
AINM A 3 ADC analog input
BGPAD A 9 Test terminal to force band gap to 1.0 V
RSTEXT A 10 Reference resistor for band gap bias current setting
XTAL_OUT A 16 XTAL oscillator connection
XTAL_IN A 18 XTAL oscillator connection
AMPC OUT 173 Upstream amplifier clock
AMPD OUT 174 Upstream amplifier data
AMPE_n OUT 176 Upstream amplifier enable
AMPPD_n OUT 177 Upstream amplifier power-down control
TAGCS OUT 191 Automatic gain control (RF AGC)
AGCS OUT 192 Automatic gain control
ION A 197 DAC current output
IOP A 198 DAC current output
REFP A 204 ADC reference 2 V
REFM A 205 ADC reference 1 V
(E)JTAG PORT (eight signals)
EJTAG_TDI IN 167 Test data input ( ↓=)
EJTAG_TDO OUT 168 Test data output
EJTAG_TMS IN 169 Test mode select ( ↑ )
EJTAG_TCK IN 172 Test clock ( ↓ )
EJTAG_TRST0_n IN 178 Test reset (MIPS JTAG) ( ↓ )
EJTAG_TRST1_n IN 179 Test reset (Chip JTAG) ( ↓ )
EJTAG_DINT IN 180 Debug exception request ( ↓ )
EJTAG_SYS_RESET IN 181 JTAG reset ( ↑ )
MISCELLANEOUS (five signals)
TEST IN 189 Test mode terminal, used to latch test modes from functional terminals (↓ )
RST_n IN 190 Chip power-on reset
EM_HIZ IN 124 EMIF terminals 3-state control ( ↓ )
VPP 186 Should be tied to VDD
FOUT_PLL A 13 PLL clock output for test
Terminal Description
Name Direction No.
POWER & GROUND (17 signals)
VDD D Power 21, 37, 52, 68, 84, 97, Core digital 1.5-V supply
104, 117, 130, 140,
152, 160, 170
GND D Power 19, 22, 38, 53, 69, 85, Core digital GND
98, 105, 118, 141,
153, 161, 171, 182
VDDSHV D Power 35, 51, 58, 72, 83, 96, I/O digital 3.3-V supply
106, 132, 139, 151,
159, 166, 175, 187
DAC AVDD A Power 195, 200 DAC analog 3.3-V supply
DAC AGND A Power 196, 199 DAC analog GND
DAC DVDD D Power 194 DAC digital 1.5-V supply
DAC DGND D Power 193 DAC digital GND
ADC AVDD A Power 203, 206, 207, 4 ADC analog 3.3-V supply
ADC AGND A Power 201, 202, 208, 1 ADC analog GND
BG AVDD A Power 7 Band gap analog 3.3-V supply (can be tied with ADC AVDD)
BG AGND A Power 8 Band gap analog GND (can be tied with ADC AGND)
PLL AVDD A Power 11 PLL analog 3.3-V supply
PLL AGND A Power 12,14 PLL analog GND
PLL VDD D Power 5 PLL digital 1.5-V supply
PLL GND D Power 6 PLL digital GND
XTAL VDD D Power 17 XTAL digital 1.5-V supply
XTAL GND D Power 15 XTAL digital GND. Should NOT connect to board GND; instead,
connected to XTAL capacitors. Refer to section 10.1.
LEGEND: (_n) – active low ( ↑ ) – pull-up ( ↓ ) – pull-down
Electrical Specifications
Table 9-1. TNETC4401 Absolute Maximum Ratings over Operating Case Temperature Range (unless otherwise
†
noted)
Supply voltage range: CVDD (CORE) ‡ -0.5 V to 1.836 V
Supply voltage range: DVDD (I/O) -0.5 V to 4 V
Input-voltage range, VI -0.5 V to 4 V
Output-voltage range, VO -0.5 V to 4.5 V
Ambient temperature range (case temperature should not fall below 0°C or exceed 80°C) 0°C to 70°C
Junction-to-ambient thermal resistance, RθJA: 0-LFPM airflow, PYP package 15°C/W
Junction-to-ambient thermal resistance, RθJA: 250-LFPM airflow, PYP package 10°C/W
Junction-to-case thermal resistance, RθJC: PYP package 5°C/W
Storage temperature range, Tstg -55°C to 150°C
CDM 500 V
HBM 2000 V
† Stresses beyond those listed in Table 9-1 may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ Voltage values are with respect to ground terminals.
Table 9-3. Electrical Characteristics over Recommended Range of Supply Voltage and Operating Case
Temperature Range for USB Terminals USBDM and USBDP (unless otherwise noted)
Parameter Test Conditions Min. Typ. Max. Unit
VDI Differential input sensitivity |DP-DM| ±0.2 V
VCM Differential common-mode range Included VDI range 0.8 2.5 V
VIL Low-level input voltage 0.8 V
VIH High-level input voltage 2 V
VOL Low-level static output voltage RL of 1.5 kΩ to 3.6 V 0.3 V
VOH High-level static output voltage RL of 1.5 kΩ to GND 2.8 3.6 V
ILO High-impedance state data-line leakage current ±10 nA
CIN Transceiver capacitance 20 pF
RO(DRV) Driver output resistance 14 Ω=
Table 9-4. Electrical Characteristics over Recommended Range of Supply Voltage and Operating Case
Temperature (unless otherwise noted)
Parameter Test Conditions Min. Typ. Max. Unit
II Input current† VI = VSS to DVDD ±20 µA
IOZ Off-state output current VO = DVDD or 0 V ±20 µA
ICVDD Core and AFE supply current CVDD = Max., RISC bus = 125 MHz, 260 mA
Peripherals bus = 62.5 MHz
with activity on all I/O terminals
IDVDD I/O supply current (including ADC, CVDD = Max., RISC bus = 125 MHz, 87 mA
PLL, DAC and Bandgap) Peripherals bus = 62.5 MHz
with activity on all I/O terminals
Ci Input capacitance 10 pF
Co Output capacitance 10 pF
†
SNDR measured when transmitting a 160ksps QPSK modulated signal with even power function enabled, in a 160kHz measurement
interval.
2
Guaranteed by design
3
This parameter includes the DAC sinc response for the typical sample rate (without Anti-sinc).
4
SNDR measured when transmitting a 160ksps QPSK modulated signal with even power function enabled, in a 160kHz measurement
interval.
5
Guaranteed by design
Notes:
Terminal 15 MUST NOT BE connected on board to GND. It must be connected ONLY to
caps C1 and C2.
C1 = C2 = 20pF, total capacitance, including PCB parasitic capacitance.
Rd = 0 Ω
Rbias = 1 MΩ
Terminal 17 should be connected to the device digital core VDD. When using external
clock, it can connect directly to XTAL_IN (terminal 18). In that case, terminal 15 should
remain floating, C1 and C2 are not needed. The external clock should not exceed 1.5 V.
TNETC4401
15, VSS
C2 Rd
16, XO
XTAL Rbias
25/ 28.9 17, VDD
C1
18, XI
10.3 Analog
10.3.1 DAC
The DAC connections need impedance matching for optimum performance. The DAC output impedance is
optimized for a 50-Ω=termination between each output and ground. Also, each output must have a ground path.
This configuration results in a voltage swing of 0V to 0.5V in each output, according to the typical output current.
Tx_IN 198
IOP
The effective impedance from each DAC output to ground is given by (R || Z/2), which should be equal to 50 Ω.
The value of R determines the DC level of the output signal. Recommended levels are between 0.25 VDC to 0.5
VDC at each output terminal.
10.3.2 ADC
10.3.2.1 General
The ADC has been designed for AC coupled input. The connections to the ADC require two 220-nF capacitors for
AC coupling. The 200-Ω resistor is for impedance matching with the tuner.
TNETC4401
220nF
IFOUT+ 2
AINP
R
Tuner
220nF
IFOUT- 3 AINM
From TNETC4401
AGC control pins To RF/IF gain
10kohm
control stages
10 nF
For more information regarding the AGC configuration, please refer to Chapter 4 in the TNETC4401 DOCSIS
Cable Modem Block User’s Guide.
10. If the power plane exists above critical sensitive lines (for example, upstream or downstream signals), an
additional capacitance between it and the GND plane (small capacitance pF-nF) can be added around these
lines to filter noise currents that flow in their environment. An area of thermal land is required underneath the
body of the PowerPAD package. The thermal land should be as large as possible (maximum package body
size, minus 2.0 mm). A solder mask area at the center of the thermal land should be available for soldering
the package thermal pad. For heat transfers from thermal land to internal and external copper planes, apply
thermal vias (13 mil diameter and 65 mil pitch). It is highly recommended that an internal ground plane be
used for heat removal.
For more details regarding the PCB design guidelines, refer to the PowerPAD Thermally Enhanced Package
document.
Switching Characteristics
4 5
1
EJTAG_TCK
(input)
6 6
EJTAG_TDO
(output)
3
EJTAG_TDI/TMS/TRST_n 2
(inputs)
Table 11-4. EJTAG Test – Switching Characteristics over Recommended Operating Conditions
No. Min. Max. Unit
6 td1 Delay time from EJTAG_TCK↓ to EJTAG_TDO valid 0 15 ns
1
2 3
EJTAG_TCK
(input)
EJTAG_TMS
EJTAG_TDI
EJTAG_TRST
(inputs)
4 5
EJTAG_TDO Z
(output)
6
1
2 3 7
EJTAG_TCK
( input)
7
EJTAG_TMS
EJTAG_TDI
(inputs)
5 6 10 7
EJTAG_TDO Z
(output)
7 8 9
EJTAG_TRST0_n
4
EJTAG_TRST1_n
(input)
Note:
Both MII_CRS and MII_COL are driven asynchronously by the PHY.
MII_RXD3-MII_RXD0 is driven by the PHY on the falling edge of MII_RCLK.
MII_RXD3-MII_RXD0 timing must be met during clock periods when MII_RXDV is
asserted. MII_RXDV is asserted and de-asserted by the PHY on the falling edge of
MII_RCLK. MII_RXER is driven by the PHY on the falling edge of MII_RCLK.
1
4 5
2 3
MII_RCLK
(input)
MII_RXD3-MII_RXD0
MII_RXDV
(inputs)
Note 2:
Both MII_CRS and MII_COL are driven asynchronously by the PHY.
The reconciliation sublayer drives MII_TXD3-MII_TXD0 synchronous to the MII_TCLK.
MII_TXEN is asserted and de-asserted by the reconciliation sublayer synchronous to the
MII_TCLK rising edge.
1
4
2 3
MII_TCLK
(input)
MII_TXD3-MII_TXD0
MII_TXEN
(outputs)
MII_DIOCLK
(outputs)
1 2
MII_DIO
(inputs)
4
MII_DIOCLK
(outputs)
3
MII_DIO
(outputs)
I/O
Table 11-11. USB I/O – Switching Characteristics over Recommended Operating Free-Air Temperature Range
(Full Speed)
No. Parameter Test Conditions Min. Max. Unit
4 tr Rise time, USB_DP/USB_DN Between same two reference points (10% and 90%), 4 20 ns
CL = 50 pF, RL = 1.5 kΩ=
5 tf Fall time, USB_DP/USB_DN Between same two reference points (10% and 90%), 4 20 ns
CL = 50 pF, RL = 1.5 kΩ=
VO(CRS) Voltage output signal crossover 1.3 2 V
4, 5 tr = tf
USB_DN VOH
VO(CRS) 90%
USB_DP 10%
VOL
(I/Os)
Notes:
Exact timing is dependent on the IIC_SCL period (clock cycle time). This value is chosen
by the programmed value in the clock divider register, which is a percentage of the
IIC_CLK period. For more details, see the TNETC4400/4401 User's Guide.
Both IIC_SCL and IIC_SDA are tested under 4.7KΩ pull-up resistors to 3.3 V.
1 2 3 4
IIC_SCL
(output)
5 6
IIC_SDA
(output)
IIC_SCL
(output) 1 2 8 9
IIC_SDA
(output)
IIC_SDA
(input)
IIC_SCL
(output)
8 10
9 7
IIC_SDA
(output)
Start Condition Stop Condition
Notes:
Table 11-13 assumes that the difference in the board delay for VLYNQ_CLK and any
VLYNQ_TXDx pin is less than 0.25 ns (used for the Rx hold time margin). It also
assumes that the total board delay for VLYNQ_CLK plus any VLYNQ_TXDx signal is less
than 1.00 ns (used for maximum VLYNQ_CLK to VLYNQ_TXDx valid delay time).
Maximum pin loading is assumed to be 15 pF.
5 6 4,7 3 2
VLYNQ_CLK
VLYNQ_TXD
VLYNQ_RXD
Table 11-14. Synchronous DRAM Read – Switching Characteristics over Recommended Operating
Conditions
No. Parameter Half Rate Full Rate Unit
Min. Max. Min. Max.
0 tct Cycle time, EM_SDCLK 8 8
1 td1 Delay time, EM_SDCLK↑ to EM_CE3_n-CE0_n/SDRAS_n/SDCAS_n/SDWE_n 5.5 5.5 ns
Valid
2 td2 Delay time, EM_SDCLK↑ to EM_A23- EM_A0 valid 5.5 5.5 ns
3 td3 Delay time, EM_SDCLK↑ to EM_A23- EM_A0 invalid 1 1 ns
4 td4 Delay time, EM_SDCLK↑ to EM_WE_SDQM0,1↓ (mask) 5.5 5.5 ns
5 td5 Setup time, EM_D15-EM_D0 valid to EM_DSCLK↑ 3 2 ns
6 td6 Hold time, EM_SDCLK↑ to EM_D15-EM_D0 invalid 1.5 1.5 ns
1 2 3 4 5 6 7 8 9 10 11 12 13 14
EM_SDCLK
(output)
EM_CE3_n-_CE0_n
- 1
SDRAS_n/
SDCAS_n/ Active NOP* NOP* Read Read NOP* NOP* NOP* Read NOP* NOP* DA*
SDWE_n
(outputs) 2 3
EM_A23-0
- Row A§ B§ C§
(output)
EM_WE_SDQM0-1 4
(output)
5
6
EM_D15-0
- Data Data Data Data Data Data
(input) A B0 B3 C0 C1 C2
CAS Latency = 2
Burst Length = 4
* No operation (NOP)
* Deactivate (DA) can be referred to as precharge.
§ A, B, C = Column A, column B, column C
Table 11-15. Synchronous DRAM Write – Switching Characteristics over Recommended Operating Conditions
No. Parameter Half Rate Full Rate Unit
Min. Max. Min. Max.
0 tct Cycle time, EM_SDCLK 8 8
1 td1 Delay time, EM_SDCLK↑ to EM_CE3_n-CE0_n/SDRAS_n/SDCAS_n/SDWE_n 5.5 5.5 ns
Valid
2 td2 Delay time, EM_SDCLK↑ to EM_A23-EM_A0 valid 5.5 5.5 ns
3 td3 Delay time, EM_SDCLK↑ to EM_A23-EM_A0 invalid 1 1 ns
4 td4 Delay time, EM_SDCLK↑ to EM_WE_SDQM0,1↓ (mask) 5.5 5.5 ns
5 td5 Min Prop time, EM_D15-EM_D0 valid to EM_SDCLK↑ 1 1 ns
6 td6 Max Prop time, EM_SDCLK↑ to EM_D15-EM_D0 invalid 5.5 5.5 ns
1 2 3 4 5 6 7 8 9 10 11 12 13 14
EM_SDCLK
(output)
EM_CE3_n-CE0_n/ 1
SDRAS_n/
SDCAS_n/ Active NOP* NOP* Write Write NOP* NOP* NOP* Write NOP* NOP* DA*
SDWE_n
(outputs)
2 3
EM_A23-0 Row A§ B§ C§
(output)
4
EM_WE_SDQM0-1
-
(output)
5 6
CAS Latency = 2
Burst Length = 4
* No operation NOP)
(
* Deactivate (DA) can be referred to as precharge.
§ A, B, C = Column A, column B, column C.
Setup = 2 Cycles
EM_SDCLK
(output)
1 Strobe = 7 Cycles 2
EM_CE3_n-CE0_n
(output)
3 4
EM_A23-0
-
(output)
8
7
EM_D15-0 High Z
(input)
5 6
EM_OE_n
(output)
High
SDRAM_WE_n
(output)
Not Ready =
Setup = 2 Cycles* Strobe = 5 Cycles* 2 Cycles
EM_SDCLK
(output)
1 2
EM_CE3_n-CE0_n
(output)
3 4
EM_A23-0
(output)
8
7
High Z
EM_D15-0
(input)
SDRAM_WE_n High
(output)
10
9
EM_WAIT_n
(input)
5 6
EM_OE_n
(output)
Setup = 2 Cycles
EM_SDCLK
(output)
1 Strobe = 7 Cycles 2
EM_CE3_n-CE0_n
(output)
3 4
EM_A23-0
(output)
5 6
EM_D15-0
High Z
(output)
EM_OE_n High
(output)
SDRAM_WE_n 7 8
(output)
Not Ready =
Setup = 2 Cycles Strobe = 5 Cycles 2 Cycles
EM_SDCLK
(output)
1 2
EM_CE3_n-CE0_n
(output)
3 4
EM_A23-0
(output)
5 6
EM_D15-0 High Z
(output)
EM_OE_n High
(output)
7 8
SDRAM_WE_n
(output)
10
EM_WAIT_n 9
(input)
Parameter Measurement
Information
IOL
Tester-Pin Electronics
Output
50 Ω= Under
Vref Test
CT† = 60 pF
IOH
†
Typical distributed load circuit capacitance
Vref = 1.5 V
Figure 12-2. Input and Output Voltage Reference Levels for Timing Measurements
Mechanical Data