Embedded Systems

Question Bank
Chapter 3 Devices and Busses for Network Devices

SUDARSHAN
K.

1. Characteristics of synchronous communication are:

a. Bytes maintain a constant phase difference.

b. Bytes need not maintain a constant phase difference.

c. Clock is not always implicit to the synchronous data receiver.

d. Clock is always implicit to the synchronous data receiver.

Options:

1. a and d

2. a and c
3. b and c

4. b and d

Ans: 2.

2. Characteristics of asynchronous communication are:

a. Bytes maintain a constant phase difference.

b. Bytes need not maintain a constant phase difference.

c. Clock is not always implicit to the synchronous data receiver.

d. Clock is always implicit to the synchronous data receiver.

Options:

1. a and d

2. a and c

3. b and c

4. b and d

Ans: 4.

3. In _____________the transmitter does not transmit along with the serial stream
of bits any clock rate information.

Ans: asynchronous communication

4. There are __________methods for encoding the clock information into a serial
stream of bits.

a. 5

b. 10

c. 7

d. 2

Ans: a.

5. PISO stands for_______________.

Ans: Parallel-in serial-out

6. Five methods of encoding clock information are:

a. Frequency modulation

b. Mid frequency modulation

c. Manchester coding

d. Quadrature amplitude modulation

e. Bi-phase coding

f. Manchester decoding

g. Differential coding

Options:

1. a,b,c,d,e

2. a,b,f,d,e

3. g,f,e,b,a

Ans: 1.

7. DTE stands for______________.

a. Data Terminal Equipment.

b. Data Transfer Equipment.

c. Digital Terminal Equipment.

d. Digital Transfer Equipment.

Ans: a.

8. DCE stands for_______________.

 a. Data Communication Equipment.

b. Data Computer Equipment.

c. Data Commanding Equipment.

d. Data Command Exchange.

Ans: a.

9. ________________is an interfacing signal standard between DCE and DTE.

a. RS232C

b. RS233C

c. RS222C

d. RS200C

Ans: a.

10. HDLC is a _____________protocol.

a. Bite oriented

b. Byte oriented

c. Bit oriented

d. Key oriented

Ans: c.

11. In HDLC protocol based network device the address bits for destination
has__________ bits in standard format and _______ bits in extended format.

a. 8 and 16

b. 16 and 32

c. 32 and 64

d. 2 and 2

Ans: a.
12. Match the following:

a. Embedded internet a. Web protocols

applications

b. Embedded system designers b. Bridges and routers

c. ESMTP c. Application protocol

d. ATM,DSL,ADSL d. Network protocol

Options:

1. a,b,c,d

2. a,c,d,b

3. b,d,c,a

4. c,b,a,d

Ans: 1.

13. ________________register is for write operation only.

a. Control

b. Status

c. Indexed

d. Displacement

Ans: a.

14. Status register is for _________operation.

a. Read

b. Write

c. Modify

d. Read and write

Ans: a.

15. Keypad is said to connect and I/O port.

Option: True or False

Ans: true.

16. _____________________is a register buffer that from where an output device

receives the byte after processor write operation.
 a. Input buffer.

b. Output buffer.

c. Parallel port

d. Serial port

Ans:b.

17. Match the following:

a. FSK 1. The 0 and 1 logic states are at

different frequency levels.

b. PSK 2. The 0 and 1 logic have different

phases in a high frequency
signal.

c. QPSK 3. Pair of bits 00,01,10,11 is sent

at different phase differences.

4. The 0 and 1 logic states are at

same frequency levels.

Options:

a. 1,2,3

b. 1,3,4

c. 2,3,4

d. 4,1,2

Ans: a.

18. In __________________communication a constant phase difference is not

maintained between the frames but maintained within the frame.

a. Synchronous

b. Asynchronous

c. Isosynchronous

Ans: c.

19. Match the following:

a. PISO 1. Serial bits transmission in

synchronous mode

b. SIPO 2. Serial bits reception in

synchronous mode
 3. Parallel bits reception in
synchronous mode

4. Parallel bits transmission in

synchronous mode

Options:

a. 2,1

b. 1,2

c. 3,4

d. 1,4

Ans: a.

20. GMII stands for______________.

a. Gigabit Ethernet MAC Interchange Interface.

b. Gigabit Internet MAC Interchange Interface.

c. Gigabit Exchange MAC Interconnect Interface.

d. Gigabit Ethernet MAC Interconnect Interface.

Ans: a.

21. PCI/X supports________________transfers.

a. 64/100MHZ.

b. 50/100MHZ.

c. 10/100MHZ.

d. 1/100MHZ.

Ans: a.

22. Match the following:

a. Real time 1. Which always increments

without stopping or resetting

b. Real time clock 2. Continuously generates

interrupts at regular intervals
endlessly

c. System clock 3. Clocked scaled to the processor

clock and generates interrupts
at present time intervals

d. Hardware timer 4. Which gets inputs from the

 internal clock with the
processor or system clock

e. Timer finish 5. A state after the timer acquired

the preset count-value and
stopped.

f. Timer overflow 6. An interrupt can be generated

Options:

a. 1,2,3,4,5

b. 1,3,4,2,5

c. 2,3,4,1,5

d. 5,4,3,2,1

Ans: a.
23. Match the following:

a. Timer reset 1. Timer is programmed for

continuous running

b. Timer reload 2. Timer is programmed for auto

reload and start again

c. Software timer 3. Increases or decreases a count

variable on interrupt from a
timer output

d. Watchdog timer 4. Resets the system after a

predefined timeout

Options:

a. 1,2,3,4

b. 2,1,4,3

c. 4,2,3,1

d. 2,4,1,3

Ans:a.
24. Match the following:

a. Device decoder 1. Generates a Chip Select signal

b. UART 2. Sends a byte in 10-bits or 11-

bits format

c. TxD 3. Line used for transmission of

UART serial bits

d. RxD 4. Line used for reception of UART

serial bits

Options:

a. 1,2,3,4

b. 2,3,4,1

c. 3,4,2,1

d. 1,3,2,4

Ans:1.

25. In SCI receiver ___________feature is programmable.

a. Wake up

b. Sleep

c. Wait

d. Suspend

Ans: 1.

26. When SBUF is read, ______________________.

a. The intermediate register gets a new value of the last frame.

b. The intermediate register transfers the values to SBUF.

c. An overrun error occurs after the intermediate register gets a new value
of the last frame.

Ans: b.
27. When SBUF is not read,______________________.

a. The intermediate register gets a new value of the last frame.

b. The intermediate register transfers the values to SBUF.

c. An overrun error occurs after the intermediate register gets a new value
of the last frame.

Ans: c.

28. Serial interface operates in half duplex synchronous mode called

mode________.

a. 0

b. 1

c. 2

d. 3

Ans: 0.

29. DDR means____________.

a. Data Direction Register

b. Data Directional Register

c. Dynamic Direction Register

d. Data Digital Register.

Ans: a.

30. CAN line is at logic 1 in its idle state, also called as _______________.

a. Recessive state

b. Restart state

c. Reload state

d. Remember state.

Ans: a.