Registration Form Course Fee:

For Faculty/R&D organization

Name: ............................................................ `. 4100/- [course fee + accommodation]
`. 3000/- [course fee only]
Department: ……………………………….
For Students
Organization: ……………………………... `. 3100/- [course fee + accommodation]
`. 2000/- [course fee only]
Address for Correspondence: Hands on Training Program
Note:
........................................................................ DD should be taken in favor of VIT in
University payable at Vellore.
........................................................................ IC Layout Design
No. of participants restricted to 40 only.
........................................................................
Accommodation (Including Food) will be (24th - 27th Jan 2011)
........................................................................ provided based on the request.
Charges `. 275 per Day Organized by
Email: ........................................................... VLSI Division
Course Coordinator: School of Electronics Engineering
Phone: ...........................................................
VIT University
Prof. S. Muthukumar,
Accommodation Required: Yes / No Assistant Professor (Sr.)
VLSI Division, SENSE.
Demand Draft Details: Faculty/Student Mobile: 9486406436
smuthukumar@vit.ac.in
Amount: …………………………………....
Last date for Registration:
DD. No.: …………………………………....
On or before Jan 13th, 2011.
Bank: …………………………….………...
Registration form can also be obtained
Dated: …………………………….……….. from:
V.Karthikeyan, (9894972399)
Technical Officer,
IC Design Lab (TT237)
Signature: ……………………..………. …. VIT: A place to learn; A chance to grow
VIT University
Founded in 1984 as Vellore
Engineering College, the institute was
declared a University in recognition of its
academic excellence by the Ministry of
Human Resources Development,
Government of India in 2001. The
University has since grown by leaps and
bounds – establishing excellent
infrastructure spread over an impeccably
clean and green campus. VIT today
comprises of nine constituent Schools and
interdisciplinary Centers offering
undergraduate, graduate and research
programs. VIT is the first educational
institution in India to get ISO 9002
certificate by the DNV of The Netherlands.
It is again the first Institute in India to get
accreditation from the IET (formerly IEE)
UK, in 2005. Further it has also been
accredited by NBA (AICTE) and NAAC
(UGC).
School of Electronics Engineering
The School of Electronics
Engineering at VIT University was
established for imparting a state-of the- art
education, training and research in the field
of Electronics and Communication
Engineering and allied areas. The School
offers a Bachelor's level program in
Electronics and Communication Engineering
and Master's program in Communication
Engineering, Sensor System Technology,
VLSI Design and Nanotechnology. The
School has faculty strength of around 100
and attracts the brightest students. The
School offers a double degree program in Course description
M.Tech Sensor System Technology with the
University of Applied Sciences, Karlsruhe, Day 1
Germany, and M.Tech. Communication Theory: Design Flow, Layout Design Rules,
Engineering with the UAS, Darmstadt,
Analog and Digital Layout Design
Germany. The School also offers M.S. and
Ph.D programs. Techniques.
The School of Electronics Engineering has Day 2
state-of the- art laboratories in the areas of Lab: Schematic Driven Layout of basic
communication, Embedded systems, DSP, Gates, Full Custom layout design of Basic
Microwave and Photonics, MEMS (Design Gates.
center supported by NPMASS), Sensors,
VLSI/ULSI system design, Nanotechnology
(under DST, nano initiative). The school has Day 3
entered into MoUs and agreements with Lab: Standard Cell layout Design for Digital
national and international R&D and IC’s. SDL and Full Custom Layout of
academic institutions. Analog Circuits.
About ASIC design Lab Day 4
The ASIC Design Laboratory is equipped
Lab: I/O Pad Insertion, Parasitic Extraction
with
™ Mentor Graphics EDA Tools – R and C, Post Layout Simulation, GDSII
™ Cadence EDA Tools
™ Cypress Semiconductors Tools and Tools :
Development Boards
™ FPGA Development Boards and
Mentor graphics: Design Architect, IC
Tools sponsored by ALTERA
station and Calibre xRC
The Lab has NDA with FAB labs like
TSMC, UMC through EURO Practice.
Who Can Attend?
Faculty from Educational Institutions
Research Scholars
Students – Graduates and post Graduates of
all circuit branches