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Ref. No............................ September 26, 2010

Dated, the………………………….

Look-Ahead Carry Generator:

The parallel adder performs additions at a relatively high speed, since it adds the bits from each position
simultaneously. But its speed is limited by an effect called carry propagation or carry ripple.
In this case, addition of the LSB position produces a carry into the second position. This carry, when added to the bits
of the second position, produces a carry into the third position. Thus, the sum bit generated in the last position (MSB)
depended on the carry that was generated by the addition in the first position (LSB). This represents a time delay that
depends on the propagation delay produced in a FA. The situation becomes much worse if the adder circuit have to
add a greater number of bits.
One of the possible methods for reducing carry propagation delay time is to use faster logic gates. But then there is a
limit below which the gate delay cannot be reduced.
The most widely used technique is the concept of look-ahead carry. This concept attempts to look ahead and
generate the carry for a certain given addition that would otherwise have resulted from some previous operations. It
utilizes logic gates to look at the lower-order bits of the augend and addend to see if a higher-order carry is to be
generated. This logic circuit would have a shorter delay than is obtained by the carry propagation through the FAs.
Let us define tow binary variables –
(I) Pi called CARRY PROPAGATE – it is instrumental in propagation of Ci to Ci+1.
(II) Gi called CARRY GENERATE – it generates a carry whenever Ai and Bi are 1.
CARRY GENERATE, CARRY PROPAGATE, SUM and CARRY parameters are given by following expressions –
Pi = Ai ⊕ Bi
Gi = Ai .Bi
S i = Pi ⊕ C i
Ci +1 = Pi .Ci + Gi

C4

P3
G3

C3

P2
G2

P1 C2
G1
C1
Fig.: Look-ahead carry generator.

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Ref. No............................ September 26, 2010

Dated, the………………………….

The Boolean expressions for the CARRY output of each full adder stage in the four-bit binary adder are –
C2=G1+P1.C1
C3=G2+P2.C2=G2+P2.(G1+P1.C1)=G2+P2.G1+P1.P2.C1
C4=G3+P3.C3=G3+P3.(G2+P2.G1+P1.P2.C1)=G3+P3.G2+P3.P2.G1+P1.P2.P3.C1
From the expressions it is clear that C4 need not wait for C3 and C2 to propagate. Similarly, C3 does not wait for C2 to
propagate. A look-ahead carry generator that implements the above expressions using AND-OR logic is shown in the
above figure.
A4
B4 C5

P4

S4
C4
A3
B3 P3

S3
C3
Look ahead
A2 carry generator P2
B2
S2
C2

P1
A1
S1
B1

C1

Fig.: Four-bit full adder with a look-ahead carry generator.

Figure above shows the four-bit adder with the look-ahead carry concept incorporated.
The logic gates shown to the left of the look-ahead carry generator block represent the input half-adder portion of
various full adders constituting the four-bit adder.
The EX-OR gates shown on the right are a portion of the output half-adders of various full adders.
[Ref.: Digital Electronics Principles, Devices and Applications, Anil K. Maini]

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Ref. No............................ September 26, 2010

Dated, the………………………….

Integrated-Circuit Parallel Adder:

A3 A2 A 1 A0

4-bit
C4 parallel adder C0
74HC283

B3 B2 B 1 B0
Σ3 Σ2 Σ 1 Σ0
Fig.: Block symbol for 74283 four-bit parallel adder.
Figure shows the functional symbol for the 74283 four-bit parallel adder that contains four interconnected FAs and
the look-ahead carry circuitry needed for high-speed operation.
The inputs to this IC are two four-bit numbers A3A2A1A0 and B3B2B1B0, and the carry C0 into the LSB position.
The outputs are the sum bits Σ3Σ2Σ1Σ0 and the carry C4 out of the MSB position.
8-bit augend
A7 A6 A5 A4 A 3 A2 A1 A0

74HC283 C4 74HC283
C8 (high-order adder) (low-order adder) C0

B 7 B6 B5 B4 B3 B2 B 1 B0
8-bit addend

Σ7 Σ6 Σ 5 Σ4 Σ3 Σ 2 Σ1 Σ 0
Fig.: Cascading two 74283s.
Two or more IC adders can be connected together to accomplish the addition of larger binary numbers. Figure shows
two 74283 adders connected to add two 8-bit numbers A7A6A5A4A3A2A1A0 and B7B6B5B5B4B3B2B1B0.
The adder on the right adds the lower-order bits of the numbers. The adder on the left adds the higher-order bits plus
the C4 carry out of the lower-order adder.
The eight sum outputs are the resultant sum of the two 8-bit numbers.
C8 is the carry out of the MSB position. It can be used as the carry input to a third adder stage if larger binary
numbers are to be added.
[Ref.: Digital Systems Principles and Applications, R.J. Tocci and N.S. Widmer]

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Ref. No............................ September 26, 2010

Dated, the………………………….

Half-Subtractor:
A half-subtractor is a combinational circuit that can be used to subtract one binary digit from another to produce a
DIFFERENCE output and a BORROW output. The BORROW output specifies whether a 1 has been borrowed to
perform the subtraction.
A B D B0
A D=A-B 0 0 0 0
Half
Subtractor 0 1 1 1
B B0 1 0 1 0
1 1 0 0
Fig.: Truth table of a half subtractor.
The truth table of a half-subtractor is shown in the figure. The Boolean expressions for the two outputs are given by
the equations –
D = A.B + A.B
B0 = A .B
Figure below shows the logic implementation of a half-subtractor.
A
D=A-B
B

B0

Fig.: Logic diagram of a half-subtractor.

Full Subtractor:
A full subtractor performs subtraction operation on two bits –
(I) a minuend – the number the subtrahend is being subtracted from and
(II) a subtrahend – the number to be subtracted.
It also takes into consideration whether a 1 has already been borrowed by the previous adjacent lower minuend bit or
not. This borrow bit is designated as Bin.
There are two outputs –
(I) the DIFFERENCE output D and
(II) the BORROW output B0 – it tells whether the minuend bit needs to borrow a 1 from the next possible higher
minuend bit.
Figure below shows the truth table of a full subtractor.
Minuend Subtrahend Borrow In Difference Borrow Out
(A) (B) (Bin) (D) (BO)
0 0 0 0 0
A D 0 0 1 1 1
Full
B Subtractor 0 1 0 1 1
Bin BO 0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Fig.: Truth table of a full subtractor.
The Boolean expressions for the two output variables are given by the equations –

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Ref. No............................ September 26, 2010

Dated, the………………………….

D = A.B .Bin + A.B.Bin + A.B .Bin + A.B.Bin

= Bin .( A.B + A.B ) + Bin .( A.B + A.B )
= Bin .( A ⊕ B) + Bin .( A ⊕ B)
= ( A ⊕ B) ⊕ Bin
B0 = A.B .Bin + A.B.Bin + A.B.Bin + A.B.Bin
= A.B( Bin + Bin ) + Bin .( A.B + A.B )
= A.B + Bin .( A ⊕ B)
The corresponding logic implementation of full subtractor are as shown below.
Bin
D
A
B

BO

Fig.: Logic implementation of a full subtractor.

[Ref.: Digital Electronics Principles, Devices and Applications, Anil K. Maini]

2’s Complement System:

Most modern computers use the 2’s complement system to represent negative numbers and to perform subtraction.
When the 2’s complement system is used, the subtrahend is changed to its 2’s complement and then added to the
minuend. The sum outputs of the adder circuit represent the difference between the minuend and the subtrahend.
Assume the minuend is already stored in the accumulator register.
Subtrahend is then placed in the B register. The inverted outputs of the B register are fed to the adder inputs. Also,
C0 is made a logical 1; this accomplishes the same effect as adding 1 to the LSB of the B register for forming the 2’s
complement.
The outputs Σ3 to Σ0 represent the results of the subtraction operation, where Σ3 is the sign bit of the result and
indicates whether the result is + or -.
The carry output C4 is disregarded.
A3 A 2 A1 A 0 From A register

4-bit
C4 parallel adder C0=1
(disregarded) 74HC283

Inverted output
of B register B3 B2 B1 B0
Σ3 Σ2 Σ1 Σ0 Represents DIFFERENCE output
Fig.: Parallel adder used to perform used to perform subtraction.

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Ref. No............................ September 26, 2010

Dated, the………………………….

For example – subtracting +6 from +4 is equivalent to addition of -6 with +4. The steps followed to do this are –
1) +4 is stored in the A register as 0100 with first 0 as the sign bit.
2) +6 is stored in the B register as 0110 with first 0 as the sign bit.
3) The inverted outputs of the B-register FFs (1001) are fed to the adder.
4) The parallel-adder circuitry adds [A]=0100 to [B ] =1001 along with a carry C0=1 into the LSB.
The result at the sum outputs is 1110. This actually represents [A]-[B]. Since the sign bit = 1, it is a negative
result and is in 2’s complement form. 1110 represents -210 which is the actual result.
The basic parallel-adder circuit can be used to perform addition or subtraction depending on whether the B number is
left unchanged or is converted to its 2’s complement. A complete circuit that can perform both addition and
subtraction in the 2’s complement system is shown in the figure below.
B register

B3 B3 B2 B2 B1 B1 B 0 B0
ADD

5 3 1
7

SUB

6 4 2
8

12 11 10 9

B3 B2 B1 B0
C4 74LS283
CO
A3 A2 A1 A0
Q
_
Q

Q
_
Q

Q
_
Q
Q
_
Q
CP

CP

CP
CP
D

D
D

Σ3 Σ2 Σ1 Σ 0
Transfer
pulse

Fig.: Parallel adder/subtractor using 2’s complement system.

This adder/subtractor circuit is controlled by the two control signals ADD and SUB. When the ADD level is HIGH, the
circuit performs addition of the numbers stored in the A and B registers. When the SUB level is HIGH, the circuit
subtracts the B-register number from the A-register number. The operation is described as follows –
1) Assume that ADD=1 and SUB=0. The SUB=0 disables AND gates 2, 4, 6 and 8 holding their outputs at 0.
The ADD=1 enables AND gates 1, 3, 5 and 7 allowing their outputs to pass the B0, B1, B2 and B3 levels,
respectively.

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Ref. No............................ September 26, 2010

Dated, the………………………….

2) The levels B0 to B3 pass through the OR gates into the four-bit parallel adder to be added to the bits A0 to A3.
The sum appears at the outputs Σ0 to Σ3.
3) SUB=0 causes a carry C0=0 into the adder.
4) Now assume that ADD=0 and SUB=1. The ADD=0 inhibits AND gates 1, 3, 5 and 7. The SUB=1 enables
AND gates 2, 4, 6 and 8 so that their outputs pass the B0 , B1 , B2 and B3 levels, respectively.
5) The levels B0 to B3 pass through the OR gates into the adder to be added to the bits A0 to A3.
6) C0 is now 1. Thus, the B-register number has essentially been converted to its 2’s complement.
7) The difference appears at the outputs Σ0 to Σ3.
[Ref.: Digital Systems Principles and Applications, R.J. Tocci and N.S. Widmer]

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