DP0 XTraining

JANUARY 19, 2001 Training Materials Prepared by: ALVIE RODGERS C.E.T.
2000
MODEL RELEASE
MODEL CHASSIS
53FDX01B DP-05
43FDX01B DP-05F
53SDX01B DP-06
61SDX01B DP-06
DIGITAL
53SWX01W DP-07
61SWX01W DP-07
53SDX88BA DP86V
60SDX88BA DP86V
CONTENTS... 2000 DP-0X Chassis Projection Television Information

INSTRUCTOR… Alvie Rodgers C.E.T. (Norcross, GA.)
January 19, 2000 Table of Contents Page 1 of 3
DP-0X CHASSIS TABLE OF CONTENTS

SECTION (1) GENERAL INFORMATION:
• DP-0X FUNCTION Reference Chart --------------------------------------------------------------------------------- 01-01
• PTV CHASSIS to CHASSIS Cross Reference Chart -------------------------------------------------------------- 01-03
• PTV CHASSIS to CHASSIS Cross Reference Chart -------------------------------------------------------------- 01-04
• CTV MODEL to CHASSIS Cross Reference Chart --------------------------------------------------------------- 01-05
• CTV CHASSIS to MODEL Cross Reference Chart --------------------------------------------------------------- 01-06
• DP-06 and DP-07 REAR PANEL ------------------------------------------------------------------------------------- 01-07
• DP-05 and DP-05F REAR PANEL ----------------------------------------------------------------------------------- 01-08
SECTION (2) MICROPROCESSOR INFORMATION:
• Microprocessor PORT DESCRIPTION Explanation ------------------------------------------------------------ 02-01
• Microprocessor PORT DESCRIPTION Circuit Diagram-------------------------------------------------------- 02-10
• DP-05 and 05F Microprocessor PORT DESCRIPTION Explanation ------------------------------------- 02-11
• DP-05 and 05F Microprocessor PORT DESCRIPTION Circuit Diagram--------------------------------- 02-12
• Microprocessor DATA COMMUNICATION Explanation ----------------------------------------------------- 02-13
• Microprocessor DATA COMMUNICATION Circuit Diagram ------------------------------------------------ 02-18
• DP-05 and 05F Microprocessor DATA COMMUNICATION Explanation ------------------------------ 02-19
• DP-05 and 05F Microprocessor DATA COMMUNICATION Circuit Diagram ------------------------- 02-20
• On Screen Display OSD Signal Path Explanation ------------------------------------------------------------------ 02-21
• On Screen Display OSD Signal Path Circuit Diagram ------------------------------------------------------------- 02-23
• Audio and Video MUTE Explanation -------------------------------------------------------------------------------- 02-24
• Audio and Video MUTE Circuit Diagram --------------------------------------------------------------------------- 02-26
• DP-05 and 05F Audio and Video MUTE Explanation --------------------------------------------------------- 02-27
• DP-05 and 05F Audio and Video MUTE Circuit Diagram ---------------------------------------------------- 02-28
• Mute Circuit SURROUND PWB Explanation --------------------------------------------------------------------- 02-29
• Mute Circuit SURROUND PWB Circuit Diagram----------------------------------------------------------------- 02-30
• DP-05 and 05F Mute Circuit SURROUND PWB Explanation ---------------------------------------------- 02-31
• DP-05 and 05F Mute Circuit SURROUND PWB Circuit Diagram------------------------------------------ 02-32
• MEMORY INITIALIZATION Explanation ---------------------------------------------------------------------- 02-33
• EEPROM I2C AVERAGE DATA VALUES --------------------------------------------------------------------- 02-34
• DAC 1 and 2 Pin Function Explanation ---------------------------------------------------------------------------- 02-37
SECTION (3) POWER SUPPLY DIAGRAMS:
• POWER ON/OFF Explanation --------------------------------------------------------------------------------------- 03-01
• POWER ON/OFF Circuit Diagram----------------------------------------------------------------------------------- 03-04
• Green and Red LED Used for Visual Trouble Shooting Explanation ----------------------------------------- 03-05
• Green and Red LED Used for Visual Trouble Shooting ---------------------------------------------------------- 03-08
• DP-05 and 05F Green and Red LED Used for Visual Trouble Shooting Explanation ------------------ 03-09
• DP-05 and 05F Green and Red LED Used for Visual Trouble Shooting ----------------------------------- 03-10
• Low Voltage Power Supply SHUT DOWN Explanation --------------------------------------------------------- 03-11
• Low Voltage Power Supply SHUT DOWN Diagram ------------------------------------------------------------- 03-15
• High Voltage Green and Red LED Used for Visual Trouble Shooting Explanation ------------------------- 03-16
• High Voltage Green and Red LED Used for Visual Trouble Shooting ----------------------------------------- 03-18
• High Voltage Power Supply SHUT DOWN Explanation -------------------------------------------------------- 03-19
• High Voltage Power Supply SHUT DOWN Diagram ------------------------------------------------------------ 03-24
Continued on Next Page
SECTION (4) VIDEO CIRCUIT INFORMATION:

• Model VIDEO Signal Circuit Description ----------------------------------------------------------- 04-01
• Model VIDEO Signal Circuit -------------------------------------------------------------------------- 04-02
• COMPONENT Circuit Description ------------------------------------------------------------------ 04-03
• COMPONENT Circuit Diagram ---------------------------------------------------------------------- 04-04
• DP-05 and 05F COMPONENT Circuit Description ---------------------------------------------- 04-05
• DP-05 and 05F COMPONENT Circuit Diagram -------------------------------------------------- 04-06
• CHROMA After Flex Converter Circuit Description ---------------------------------------------- 04-07
• CHROMA PHASE ROTATION Circuit Description -------------------------------------------- 04-08
• CHROMA After Flex Converter Circuit Diagram -------------------------------------------------- 04-09
• SYNC Circuit Description ----------------------------------------------------------------------------- 04-10
• SYNC Circuit Diagram --------------------------------------------------------------------------------- 04-11
• COMPONENT SYNC SEPARATION Circuit Description ------------------------------------- 04-12
• COMPONENT SYNC SEPARATION Circuit Diagram ---------------------------------------- 04-13
• DP-05 and 05F COMPONENT SYNC SEPARATION Circuit Description ----------------- 04-14
• DP-05 and 05F COMPONENT SYNC SEPARATION Circuit Diagram --------------------- 04-15
• Auto Brightness Limiter ABL Description ---------------------------------------------------------- 04-16
• Auto Brightness Limiter ABL Circuit ---------------------------------------------------------------- 04-17
• Horizontal and Vertical SWEEP LOSS Detection Circuit Description -------------------------- 04-18
• Horizontal and Vertical SWEEP LOSS Detection Circuit ---------------------------------------- 04-19
• Zenith ZP-04 (Using 3-Line Comb Filter Video Signal Path Description ------------------------ 04-20
• Zenith ZP-04 (Using 3-Line Comb Filter Video Signal Path -------------------------------------- 04-21
SECTION (5) AUDIO CIRCUIT INFORMATION:

• AUDIO SIGNAL (Main & Terminal) Circuit Description -------------------------------------- 05-01
• AUDIO SIGNAL (Main & Terminal) Circuit Diagram ------------------------------------------ 05-02
• AUDIO SURROUND Circuit Description ---------------------------------------------------------- 05-03
• AUDIO SURROUND Circuit Diagram -------------------------------------------------------------- 05-04
• DP-05 and 05F CHASSIS SURROUND Circuit Description ------------------------------------ 05-05
• DP-05 and 05F CHASSIS SURROUND Circuit Diagram --------------------------------------- 05-06
SECTION (6) DIGITAL CONVERGENCE CIRCUIT INFORMATION:

• DIGITAL CONVERGENCE Interface Circuit Description -------------------------------------- 06-01
• DIGITAL CONVERGENCE Interface Circuit Diagram------------------------------------------ 06-05
• CLU-572 TSI Remote Control used on DP-05, DP-05, DP-06 and DP-07 Chassis ------------ 06-06
• CLU-573 TSI Remote Control used on AP-93R Chassis ------------------------------------------ 06-07
• CLU-614 MP Remote Control used on DP-85V Chassis ------------------------------------------ 06-08
• CLU-436 UII Remote Control used on AP-91 and AP-01 Chassis ------------------------------- 06-09
• DP-05 and 05F DIGITAL CONVERGENCE Interface Circuit Description ------------------ 06-10
• DP-05 and 05FF DIGITAL CONVERGENCE Interface Circuit Diagram -------------------- 06-11
SECTION (7) DEFLECTION CIRCUIT:

• DEFLECTION POWER SUPPLY Generation Circuit Description --------------------------- 07-01
• DEFLECTION POWER SUPPLY Generation Circuit Diagram ------------------------------ 07-02
• HORIZONTAL DRIVE Circuit Description ------------------------------------------------------- 07-03
• HORIZONTAL DRIVE Circuit Diagram ---------------------------------------------------------- 07-06
SECTION (8) ADJUSTMENTS:

• FACTORY RESET PROCEDURE AND CONDITION ------------------------------------------- 08-01
• SIGNAL PWB IDENTIFICATION ------------------------------------------------------------------- 08-03
• DEFLECTION PWB IDENTIFICATION ----------------------------------------------------------- 08-04
• CONTROL PWB IDENTIFICATION ---------------------------------------------------------------- 08-05
• SUB POWER SUPPLY PWB IDENTIFICATION ------------------------------------------------- 08-06
• CRT PWB IDENTIFICATION ------------------------------------------------------------------------ 08-07
• CLOCK SPEED ACCELERATION ------------------------------------------------------------------- 08-08
• HIGH VOLTAGE ADJUSTMENT -------------------------------------------------------------------- 08-09
• HIGH VOLTAGE LIMITER CIRCUIT CHECK---------------------------------------------------- 08-10
• FLYBACK PROTECTION CIRCUIT CHECK ----------------------------------------------------- 08-11
• SWEEP LOSS DETECTION CIRCUIT CHECK --------------------------------------------------- 08-12
• POWER SUPPLY VOLTAGE CHECK -------------------------------------------------------------- 08-13
• MAGNET AND YOKE LOCATIONS --------------------------------------------------------------- 08-14
• ADJUSTMENT ORDER ------------------------------------------------------------------------------- 08-15
• PRE HEAT RUN ---------------------------------------------------------------------------------------- 08-16
• CUT OFF ADJUSTMENT ----------------------------------------------------------------------------- 08-17
• PRE-FOCUS ADJUSTMENT ------------------------------------------------------------------------- 08-18
• DCU CROSS HATCH PHASE SETTING ----------------------------------------------------------- 08-19
• HORIZONTAL POSITION (COARSE) ADJUSTMENT ----------------------------------------- 08-20
• RASTER TILT ------------------------------------------------------------------------------------------- 08-21
• BEAM ALIGNMENT ---------------------------------------------------------------------------------- 08-22
• RASTER POSITION [Off-Set for Red and Blue]---------------------------------------------------- 08-23
• HORIZONTAL AND VERTICAL SIZE ADJUSTMENT ---------------------------------------- 08-24
• BEAM FORM ADJUSTMENT ----------------------------------------------------------------------- 08-26
• LENS FOCUS ADJUSTMENT ----------------------------------------------------------------------- 08-27
• STATIC FOCUS ADJUSTMENT -------------------------------------------------------------------- 08-28
• BLUE DEFOCUS ADJUSTMENT ------------------------------------------------------------------- 08-29
• WHITE BALANCE ADJUSTMENT ----------------------------------------------------------------- 08-30
• SUB BRIGHTNESS ADJUSTMENT ---------------------------------------------------------------- 08-31
• HORIZONTAL POSITION (FINE) ADJUSTMENT ----------------------------------------------- 08-32
• OVERLAY DIMENSIONS ---------------------------------------------------------------------------- 08-33
• STOPPING POSITIONS IN THE 3X3, 5X7 and 13X9 MODES --------------------------------- 08-38
• DIGITAL CONVERGENCE -------------------------------------------------------------------------- 08-40
SECTION (9) KEY COMPONENTS:

• DP-06 KEY COMPONENTS ------------------------------------------------------------------------ 09-01
!"#"$%&'
(#)*$+%,(*#'
-".,(*#'/'
MODEL No 53SDX88BA 53SDX01B 53FDX01B 43FDX01B 53SWX01W IQ50H95W IQ50H94W 50NHP400
60SDX88BA 61SDX01B 61SWX01W IQ60H95W IQ60H94W 60NHP400
CHASSIS DP86V DP06 DP05 DP05F DP07 ZP04 (OEM) ZP05 (OEM) SP05 (OEM)
Aspect 4X3 4X3 4X3 4X3 16 X 9 4X3 4X3 4X3
Listening Mod Standard No Yes No No Yes No No No
Listening Mod Night No Yes No No Yes No No No
Listening Mod Maximum No Yes No No Yes No No No
Spk Setup Front L-R Internal No Yes No No Yes No No No
wExt Amp wLarge No Yes No No Yes No No No
wExt Amp wSmall No Yes No No Yes No No No
Surround No Yes No No Yes No No No
Sub Woofer No Yes No No Yes No No No
Dig Input Coaxial V1/V2 No Yes No No Yes No No No
Optical V1/V2 No Yes No No Yes No No No
SRS Mode On-Off No No Yes Yes No Yes Yes Yes
Graphic EQ 7 band Yes No No No No No No No
Wireless Sound System MainPinPRear Yes No No No No No No No
Wireless Sound System MainPinP No No No No No No No No
Sub Woofer System Sub Volume Yes Yes No No Yes No No No
INFORMATION Special Event Reminder Yes No No No No No No No
Calendar Yes No No No No No No No
Auto Help No No No No No No No No
GUIDE+ PROGRAM GUIDE WITH IR BLASTER
OTHERS On TV Advanced Auto Demo Hold Power Yes Yes Yes Yes Yes Yes Yes Yes
On TV Menu Button Yes Yes Yes Yes Yes Yes Yes Yes
On TV Cursor Key on Ft Panel Yes Yes Yes Yes Yes Yes Yes Yes
On Remote Sleep Timer Yes Yes Yes Yes Yes Yes Yes Yes
2000 Model Functions (1 of 2)
On Remote Help Yes Yes Yes Yes Yes Yes Yes Yes
On Remote Commercial Skip Yes Yes Yes Yes Yes Yes Yes Yes
On PinP Single PinP Size No Yes Yes Yes Yes Yes Yes Yes
On PinP Multi PinP 7 Pix Yes No No No No No No No
On PinP Multi PinP 4 Pix No No No No No No No No
On PinP Multi PinP 3 Pix No Yes Yes Yes Yes Yes Yes Yes
On PinP Multi PinP Split Screen Yes Yes No No Yes No No No
On PinP Strobe Action Yes (7Pix) Yes (3Pix) Yes (3Pix) Yes (3Pix) Yes (3Pix) Yes (3Pix) Yes (3Pix) Yes (3Pix)
On PinP Variable position on Single PinP No No No No No No No No
Set Up Plug and Play Easy Set Up wColor Yes Yes Yes Yes Yes No No No
Set Up Auto Clock XDS No Yes Yes Yes Yes Yes Yes Yes
Set Up Power Resume Yes Yes Yes Yes Yes Yes Yes Yes
V Chip Yes Yes Yes Yes Yes Yes Yes Yes
SP Matrix No No No No No No No No
Page 01 -01
Soft Mute Yes Yes Yes Yes Yes Yes Yes Yes
MODEL No 53SDX88BA 53SDX01B 53FDX01B 43FDX01B 53SWX01W IQ50H95W IQ50H94W 50NHP400
60SDX88BA 61SDX01B 61SWX01W IQ60H95W IQ60H94W 60NHP400
CHASSIS DP86V DP06 DP05 DP05F DP07 ZP04 (OEM) ZP05 (OEM) SP05 (OEM)
CONTROL PANEL 2 Piece Yes Yes Yes Yes Yes No No Yes
1 Piece No No No No No Yes Yes No
FRONT PANEL Power Yes Yes Yes Yes Yes Yes Yes Yes
CH Up Cursor Up Yes Yes Yes Yes Yes Yes Yes Yes
CH Down Cursor Down Yes Yes Yes Yes Yes Yes Yes Yes
Vol Up Cursor Right Yes Yes Yes Yes Yes Yes Yes Yes
Vol Down Cursor Left Yes Yes Yes Yes Yes Yes Yes Yes
Input Exit Yes Yes Yes Yes Yes Yes Yes Yes
Menu Yes Yes Yes Yes Yes Yes Yes Yes
Magic Focus Dig Array Static Yes M.F. Yes M.F. Yes (ST) Yes (ST) Yes M.F. Yes (ST) Yes (ST) Yes (ST)
IR Receiver Yes Yes Yes Yes Yes Yes Yes Yes
Dimmer Sensor Yes Yes Yes Yes Yes Yes Yes Yes
Input 3 S Input Yes Yes Yes Yes Yes Yes Yes Yes
V Input Yes Yes Yes Yes Yes Yes Yes Yes
L/Mono Input Yes Yes Yes Yes Yes Yes Yes Yes
R Input Yes Yes Yes Yes Yes Yes Yes Yes
REAR PANEL Ant A Yes Yes Yes Yes Yes Yes Yes Yes
Ant B Yes Yes Yes Yes Yes Yes Yes Yes
To Converter Yes Yes Yes Yes Yes Yes Yes Yes
Input 1 Component No Yes Yes Yes Yes Yes Yes Yes
S Input Yes Yes Yes Yes Yes Yes Yes Yes
Input 2 Component Yes Yes Yes Yes Yes Yes Yes Yes
2000 Model Functions (2 of 2)
S Input Yes Yes Yes Yes Yes Yes Yes Yes

Dig Audio Input Coaxial No Yes No No Yes No No No
Dig Audio Input Optical No Yes No No Yes No No No
Monitor Out S Yes Yes Yes Yes Yes Yes Yes Yes
V Yes Yes Yes Yes Yes Yes Yes Yes
L Yes Yes Yes Yes Yes Yes Yes Yes
R Yes Yes Yes Yes Yes Yes Yes Yes
Audio Hi-Fi Out L Yes Yes Yes Yes Yes Yes Yes Yes
R Yes Yes Yes Yes Yes Yes Yes Yes
Wireless Out L Yes No No No No No No No
R Yes No No No No No No No
Page 01 -02
Sub Woofer Out Yes Yes No No Yes No No No
Rear Spk Out L Yes Yes No No Yes No No No
R Yes Yes No No Yes No No No
PTV MODEL TO CHASSIS CROSS REFERENCE CHART
ModelNo Chassis ModelNo Chassis ModelNo Chassis

43FDX01B DP05F 50SX6P AP43B 60SX11K AP53D
43GX01B AP02 50UX10B AP23 60SX11KA AP53DP
46EX2B/K AP22 50UX11K AP23 60SX12B AP63B
46EX3B/BS AP32 50UX14B AP33 60SX13K AP63B
46EX4K/KS AP32 50UX15K AP33 60SX1K AP14
46GX01B AP92R 50UX18B AP43 60SX2K AP24
46UX10BA AP13 50UX19K AP43 60SX3B AP34
46UX10BF AP23 50UX22B AP53 60SX4K AP34
46UX11KA AP13 50UX22BA AP53P 60SX8B AP43B
46UX11KF AP23 50UX23K AP53 60SX9K AP43B
46UX12B AP33 50UX23KA AP53P 60UX54B AP73
46UX13K AP33 50UX26B AP63 60UX55K AP73
46UX16B AP43 50UX27K AP63 60UX57B AP83R
46UX17K AP43 50UX52B AP73 60UX58B AP83
46UX20B AP53 50UX53K AP73 60UX58K AP83
46UX20BA AP53P 50UX57B AP83R 60UX59B AP93
46UX21K AP53 50UX58B AP83 61DMX01W NEW
46UX21KA AP53P 50UX58K AP83 61HDX01W DP85
46UX24B AP63 50UX59B AP93 61HDX98B DP85
46UX25K AP63 50UX7B/K/W AP13 61SBX01B AP93R
46UX50B AP73 50UX8D/W AP13 61SBX59B AP93
46UX51K AP73 52LDX99B DL1 61SDX01B DP06
46UX7B/K AP13 53FDX01B DP05 61SWX01W DP07
50CX01B AP90R 53SBX01B AP93R 70SBX74B AP74
50CX29B AP90 53SBX59B AP93 CT4271 VP6
50ES1B/K AP31 53SDX01B DP06 CT4275 VP6X2
50EX01B AP91R 53SDX88BA DP86V CT4520K VP7X2
50EX10B AP32 53SDX89B DP86 CT4521K VP7X2
50EX11BV AP32 53SWX01W DP07 CT4525 VP2
50EX12B AP32F 55EX15K AP52 CT4531 VP2
50EX12BA AP32V 55EX1K AP12 CT4532 VP2
50EX12BX AP52 55EX7K AP32 CT4533K VP9X1
50EX13K AP32F 55EX9K AP32 CT4534 VP3
50EX13KA AP32V 55FX20B AP62 CT4535K VP9X1
50EX13KX AP52 55FX48B AP82 CT4536 VP3
50EX14BV AP52 55FX49B AP92 CT4546 VP3
50EX16B AP52 55UX58B AP83P CT4555 VP3
50EX20B AP52 55UX58BA AP83 CT4580K VP7X2
50EX2K AP22 55UX59B AP93 CT5033K VP9X1
50EX39B AP91 60CX01B AP90R CT5071 VP6
50EX6K AP32 60CX29B AP90 CT5072 VP6
50EX8K AP32 60EX01B AP91R CT5075 VP6X2
50FX18B AP62 60EX28B AP52P CT5080 VP7X2
50FX19K AP62 60EX38B AP52P CT5081K VP7X2
50FX30B AP62 60EX39B AP91 CT5522K VP7X2
50FX48B AP62P 60FX32B AP62 CT5533K VP9X1
50FX49B AP92 60GX49B AP92 CT5582K VP7X2
50GX10B AP92R 60SBX72B AP74 CU4600K VP8X2
50GX20B AP92R 60SBX78B AP84 CU4601K VP8X2
50GX49B AP92 60SDX88B DP86 CU5000K VP8X2
50SBX70B AP74 60SDX88BA DP86V CU5001B VP8X2
50SBX78B AP84 60SX10B AP53D CU5002K VP8X2
50SX5P AP33B 60SX10BA AP53DP CU5003D VP8X2
PAGE 01-03
PTV CHASSIS TO MODEL CROSS REFERENCE CHART
Chassis ModelNo Chassis ModelNo Chassis ModelNo

AP02 43GX01B AP53 50UX23K AP92R 46GX01B
AP12 55EX1K AP53D 60SX10B AP92R 50GX10B
AP13 46UX10BA AP53D 60SX11K AP92R 50GX20B
AP13 46UX11KA AP53DP 60SX10BA AP93 50UX59B
AP13 46UX7B/K AP53DP 60SX11KA AP93 53SBX59B
AP13 50UX7B/K/W AP53P 46UX20BA AP93 55UX59B
AP13 50UX8D/W AP53P 46UX21KA AP93 60UX59B
AP14 60SX1K AP53P 50UX22BA AP93 61SBX59B
AP22 46EX2B/K AP53P 50UX23KA AP93R 53SBX01B
AP22 50EX2K AP62 50FX18B AP93R 61SBX01B
AP23 46UX10BF AP62 50FX19K DL1 52LDX99B
AP23 46UX11KF AP62 50FX30B DP05F 43FDX01B
AP23 50UX10B AP62 55FX20B DP05 53FDX01B
AP23 50UX11K AP62 60FX32B DP06 53SDX01B
AP24 60SX2K AP62P 50FX48B DP06 61SDX01B
AP31 50ES1B/K AP63 46UX24B DP07 53SWX01W
AP32 46EX3B/BS AP63 46UX25K DP07 61SWX01W
AP32 46EX4K/KS AP63 50UX26B DP85 61HDX01W
AP32 50EX10B AP63 50UX27K DP85 61HDX98B
AP32 50EX11BV AP63B 60SX12B DP86 53SDX89B
AP32 50EX6K AP63B 60SX13K DP86 60SDX88B
AP32 50EX8K AP73 46UX50B DP86V 53SDX88BA
AP32 55EX7K AP73 46UX51K DP86V 60SDX88BA
AP32 55EX9K AP73 50UX52B NEW 61DMX01W
AP32F 50EX12B AP73 50UX53K VP2 CT4525
AP32F 50EX13K AP73 60UX54B VP2 CT4531
AP32V 50EX12BA AP73 60UX55K VP2 CT4532
AP32V 50EX13KA AP74 50SBX70B VP3 CT4534
AP33 46UX12B AP74 60SBX72B VP3 CT4536
AP33 46UX13K AP74 70SBX74B VP3 CT4546
AP33 50UX14B AP82 55FX48B VP3 CT4555
AP33 50UX15K AP83 50UX58B VP6 CT4271
AP33B 50SX5P AP83 50UX58K VP6 CT5071
AP34 60SX3B AP83 55UX58BA VP6 CT5072
AP34 60SX4K AP83 60UX58B VP6X2 CT4275
AP43 46UX16B AP83 60UX58K VP6X2 CT5075
AP43 46UX17K AP83P 55UX58B VP7X2 CT4520K
AP43 50UX18B AP83R 50UX57B VP7X2 CT4521K
AP43 50UX19K AP83R 60UX57B VP7X2 CT4580K
AP43B 50SX6P AP84 50SBX78B VP7X2 CT5080
AP43B 60SX8B AP84 60SBX78B VP7X2 CT5081K
AP43B 60SX9K AP90 50CX29B VP7X2 CT5522K
AP52 50EX12BX AP90 60CX29B VP7X2 CT5582K
AP52 50EX13KX AP90R 50CX01B VP8X2 CU4600K
AP52 50EX14BV AP90R 60CX01B VP8X2 CU4601K
AP52 50EX16B AP91 50EX39B VP8X2 CU5000K
AP52 50EX20B AP91 60EX39B VP8X2 CU5001B
AP52 55EX15K AP91R 50EX01B VP8X2 CU5002K
AP52P 60EX28B AP91R 60EX01B VP8X2 CU5003D
AP52P 60EX38B AP92 50FX49B VP9X1 CT4533K
AP53 46UX20B AP92 50GX49B VP9X1 CT4535K
AP53 46UX21K AP92 55FX49B VP9X1 CT5033K
AP53 50UX22B AP92 60GX49B VP9X1 CT5533K
PAGE 01-04
CTV MODEL TO CHASSIS CROSS REFERENCE CHART
ModelNo Chassis ModelNo Chassis ModelNo Chassis

13SA10B OEM 31KX41K M1CLXU 36SX78B M8LXU
13VR12B OEM 31KX6B G9LXU1M 36TX53K M7LXU
19VR13B OEM 31KX7B G9LXU1M 36UX01B M10
20CX20B PANA 31KX9K G9LXU1M 36UX52B M7LXU
20MA1B FH92XS-1 31UX5B A3LXU 36UX58B M7LXU2
20SA2B M2XU 32CX10B A3LXU2 36UX59B M9LXU
20SA3B M3L 32CX11B A3LXU3 CT1386W/B G7
20SA4B M2XU 32CX12B A3LXU4 CT2075W G7NU
20SA5B M3XU 32CX32B A3LXU3 CT2076W/B G7NU
27AX0B M1LXU 32CX33B A3LXU3 CT2077W/B G7XU
27AX1B M1LXU 32CX38B A3LXU3 CT2079B G7XU
27AX2B M1LXU 32CX39B M9LXU CT3170 G7LXU
27AX3B M1CLXU 32CX39B M9LXU CT3175 G7LXU
27AX4B M1CLXU 32CX7B A3LXU2 CT3190B/K G9LXU
27AX5BX M1CLXU 32FX41B-501 M7LXU CT3196B/K G9LXU
27CX01B SHARP 32FX48B M7LXU2 CT3198K G9LXU
27CX0B M1CLXU 32FX49B M9LXU CT7872B/K G9LXU
27CX15B M3LXU 32GX01B M10 CT7880 G7NU
27CX1B M3LXU 32TX78B A3LXU3 CT7881B/K G9LXU
27CX21B M3LXU2 32TX79K A3LXU3 CT7882B/K G9LXU
27CX22B Zenith GX 32UX01B M10 CT7883B A1LXU
27CX25B M3LXU 32UX51B M7LXU CT7892B/K G9LXU
27CX28B NA6L Pan 32UX58B M7LXU2 CT7893B A1LXU
27CX29B OEM 32UX59B M9LXU CT7894B A1LXU
27CX31B Zenith GX 32UX8B A4LXU CT7896B G9LXU
27CX3B A3LXU 35CX30B A3LXU3 CT7897B G9LXU
27CX4B A3LXU 35CX45B A3LXU4 CT7898B G9LXU
27CX5B M3LXU 35TX10B A3LXU CT7899K G9LXU
27CX6B M3LXU 35TX20B A3LXU2
27CX75B M3LXU2 35TX30B A2LXU
27CX7B M3LXU2 35TX50B A2LXU
27DX5B A1LXU 35TX59K A2LXU
27FX48B NA6D Pan 35TX69K A2LXU
27FX90BC A2LXU 35TX79K A4LXU
27GX01B PANA 35TX88B A3LXU3
27MM20B PA-1 35TX89K A3LXU3
27MMV30B PA-2 35UX60B A2LXU
27UX01B PANA 35UX70B A4LXU
27UX5B A3LXU 35UX70B A4LXUP
31CX4B A3LXU 35UX80B A4LXUP
31CX5B A3LXU2 1995 35UX85B A6LXU
31CX5B A3LXU2 1996 36CX35B M7LXU
31CX6B A3LXU2 36FX38B M7LXU2
31DX10B M1LXU1 36FX42B-501 M7LXU
31DX11B M1CLXU 36FX48B M7LXU2
31DX20B M1LXU1 36FX49B M9LXU
31DX21B M1CLXU 36GX01B M10
31DX22B M1CLXU 36MMV60B MM1
31GX31B M1CLXU 36MMV70B MM1
31KX1B G9LXU1M 36SDX01B MM-1T
31KX2B G9LXU1M 36SDX01BR MM-1R
31KX39K M1CLXU 36SDX88B MM1
31KX3K G9LXU1M 36SX72B M8LXU
PAGE 01-05
CTV CHASSIS TO MODEL CROSS REFERENCE CHART
Chassis ModelNo Chassis ModelNo Chassis ModelNo

A1LXU CT7893B G9LXU CT3198K M7LXU2 36FX38B
A1LXU CT7883B G9LXU CT7896B M8LXU 36SX72B
A1LXU 27DX5B G9LXU CT7892B/K M8LXU 36SX78B
A1LXU CT7894B G9LXU CT3196B/K M9LXU 36FX49B
A2LXU 35TX50B G9LXU CT7881B/K M9LXU 36UX59B
A2LXU 35UX60B G9LXU CT7882B/K M9LXU 32CX39B
A2LXU 35TX59K G9LXU1M 31KX3K M9LXU 32UX59B
A2LXU 35TX30B G9LXU1M 31KX1B M9LXU 32FX49B
A2LXU 27FX90BC G9LXU1M 31KX2B M9LXU 32CX39B
A2LXU 35TX69K G9LXU1M 31KX6B MM1 36MMV70B
A3LXU 27CX3B G9LXU1M 31KX7B MM1 36MMV60B
A3LXU 35TX10B G9LXU1M 31KX9K MM1 36SDX88B
A3LXU 27UX5B M10 36UX01B MM-1R 36SDX01BR
A3LXU 27CX4B M10 32GX01B MM-1T 36SDX01B
A3LXU 31CX4B M10 36GX01B NA6D Pan 27FX48B
A3LXU 31UX5B M10 32UX01B NA6L Pan 27CX28B
A3LXU2 32CX10B M1CLXU 31DX22B OEM 13SA10B
A3LXU2 31CX6B M1CLXU 27CX0B OEM 19VR13B
A3LXU2 35TX20B M1CLXU 31DX21B OEM 13VR12B
A3LXU2 32CX7B M1CLXU 27AX4B OEM 27CX29B
A3LXU2 1995 31CX5B M1CLXU 31KX39K PA-1 27MM20B
A3LXU2 1996 31CX5B M1CLXU 27AX5BX PA-2 27MMV30B
A3LXU3 32TX78B M1CLXU 27AX3B PANA 27UX01B
A3LXU3 35TX89K M1CLXU 31DX11B PANA 27GX01B
A3LXU3 35TX88B M1CLXU 31GX31B PANA 20CX20B
A3LXU3 32TX79K M1CLXU 31KX41K SHARP 27CX01B
A3LXU3 32CX38B M1LXU 27AX0B Zenith GX 27CX22B
A3LXU3 32CX33B M1LXU 27AX1B Zenith GX 27CX31B
A3LXU3 32CX32B M1LXU 27AX2B
A3LXU3 32CX11B M1LXU1 31DX20B
A3LXU3 35CX30B M1LXU1 31DX10B
A3LXU4 35CX45B M2XU 20SA2B
A3LXU4 32CX12B M2XU 20SA4B
A4LXU 32UX8B M3L 20SA3B
A4LXU 35TX79K M3LXU 27CX5B
A4LXU 35UX70B M3LXU 27CX25B
A4LXUP 35UX80B M3LXU 27CX1B
A4LXUP 35UX70B M3LXU 27CX15B
A6LXU 35UX85B M3LXU 27CX6B
FH92XS-1 20MA1B M3LXU2 27CX75B
G7 CT1386W/B M3LXU2 27CX21B
G7LXU CT3170 M3LXU2 27CX7B
G7LXU CT3175 M3XU 20SA5B
G7NU CT2075W M7LXU 36UX52B
G7NU CT2076W/B M7LXU 32UX51B
G7NU CT7880 M7LXU 32FX41B-501
G7XU CT2079B M7LXU 36TX53K
G7XU CT2077W/B M7LXU 36FX42B-501
G9LXU CT3190B/K M7LXU 36CX35B
G9LXU CT7872B/K M7LXU2 32UX58B
G9LXU CT7898B M7LXU2 36UX58B
G9LXU CT7897B M7LXU2 36FX48B
G9LXU CT7899K M7LXU2 32FX48B
PAGE 01-06
REAR PANEL for the
53SDX01B, 61SBX01B (DP-06) and 61SWX01W, 53SWX01W (DP-07)
OPTICAL
INPUT ANT A STOP
COAXIAL CONNECT ONLY 8 Ohm SPEAKERS
DO NOT SHORT CIRCUIT
INPUT
THESE TERMINALS.
REAR SPEAKER To (such damage is NOT COVERED
by your television warranty)
8 ONLY Converter
+ + S-VIDEO S-VIDEO S-VIDEO
R L
ANT B
- -
VIDEO Y VIDEO Y VIDEO
(MONO) PBCB (MONO) PBCB (MONO)

L L
R L PRCR PRCR
R R R
AUDIO SUB
AUDIO AUDIO AUDIO
TO HI-FI WOOFER
MONITOR
INPUT 1 INPUT 2 OUT
PAGE 01-07
REAR PANEL for the 53FDX01B (DP-05) and 43FDX01B (DP05F)
ANT A
To
Converter
S-VIDEO S-VIDEO S-VIDEO
ANT B
VIDEO Y VIDEO Y VIDEO
(MONO) PBCB (MONO) PBCB (MONO)

L L
R L
PRCR PRCR
R R R
AUDIO
AUDIO AUDIO AUDIO
TO HI-FI
MONITOR
INPUT 1 INPUT 2 OUT
PAGE 01-08
MICROPROCESSOR
INFORMATION
SECTION 2
MICROPROCESSOR PORT DESCRIPTION
DP-0X MICROPROCESSOR PORT DESCRIPTION EXPLANATION:
The DP-0X Microprocessor is a Dual In-Line 64 pin chip. Generic number is MN102H51K. The Microprocessor
is responsible for many different operations related to the control of the Projection Television. Some of these con-
trols are automatic and some require customer intervention, either by the Remote control or front panel keys and/
or by the customer’s menu.
When power is first applied, the Microprocessor receives it’s B+. This Microprocessor utilizes a 3.3V power sup-
ply instead of the usual 5V as in past chassis.
As the 3.3V is rising, the Reset IC (I006) holds the reset pin (54) low long enough for the main B+ to stabilize.
After stabilization, the Reset IC brings pin (54) high. During the Reset condition, the Microprocessor is initiated
into its start up state. At the same time this is happening, the Microprocessor Oscillator is generating the Micro-
processor’s internal clock. The Crystal responsible for this is X001 (4Mhz) connected to pins (52 and 53). When
trouble shooting a Microprocessor for problems, it’s very important to remember the sequence described above.
Always examine the process before looking for any other problem area. The order is;
1. Vcc Applied. Generated from the Always Voltage (STY+7V I905) on the Sub Power Supply then through
the (STBY +5V I008 on the Signal PWB) to the 3.3V regulator Q026.
2. Ground is available. Look for open traces, etc….
3. The Reset circuit is working (I006). It should hold the Reset pin on the Microprocessor Low until main Vcc
is stabilized.
4. The Oscillator is running. Be careful here because a low resistance measuring probe will kill the Oscillator or
give a false reading.
After checking for the preliminary functionality of the circuits described above, then check for active clock pulses
leaving data port pins. (See the Data Communications Circuit Diagram for details). If some other IC is grounding
the data or clock pins, the Microprocessor will not work. This usually require a Pull-Up resistor. If no Pull-Up
resistor is noted in the schematic, then the responsibility for Pull-Up lies within the Microprocessor. Unloading
the pin in a good way to investigate for Pull-Up.
When a command is entered by either Remote Control, Front Keys or some internal process, the Microprocessor
runs a set of predetermined routines. These routines are hard programmed into the Microprocessor RAM and are
unchangeable. There are routine instructions that can be modified by either the customer or the Servicer and in-
volve pre-programmed routines and variables entered by the customer or technician. These would include such
things as changing the channel , audio set-ups, on/off timer, auto-link, etc...
CONTROL OF THE PROJECTION TELEVISION:

• Receiving Infrared Remote Control Commands
• Receiving Key Input Commands
• Controlling the On and Off state of the High Voltage Power Supply.
• Interaction between the Customer’s Menu and Chassis controls.
• Outputting On Screen Display information.
• Interaction between the Servicer’s Menu and Chassis I2C Data Bus controls.
• Automatically Scanning the Tuner’s searching for Active Channels when requested by the Customer
from the Menu.
• Automatically Controlling the Tuners when Channels are changed for the Main and PinP Tuners.
• Automatically Controlling the Video Processor (Rainforest IC) when directed by the Customer.
• Controlling the Audio Circuits when directed by the Customer.
• Controlling Switching between Tuner (Main), AVX 1, 2, 3 and 4, Component 1, 2, and Tuner 2 (AUX)
or In From Converter.
The following section will explain the controls listed above.
PAGE 02-01
Continued from Preceding Page
Receiving Infrared Remote Control Commands:

Whenever the Customer utilizes the Infrared Remote, the IR receiver will detect these 38Khz Infrared pulse
train and amplify them. These pulses are delivered to the Microprocessor at Pin (1). The Microprocessor decodes
this data train and sets off the internal routine related to the command.
There is a time when the Microprocessor ignores the remote commands and that is when the Digital Convergence
Unit, (DCU here after) is in operation. The Microprocessor receives a BUSY notification that the DCU is in op-
eration and simply doesn’t respond to remote commands. (See the Digital Convergence Interconnect Diagram and
explanation for complete details.) The BUSY signal is generated from the DCU at pin (10). Then out pin (1) of
the PSD1 connector to pin (10) of I004 DAC2. I004 sends the information via SCL1 and SDA1 lines from Pin
(14 and 15) to the Microprocessor pins (2 and 3).
Receiving Key Input Commands:

The front panel function keys are detected by the Microprocessor via R2 ladder style circuit. In other words, in-
side the microprocessor is a group of comparators. The function keys are strung together and each one has a dif-
ferent resistor value to ground. When the key is pressed, the comparators detect the change is resistance to ground
at pin (20) Clock and convert the related DC value into data the Microprocessor can understand.
The following shows the resistor value to ground from pin (20) of the Microprocessor, though pin (7) of the PFS
connector to the individual keys.
Channel Up = ground
Channel Down = 1K
Volume Up = 1K + 1.5K or 2.5K
Volume Down = 1K + 1.5K + 2.7K or 5.2K
AVX = 1K + 1.5K + 2.7K + 4.7K or 9.9K
Menu = 1K + 1.5K + 2.7K + 4.7K + 10+ or 19.9K
Controlling the On and Off state of the High Voltage Power Supply.
The Power On/Off function switch has STBY+3.3V applied for the Sub Power Supply, via pin (8) of the PFS
connector through a 1K resistor. The output of the Power On/Off switch is sent through pin (6) of the PFS to
Q014. Q014 is turned on at this time and connected to it’s Emitter is Data from the Microprocessor pin (21). The
Data is routed from Q014’s Collector to Key In pin (10) of the Microprocessor. When the Microprocessor re-
ceives this data at pin (10), it knows to turn on or off the television. This function is performed by and output
from pin (53) which controls Q002. This output from this pin is High when the set is On and Low when the set is
Off.
(For more details related to Power On/Off, see the Power On & Off Circuit Diagram Explanation and Diagram).
Interaction between the Customer’s Menu and Chassis controls.

When the Customer accesses the Main Menu, selections can be made by scrolling up and down or left to right.
Each selected input activates a set of instructions within the Microprocessor and determines the output state of
the related pins.
Outputting On Screen Display information.

When it’s necessary, the Microprocessor generates 1uSec pulses from pins (37 Red, 38 Green and 39 Blue) that
are sent to the Rainforest IC (IX01) pins (37 Blue, 38 Green and 39 Red) as OSD signals. When the OSD sig-
nals are high, they turn on the output of the Red or Green or Blue amps inside the Rainforest IC and output a
pulse to the CRTs to generate that particular character in the particular color.
(See the On Screen Display Circuit Diagram and Explanation for further details.)
(Continued on page 3)
PAGE 02-02
(Continued from page 2)
Interaction between the Servicer’s Menu and Chassis I2C Data Bus controls.
When it becomes necessary for the Service Technician to make an adjustment to the set, the Service Menu must
be entered. This is accomplished with the TV turned off, then by pressing and holding the INPUT Key and then
the POWER SWITCH. The Adjustment Menu will be displayed at this time. With the Service Menu activated, the
Technician moves up and down to the desired adjustment using the Remote control or front panel Up or Down
cursor keys. To make the adjustment, the Technician uses the Remote control or front panel Left and Right cursor
Keys to change the data values for the particular adjustment.
The Microprocessor controls the individual IC related to the adjustment using I2C technology. I2C technology
allows the Microprocessor to control and IC using only two pins, (SCL and SDA).
The following pins on the Microprocessor and the ICs that it controls are described in the following table.
PINS CONTROLLED ICs
2 SDA1 and 3 SCL1 I401 AV Selector, I002 EEPROM, I003 DAC 1, I004 DAC 2
59 SDA2 and 60 SCL2 U204 3D/YC, I701 Deflection Drive, IX01 Rainforest,
IS03 Front Audio Control, IS05 Front EQ, IS10 Center EQ, IS08 Center/LFE/
PinP Audio Control, IS01 DAC3, I201 1H Main Video, and I403 H Sub Video.
57 SDA3 and 58 SCL3 IS11 Rear Audio Control.
(See the Adjustment Section for actual adjustment made in the Service Mode condition).
Automatically Scanning the Tuner’s searching for Active Channels when requested by the Customer from
the Menu.
When the Projection is first installed, the active channels must be scanned and memorized in the Channel Scan
List. This list is actually stored within the EEPROM and the Microprocessor uses the information to Scan up or
down. Held within the Microprocessor is the Initial FCC Lookup table. This table give information related to all
the channels frequency, band, and channel number. The frequency is actually a given value for the Phase Lock
Loop circuit within the tuner. Then band is data to tell the band selection circuit in the tuner where the particular
channel is located and the channel number is given to the microprocessor to indicate what OSD outputs to pro-
duce. When the set is first opened, it’s in what is called Factory Reset Condition. For the Tuner this means that
the signal source is AIR, and channels 2 through 13 are in the channel scan list. Before the customer runs Auto
Program, they must set the signal source to the type they are using, Air, Cable 1 or Cable 2. After the source is
set, the customer then proceeds with Auto Programming.
When Auto Programming is initiated, the Microprocessor has a specific program to run. This program starts by
placing the tuner in the lowest channel in the lowest band. That would normally be channel 2. Then the program
instruct the Microprocessor to look for Sync. To do this, the Microprocessor actually need Horizontal Blanking
(H.Blk) at pin (49) which is labeled H.Sync and Video Sync (24) labeled Main/Sub SD Det.
Horizontal Blanking is use as a gate pulse for the coincidence detector. Within the coincidence detector is a cir-
cuit that looks at the timing of the Sync in relationship to (H.BLK). If the signal being checked is not in time with
(H.Blk). The signal is ignored. However, if the signal being monitored is in coincidence with (H.Blk) the signal
is deemed to be true Video Sync and that particular channel is stored as an active channel in the EEPROM Scan
List.
Then the Microprocessor sends information to the tuner to move up one channel and the whole process begins
again. This is repeated until every channel is checked. After completion of the scan, the microprocessor retrieves
information from the EEPROM concerning the first channel in the lowest band that appears in the scan list and
directs the tuner to tune to that channel.
PAGE 02-03
Automatically Controlling the Tuners when Channels are changed. (See Figure 1)
MAIN TUNER:
When channels are changed, the Microprocessor runs another routine. This routine detects the command if it’s
input by the Remote Control or the Front keys, whether it’s Scan Up/Down or direct access, and begins to control
the Tuner. First the Microprocessor output a Mute command to blank the video, then data is sent to the tuner to
move it to the desired channel. After that the Microprocessor again checks the coincidence detector for active
sync. If active sync is detected, the Microprocessor opens what is called the AFC Loop. The AFC Loops com-
prises two cycles trying to lock the tuner to the specific IF frequency of 45.5 Mhz. A DC voltage is sent from ei-
ther the Main Tuner U201 pin (10) or the PinP Tuner U202 pin (21) back to the Microprocessor pin (6). This
DC voltage indicates the error between the IF detected and the IF frequency reference. This error voltage tells the
Microprocessor to do one of two things. 1st, if the error is large, the Microprocessor changes the Programmable
Divider’s division rate to a larger or smaller degree to get closer to the actual IF frequency desired. Or 2nd move
the Pulse Swallow division rate to either 1/32 or 1/33. The Pulse Swallow tuning circuit is a second divider that is
on the output from the Prescaler. The main Prescaler takes the very high frequency output from the tuners mixer
circuit which is produced when the tuners main oscillator is beat against the incoming RF frequency. The Pro-
grammable Divider is instructed by the Microprocessor exactly what division rate to apply to the Beat Frequency
generating the IF frequency. The IF frequency is then sent through the Pulse Swallow circuit which again divides
the IF frequency at a much smaller rate . This allows the IF output frequency to become much more finite and can
correct for much smaller errors between the Phase comparators reference frequency. The error voltage generated
is directed back to the main internal Oscillator in the front end and corrects for Tuning errors.
(See the Microprocessor Data Communications Circuit Diagram Explanation for Details related to Data Com-
munication for controlling the Main Tuner).
INTEGRATED TUNER
BM (B+ Mains)
IF Out IF In
B+ Distribution Video Det Video

Pulse 5K
Pre- Programm- Ref
Swallow Phase
RF Scaller able
Comparator Osc
1/32 or
Mix Fixed Divider
1/33
Band
Tuning
Error
Voltage
Amp
IF
Main Comparator
Osc
Ref
Interface Freq.
45.5K
Data Clock Load AFC
Tuning MAIN
Voltage Figure 1
+33V
MICROPROCESSOR
PAGE 02-04
Automatically Controlling the Tuners when Channels are changed. (See Figure 1)
PinP TUNER:
As far as the internal function of the PinP Tuner, it is the same as the Main Tuner.
(See the Microprocessor Data Communications Circuit Diagram Explanation for Details related to Data Com-
munication for controlling the Main Tuner).
When the customer presses the PinP button on the Remote Control, the Microprocessor outputs Clock, Data and
Enable controls to the Flex Converter. The Flex Converter also has the PinP circuit inside. The Clock, Data and
Enable pins on the Microprocessor are pins (20 Clock, 21 Data and 46 FCENABLE) These are routed to the
Level Shift IC, I014 pins (2, 3 and 4). They are output on pins (18, 17 and 16) to the Flex Converter U205 con-
nector PFC1 and input on pins (10, 11 and 12). The Flex Converter’s PinP unit is then switched on and insertion
is made into the regular Main Video line. The position of the PinP window, the PinP window itself and other dif-
ferent display conditions are controlled by this process. When SWAP is pressed on the remote control, the chan-
nel or input that the PinP tuner was on, now becomes the Main Video’s source and the channel or input that the
Main signal was on, now becomes the PinP source.
Automatically Controlling the Video Processor (Rainforest IC) when directed by the Customer.
The Rainforest IC has many enhancement circuits built in. These would include the Black Peak Expansion circuit,
the Dynamic Noise Reduction circuit, Time Compression and of course Sharpness, Black Level and Contrast ad-
justments as well.
• Black Peak Expansion Circuit:
This circuit is utilized to increase the contrast ratio. The standard video signal is 1 Volt Peak to Peak (p/p
hear after), the actual video (Y) content is 730mVp/p. The 1 Vp/p is explained it IRE figures from this
point on. The Standard video signal is divided into units called IRE. The units are equal to 140 total for
the 1Vp/p signal. Sync occupies 40IRE which are negative. And the Luminance represents 100 IRE
units. Each unit represents 7.1428mVp/p of information. (See Figure 2 below.)
The Black Peak Expansion circuit monitors the 1/2 way point of luminance, (50 IRE or 357mV) and
pulls the signal towards pure black or the 7.5 IRE level. This increases the distance from Black Peak to
White Peak which is contrast.
• Dynamic Noise Reduction Circuit:
This circuit again monitors the area from 50 IRE down and subtracts noise. This circuit is dynamic
meaning that it characteristics change. In other words, the subtraction process is greater near black level
that it is near 50 IRE. The subtraction is 6dB at maximum, meaning that there would be some frequency
loss near black, but the noise which is seen as white speckles would be reduced.
• Time Compression Circuit:
Any time an analog signal is passed through a capacitive circuit, its high frequencies are reduced. To re-
place these high frequencies, Hitachi uses Time Compression. This circuit is on the order of Aperture
Compensation, however it differs in the fact that it uses 5 delay lines. The actual signal should look like
Figure 2
PAGE 02-05
Figure 3, however after passing through a capacitive circuit, it looks like Figure 4. After Time Compres-
sion takes place, the beginning rise is advanced. Just before white peak the signal is delayed. Just before
the signal falls the signal is advanced and just before the signal reaches black peak the signal is delayed.
This causes the signal to appear more like the actual signal and thus restores the high frequencies lost
through capacitance.
Actual Signal After passing through a capacitor After Time Compression
Figure 3 Figure 4 Figure 5
• Sharpness:
During the Time Compression process, switching pulses that are detected at the transition point, (A tran-
sition is the point at which the luminance signal goes for black to white or white to black) are used in the
sharpness circuit.. This signal is the routed through a sort of variable resistor and according to how much
sharpness the customer has selected, determines how much of the transition signal is added to the origi-
nal signal. The greater the sharpness setting, the greater the transition signal added.
Original Signal Transition Point pulses Transition Pulses Added
Figure 6 Figure 7 Figure 8
Controlling the Audio Circuits when directed by the Customer.

The customer has control over how the set accesses audio information for all of it’s inputs. The tuner for example
is an integrated type. This not only means that held within the Main Tuner are all the necessary components for
Reception and Video detection. It also has a built in audio and MTS decoder. The Main Tuner outputs Left Total
and Right Total signals. (Left Total and Right Total means that the encoding for Pro-Logic is held within the indi-
vidual signal.) The customer can select first of all, how the Tuner decodes it’s audio. Stereo, Mono, or SAP can
be selected. The Main Tuner must tell the Microprocessor what signal it is receiving. The Main Tuner has a ST
LED output at pin (19) which tells the Microprocessor it is receiving MTS Stereo and a SAP LED output at pin
(20) which tells the Microprocessor it is receiving Second Audio Program. How these are selected by the con-
sumer via the Main Menu determines the output from the Microprocessor.
• ST LED is routed from the Main Tuner at pin (19), through Q204, to the DAC1 I003 pin (10). The DAC1
outputs Clock and Data via pins 15 SCL1 and 14 SDA1 signals to the Microprocessor input on pins 3 SCL1
and 2 SDA2. The Microprocessor knows how to switch the tuners decoder circuit by making judgment upon
these inputs. Then the Microprocessor can use Clock, Data and Enable lines to control the Tuner.
PAGE 02-06
• SAP LED is routed from the Main Tuner at pin (20), through Q203, to the DAC1 I003 pin (9). The DAC1
outputs Clock and Data via pins 15 SCL1 and 14 SDA1 signals to the Microprocessor input on pins 3 SCL1
and 2 SDA2.
The Microprocessor knows how to switch the tuners decoder circuit by making judgment upon these inputs. Then
the Microprocessor can us Clock, Data and Enable lines to control the Tuner.
Clock, Data and Enable lines for the Main Tuner are output from the Microprocessor at pins (20, 21 and 44) re-
spectively. Pin (44) FEENABLE1 goes directly to the Main Tuner at pin (6), where as the Clock and Data lines
must be routed through the Level Shift IC I014 to be brought up to 5V. Clock and Data arrive at I014 at pins (2
and 3) and are output at pins (18 and 17). They arrive at the Main Tuner at pins (4 and 5).
The PinP Tuner doesn’t have MTS capability. It only output mono audio, so no switching takes place for the PinP
Tuner U202 audio circuit. The only difference for the PinP tuner control lines is related to the PinP Enable line.
This is output from the Microprocessor pin (43 FEENABLE2) to the PinP Tuner at pin (17). Clock and Data are
the same as for the Main Tuner.
(See Microprocessor Data Communications Circuit Diagram and Explanation for further details).
Controlling Switching between Tuner (Main), AVX 1, 2, 3 and 4, Component 1, and 2, and
Tuner 2 (AUX) or In From Converter.
The different inputs can be selected by the Remote Control or the Front Panel switches. This is accomplished by
the INPUT button. Each time the Input button is pressed, the different inputs are sequentially selected. The se-
quential order is, Main Tuner, AVX 1, AVX 2, AVX 3, AVX 4, 2nd Antenna and back to Main Tuner. Also, if
there are S-Inputs on AVX1, 2 or 4, there is an internal mechanical switch inside the S-Jack that tells the Micro-
processor an S-Jack is inserted. Then when that particular input is selected, it automatically selects S as it’s
source. The same thing holds true for Component inputs. The set should never have Component inputs and S-Jack
inserted at the same time and a black and white picture will be displayed.
(See Video Signal Processing for details related to Video Switching.)
PAGE 02-07
DP-0X CHASSIS MICROPROCESSOR I-001 PIN/PORT DESCRIPTION 1 through 35
Pin No. ID Function Active
1 IRIN Receives Remote Control Inferred pulses. Data
2 SDA1 Serial Data Sent and Received from the EEPROM, A/V Selector, DAC1, DAC2. Function of I2C. Data
3 SCL1 Serial Clock Synchronization Sent to the EEPROM, A/V Selector, DAC1, DAC2. Function of I2C. Data
4 Dimmer Receives DC voltage generated from the Photo Receiver on the Front Panel monitoring Room Light. For AI DC
5 AD Key In Receives Level Shifted DC voltage from Front Panel Key presses. DC
6 Main/Sub AFC Receives the Main Tuner AFC or Sub AFC DC Voltage switched by I005. Used during channel change. DC
7 Key In When the Power switch is pressed, Clock data from pin 21 is routed through Q014 back to this pin. Power is toggled On or Off. Data
8 Not Used Not Used N/A
9 Not Used Not Used N/A
10 Main FV Det Receives Composite 1 V Sync from I015 pin 4 for OSD Positioning. Sync
11 Sub FV Det Receives Composite 2 V Sync from I016 pin 4 for OSD Positioning. Sync
12 DSP Busy Receives the Busy command from the Digital Surround Processor on the Surround PWB. DC
13 DSP SO Control command to the DSP Unit for controlling Modes. Data
14 DSP Dir Receives Digital Surround Processor Error information from the DSP unit on the Surround PWB. Data
15 DSP SS Control command to the DSP Unit for controlling Modes. Data
16 DSP SCK Digital Surround Processor Clock. Data
17 DSP S1 Control command to the DSP Unit for controlling Modes. Data
18 DSP ERR Mute Mutes Audio when a DSP Dir input is detected. (DSP Error). DC High
19 DSP Reset Resets the DSP module on the Surround PWB DC High
20 Clock Sent to the Level Shift I014 then to both Tuners and the Flex Converter as a timing signal. Also see pin 7. Data
21 Data Sent to the Level Shift I014 then to both Tuners and the Flex Converter to control each unit. Data
22 Comp 1/2 FH Det Either Component One or Two Horizontal Input from I005 through Q046. Used for OSD Display. And Auto Link DC
23 AC In Receives Timing pulses for advancing the Clock. Received from the Smitt Amp Q008 and Q009 60Hz.
24 Main/Sub SD Det Station Detection. Used during Auto Programming and when channels are changed to open AFC Loop. Switched by I005. Sync
25 VDD Stby +3.3V generated by 0029. Main Microprocessor B+. DC
26 CHL Clamp level High DC
27 VRefFHS Use as a reference signal within the Microprocessor High Frequencies. DC
28 CVBS0 Composite Sync used for Closed Caption Detection for the Main Tuner. Sync
29 VSS Ground N/A
30 CVBS1 Not Used. Composite Sync used for Closed Caption Detection for the PinP Tuner. N/A
31 VREFLS Reference Signal used within the Microprocessor Low Frequencies. N/A
32 CLL Internal function of the Microprocessor. N/A
33 AVDD Stby +3.3V generated by 0029. DC
34 COMP Internal function of the Microprocessor. DC
Page 02-08
35 IREF Internal function of the Microprocessor. DC

DP-0X CHASSIS MICROPROCESSOR I-001 PIN/PORT DESCRIPTION 36 through 64
Pin No. ID Function Active
36 VREF Internal function of the Microprocessor. DC
37 OSD R Outputs Red characters for the Service Menu. Data
38 OSD G Outputs Green characters for the Service Menu. Data
39 OSD B Outputs Blue characters for the Service Menu. Data
40 HALF TONE Controls the Translucency of the Main Menu Background. Low = Clear, Mid = Transparent, Hi = Gray. Data
41 PDO Internal function of the Microprocessor. DC
42 BVC0I Internal function of the Microprocessor. DC
43 FE ENABLE 2 Front End Enable. Enables the reception of data from the Microprocessor by the PinP Tuner. Data
44 FE ENABLE 1 Front End Enable. Enables the reception of data from the Microprocessor by the Main Tuner. Data
45 V.MUTE Mutes Audio and Video through Q008 and Q010 to Sub Video and Surround PWB during channel change. High = Mute DC
46 FC ENABLE Flex Converter Enable Line. Allows the Flex Converter to receive commands from the Microprocessor. Data
47 OSD X0 Reference Frequency for OSD. Determines the OSD Size. Data
48 OSD X1 Reference Frequency for OSD. Determines the OSD Size. Data
49 H SYNC Receives Horizontal Blanking pulses 3.3Vp/p for OSD positioning. Generated from H Blk through Q006 H Blk
50 SD SELECT Sent through Q030 to I015 for setting the internal selection switches. Hi = Main, Lo = Sub DC
51 OSD BLK Outputs a pulse slight wider and in time with the OSD characters to clean up video where character will be displayed. Data
52 TEST Use by the factory for internal test of the Microprocessor and to place in a specific set of criteria. DC
53 Power ON/OFF This output goes high when the Power Button is pressed for ON and Low for Off. DC
54 RESET Low when Power first applied then rises to a high of 3.3V. Received from I006. Resets the Microprocessor. DC
55 VSYNC Receives Vertical Blanking pulses 3.3Vp/p for OSD positioning. Generated from V Blk through Q005 Data
56 P BLK Sent to the Rainforest IC IX01. Used to Mute the Video during Channel change, Child Lock, AVX selected with no input. Hi = Mute DC
2
57 SDA3 Serial Data Sent to the Rear Audio Output IC IS11 on Surround PWB. Controls Volume, Bass, Treble, and Bal. Function of I C. Data
2
58 SCL3 Serial Clock Sent to the Rear Audio Output IC IS11 on Surround PWB. Used for Timing of Data. Function of I C. Data
59 SDA2 Serial Data Sent to U204, I701, IX01, IS03, IS05, IS10, IS08, IS01, I201 and I403. Function of I2C. Data
2
60 SCL2 Serial Clock Sent to U204, I701, IX01, IS03, IS05, IS10, IS08, IS01, I201 and I403. Function of I C. Data
61 VDD Stby +3.3V generated by 0029. Main Microprocessor B+. DC
62 OSC In OSC In (4MHz) Data
63 OSC Out OSC Out (4MHz) Data
Page 02-09
64 VSS Ground. N/A

DP0X SYSTEM CONTROL PORT DESCRIPTION
I001
Dimmer 4 VDD (3.3V) 61 CLOCK
U201
POO 41 DATA
MAIN
FE Enable1 44 ENABLE TUNER
VSS (Gnd) 29
Main/Sub AFC 6 AFC
AC In 23
DATA
OSD X1 48 U202
CLOCK PinP
OSD Xo 47
FE Enable2 43 TUNER
ENABLE
OSD B 39
Key In 7 AFC
OSD R 37 Power Switch
OSD G 38
Clock 20 Clock
U205
Half Tone 40 Data 21 Data Flex Conv & PinP
OSD Blk 51 46 Unit
FC Enable Enable
Power On/Off 53 I014

DSP SI 17 Level DSP SI
VRef 36
Shift
DSP Err Mute 18 DSP Err
B+Fail 9 Audio DSP
DSP Sck 16 DSP Sck
AC3/ProLogic
P Blk. 56
DSPSS 15 DSPSS
VMute 45
DSPRST 19 DSPRST
Rear Audio SDA 57 SDA3 DSP S0 13

Control IS11 SCL
SCL 58 SCL3 12 3D/YC
DSP Busy U204
SDA Comb Filter
SCL SCL2 60
A/V SCL
I401 I701 Deflection
Selector SDA
SDA2 59 SDA
SCL SO Select 50 SCL
EEPROM I002 IX01 Rainforest
SDA Reset 54 SDA IC
SCL IRef 35 SCL

DAC 1 I003 IS03 Front Audio
SDA SDA Control
BVCOI 42
SCL 3 SCL1 AVDD 3.3V 33 SCL
DAC 2 I004 IS05 Front EQ
SDA 2 SDA1 SDA
Test 52
Main V. Chip Data and CCD 28 SCL
CLL 32 IS10 Cent EQ
SDA
Sub V. Chip Data 30
Sub FV Det 11
SCL
62 Cent/LFE/
OSC In Main FV Det 10 IS08
SDA Audio Control
OSC Out 63 Comp 34
SCL
64 IS01 DAC3
VSS (Gnd) G+Reset 8 N/C SDA
IRIn 1 SCL
I201 1 H Main Video
VRefHS 27 SDA
VSync 55
CLH 26 H.Blk/H.Sync 49 SCL
I403 1 H Sub Video
Ft. Panel Control Keys 5 AD SDA
KeyIn Main/Sub SD Det 24
PAGE 02-10
DP-05 and DP-05F MICROPROCESSOR PORT DESCRIPTION
DP-05F PORT DESCRIPTION
Refer to the DP-05 and DP-05F System Control Port Description Circuit Diagram
The only difference between the DP-05 & DP-05F and the DP-06 or DP-07 System Control Port Description Cir-
cuit Diagram is;
• The DP-05 and DP-05F doesn’t have the DSP Module. Therefore, it uses a SRS Surround PWB. There is no
Rear or Center Audio, so the Serial Data Communications (SCL3 and SDA3) to the Rear Audio B+ isn’t
Used.
• The Data Communications to the Level Shift IC (I014) going to the (DSP) is not used.
• The Rear Audio IC, Center Audio IC and the Center Graphic EQ IC are not used.
• The Front Audio Control IC designation is (IA05).
• The DAC3 IC designation is (IA01).
All else remains the same.
(See Next page for diagram).
PAGE 02-11
DP-05 and DP-05F SYSTEM CONTROL PORT DESCRIPTION
I001
Dimmer 4 VDD (3.3V) 61 CLOCK
U201
POO 41 DATA
MAIN
VSS (Gnd) 29
Main/Sub AFC 6 AFC
AC In 23
DATA
OSD X1 48 U202
CLOCK PinP
OSD Xo 47
OSD B 39
Key In 7 AFC
OSD R 37 Power Switch
OSD G 38
Clock 20 Clock
I014 U205
Half Tone 40 Data 21 Data
Level Flex Conv &
Shift PinP Unit
OSD Blk 51 FC Enable 46 Enable
Power On/Off 53
17 N/A
DSP SI
VRef 36 DSP Err Mute 18 N/A
B+Fail 9 DSP Sck 16 N/A
P Blk. 56 DSPSS 15 N/A
VMute 45 DSPRST 19 N/A
DSP S0 13 N/A
N/A 57 SDA3
DSP Busy 12 N/A
N/A 58 SCL3
SCL SCL2 60 SCL

A/V 3D/YC
I401 U204
Selector SDA SDA2 59 SDA Comb Filter
SCL SCL
SO Select 50 Deflection
EEPROM I002 I701
SDA SDA
Reset 54
SCL SCL
IRef 35 IX01 Rainforest
DAC 1 I003 IC
SDA SDA
BVCOI 42
SCL
SCL 3 SCL1 AVDD 3.3V 33 IA05 Front Audio
DAC 2 I004
SDA Control
SDA 2 SDA1 Test 52
Main V. Chip Data and CCD 28 SCL
CLL 32 IA01 DAC3
SDA
Sub V. Chip Data 30
Sub FV Det 11
SCL
OSC In 62 I201 1 H Main Video
Main FV Det 10
SDA
OSC Out 63 Comp 34
SCL
VSS (Gnd) 64 I403 1 H Sub Video
G+Reset 8 N/C
SDA
IRIn 1
VRefHS 27 VSync 55
CLH 26 H.Blk/H.Sync 49
Ft. Panel Control Keys 5 AD

KeyIn Main/Sub SD Det 24
PAGE 02-12
MICROPROCESSOR DATA COMMUNICATION DESCRIPTION
Use this explanation in conjunction with the Microprocessor Data Communications circuit diagram.
The Microprocessor must keep in communication with the Chassis to maintain control over the individual cir-
cuits. Some of the circuits must return information as well so the Microprocessor will know how to respond to
different request.
The Microprocessor uses a combination of I2C Bus communication and the Serial Data, Clock and Load lines for
control. The I2C communication scheme only requires 2 lines for control. These lines are called SDA and SCL.
Serial Data and Serial Clock respectively.
The Microprocessor also requires the use of what are called Fan Out IC or DACs, (Digital to Analog Converters).
This allows the Microprocessor to use only two lines to control many different circuits.
Also, due to the fact that this Microprocessor operates at the new 3.3Vdc voltage, it requires a Level Shift IC to
bring up the DC level of the control lines to make it compatible with the connected ICs.
The Microprocessor communicates with the following ICs:
ON THE SIGNAL PWB:

Main Tuner U201
PinP Tuner U202
EEPROM I002
Flex Converter U205
DAC1 I003
DAC2 I004
Level Shift I014
3D Y/C U204
Main Video Chroma I201
ON THE TERMINAL PWB:

A/V Selector I401
Sub Video Chroma I403
ON THE DEFLECTION PWB:

Sweep Control I701
ON THE SUB VIDEO PWB (2H VIDEO):

Rainforest IX01
ON THE SURROUND PWB:

Front Audio Control IS03
Center/LFE (Low Frequency Effects) Audio Control IS08
Surround Board DAC3 IS01
Front Equalizer IS05
Center Equalizer IS10
Rear Audio Control IS11
Audio DSP (Digital Signal Processor) DSP Unit HC4051
The following explanation will deal with the communication paths used between the Microprocessor and the re-
spected ICs.
ON THE SIGNAL PWB:
Main Tuner U201
The Microprocessor controls the Main Tuner by Clock, Data and Enable lines.
Clock, Data and Enable lines for the Main Tuner are output from the Microprocessor at pins (20 Clock, 21 Data
and 44 FEENABLE1) respectively. Pin (44) FEENABLE1 goes directly to the Main Tuner at pin (6), where as
the Clock and Data lines must be routed through the Level Shift IC I014 to be brought up to 5V. Clock and Data
from the Microprocessor arrive at I014 (Level Shift) at pins (2 and 3) and are output at pins (18 and 17).
They arrive at the Main Tuner at pins (4 and 5).
PAGE 02-13
PinP Tuner U202

The only difference for the PinP tuner control lines is related to the PinP Enable line. This is output from the
Microprocessor pin (43 FEENABLE2) to the PinP Tuner at pin (17). Clock and Data are the same as for the
Main Tuner.
For further details about tuner operation, please see the Microprocessor Port Description and Circuit Dia-
gram.
EEPROM I002
The EEPROM is ROM for many different functions of the Microprocessor. Channel Scan or Memory List,
Customer set ups for Video, Audio, Surround etc… are memorized as well. Also, some of the Microprocessors
internal sub routines have variables that are stored in the EEPROM, such as the window for Closed Caption
detection.
Data and Clock lines are SDA1 from pin (2) of the Microprocessor to pin (5) of the EEPROM and SCL2 from
pin (3) of the Microprocessor to pin (6) of the EEPROM. Data travels in both directions on the Data line.
Flex Converter U205

The projection television is capable of two different horizontal frequencies. 31.5Khz for everything except HD
and 33.75Khz for HD. (High Definition). The Flex Converter is responsible for receiving any video input and
converting it to the related output. This output is controlled by sync and by the customer’s menu and how it is
set up. The set up can be 4X3 or 16X9 sometimes called letterbox. The Flex Converter can take any NTSC, S-
In, Component in in NTSC, Progressive, Interlaced, 480I, 720P, 1080I signal.
Control for the Flex Converter is Clock, Data and Enable lines.
Clock, Data and Enable lines for the Flex Converter are output from the Microprocessor at pins (20 Clock, 21
Data and 46 FCENABLE). FCENABLE Clock and Data lines must be routed through the Level Shift IC
I014 to be brought up to 5V. They arrive at I014 at pins (2 Clock, 3 Data and 4 FCENABLE) and are output
at pins (18, 17 and 16) respectively.
DAC1 I003
This Digital to Analog converter acts as an extension of the Microprocessor. Sometimes called an Expansion
IC. The purpose of this IC is to reduce the number of pins, (fan out) of the Main Microprocessor I001. The
Main Microprocessor send Clock and Data via I2C bus to the DAC1 IC. The output from the Microprocessor is
pin (2 SDA1 and 3 SCL1) which arrives at the DAC1 IC at pins (5 and 6) respectively.
The following is a list of the input and output pins on DAC1.
PIN FUNCTION
1 IR Det The IR pulse from the Remote Control is monitored when Auto Link is set. (See Auto Link in Index).
2 YN Det Active Low. This pin monitors for active sync when Auto Link is set. (See Auto Link in Index).
3 Blk Main Normal High, Blanking Low. Blanks Y-Cb/Cr into Flex Converter.
4 MTS Places the Main Tuner pin (21 mode) into MTS Stereo. If Tuner receiving MTS signal. See pin 10.
5 F Mono Places the Main Tuner pin (22 mono) into forced Mono Mode.
6 Ant Switches the antenna block into Antenna A or Antenna B when selected.
7 Blk Sub Normal High, Blanking Low. Blanks PinP Sub Y-Cb/Cr on Terminal PWB before going into Flex Converter.
8 Gnd Ground
9 SAP Det The Main Tuner outputs an SAP LED signal when SAP is detected. Active Low.
10 ST Det The Main Tuner outputs an ST LED signal when Stereo is detected. Active Low.
11 SAD0 Ground Not Used
14 SDA Data I2C communications between DAC1 and Microprocessor
15 SCL Clock I2C communications between DAC1 and Microprocessor
16 Vcc IC B+. (STBY +5V)
PAGE 02-14
DAC2 I004
pin (2 SDA1 and 3 SCL1) which arrives at the DAC2 IC at pins (5 and 6) respectively.
PIN FUNCTION
1 YUV Det1 Detects activity on Component Input number 1.
2 YUV Det2 Detects activity on Component Input number 2.
3 FH Det Out 1 Test Point 1 (TP1).
4 Sel5 Controls IX02 on 2H PWB. Selects either Y Cb/Cr or Y IQ to compensate for Chroma Phase angle used in Auto Color.
5 F Mono Places the Main Tuner pin (22 mono) into forced Mono Mode.
6 FH Det Out 1 Test Point 2 (TP2).
7 31/33 Notifies the DCU related to Horizontal Frequency. Either 31.5Khz for everything but HD or 33.75Khz for HD.
The DCU uses two sets of memory. One for everything but HD and one for HD. This relates to both Digital Convergence
adjustment data and for Magic Focus memory.
Also notifies the Dynamic Focus Horizontal Parabolic generator to compensate for phase distortion. Also, notifies I701
Horizontal Drive generation IC concerning the Horizontal operation frequency.
8 Gnd Ground
9 CS Sel Not Used.
10 Busy Informs the Microprocessor that the DCU is in the Digital Convergence Adjustment Mode. The Micro. Ignores IR pulses.
13 SAD2 IC B+. (STBY +5V).
14 SDA Data I2C communications between DAC2 and Microprocessor
15 SCL Clock I2C communications between DAC2 and Microprocessor
16 Vcc IC B+. (STBY +5V).
Level Shift I014

The Microprocessor operates at 3.3Vdc. Most of the Circuits controlled by the Microprocessor operate at 5Vdc.
The Level Shift IC steps up the DC voltage to accommodate.
3D Y/C U204
The 3D Y/C module is a Luminance/Chrominance separator, as well as a 3D adder. Separation takes place digi-
tally inside the module. Using advanced separation technology, this module separates and doesn’t produce dot
pattern interference or dot crawl. The 3D effect is a process of adding additional signals to the Luminance and
Chrominance. These signals relate specifically to transitions. Transitions are the point where the signal goes
from dark to light or vice versa. The 3D adds a little more black before the transition goes to white and a little
more white just before it gets to white. It also adds a little more white just before it goes dark and a little more
dark just before it arrives. This gives the impression that the signal pops out of the screen or a 3D effect.
The Microprocessor communicates with the 3D Y/C module via I2C bus data and clock. The communications
ports are from the Microprocessor pins (59 SDA2 and 60 SCL2) to the 3D Y/C PYC1 connector pins (2 and 3)
respectively.
The Microprocessor also is able to turn on and off circuits within the 3D Y/C module determined by customer
menu set-up.
Main Video Chroma I201

The Main Video Chroma IC processes the video and chroma from the 3D Y/C module for the main picture. It
converts video into Y and chroma into Cr/Cb (NTSC Only). Communication from the Microprocessor via pins
(59 SDA2 and 60 SCL2) to I201 pins (34 and 33) respectively.
PAGE 02-15
ON THE TERMINAL PWB:
A/V Selector I401
The A/V Selector IC is responsible for selecting the input source for the Main Picture as well as the source for
the PinP or Sub picture. Communication from the Microprocessor via pins (2 SDA1 and 3 SCL1) to the PST1
connector pins (5 and 6) respectively then to I401 pins (34 and 33) respectively.
Sub Video Chroma I403

The Sub Video Chroma IC processes the video and chroma for the Sub or PinP picture. It converts video into Y
and chroma into Cr/Cb (NTSC Only). Communication from the Microprocessor via pins (59 SDA2 and 60
SCL2) to connector PST1 pins (1 and 2) I403 pins (34 and 33) respectively.
ON THE DEFLECTION PWB:

Sweep Control I701
The Sweep Control IC is responsible for generating Horizontal Drive and Vertical Drive signals. The Micro-
processor must tell the IC when certain things are done in the Service Menu. When Cut Off is performed, the
Vertical is collapsed. The Microprocessor tells I701 to stop producing Vertical Drive. At the same time, I701
must stop the Spot Killer circuit from operating. This is accomplished by placing pin (24 DAC3) high which
activates QN07 which inhibits spot killer high.
Also, when H.Phase is adjusted, the Microprocessor controls the H. Drive signals phase in relationship to H.Blk
which is timed with video sync. This gives the appearance that the horizontal centering is being moved.
Communication from the Microprocessor via pins (59 SDA2 and 60 SCL2) to the PSD2 connector pins (2 and
3) and then to I701 pins (16 and 17) respectively.
ON THE SUB VIDEO PWB (2H VIDEO):

Rainforest IX01
The Video Processing IC (Rainforest) is responsible for controlling video/chroma processing before the signal
is made available to the CRTs. Some of the emphasis circuits are controlled by the customer’s menu. As well as
some of them being controlled by AI, (Artificial Intelligence).
Communication from the Microprocessor via pins (59 SDA2 and 60 SCL2) to the PSZ2 connector pins (1 and
2) and then to IX01 pins (27 and 26) respectively.
ON THE SURROUND PWB:

Surround Board DAC3 IS01
pins (59 SDA2 and 60 SCL2) then through the connector PSU1 pins (2 and 1) which arrives at the DAC3 IC at
pins (14 and 15) respectively.
PIN FUNCTION
1 SW Sel 1 Turns on/off QS01 which either adds or doesn’t add Sub Woofer to Front L and Front R for 3 way audio set up.
2 DSP CSI Digital Surround Module signal. If the Coax Audio input is noisy, the DSP tells DAC3 to 2X invert the signal.
3 Opti/Coax Sel Controls IS17. Determins if the signal is 2X inverted due to noise.
4 RSPOFF Turns off the Rear Speaker outputs. Controlled by the customer’s menu.
5 CSPOFF Turns off the Center Speaker outputs. Controlled by the customer’s menu.
6 FSPOFF Turns off the internal Front Speaker outputs. Controlled by the customer’s menu.
7 SWSEL 2 Controls QS25 to add Front Left and Right to Sub Woofer.
8 Gnd Ground
PAGE 02-16
9 P. Vol Perfect Volume On/Off controlled by the customer’s menu. Note, when in Pro-Logic mode, Perfect Volume is Off.
10 DSPREQ DSP Request Input.
14 SDA2 Data I2C communications between DAC3 and Microprocessor
15 SCL2 Clock I2C communications between DAC3 and Microprocessor
16 Vcc IC B+. (STBY +5V)
Front Audio Control IS03

The Front Audio Control IC has the ability to adjust balance, treble, bass, volume and mute. This mute is the
one that is activated when the mute button is pressed on the remote control.
Communication from the Microprocessor via pins (59 SDA2 and 60 SCL2) then through the connector PSU1
pins (2 and 1) which arrives at the IS03 at pins (4 and 5) respectively.
Center/LFE (Low Frequency Effects) Audio Control IS08

This IC has the ability to adjust balance, treble, bass, volume and mute for the Center channel. This mute is the
It also adjust the volume for the Sub Woofer called LFE (Low Frequency Effects).
Front Equalizer IS05

The Front Audio can be frequency adjusted to suite the particular room environment. The individual frequency
notches are adjusted via the customer’s menu. The following frequency notches are adjusted by this IC. 60HZ,
250HZ, 1KHz, 3KHz, and 10KHz.
Center Equalizer IS10

The Center Audio can be frequency adjusted to suite the particular room environment. The individual fre-
quency notches are adjusted via the customer’s menu. The following frequency notches are adjusted by this IC.
60HZ, 250HZ, 1KHz, 3KHz, and 10KHz.
Rear Audio Control IS11

The Rear Audio Control IC has the ability to adjust balance, treble, bass, volume and mute. This mute is the
Audio DSP (Digital Signal Processor) DSP Unit HC4051

The Digital Signal Processor is responsible for decoding Dolby Pro-Logic, AC-3 audio and selecting the output
of the audio determined by the customer’s menu. Such as Off, Matrix, Hall, etc…
Control for the DSP is routed from the Microprocessor pins (15 DSPSS DSP Surround Sound Mode, 16
DSPSCK DSP Clock, 17 DSPI DSP Mode 1, 18 DSPERR Mute DSP Error Mute, and 19 DSPRST DSP Re-
set). Then to the Level Shift IC I014 pins (5, 6, 8, 7, 9) respectively.
These signals are then routed to the PSU2 connector pins (5, 2, 3, 6, and 1) respectively to the DSP module via
the PMU1 connector pins (9, 12, 11, 8 and 13) respectively.
PAGE 02-17
DP0X CHASSIS MICROPROCESSOR DATA COMMUNICATIONS CIRCUIT DIAGRAM
PYC1
Sweep Control
3 SCL2 U204
PSD2 PSZ2 2H Video PWB
IOO1 I701 2 SDA2 3DY/C
2 16 SDA2
2 26 SCL2 IX01
1 17 SCL2 34 SDA2 I201 Rainforest
Main Video 1 27 SDA2 RGB Processor
Deflection PWB 33 SCL2 Chroma
SDA2 59
SCL2 60
PSU1
PST1
U201 Data 5 2
SDA2
4 IS03
SDA2
Enable Tuner 1 1 34 SDA2 I403 Front
Clock 4 SCL2
Sub Video 1 5 SCL2 Audio Control
FEENABLE1 44 6 Main 2 33 SCL2
Chroma
U202 Data 16 5 34 SDA1

Enable Tuner 2 I401 SDA2 IS05
Clock 15 6 33 SCL1 A/V Select 17
FEENABLE2 43 17 Pinp SCL2 Front
16 Equalizer
Terminal PWB
SDA1 2 5 SDA1 IOO2 SDA2

17 IS10
SCL1 3 6 SCL1 EEPROM
SCL2 Center
16 Equalizer
SDA1 14 15 SCL1 I004

I003
DAC1 SCL1 15 14 SDA1 DAC2
SDA2
IS11 4 IS08
SCL3 Center/LFE/
SCL3 58 3 5 Rear SCL2
5 Audio Control
SDA3 Audio Control
SDA3 57 4 4
PFC1
SDA2
Clock 20 2 18 10 Clock U205 14 IS01
FLEX SCL2 DAC3
Data 21 3 17 11 Data 15
&
FCENAble 46 4 16 12 Enable PinP
FCEN PSU2 PMU1
DSPSS 15 5
I014 15
DSPSS DSPSS
5 9
3.3V -> 5V DSPSCK DSPSCK
PAGE 02-18
DSPSCK 16 6 Level Shift 14 2 12 DSP

DSPERR Mute DSPERR Mute
DSPERR Mute 18 7 13 6 8 Unit
DSPI DSPI
DSPI 17 8 12 3 11 HC4051
DSPRST DSPRST Surround PWB
DSPRST 19 9 11 1 13
Signal PWB
DP-05 & DP-05F MICROPROCESSOR DATA COMMUNICATION Description
DP-05 and DP-05F DATA COMMUNICATIONS DESCRIPTION
Refer to the DP-05 and DP-05F Microprocessor Data Communication Circuit Diagram
The only difference between the DP-05 & DP-05F and the DP-06 or DP-07 Microprocessor Data Communication
Circuit Diagram is;
Rear or Center Audio, so the Serial Data Communications (SCL3 and SDA3) to the Rear Audio B+ isn’t
Used.
• The Data Communications to the Level Shift IC (I014) going to the (DSP) is not used.
• The Rear Audio IC, Center Audio IC and the Center Graphic EQ IC are not used.
• The Front Audio Control IC designation is (IA05).
• The DAC3 IC designation is (IA01).
PAGE 02-19
DP-05 and DP-05F CHASSIS MICROPROCESSOR DATA COMMUNICATIONS CIRCUIT DIAGRAM
PYC1
Sweep Control
3 SCL2 U204
PSD2 PSZ2 2H Video PWB
I701 2 SDA2 3DY/C
2 16 SDA2
2 26 SCL2 IX01
1 17 SCL2 34 SDA2 I201 Rainforest
Main Video 1 27 SDA2 RGB Processor
IOO1 33 SCL2 Chroma
Deflection PWB
SDA2 59
SCL2 60
PST1 PSU1
U201 Data 5 2
SDA2
4 IS03
I403 SDA2
Enable Tuner 1 1 34 SDA2
SCL2
Front
Clock 4 Sub Video 1 5 Audio Control
FEENABLE1 44 6 Main 2 33 SCL2 SCL2
Chroma
U202 Data 16 5 34 SDA1

Tuner 2 I401
Enable SDA2 IS05
Clock 15 6 33 SCL1 A/V Select 17
FEENABLE2 43 17 Pinp Front
SCL2
16 Equalizer
Terminal PWB
SDA1 2 5 SDA1
IOO2 SDA2
EEPROM 17 IS10
SCL1 3 6 SCL1 Center
SCL2
16 Equalizer
I003 SDA1 14 15 SCL1 I004

DAC1 DAC2
SCL1 15 14 SDA1 SDA2
14 IS01
SCL2 DAC3
15
PFC1
Clock 20 2 18 10 Clock U205

I014 FLEX Surround PWB
Data 21 3 3.3V -> 5V 17 11 Data
&
FCENAble 46 4 Level Shift 16 12 Enable PinP
FCEN
PAGE 02-20
Signal PWB
ON SCREEN DISPLAY (OSD) SIGNAL PATH DESCRIPTION
The Microprocessor is responsible for generating On Screen Display (OSD) related to the Main Menu, Volume
Control, Channel Number, Closed Caption Display, Clock, etc… It also generates the OSD for the Service Menu.
However there are actually two different sources for generating OSD, the Microprocessor and the Digital Conver-
gence Unit, (DCU).
MICROPROCESSOR AS THE SOURCE FOR OSD:

The Microprocessor receives information related to timing for H. Blanking and V. Blanking. These arrive at pins
(49 and 55) respectively. The Microprocessor determines the position for each display using these signals as a
timing pulse.
When it’s necessary, the Microprocessor generates 1uSec pulses from pins (37 Red, 38 Green and 39 Blue) that
are routed through the PSZ1 connector pins (14 Red, 16 Green and 18 Blue) and then through (QX07 Red,
QX08 Green and QX09 Blue) and then sent to the Rainforest IC IX01 pins (39 Red, 38 Green and 37 Blue) as
OSD signals. When the OSD signals are high, they turn on the output of the Red or Green or Blue chroma amps
inside the Rainforest IC and output a pulse to the CRTs to generate that particular character in the particular color.
HALF TONE PIN (40):

This pin is responsible for controlling the background transparency of the Main Menu. When the customer calls
up the Main Menu, they can select the CUSTOM section. Within the CUSTOM section is MENU BACK-
GROUND. There are three selections for this, GRAY, SHADED, and CLEAR.
• CLEAR: Selection turns off any background for the Menu and video is clearly seen behind the Menu.
• SHADED: Selection add a transparent background which makes the Menu easier to see and also some of the
video behind the Menu.
• GRAY: Selection generates a GRAY background for the MENU blocking video behind the Menu.
This is accomplished by outputting any one of three different pulses from pin (40) of the Microprocessor. This
signal is then routed through the PSZ1 connector pin (20) to the Rainforest IC IX01 pin (47) as YM signal which
does the following:
• CLEAR: No output during the display of the Menu.
• SHADED: 1/2 Vcc pulse equal to the timing of the Menu background.
• GRAY: Full Vcc equal to the timing of the Menu background.
OSD BLANKING PIN (51):

This pin is responsible for muting the video behind each character produced by the Microprocessor. This pulse is
in exact time with the character, however it is slightly longer. In other words, just before any character is pro-
duced, this pin goes high and just after any character turns off, this pin turns off. This clears up the video behind
the OSD character to make it easier to read.
OSD Blk is produced from pin (51) of the Microprocessor. This signal is then routed through Q013, then through
Q007, through the PSZ1 connector pin (19) to the Rainforest IC IX01 pin (36) as YS1 signal which mutes the
video.
P Blk PICTURE BLANKING PIN (56):

This pin is responsible for muting the video when the Microprocessor deems it necessary. This would be during
power up or power off, child lock, channel change, or selecting a video input with no video input available.
P Blk is produced from pin (56) of the Microprocessor. This signal is then routed through Q007, through the
PSZ1 connector pin (19) to the Rainforest IC IX01 pin (36) as YS1 signal which mutes the video.
CLOSED CAPTION DISPLAY FROM THE MICROPROCESSOR SOURCE:

The Microprocessor is also responsible for stripping the Closed Caption Display (CCD) from within the Vertical
Sync on horizontal line 21. It receives the composite video signal at pin (28). This signal is tapped off the main
video path before it arrives at I005 pin (5). See Video Path Circuit Diagram and Explanation for Details. The
tapped video is routed through Q021 to the Microprocessor at pin (28). See Sync Signal Path Circuit Diagram
and Explanation for Details.
PAGE 02-21
ON SCREEN DISPLAY (OSD) SIGNAL PATH DESCRIPTION
DCU AS THE SOURCE:
The DCU (Digital Convergence Unit) generates it’s own OSD patterns and text. The DCU generates these
characters in the same fashion as the Microprocessor. The DCU generates Digital Red from pin (11), Digital
Green from pin (12) and Digital Blue from pin (10) output from the PDG and then through (QK06 Dig Red,
QK07 Dig Green and QK08 Dig Blue). The DCU characters are then routed through the PSD1 connector pins
(2 Red, 4 Green and 6 Blue) and then through (QX01 Red, QX02 Green and QX03 Blue) and then sent to
the Rainforest IC IX01 pins (35 Analog Red In, 34 Analog Green In and 33 Analog Blue In) as Digital Con-
vergence graphic signals.
When the DCU is activated by pressing the Service Only switch on the Deflection PWB, the DCU outputs a
BUSY signal. This signal does two things.
1. It tells the Microprocessor to ignore Infrared Remote commands. It does this by outputting the BUSY sig-
nal from pin (10) of the PDG connector and then through the PSD1 connector pin (1). Then to I004 the
Analog to Digital converter. The Analog to Digital converter outputs this information in digital form
through the I2C bus to the microprocessor. The I2C data is output from pin (14 SDA1 and 15 SCL1) and
arrives at the Microprocessor I001 pins (2 and 3). When the Microprocessor receives this BUSY signal, it
ignores all Infrared Remote commands.
2. It blanks video so that the DCU graphics can be see easily. This is accomplished by the same BUSY signal
being routed from pin (10) of the PDG connector and then through the PSD1 connector pin (1). It is then
routed through the PSZ1 connector pin (7) to the Rainforest IC IX01 pin (32) as YS2 signal which mutes
video.
GRAPHICS PRODUCED BY THE DCU:

• Cross hatch grid.
• Colored Cursor which blinks indicating the adjustment point
• Different text such as, Read from ROM?, Write to ROM?
• Light pattern for Sensor Initialization
• Light pattern for Magic Focus.
• The DCU can also turn off individual colors during adjustment. Everything except Green. This is accom-
plished by not producing the particular color’s characters from the DCU.
PAGE 02-22
DP-0X CHASSIS "On Screen Display, OSD" SIGNAL CIRCUIT DIAGRAM
Signal PWB I001 IX01

Main uP PSZ1 Rainforest
Sync for Closed Caption QX09
28 Main
39 OSD Blue
18 QX08 37
and V-Chip Data OSD B Analog B In
Sync2 for Closed Caption OSD Green
30 Sub OSD G 38 16 QX07 38 Analog G In
and V-Chip Data OSD Red
OSD R 37 14 39 Analog R In
SCL1 OSD YM
I004 15 3 Half Tone 40 20 47 YM
SDA1 Q007 PZC
DAC2 14 2 P Blk 56
OSD YS
19 36 YS1
Q013 QX41
10 B Out 41 5 B
OSD Blk 51
To CRTs
BUSY QX36
G Out 42 3 G
PDG PSD1 QX31

R Out 43 1 R
BUSY
10 1 7 32 YS2
QK08 QX03
UKDG Dig B
13 26 12 33 Analog B In
HC2151 QK07 QX02
Dig G
12 4 10 34 Analog G In
QK06 Dig R QX01
11 26 8 35 Analog R In
Digital
Convergence 1 -5V
Unit 2
"DCU" 3 +5V Signal SUB PWB
"Mounted on 4 +5V SRAM
Deflection 5 H Blk
PWB" 6 D Size
7 V Blk
PAGE 02-23
Deflection PWB
AUDIO and VIDEO MUTE SIGNAL PATH DESCRIPTION
V MUTE 1 EXPLANATION:
There are certain times when the Microprocessor or other circuits must Mute the video or audio. The Microproc-
essor is responsible for Muting the Audio/Video during Channel Change, Power On/Off, Child Lock, AVX Se-
lected with no input, etc….
This is accomplished via pin (45) of the Microprocessor. When V Mute is activated, a high is routed through
D028 to the base of Q022 turning it ON. The collector goes low and pulls the base of Q023 low turning it ON.
The emitter of Q023 is connected to STBY +11V, so when it turns ON, it’s collector output goes HIGH. This
high is now called V Mute 1. V Mute 1 is routed to two circuits, for Video Mute and for Audio Mute.
FOR VIDEO MUTE:

There are three different signals that mute video on the Rainforest IC, IX01 pin (25 FBP In):
1. V Mute 1 high is routed through the PSZ2 connector pin (6) to DX08. DX08 sends this high to the base
of QX18 turning it OFF. The emitter of QX18 is connected to the SW +9V line and when it turns OFF
the emitter pulls up HIGH. This pulls up pin (25) of IX01 the rainforest IC and Mutes the Video. Oddly
enough, this high is sent into the same pin as the Flyback Pulse used for horizontal blanking. So it can be
thought of as an extremely long blank pulse.
2. H Blk FC which is generated by the Flex Converter U205 at pin (12 H.BLK). This positive going blank-
ing signal generated in time with Horizontal Sync from the main picture is routed through the PSZ2 con-
nector pin (12) to DX09 to the base of QX18 turning it OFF with each positive going pulse. The emitter
of QX18 is connected to the SW +9V line and when it turns OFF the emitter pulls up HIGH. This inputs
positive horizontal blanking signals into pin (25) of IX01 the rainforest IC and Mutes the Video. This
signals is used for horizontal blanking.
3. V Blk FC which is generated by the Flex Converter U205 at pin (11 V.BLK). This positive going blank-
ing signal generated in time with Vertical Sync from the main picture is routed through the PSZ2 con-
nector pin (13) to DX10 to the base of QX18 turning it OFF with each positive going pulse. The emitter
of QX18 is connected to the SW +9V line and when it turns OFF the emitter pulls up HIGH. This inputs
positive vertical blanking signals into pin (25) of IX01 the rainforest IC and Mutes the Video. This sig-
nals is used for vertical blanking.
V Mute 1 FOR AUDIO MUTE:

The V Mute 1 signal is also routed to the base of Q024 turning it ON. The high produced on it’s emitter is now
called V Mute 2 which is routed to two places.
1. To the anode of DC04, to the base of QC03 which turn ON and grounds pin (11) of IC01 placing the
Front Audio output IC into Mute.
2. To PSU1 connector pin (14) which mutes the Center and Rear audio output ICs. See the Surround Mute
Circuit diagram and explanation for details.
ERRMUTE pin (18) of the Microprocessor:

When the Microprocessor deems it necessary to mute the audio, it outputs a ERRMute signal from pin (18) to
I014 pin (7) the Level Shift IC. This IC outputs the high from pin (13) to three places;
1. To the Audio DSP circuit via the PSU2 connector pin (6) to mute the internal functions of the DSP.
See the Surround Mute Circuit diagram and explanation for details.
2. To the Surround PWB via the PSU1 connector pin (7) called Mute. Here the audio outputs for out to
Hi-Fi, Transmitter out and Sub woofer are muted.
See the Surround Mute Circuit diagram and explanation for details.
3. To the anode of DC01, then to the base of QC01 and QC02 which grounds the audio input to pin (4
Right audio in and 2 Left audio in) of IC01.
PAGE 02-24
AUDIO and VIDEO MUTE SIGNAL PATH DESCRIPTION
F.Spk Off FRONT SPEAKER OFF:
When the customer accesses the Main Menu and selects the Front Speaker Off selection, DAC IS01 on the Sur-
round PWB outputs a high from pin (6), see the Surround Mute Circuit diagram and explanation for details.
This high is routed through the PSU1 connector pin (6) to the anode of two diodes;
1. To the anode of DC03, to the base of QC03 which turn ON and grounds pin (11) of IC01 placing the
Front Audio output IC into Mute.
2. To the anode of DC02, then to the base of QC01 and QC02 which grounds the audio input to pin (4
Right audio in and 2 Left audio in) of IC01.
AC LOSS DETECTION:
AC is monitored by the AC Loss detection circuit. The AC input from PQS1 pin (10) is rectified by DN09.
This charges up C009 and through DN08 it charges C008. When AC is first applied, C008 charges slightly be-
hind C009 preventing activation of Q001. If AC is lost, C009 discharges rapidly pulling the base of Q001 low,
however DN08 blocks C008 from discharging and the emitter of Q001 is held high. This action turns on Q001
and produces a high. This high is routed through D029 to the base of Q022 turning it ON. The collector goes
low and pulls the base of Q023 low turning it ON. The emitter of Q023 is connected to STBY +11V, so when
it turns ON, it’s collector output goes HIGH. This high is now called V Mute 1. V Mute 1 is routed to two cir-
cuits, see V Mute 1 explanation on the previous page.
SPOT:
SPOT is generated from the deflection PWB when either Horizontal or Vertical deflection is lost. This is to pre-
vent a horizontal or vertical line from being burnt into the CRTs. See Horizontal and Vertical Sweep Loss De-
tection circuit and explanation for details. This high is input from PSD2 pin (6), through D027 to the base of
Q022 turning it ON. The collector goes low and pulls the base of Q023 low turning it ON. The emitter of Q023
is connected to STBY +11V, so when it turns ON, it’s collector output goes HIGH. This high is now called V
Mute 1. V Mute 1 is routed to two circuits, see V Mute 1 explanation on the previous page.
PAGE 02-25
DP-0X Series Chassis AUDIO and VIDEO MUTE Circuit
(See also Surround Mute Circuit)
SBY +11V
"SPOT" R198 D031
From I904 Horizontal Sweep Loss Det.
Pin 3 Vertical Sweep Loss Det. D030
AC Photo C070
(From Deflection PWB)
Coupler R190 R191 Q023 2H Video PWB
AC Sig 10V p/p
Q001
2 PSD3 Q024 SW+9V
PQS1 R192 PSZ2
Q022 RX52 IX01
10 R010
R195 DX10
RN15
R008
D027 R193 V Blk FC

R196 13 RX57
R011
D029 R194 H Blk FC DX09 25 FBP

DN09 DN08 V Mute 1 12 In
C008
V. Mute 1 DX08
R007 6
C009
D028 QX18
Micro Processor
Signal PWB V Mute 2
I001 R029
V MUTE 45 A5V
ERRMute 18 7 I014
Level Shift
PSU2 DC04 Mute = Lo
13 QC03 RC09 IC01
DC03 RC07 11 Mute
Audio 6
DSP ERR Mute FRONT
CC09
PSU1 RC08 L&R
CC08 Audio
VMute
V Mute 2
14 Output
Right Ft. Audio CC02 CC04
9 4 R In R Out 7
Left Ft. Audio CC01
8 2 L In L Out 12
PAGE 02-26
F. Spk Off DC02 RC03 QC01 CC03

From IS01 Pin 6 6 QC02
ERRMute RC04
Mute 7
DC01
Surround PWB
DP-05 & DP-05F AUDIO and VIDEO MUTE SIGNAL CIRCUIT DESCRIPTION
DP-05 and DP-05F AUDIO and VIDEO MUTE SIGNAL CIRCUIT DESCRIPTION
Refer to the DP-05 and DP-05F Audio and Video Mute Circuit Diagram
The only difference between the DP-05 & DP-05F and the DP-06 or DP-07 AV Mute Circuit Diagram is;
Rear or Center Audio, so the Mute to the Rear and Center Audio ICs isn’t Used.
• The (DSP) is not used. So ERRMUTE isn’t routed to the Surround PWB DSP module.

PAGE 02-27
DP-05 and DP-05F Series Chassis AUDIO and VIDEO MUTE Circuit
(See also Surround Mute Circuit)
SBY +11V
"SPOT" D031
From I904 R198
Horizontal Sweep Loss Det.
Pin 3 Vertical Sweep Loss Det. D030
AC Photo C070
(From Deflection PWB)
Coupler R190 R191 Q023 2H Video PWB
AC Sig 10V p/p
Q001
2 PSD3 Q024 SW+9V
PQS1 R192 PSZ2
Q022 RX52 IX01
10 R010
D027 R193 R195 V Blk FC DX10
RN15
R008
R196 13 RX57
R011
D029 R194 H Blk FC DX09 25 FBP

DN09 DN08 C008 V Mute 1 12 In
V. Mute 1 DX08
R007 6
C009
D028 QX18
Micro Processor
Signal PWB V Mute 2
I001 R029
V MUTE 45 A5V
ERRMute 18 7 I014
Level Shift
DC04 Mute = Lo
13 QC03 RC09 IC01
DC03 RC07 11 Mute
ERR Mute
FRONT
CC09
PSU1 RC08 L&R
CC08 Audio
V Mute 2
VMute
14 Output
Right Ft. Audio CC02 CC04
9 4 R In R Out 7
Left Ft. Audio CC01
8 2 L In L Out 12
PAGE 02-28
F. Spk Off DC02 RC03 QC01 CC03

From IA01 Pin 12 6 QC02
ERRMute RC04
Mute 7
DC01
SRSPWB
SURROUND PWB MUTE SIGNAL PATH DESCRIPTION
V Mute 2 FOR SURROUND MUTE:
The V Mute 1 signal explained in the Audio Video Mute signal path explanation is also routed to the base of
Q024 turning it ON. The high produced on it’s emitter is now called V Mute 2 which is routed to the Surround
PWB via the PSU1 connector pin (14). V Mute 2 is labeled VMute on the Surround PWB. This high arrives at
the anode of the following diodes;
1. DS27 which puts a high on the base of QS06 turning it ON which grounds pin (11) of IC15 placing the
Center Audio output IC into Mute.
2. DS49 which puts a high on the base of QS20, turning it ON. This grounds the Sub Woofer audio output.
3. DS45 which puts a high on the bases of QS17 and QS16. Turning them ON. This grounds the Out to Hi-
Fi outputs.
4. DS37 which puts a high on the base of QS10, turning it ON. This grounds the Rear audio output
ERRMUTE PIN 7 of the PSU1 CONNECTOR:

The ERRMute signal explained in the Audio Video Mute signal path explanation is routed to the Surround PWB
via the PSU1 connector pin (7). See the Audio Video Mute Signal Path explanation and diagram for details con-
cerning the generation of the ERRMute signal.
ERRMute is labeled Mute on the Surround PWB. This high arrives at the anode of the following diodes;
1. DS24 which puts a high on the base of QS04 and QS05 turning them ON. This grounds the audio input
to the Center audio output IC, IS15 at pins (4 and 2).
2. DS48 which puts a high on the base of QS20, turning it ON. This grounds the Sub Woofer audio output.
3. DS44 which puts a high on the bases of QS17 and QS16. Turning them ON. This grounds the Out to Hi-
Fi outputs.
to the Rear audio output IC, IS16 at pins (4 and 2).
ERRMUTE PIN 14 of the PSU2 CONNECTOR:

The ERRMute signal explained in the Audio Video Mute signal path explanation is routed to the Surround PWB
via the PSU2 connector pin (6). ERRMute places the DSP Audio Module into Mute when the Microprocessor
deems it necessary. See the Audio Video Mute Signal Path explanation and diagram for details concerning the
generation of the ERRMute signal.
RSpkOff (REAR SPEAKER OFF) IS01 PIN 4:

The Rear Speaker Off signal is output from IS01 pin (4). This high arrives at the anode of the following diodes;
Rear Audio output IC into Mute.
CSpkOff (CENTER SPEAKER OFF) IS01 PIN 4:

The Center Speaker Off signal is output from IS01 pin (5).
This high arrives at the anode of the following diodes;
Center Audio output IC into Mute.
FSpkOff (FRONT SPEAKER OFF) IS01 PIN 6:

The Front Speaker Off signal is output from IS01 pin (6). This high is routed out the PSU1 connector pin (6)
and sent to the Signal PWB into the V Mute Circuit. See the Audio Video Mute Circuit Signal Path Explanation
and Diagram for more details.
PAGE 02-29
DP-0X Series Chassis SURROUND MUTE Circuit
(See also Audio Video Mute Circuit)
PSU2 PMU1
Surround
ERR Mute 6 8 DSP
Module
PSU1 IS01 Mute = Lo

QS06 RSF7 IS15
DS27 RSF5 11 Mute
VMute
F. Spk Off 6 6 F. Spk Off
CSK01 CENTER
DS26 RSF6
CSJ9 Audio
CSpkOff 5
Output
RSpkOff
CENTER CSJ2 CSJ4
4 4 C In C Out 7
DS25
VMute CSJ3
2 C In C Out 12
V Mute 2 14
RS03 QS04 CSJ5
QS05
Mute Mute DS24 RS04
ERRMute 7
RSpkOff
Mute = Lo
QS10 RSJ9 IS16
Sub Woofer DS49 DS37 11 Mute
RSJ7
CSM9 REAR
QS20 SD50 DS36 RSJ8
DS48 CSM8 Audio
Output
REAR R CSM1 CSM3
HiFi L
DS35 4 R In R Out 7
DS45 CSM2
REAR L
QS17 SD47 2 L In L Out 12
RSJ6 QS09 CSM4
QS08
DS44
PAGE 02-30
HiFi R RSJ5
Mute
QS16 SD46 DS34
DP-05 and DP-05F SRS MUTE SIGNAL CIRCUIT DESCRIPTION
DP-05 and DP-05F SRS MUTE SIGNAL CIRCUIT DESCRIPTION
Refer to the DP-05 and DP-05F SRS Mute Circuit Diagram
The only difference between the DP-05 & DP-05F and the DP-06 or DP-07 AV Mute Circuit Diagram is;
• The DP-05 and the DP-05F doesn’t have the DSP Module. Therefore, it uses a SRS Surround PWB. There is
no Rear or Center Audio, so the Mute to the Rear and Center Audio ICs isn’t Used.
• The (DSP) is not used. So ERRMUTE isn’t routed to the Surround PWB DSP module.

PAGE 02-31
DP-05 and DP-05F Series Chassis SRS MUTE Circuit
(See also Audio Video Mute Circuit)
PSU1 IA01
F. Spk Off 6 12 F. Spk Off
SCL2 1 2 SCL
HiFi L
SDA2 2 3 SDA
QA11
VMute DA08 DA11
V Mute 2 14
HiFi R
DA04 DA16
QA12
Mute
ERRMute 7
PAGE 02-32
DP-0X MEMORY INITIALIZATION PROCEDURE
(EEPROM RESET)
WARNING: This should only be done in extreme cases. I2C Data will be reset as well.
Be sure and write down all data values before continuing.
Ø Disconnect Power to Television.

Ø Remove the Back Cover.
Ø Remove the two screws holding the Main chassis to the Cabinet if necessary.
Ø Disconnect wiring harness clips to free up the chassis if necessary.
Ø Reconnect Power to the Television and turn the set ON.
Ø Locate PP1 and add a jumper between pins 1 and 2 of the PP1 connector as shown below.
Ø Hold jumper in place for 5 seconds. (A beep will NOT be heard).
Ø Remove the jumper.
Ø Confirm EEPROM reset, Input source is now set to Air and not to Cable 1 or 2. No Child
Lock, and only channels 2 through 13 are in memory.
Ø Reassemble Chassis and reinstall PTV back. Set is now ready to operate.
NOTE: All customers' Auto Programming and Set-Ups are returned to factory settings.
Jumper 3.3V
1 2 PP1 Connector R1E4

D024
R100
7 20
KEY-IN1 CLOCK
I001
MicroProcessor
PAGE 02-33
MEMORY SWITCH SETTINGS ON SET FROM FACTORY
To Access Service Menu, press and hold INPUT then POWER
NTSC SIGNAL INPUT
PAGE 01 PAGE 02
ADJUST MODE HP DP062b TA1300 NTSC
Sub Brit H Posi 30
Service
FLEX CONT
Def Reset 47 VD-Pos 3F
V/P Reset UPD64081
3DYC Reset DYGA 09
Flex Reset DCGA 06
DSP Reset VAPGA 05
CCD Reset VAPIN 0B
Fact Reset YHCOR 00
Mem Init
PAGE 03 PAGE 04
TA1270-M FLEX CONT NTSC
TINT (TV) 3C 39 HHPF1 00
TOFFO (TV) 00 41 V-CRG 00
TOFQ 00 42 H-CRG 00
Sub CNT 0F 43 V-ENH 00
Sub Clr 1B 44 H-ENH 00
96 YVHENH 0B
100 CVHENH 12
PAGE 05 PAGE 06
FLEX CONT NTSC FLEX CONT NTSC
71 YV-ENH 00 97 YV NLP 00
79 CV-ENH 00 98 YH NLP 0A
87 YH-ENH 07 101 Y-LMT FF
94 CH-ENH 0F 83 YH FTQ 00
66 YV-DSB 00 91 CY FRQ 02
75 CV-DSB 00 70 YV LTI 00
82 YH-DSB 00 78 CV CTI 00
90 CH-DSB 00 86 YH LTI 01
68 YV-CLP 00 93 CH CTI 01
84 YH-CLP 00
PAGE 07 PAGE 08
69 YVDSBC 00 65 YNRRDC 00
77 CVDSBC 00 74 CNRRDC 00
85 YHDSBC 00 67 YNR-DC 00
92 CHDSBC 00 76 CNR-DC 00
95 Y-CRG 00 81 YNR-O 00
99 C-CRG 00 89 CNR-O 00
64 YNR-IN 04 45 CB-BLK 07
73 CNR-IN 04 46 CR-BLK 07
80 YNRPAS 00 27 FRMBRT 60
88 CNRPAS 02 102 CLPOUT 7F
PAGE 02-34
PAGE 09 PAGE 10
10 MPLL-S 0F 23 V-POS 1F
17 SPLL-S 0F 24 VSIZ 7F
12 MPLL-E 0F 50 HD-POS 3F
19 SPLL-E 0F 48 VBLK-T 7F
11 MVW-PH 05 49 VBLK-B 7F
18 SVW-PH 05 51 HBLK-R 7F
14 MHS-HP 0F 52 HBLK-L 7F
21 SHS-HP 0F 40 READ-F 10
13 MY-CLP 03
20 SY-CLP 03
PAGE 11 PAGE 12
35 FRMTOP-2 07 120 TV/CINE 01
FRMTOP-L 07 121 T/C DET 07
36 FRMBTM-2 07 122 T/C UNL 01
FRMBTM-L 07 123 T/C LCK 03
37 FRM RGT 07 126 T/C ARE 05
38 FRM LFT 07 127 T/C CBR 07
59 BS-TOP 07 128 T/C YBR 07
60 BS-BTM 07
61 BS-RGT 07
62 BS-LFT 07
PAGE 13 PAGE 14
TA1298 NTSC TA1298 NTSC
SHARP 0C COLOR 40
APACON 06 TINT 45
YNR 00 R-Y PH 02
R/B GH 01
G-Y PH 00
G/B GH 00
Color System
00
PAGE 15 PAGE 16
TA1298 NTSC TA1298 NTSC
RGB BRT 50 CLRG 00
RGB CNT 50 CLT 00
G DRV (W) 39 YOUTG 00
B DRV (W) 2D YGPNT 00
SUB CLR 10 S TRK 00
SUB CNT 1F RGBG 00
VSM PH 05 DC PNT 00
VSM GA 00 DC RAT 00
OS ACL 01 DC LMT 00
RGB ACL 00
PAGE 02-35
PAGE 17 PAGE 18
TA1298 NTSC V CHIP RATINGS
BSP 03 POLLING 0F
APL/BS 00 TIMEOUT 05
B COR 01 STATUS 02
B GA 00
B DET 00 AFC/CLOCK TEST
DABL PN 00
DABL GA 07
ABL PN 07
ABL GA 05
PAGE 02-36
DP-0X SERIES CHASSIS DAC 1 and DAC 2 INFORMATION
16 Vcc
IR Det 1 Detects IR from Remote for Auto Link Remote Set Up
8 Gnd
YN Det 2 Detects the presents of Luminanace Sync from the Main Signal Path Active Low
11 Not Used
Blk Main 3 Inputs Blanking for Main Signal to the Flex Converter
12 Not Used
MTS 4 Places the Main Tuner into MTS mode if Stereo MTS Detected by Microprocessor
13 Not Used
F Mono 5 Places the Main Tuner into Forced MONO mode
ANT 6 Switches the Antenna Switch Assembly from Antenna 1 to Antenna 2
Blk Sub 7 Inputs Blanking for Sub Signal to the Flex Converter
SAP Det 9 Receives the Low from the Main Tuner indicating SAP signal received.
ST Det 10 Receives the Low from the Main Tuner indicating Stereo signal received.
I003 SDA 14 Serial Data from Microprocessor
DAC1 SCL 15 Serial Clock from Microprocessor
16 Vcc
YUV/Det1 1 Detects Component 1 input activity
8 Gnd
YUV/Det2 2 Detects Component 2 input activity
11 Not Used
FH Det 3 Not Used
12 Not Used
SEL5 4 Select 5 output. Controls Chromal Rotation Switch IX02 on 2H Video PWB. Hi = NTSC Lo = Y Cr/Cb
13 Not Used
31/33 5 Output Deflection Frequency Control 31.5 kHz or 33.75 kHz.
FH Det 2 6 Not Used
G Power 7 Not Used
C/S Sel 9 Not Used
PAGE 02-37
Busy 10 Receives Busy from DCU stopping Microprocessor from responding to Remote commands.
I004 SDA 14 Serial Data from Microprocessor
DAC2 SCL 15 Serial Clock from Microprocessor
POWER SUPPLY
INFORMATION
SECTION 3
POWER SUPPLY ON AND OFF (STAND-BY) OPERATION EXPLANATION
Use the DP-0X Series Power On and Off Diagram along with this explanation:
The power supply in the DP-0X chassis works very similar to the previous models, with only a few exceptions.
This power supply runs all the time when the AC is applied. The use of the power supply creating Stand By Volt-
age supplies eliminates the need for a Stand-By transformer. The following explanation will describe the Turning
ON and OFF of the projection television.
The Microprocessor I001 generates the ON-OFF control signal from pin (53). The logic states of this pin are
High = On and Low = Off. When the set is turned On, the high from pin (53) is routed to the Relay Driver Q002
base. This turns on Q002 and it’s collector goes low.
This On/Off from the Relay Driver Q002 will perform the following :
• Turns on the SW5+V I907 and SW+12V I908 regulators. Which do not operated in Standby.
• Turns on the Shut Down “Power Shorted” detection circuit, Q908 and Q909.
• Turns on the Horizontal Vcc supply to the Horizontal and Vertical drive IC, I701.
• Turns on the Relay providing AC to the Deflection Power Supply on the Power/Deflection PWB.
TURNING ON and OFF THE HORIZONTAL DRIVER B+ CIRCUIT: (See Figure

When the power supply goes into Stand-By mode (TV Off), the Horizontal Drive signal for deflection is shut off.
This is accomplished by Q002 and QP04. The Low produced from the Power On/Off pin (53) of the Microproc-
essor is inverted by Q002 located on the Signal PWB. This High is sent through the PQS1 connector pin (8) to
the Sub Power Supply PWB and then through PQD2 connector pin (1) and sent to the Deflection PWB. This
High is detected by the base of QP04 turning it Off and the SBY +11V connected to the emitter is not available
at the collector. The collector is routed through DP35 and DP36 and connected to the Deflection B+ pin of the
Horizontal and Vertical Drive IC, I701 at pin (8). This action stops I701 from producing a horizontal deflection
drive signal.
Signal PWB SBY +11V PQD2 Deflection PWB I701

I001 PQS1 To Horz.Drive
H/V Driver IC
3 Transistor QH01
Power Q002 OFF = High QP04
On/Off C On = Low B E 15 Hoz. Out
53 8 1
B C DP36
OFF = Low
8 Def.B+
On = High DP35
Sub Power C705
Micro Supply PWB Figure 1
PAGE 03-01
Continued From Previous Page
POWER SUPPLY OPERATIONAL FREQUENCY DURING STAND-BY: (See Figure 2)

When the Horizontal deflection is defeated, the power supply no longer has a deflection load. This low current
demand is detected by the three resistors connected to the source of the internal Switch MOS FET inside I901
via pin (2). Pin (1) of I901 is the over current detection pin, however it is also the current demand sensing pin.
When the current demand is low due to horizontal defeat, pin (1) will be less than 1.4V and the internal fre-
quency will switch to 200Khz. This is caused by the Quasi Resonant circuit operation.
This reduction of power supply frequency will move the frequency above the Bell of the power supply trans-
former and all secondary voltages will reduce to approximately 1/2 of their normal voltage.
Due to the fact that the power supply is still operating at 1/2 voltage output, the Green LEDs used for visual
trouble sensing will reduce in intensity, however they will remain lit. With the exception of the SW+12V and
SW+5V regulator. Which are turned off in Stand By. See Figure 2.
28V Line Power Supply

R947 Driver & Output IC
Cold Gnd. Hot Gnd.
I901 Raw B+
R946 R948
I902 3 150V
2 Regulation 3 Freq. Control &
Q902 Photocoupler Inhibit PC Line 2
D923 R918
1 R919
R920
0.22
R912 each
Normal Freq. 80 ~ 100KHz

Pin 4 > 1.4V = Normal
Pin 4 < 1.4V = 200KHz.
Figure 2
SW+12V AND SW+5V REGULATOR OPERATION IN STAND-BY: (See Figure 3)
Both of these ICs as well as the STY+11V and the STY+7V regulators are DC to DC converters just like last
year. This is because of the wide range of input voltages from Stand-By to Normal operation of the Power Sup-
ply.
The SW+12V regulator (I908) and the SW+5V regulator (I907) are shut off during Stand-By mode. This is
accomplished by Q002 and Q903. The Low from the Power On/Off at pin (53) of the Microprocessor is in-
verted by the relay driver Q002 to a High and routed through the PQS1 connector pin (8). It is detected by
Q903 base.
The collector will go Low and pull pin (5) of I907 and I908 Low, turning off the two DC to DC converters.
I001 Micro +28V 1 I908 2 SW+12V

A9.65V
PQS1 R937 5 SW+12V Reg 3
ON = Hi
3.3V Q002 Q903 0V
Power
On/Off
53 8 5 I907 2 SW+5V
R951 SW+5V Reg
1 3
OFF = Lo
0V Figure 3
PAGE 03-02
Continued From Previous Page
SOME SHUT-DOWN DETECTION CIRCUITS SHUT OFF DURING STAND-BY: (See Figure 4)
During Stand-By, all of the secondary voltages produced by the Switching Transformer (T901) are reduced to
approximately 50% of their normal voltage, except the STBY voltages after regulation. This could cause a po-
tential problem with the Short Detection circuits for shutdown. To avoid accidental shut down, Q903 also con-
trols the activity of Q908 and Q909. During Stand-By, the output from the Microprocessor On/Off pin (35) is
Low. This Low is inverted by Q002 and this High is routed to the base of Q903 turning it On. This allows the
Base of Q908 to be pulled Low through D945. This action turns off Q908. When Q908 is off, it doesn’t supply
emitter voltage to the collector of Q909. The base of Q909 is connected to 6 Low Detection inputs, (See the
Sub Power Supply Shut Down Circuit explanation and diagram for further details). When the power supply
operates at 50%, the Short Detection circuit could activate. By turning off Q909, no accidental shut down op-
eration can occur.
D945
I001 Micro R957

PQS1
Q002 Q903 Power/Deflection PWB
Power R951 C948
35 8
On/Off R958
On = Lo R950 Q908 Q909 To Gate of
Off = Hi D946
+28V
Q914
Shutdown
R959
6 Shutdown Inputs, SCR
Active Low C949
Figure 4
TURNING ON THE DEFLECTION POWER SUPPLY: (See Figure 5)
When the Projection Television is turned On, the Microprocessor outputs a high from Pin (53) which is in-
verted by Q002. This Low is routed through the connector PQS1 pin (8) on the signal PWB to the Sub Power
Supply PWB. This Low is routed to Q903s Base and its collector will go High. This will pull up pin (5) of I907
and I908, turning ON the two DC to DC converters. The output of both DC to DC converters I907 and I908,
are used by the relay which supplies AC voltage to the Deflection Power Supply on the Power/Deflection
PWB.
The output of I907 SW+5V Regulator supplies B+ for pin (3) of the relay S901.
The output of I908 SW+12V Regulator drives the base of Q911 turning it On and grounding pin (4) of the re-
lay S901.
The relay now provides AC to the bridge rectifier on the Deflection Power Supply.
Power/
S-901 Def. Power Sub Power Supply PWB
Deflection PWB AC In Supply Relay
I001 PQD1 SW+5V
Micro-
processor 2 3
AC for Def. Power 1
Supply Q911
Power
2 1 4
On/Off SW+12V
53 PQS1
1 I908 2 SW+12V
ON = Hi D928
+28V SW+12V Reg IC
OFF = Lo 5 3
Q903
Q002
R951
8 5 I907 2 SW+5V
D948
1 SW+5V Reg IC 3
Signal PWB Off On Figure 5
PAGE 03-03
DP-0X SERIES "POWER ON & OFF" DIAGRAM
AC In
PQD1 SW+5V
OV in STBY
I001 2 3
AC for Def. 1
Microprocessor Power Supply Q911
VDD Power 2 1 4
OV in STBY
Reset SW+12V
3.3V On/Off
Power/ S-901 Def. Power 25.25V
61 54 53 PQS1 Deflection PWB Supply Relay 25.96V
1 I908 2 SW+12V
ON = Hi D928
+28V SW+12V Reg IC
OFF = Lo 5 3
Q903 OV in STBY
3.3V 3.3V Q002 Off On
2.35V
R951 5.78V
8
D945 5 I907 2 SW+5V
D948
R053
R957 1 SW+5V Reg IC 3
25.96V
C032 R950
BOTH OFF IN STBY
Q908 C948
3 R958 Q909
D946
To Gate of Q905
I006 +28V (Shutdown SCR)
2
Reset R949 R959
1
11.9V
I906 C949
2 Sub Power PWB
STBY+11V 6 Shutdown
L004
D947 Inputs,
3.3V
Q026
R029 Active Low
3.3V
C074
3.9V PQD2 OFF IN STBY
STBY+5V
D034 QP04 I701

C075 D035 11.55V SBY11V 11.1V 11.1V DP35 H Drive IC
3
Hoz. Out Def.B+
RP36 RP38 CP45 15 8
Power On/Off DP21 RP37 10.4V HVcc
Signal PWB 1
PQS2 Off On 11.1V STBY DP36 L701 C701
CP44 C705
PAGE 03-04
I008 STBY +7V

3 STBY 1 1 2
I905
Power/Deflection PWB Signal Sub PWB
+5V STBY+7V
2 7.28V
2
3
LEDs USED FOR VISUAL TROUBLE SHOOTING DESCRIPTION
SUB POWER SUPPLY VISUAL LEDs.
DP-0X Chassis has 5 Green and 1 Red LED on Sub Power Supply PWB.
This chassis utilizes 5 Green LED’s in the power supply cold side and a Red LED in the HOT side.
The power supply operates it two different modes, Standby and Projection On mode.
STANDBY MODE:
4 Green LED’s and the Red LED are lit in the standby mode with the AC applied and the TV OFF;
• D903 Indicating Vcc applied to the Power Supply Driver IC Color RED
• Audio Front 29V Regulator SW+29V indicated by D912 Color GREEN
• Audio Rear and Center 29V Regulator SW+29V indicated by D913 Color GREEN
• STBY+11V Regulator I906 indicated by D949 Color GREEN
• STBY+7V Regulator I905 indicated by D927 Color GREEN
POWER ON MODE:
When the Power is turned ON, the other LED lights and the Red LED remains lit as well;
• D903 Indicating Vcc applied to the Power Supply Driver IC Color RED
• SW+5V Regulator I907 indicated by D931
LED USAGE:
The Visual LEDs are very useful in Trouble Shooting. Without removing the back cover, some diagnostics can be
made. By observing the operation of the Red and Green LEDs, the technician can determine if the Sub Power
Supply is running or not.
The following will examine each LED and how they are lit.
D903 Indicating Vcc applied to the Power Supply Driver IC Color RED
This LED indicates any of three different scenarios,
1. Is there B+ (Vcc) available to the Sub Power Supply Driver IC? LED will be ON
2. Is the B+ (Vcc) available to the Sub Power Supply Driver IC missing? LED will be OFF
3. Is the Set in Shut Down? LED will be OFF
As can be see, there are two different scenarios that can cause D903 to be off, Missing Start up voltage for the
Driver IC and/or the Sub Power Supply is in Shut Down.
B+ GENERATION FOR THE SUB POWER SUPPLY DRIVER IC. See Figure 1
Vcc for the Driver IC is first generated by the AC input. This voltage is called Start Up Voltage. I901 requires
21V DC to operate normal. However, it will begin operation between 9~10V DC on pin (4) of I901.
When AC is applied, AC is routed through the main fuse F901 (a 5 Amp fuse), then through the Line filters L901,
902, 903 and 904 to prevent any internal high frequency radiation for radiating back into the AC power line. Af-
Hot Cold
FUSE Noise Filter Rectifier
AC Input Switching
F901 5A L901,2, 3,4 D901
Transformer
Rectifier T901
D901
4
Switching 3
Control
I901
D903 Protect
Protect Photocoupler
Figure 1 SCR Q901 I903
PAGE 03-05
ter passing the filters it arrives at the main full wave bridge rectifier D901 where it is converted to DC voltage.
One leg of the AC is routed to a half wave rectifier D902 where it is rectified, routed through R905 and R906
(both a 5.6K ohm resistor), filtered by C907, clamped by a 30V Zener D904 and made available to pin (4) of I901
as start up voltage. The Red LED D903 is illuminated by this power supply. When this voltage reaches 9~10 Vdc,
the internal Regulator of I901 is turned On and begins the operation of I901.
Figure 2 is a simplified diagram of the main Power Supply used in the DP-0X series Projection Television
chassis.
The primary control element of the power supply is I901 (the Switching Regulator IC), in conjunction with
transformer T901. These two components, along with the supporting circuitry, comprise a closed loop regulation
system.
Unlike previous Pulse Width Modulated (PWM) Switch Mode Hitachi power supplies, the regulation system in
the this chassis utilizes Frequency Control Modulation with an operational frequency of 105KHZ. Primary
regulation is provided by Q902, I902 and Q910, regulating the switching frequency at pin (3) of I901 via pin 1,
the regulation input to the IC.
AC
Raw 150V
4
Run V T901
Switch Mode 28V
Drain 3 Transformer
I901
Switch
Mode Regulate 1
Q910
Buffer
I902
Opti-Coupler
Q902
Buffer
IC
Q901 I903 Q905 Shutdown
SCR Opti-Coupler SCR Inputs
Figure 2
Three primary voltages are developed that are needed to sustain run, maintain regulation, and support shutdown
circuitry; Run Voltage generated from pin (8 and 9) of T901, +28V used for regulation, and STBY +11V,
respectively.
The “STBY” represents “always on”, designating a supply that is active when the unit is connected to AC power.
The Power Supply utilizes a Shutdown circuit that can trigger Q905 from 16 input sources. (6 of these are not op-
erational in Stand By mode). I903 is activated by Q905, applying gate voltage to Q901, which grounds out the
Vcc at pin (4) of I901, disabling the power supply.
Audio Front 29V Regulator SW+29V indicated by D912

The Audio Front 29V supply is generated from pin (17) of T901. This output is protected by E992, rectified by
D910 and filtered by C918. This supply is routed to the Rear Audio Output IC IC01.
This voltage is what illuminates the Green Visual Trouble Shooting LED, D912.
PAGE 03-06
Audio Rear and Center 29V Regulator SW+29V indicated by D913 (Not in the DP-05F Chassis)/.
The Audio Rear and Center 29V supply is generated from pin (16) of T901. This output is protected by E993,
rectified by D911 and filtered by C917. This supply is routed to the Rear Audio Output IC IS16 and Center Audio
Output IC IC15.
STAND BY +11V REGULATOR:

STBY+11V Regulator I906 indicated by D949 (Not on in Stand By mode.)
The STBY+11V supply is generated from pin (11) of T901. This output is rectified by D918 and filtered by
C928. This supply is routed to the Stand By +11 Regulator I906 pin (1).
STAND BY +7V REGULATOR:

STBY+7V Regulator I905 indicated by D927
The STBY+7V supply is generated from pin (11) of T901. This output is rectified by D918 and filtered by C928.
This supply is routed to the Stand By +7 Regulator I905 pin (1).
PAGE 03-07
DP0X CHASSIS L.E.D. (VISUAL TROUBLE DETECTION) DIODES
(SUB POWER PWB) SIGNAL POWER SUPPLY 5 GREEN L.E.D.s and 1 RED L.E.D.
(6 Total L.E.Ds. for visual trouble sensing observation)
Audio Audio Stby Stby Sw
Front 29V Rear/C 29V +11V +7V +5V
8.0V Stby Not In 11.8V Stby 7.28V Stby 0.0V Stby
30.67V Run DP05F 11.9V Run 7.39V Run 5.78V Run
D912 D913 R933 R930 R936
Not On
In Stby
R926 D949 D927 D931
ALL GREEN L.E.D.s

From Pin 8 T901
D902 Start Up
65V Run Vcc
Osc B+
R905 R906 11.97V Stby D905 I903 11.9V Stby
4 R908
12.56V Run 4 1 12.23V Run
D903 is a RED L.E.D. I901 11.9V Stby
Off = No I901 B+ Driver/Output IC 13.56V Run 11.17V Stby
On = I901 Run Voltage OK 3 2
0V Stby 11.55V Run
100% Dead Time & 0V Run
IC B+ Detection I903 Shutdown Q905
Photocoupler Shutdown
R907 SCR
C907 D904 165KHz Stby
105KHz 16 Shut Down
Inputs
PAGE 03-08
D903
Q901 Shutdown SCR
DP-05 and DP-05F SUB POWER SUPPLY LEDs USED FOR TROUBLE SHOOTING
Refer to the DP-05 and DP-05F LEDs used for Trouble Shooting Diagram
The only difference between the DP-05 & DP-05F and the DP-06 or DP-07 Sub Power Supply LEDs used for
Trouble Shooting is that the DP-05 and DP-05F doesn’t have the DSP Module. Therefore, it uses a SRS Surround
PWB. There is no Rear or Center Audio, so the LED for monitoring the Rear Audio B+ isn’t there. (D913) is not
used. So there will only be (4) Green LEDs and (1) Red LED on the Sub Power Supply.
PAGE 03-09
DP-05 and DP-05F CHASSIS L.E.D. (VISUAL TROUBLE DETECTION) DIODES
(SUB POWER PWB) SIGNAL POWER SUPPLY 4 GREEN L.E.D.s and 1 RED L.E.D.
Audio Stby Stby Sw
Front 29V +11V +7V +5V
8.0V Stby 11.8V Stby 7.28V Stby 0.0V Stby
30.67V Run 11.9V Run 7.39V Run 5.78V Run
D912 R933 R930 R936
Not On
R926
In Stby
D949 D927 D931
ALL GREEN L.E.D.s

From Pin 8 T901
D902 65V Start Up Run Vcc
Osc B+
R905 R906 11.97V Stby D905 I903 11.9V Stby
4 R908
12.56V Run 4 1 12.23V Run
D903 is a RED L.E.D. I901 11.9V Stby
Off = No I901 B+ Driver/Output IC 13.56V Run 11.17V Stby
On = I901 Run Voltage OK 3 2
0V Stby 11.55V Run
100% Dead Time & 0V Run
IC B+ Detection I903 Shutdown Q905
Photocoupler Shutdown
R907 SCR
C907 D904 165KHz Stby
105KHz 16 Shut Down
Inputs
PAGE 03-10
D903
Q901 Shutdown SCR
SUB POWER SUPPLY SHUT DOWN CIRCUIT DESCRIPTION
Use this explanation in conjunction with the Sub Power Supply Shutdown diagram.
The sub power supply in the DP-0x chassis works very similar to the previous models, with some very significant
exceptions. This power supply runs at 50% efficiency when the AC is applied and the set is OFF. The use of the
power supply creating the SBY+11V supply eliminates the need for a Stand-By transformer. The following
explanation will describe the Turning ON and OFF of the projection television.
Power Supply Frequency of Operation During Run and Stand By:

When the Horizontal deflection is in operation, the power supply frequency fluctuates in accordance to current
demands. The normal operational range for the power supply is 105 KHz. During Stand-By, it operates at
165KHz.
Power Supply Shutdown Explanation

This chassis utilizes I901 as the Osc.\Driver \Switch for the sub power supply, just as the previous chassis have
done. This IC is very similar to the previous versions, however it does differ in Frequency, (described previously)
and in Stand-By detection. The Shutdown circuit, (cold ground side detection), is routed to I901 via the following
circuit, Q905 (the Shutdown SCR), I903 (the Photo Coupler), which isolates the Hot ground from the Cold
ground and couples the Shutdown signal to the Hot Ground side, Q901 the hot ground side SCR and I901 pin (4)
(the Vcc pin).
The Power Supply utilizes a Shutdown circuit that can trigger Q905 from 16 input sources. (6 of these are not op-
erational in Stand By mode). I903 is activated by Q905, applying gate voltage to Q901, which grounds out the
Vcc at pin (4) of I901, disabling the power supply.
All of the Power Supply Shutdown circuitry can be broken down into the following groups;
• Voltage Missing Detection
• Excessive Current Detection
• Voltage Too High Detection
In the following explanation, the Shutdown circuits will be grouped. This will assist the Service Technician with
trouble shooting the Chassis, by understanding these circuits and having the associated circuit routs, the
technician can then “Divide and Conquer”.
Commonly Used Shutdown Detection Circuits
Excessive Current Detection. (See Figure 1)

One very common circuit used in many Hitachi television Current Detection Resistor
products is the B+ Excessive Current Sensing circuit. In this
0.47
circuit is a low ohm resistor in series with the particular power B+
supply, (labeled B+ in the drawing). The value of this resistor
is determined by the maximum current allowable within a
particular power supply. In the case of Figure 1, the value is
shown as a 0.47 ohm, however it could be any low ohm value.
When the current demand increases, the voltage drop across the
resistor increases. If the voltage drop is sufficient to reduce the
voltage on the base of the transistor, the transistor will conduct, Figure 1 Shut-Down Signal
producing a Shutdown signal that is directed to the
appropriate circuit. Any Positive
B+ Supply
Voltage Loss or Excessive Load Detection Voltage
(See Figure 2 on next page) Loss B+
The second most common circuit used is the Voltage Detector
Loss Detection circuit. This is a very simple circuit Q1
that detects a loss of a particular power supply and
supplies a Pull-Down path for the base of a PNP Shut-Down
transistor. Figure 2 Signal
PAGE 03-11
This circuit consist of a diode connected by its cathode to a positive B+ power supply. Under normal conditions,
the diode is reversed biases, which keeps the base of Q1 pulled up, forcing it OFF. However, if there is a short or
excessive load on the B+ line, the diode in effect will have a LOW on its cathode, turning it ON. This will allow a
current path for the base bias of Q1, which will turn it ON and generates a Shutdown Signal.
B+ Voltage Too High Detection.

(See Figure 3) Any Positive
In this circuit, a Zener diode is connected to a voltage B+ Supply
divider or in some cases, directly to a B+ power supply. If Voltage Too High
the B+ voltage increases, the voltage at the voltage divider Detector
or the cathode of the zener diode will rise. If it gets to a
predetermined level, the zener will fire. This action
creates a Shutdown Signal.
Shut-Down Signal Figure 3
Negative Voltage Loss Detection.
(See Figure 4)
The purpose of the Negative Voltage Loss detection Shut-Down Signal
circuit is to compare the negative voltage with its’ counter
part positive voltage. If at any time, the negative voltage
drops or disappears, the circuit will produce a Shutdown Negative
signal. Voltage
In Figure 5, there are two resistors of equal value. One to Loss
the positive voltage, (shown here as +12V) and one to the
negative voltage, (shown here as -12V). At their tie point, Detector
(neutral point), the voltage is effectually zero (0) volts. If
however, the negative voltage is lost due to an excessive
load or defective negative voltage regulator, the neutral +12V -12V Figure 4
point will go positive. This in turn will cause the zener
diode to fire, creating a Shutdown Signal.
DP-0X Shutdown Circuit

There are a total of 16 individual Shutdown inputs. In addition, there are also two Shutdown inputs that are
specifically detected by the main power driver IC, I901 that protect it from excessive current or over voltage.
All of the Shutdown detection circuits can be categorized by the four previously described circuits
Voltage Loss Detection

• Shorted SW+2.5V on Signal PWB through Protect 1 to (D957) on Sub Power Supply PWB
• Shorted SW+9V (D015) on Signal PWB through Protect 1 to (D959) on Sub Power Supply PWB
• Shorted SW+3.3V (D016) on Signal PWB through Protect to (D959) on Sub Power Supply PWB
• Shorted Stby+3.3V on Signal PWB through Protect 2 to (D959) on Sub Power Supply PWB
• Shorted Stby+5V (D032) on Signal PWB through Protect 2 to (D959) on Sub Power Supply PWB
• Shorted Stby+9V (D007) on Signal PWB through Protect 2 to (D959) on Sub Power Supply PWB
• Shorted Stby+3.3V (D016) on Signal PWB through Protect 2 to (D959) on Sub Power Supply PWB
• SW+5V (D943)
• SW+12V (D944)
• Stby+7V (D955)
• Stby+11V (D952)
PAGE 03-12
Negative Voltage Loss Detection
• SW-12V Loss Detection (D939, D940)
Excessive Current Detection

• Not used in the Sub Power Supply.
Voltage Too High Detection

• SW+12V (D935, D936)
• SW+5V (D932, D933)
• Stby+11V (D941)
• Stby+7V (D938)
If any one of these circuits activate the power supply will STOP, and create a Power Supply Shutdown Condition.
SOME SHUTDOWN CIRCUITS ARE DEFEATED IN STANDBY MODE. (Set Off).

As indicated in the Power On/Off circuit diagram explanation, 6 of the 16 shut down inputs are not active when
the set is in standby.
• Shorted SW+2.5V on Signal PWB through Protect 1 to (D957) on Sub Power Supply PWB
• Shorted SW+3.3V (D016) on Signal PWB through Protect to (D959) on Sub Power Supply PWB
• SW+5V (D943)
• SW+12V (D944)
These SW voltage loss sensing circuits are defeated because the SW (Switched) power supplies are turned off in
standby to prevent misoperation of the shutdown circuit.
Q909 supplies the high for shutdown if any of the voltage loss circuits become activated. Q909 requires emitter
voltage to operated. Emitter voltage is supplied from the emitter of Q908. Q908’s base is connected to Q903
which in turn is connected to the power on/off line. When the set is not on or turned off, the power on/off line
goes high. This high is inverted to a low by Q903 and pulls the cathode of D945 low, removing the base voltage
of Q908 turning it OFF. This removes the emitter voltage from Q909 and this circuit can’t function.
SHUT DOWN CIRCUIT:

Shut down occurs when the shutdown SCR Q905 is activated by gate voltage. When Q905 receives gate voltage
of 0.6V, the SCR fires and give a ground path for the emitter of the LED inside I903. The light produced by turn-
ing on this LED turns on the internal photo receiver and generates a high out of pin (3). This high is routed to the
gate of Q901 turning it on. This grounds pin (4) of I901 removing Vcc and the power supply stops working.
The reason for the photo sensor I903 is to isolate hot and cold ground.
B+ GENERATION FOR THE SUB POWER SUPPLY DRIVER IC:

Vcc for the Driver IC is first generated by the AC input. This voltage is called Start Up Voltage. I901 requires
12.7V DC to operate normal. However, it will begin operation at 9~!0V DC on pin (4) of I901.
When AC is applied, AC is routed through the main fuse F901 (a 5 Amp fuse), then through the Line filters L901,
902, 903 and 904 to prevent any internal high frequency radiation for radiating back into the AC power line. Af-
ter passing the filters it arrives at the main full wave bridge rectifier D901 where it is converted to Raw 150V DC
voltage to be supplied to the power supply switching transformer T901 pin (1).
However, one leg of the AC is routed to a half wave rectifier D902 where it is rectified, routed through R905 and
R906 (both a 5.6K ohm resistor), filtered by C907, clamped by a 30V Zener D904 and made available to pin (4)
of I901 as start up voltage. The Red LED D903 is illuminated by this power supply. When this voltage reaches
9~10VDC, the internal Regulator of I901 is turned On and begins the operation of I901.
When the power supply begins to operate by turning on and off the internal Switch MOS FET, the Raw 150V DC
routed through T901, in on pin 1 and out on pin 2 which is connected to pin (3) of I901 which is the Drain. The
PAGE 03-13
Source of the internal Switch MOS FET is routed out of pin (2) through three low ohm resistors to hot ground.
This on and off action, causes the transformer to saturate building up the magnet field. When the internal Switch
MOS FET turns off, the magnet field collapses and the EMF is coupled over to the secondary windings, as well as
the drive windings. The drive windings at pin (8 and 9) produce a run voltage pulse which is rectified by D905,
filtered by C908 then routed through R908, clamped by D904 and now becomes run voltage (12.7V) for I901.
PAGE 03-14
DP-0X SIGNAL POWER SUPPLY (Low Voltage) SHUT-DOWN CIRCUIT
T901
D902 R905 R906 R908 D905 8 11 28V
AC
Sw+12V Sw-12V
D904 C908
9 12 R941 R942
C907
Vin 4
R960 I901 D921 R945 D940 D939
Power
IC D936 D935
D903 I903 Sw +12V
R909
4 1 D933 D932
Q901 Sw +5V
R911
3 2 D941
R910 Stby +11V

C910 D938
Q905
Stby +7V
C947
R198 PQS2 D957

Sw +2.5V Protect 1 R955
Pin 10 D958
D943 D946
D015
Sw +9V Sw +5V Q909
D944 R960
Sw +12V
D014
Sw +5V R959
C949
D016 Q903 Q908

Sw +3.3V D945
On/Off
R957
Off On
On Off
R958
R014 PQS2 D959 +28V

Stby +3.3V Protect 2
Pin 11
D032 D960 D951
D955
Stby +5V Q912
D952 R960
D007
Stby +9V
R969
C956
R968 D954
Stby +7V
R967 D953 D956
Stby +11V
PAGE 03-15
DEFLECTION POWER SUPPLY VISUAL LEDs.
DP-0X Chassis has 1 Green and 1 Red LED on Deflection Power Supply PWB.
This chassis utilizes 1 Green LED in the power supply cold side and a Red LED in the HOT side.
The power supply operates it two different modes, Standby and Projection On mode.
POWER ON MODE:
When the Power is turned ON, the LEDs lights;
• DP37 Indicating Vcc applied to the Power Supply Driver IC IP01 Colored RED
• DP29 Indicating 120V Deflection B+ is available Colored GREEN
LED USAGE:
The Visual LEDs are very useful in Trouble Shooting. Without removing the back cover, some diagnostics can be
made. By observing the operation of the Red and Green LEDs, the technician can determine if the Deflection
Power Supply is running or not. Remember, this power supply doesn’t operate when the set is in Standby.
The following will examine each LED and how they are lit.
DP37 Indicating Vcc applied to the Power Supply Driver IC IP01 Colored RED
This LED indicates any of three different scenarios,
1. Is there B+ (Vcc) available to the Deflection Power Supply Driver IC? LED will be ON
2. Is the B+ (Vcc) available to the Deflection Power Supply Driver IC missing? LED will be OFF
3. Is the Set in Shut Down? LED will be OFF
As can be see, there are two different scenarios that can cause DP37 to be off, (1) Missing Start up voltage for the
Driver IC and/or (2) the Deflection Power Supply is in Shut Down.
B+ GENERATION FOR THE DEFLECTION POWER SUPPLY DRIVER IC. See Figure 1
Vcc for the Driver IC is first generated by the AC input. This voltage is called Start Up Voltage. IP01 requires
10.7V DC to operate normal. However, it will begin operation at 9~10V DC on pin (4) of IP01.
When AC is applied by the relay on the Sub Power Supply R901, AC is routed through the connector PQD1.
Then it arrives at the main full wave bridge rectifier DP01 where it is converted to DC voltage. One leg of the AC
is routed to a half wave rectifier DP02 where it is rectified, routed through RP02 and RP03 (both a 5.6K ohm re-
sistor), filtered by CP05, and made available to pin (4) of IP01 as start up voltage. The Red LED DP37 is illumi-
nated by this power supply. When this voltage reaches 9~10Vdc, the internal Regulator of IP01 is turned On and
begins the operation of IP01.
Sub Power Supply Hot Cold

Relay Connector Rectifier
AC Input Switching
R901 PQD1 DP01
Transformer
Rectifier TP91
DP02
4
Switching 3
Control
IP01
DP37
Power/Deflection PWB
Figure 1
PAGE 03-16
Figure 2 is a simplified diagram of the main Power Supply used in the DP-0X series Projection Television
chassis.
The primary control element of the power supply is IP01 (the Switching Regulator IC), in conjunction with
transformer TP91. These two components, along with the supporting circuitry, comprise a closed loop regulation
system.
Unlike previous Pulse Width Modulated (PWM) Switch Mode Hitachi power supplies, the regulation system in
the this chassis utilizes Frequency Control Modulation with an operational frequency of 60KHZ to 85KHZ,
corresponding to full load and no load conditions, respectively. Primary regulation is provided by IP03, IP04 and
into IP01, regulating the switching frequency at pin (3) of I901 via pin 1, the regulation input to the IC.
Two primary secondary voltages are developed that are needed to sustain run and maintain regulation;
1. Run Voltage generated from pin (8 and 9) of TP91 rectified by DP03 and supplies run voltage to IP01 pin
(4) and
2. 120V Deflection Voltage generated from pin (13) of TP91, rectified by DP11 used for regulation and power-
ing the Deflection and regulation circuitry.
AC
Raw 150V
4
Run V TP91 120V
Switch Mode Deflection B+
Drain 3 Transformer
IP01 DP29
Switch
Mode Regulate 1
IP04
Opti-Coupler
IP03
Regulator IC
IC
HOT COLD
DP37
Figure 2
GREEN LED:
120V Deflection B+ DP29
The Deflection B+ 120V supply is generated from pin (13) of TP91. This output is rectified by DP11 and filtered
by CP17. This supply is routed to the Horizontal Drive Circuit and the High Voltage generation circuit.
This voltage is what illuminates the Green Visual Trouble Shooting LED, DP29.
PAGE 03-17
DP0X CHASSIS L.E.D. (VISUAL TROUBLE DETECTION) DIODES
DEFLECTION PWB 1 GREEN L.E.D.s and 1 RED L.E.D.
120V Deflection B+
RP28
RP29
Osc B+ DP29
DP02 65V
RP02 GREEN L.E.D.

From Pin 8 TP91
Start Up Run Vcc
11.9V
RP03 17.5V 4 DP03 IP04
4 1
CP05 RP09 17V
IP01 1 3
Driver/Output IC 2
3V
2.1V
85KHz Blk Screen IP04 Regulator 10.7V
70KHz Pic Screen Photocoupler
60KHz White Screen RP42
DP37 is a RED L.E.D. IP03 10.7V

PAGE 03-18
OFF = IP01 B+ Missing

DP37 2
May be caused by Shut Down or Faulty Start up Circuit.
ON = IP01 B+ OK
IP03 Regulator
DEFLECTION POWER SUPPLY SHUT DOWN CIRCUIT DESCRIPTION
Use this explanation in conjunction with the Deflection Power Supply Shutdown diagram.
POWER SUPPLY FREQUENCY OF OPERATION DURING RUN
When the Horizontal deflection is in operation, the power supply frequency fluctuates in accordance to screen
brightness, causing differing demands for High Voltage replacement. The normal operational range for the power
supply is between 80 KHz to 100 KHz. The lower the frequency, the higher the current supplied to the load.
During Stand-By, it operates at 200KHz.
POWER SUPPLY SHUTDOWN EXPLANATION

This chassis utilizes IP01 as the Osc.\Driver \Switch for the Deflection power supply, just as the previous chassis
have done. This IC is very similar to the previous versions, however it does differ in Frequency, (described
previously). The Shutdown circuit, (cold ground side detection), is used to turn off the Relay S901 via the follow-
ing circuit, QP01 (the Shutdown SCR), Connector PQD2, Q911 the Relay Driver and the Relay S901.
The Power Supply utilizes a Shutdown circuit that can trigger QP01 from 14 input sources. When any of these
inputs cause a high on the gate of QP01, the relay disengages, disabling the deflection power supply.
All of the Power Supply Shutdown circuitry can be broken down into the following groups;
• Voltage Missing Detection
• Excessive Current Detection
• Voltage Too High Detection
In the following explanation, the Shutdown circuits will be grouped. This will assist the Service Technician with
trouble shooting the Chassis, by understanding these circuits and having the associated circuit routs, the
technician can then “Divide and Conquer”.
COMMONLY USED SHUTDOWN DETECTION CIRCUITS
EXCESSIVE CURRENT DETECTION. (See Figure 1)

One very common circuit used in many Hitachi television Current Detection Resistor
products is the B+ Excessive Current Sensing circuit. In this 0.47
circuit is a low ohm resistor in series with the particular power B+
supply, (labeled B+ in the drawing). The value of this resistor
is determined by the maximum current allowable within a
particular power supply. In the case of Figure 1, the value is
shown as a 0.47 ohm, however it could be any low ohm value.
When the current demand increases, the voltage drop across the
resistor increases. If the voltage drop is sufficient to reduce the
voltage on the base of the transistor, the transistor will conduct, Figure 1 Shut-Down Signal
producing a Shutdown signal that is directed to the appropriate
circuit.
VOLTAGE LOSS OR EXCESSIVE LOAD DETECTION

(See Figure 2)
The second most common circuit used is the Voltage Any Positive
Loss Detection circuit. This is a very simple circuit B+ Supply
Voltage
that detects a loss of a particular power supply and Loss B+
supplies a Pull-Down path for the base of a PNP Detector
transistor.
This circuit consist of a diode connected by its Q1
cathode to a positive B+ power supply. Under normal
conditions, the diode is reversed biases, which keeps Shut-Down
the base of Q1 pulled up, forcing it OFF. However, if Figure 2 Signal
there is a short or excessive load on the B+ line, the
diode in effect will have a LOW on its cathode, turning it ON. This will allow a current path for the base bias of
Q1, which will turn it ON and generates a Shutdown Signal.
PAGE 03-19
Any Positive
B+ VOLTAGE TOO HIGH DETECTION.
B+ Supply
(See Figure 3) Voltage Too High
In this circuit, a Zener diode is connected to a voltage Detector
divider or in some cases, directly to a B+ power supply. If
the B+ voltage increases, the voltage at the voltage divider
or the cathode of the zener diode will rise. If it gets to a
predetermined level, the zener will fire. This action
creates a Shutdown Signal. Shut-Down Signal Figure 3
NEGATIVE VOLTAGE LOSS DETECTION.

(See Figure 4)
The purpose of the Negative Voltage Loss detection Shut-Down Signal
circuit is to compare the negative voltage with its’ counter
part positive voltage. If at any time, the negative voltage
drops or disappears, the circuit will produce a Shutdown Negative
signal.
In Figure 5, there are two resistors of equal value. One to
Voltage
the positive voltage, (shown here as +12V) and one to the Loss
negative voltage, (shown here as -12V). At their tie point, Detector
(neutral point), the voltage is effectually zero (0) volts. If
however, the negative voltage is lost due to an excessive
load or defective negative voltage regulator, the neutral
+12V -12V Figure 4
point will go positive. This in turn will cause the zener
diode to fire, creating a Shutdown Signal.
DP-0X SHUTDOWN CIRCUITS FOR THE DEFLECTION POWER SUPPLY
There are a total of 14 individual Shutdown inputs. In addition, there are also two Shutdown inputs that are
specifically detected by the main power driver IC, IP01 that protect it from excessive current or over voltage.
All of the Shutdown detection circuits can be categorized by the four previously described circuits
VOLTAGE LOSS DETECTION

1. Shorted 220V (DP31 and DP32) Inverted by QP03 then through DP22
2. Shorted SW+8V (DP33) Inverted by QP03 then through DP22
3. Shorted 28V (DP30) Inverted by QP03 then through DP22
4. Shorted Side Pin Cushion Circuit (D760 and Q754) then through DP34
5. Shorted Deflection Transformer or Misoperation (D756 and Q754) then through DP34
6. Heater Loss Detection (DH26, DH27,QH07 and DP34) This voltage does not go to the CRTs.
NEGATIVE VOLTAGE LOSS DETECTION

7. -M28V Loss Detection (DP23, DP24)
8. SW-8V Loss Detection (DP28, DP29)
EXCESSIVE CURRENT DETECTION

9. 120V Deflection Power Supply (RP17, QP02, DP15, DP16 and DP18)
10. 28V Vertical IC I601 Power Supply (R645, Q609, D615, and DP34)
PAGE 03-20
Voltage Too High Detection
11. Excessive High Voltage Detection (DH31, RH54, RH55 and DH24). Sensed from the Heater Voltage gener-
ated from pin (5) of the Flyback Transformer TH01. Also, (DH42) sends a high command to the Horizontal
Driver IC IH02, to defeat Horizontal Drive Output.
12. Side Pincushion failure generating a High. (D754, and D753).
13. Deflection B+ Too High. (DP17, RP21 and RP22).
14. Heater Voltage from the Deflection Power Supply Too High Detection. (DP27 and DP28)
If any one of these circuits are activated, the power supply will STOP, and create a Power Supply Shutdown
Condition.
SHUT DOWN CIRCUIT:

Shut down occurs when the shutdown SCR QP01 is activated by gate voltage. When QP01 receives gate voltage
of 0.6V, the SCR fires and give a ground path for the pin (5) of Connector PQD2 called PROTECT. This Low is
routed to the Sub Power Supply PWB and is impressed on the base of the Relay Driver Transistor Q911 turning it
Off. When Q911 turns Off the Relay S901 will disengage and remove the AC source from the Deflection Power
Supply.
DESCRIPTION OF EACH SHUT DOWN CIRCUIT:

Please use the Commonly Used Shutdown Detection Circuits for the description of how the circuit works.
VOLTAGE LOSS DETECTION

1. Shorted 220V (DP31 and DP32) Inverted by QP03 then through DP22
The cathode of DP31 is connected directly to the 220V line. If it shorts this circuit is activated and pulls
the base of QP03 low. This output High is routed through DP22 to the gate of the Shut Down SCR
QP01.
2. Shorted SW+8V (DP33) Inverted by QP03 then through DP22

The cathode of DP33 is connected directly to the SW+8V line. If it shorts this circuit is activated and
pulls the base of QP03 low. This output High is routed through DP22 to the gate of the Shut Down SCR
QP01.
3. Shorted 28V (DP30) Inverted by QP03 then through DP22

The cathode of DP30 is connected directly to the 28V line. If it shorts this circuit is activated and pulls
the base of QP03 low. This output High is routed through DP22 to the gate of the Shut Down SCR
QP01.
4. Shorted Side Pin Cushion Circuit (D760 and Q754) then through DP34
The Side Pin Cushion circuit is comprised of I651, Q652 through Q657 If a problem occurred in this
circuit that creates a Low on the cathode of D760, the low will be routed to the base of Q754, turning it
Off. This output High is routed through DP34 to the gate of the Shut Down SCR QP01.
5. Shorted Deflection Transformer or Misoperation (D756 and Q754) then through DP34
The Deflection circuit generates the actual Drive signal used in the High Voltage section. If a problem
occurs in this circuit, the CRTs could be damaged or burnt. D757 is connected to D759 which is nor-
mally rectifying pulses off the Deflection Transformer T753. This rectified voltage is normally sent
through D757, D756 to the base of Q754 keeping it On and it’s collector Low. If the Deflection circuit
fails to produce the pulses for rectification, the base voltage of Q754 disappears and the transistor turns
Off generating a High on its collector. This output High is routed through DP34 to the gate of the Shut
Down SCR QP01.
PAGE 03-21
6. Heater Loss Detection (DH26, DH27,QH07 and DP34) This voltage does not go to the CRTs.
The Flyback Transformer TH01 generates a pulse called Heater. (Note: This does not go to the CRTs as
heater voltage, its used for Excessive High Voltage Detection. If a problem occurs in this circuit, the Ex-
cessive High Voltage Detection circuit wouldn’t operate. So it would be possible for there to be High
Voltage but the circuit detecting Excessive High Voltage couldn’t work. DH26 is connected to DH24
which is normally rectifying pulses off the Flyback Transformer TH01. This rectified voltage is nor-
mally sent through DH26, DH27 to the base of QH07 keeping it On and it’s collector Low. If the
Heater Pulse fails to produce the pulses for rectification, the base voltage of Q754 disappears and the
transistor turns Off generating a High on its collector. This output High is routed through DH30 to the
anode of DP34 to the gate of the Shut Down SCR QP01.
NEGATIVE VOLTAGE LOSS DETECTION

7. -M28V Loss Detection (DP23, DP24)

RP31 (18K ohm) is connected to the negative –M28V line and RP30 (22K ohm) is connected to the
positive +29V line. The Cathode of DP23 monitors the neutral point where these two resistors are con-
nected. If the negative voltage disappears, the zener DP23 fires. This high is routed through DP24 to the
gate of the Shut Down SCR QP01 and Shut Down occurs.
8. SW-8V Loss Detection (DP28, DP29)

RP26 (3.3K ohm) is connected to the negative SW-8V line and RP25 (3.3K ohm) is connected to the
positive SW+8V line. The Cathode of DP28 monitors the neutral point where these two resistors are
connected. If the negative voltage disappears, the zener DP28 fires. This high is routed through DP29 to
the gate of the Shut Down SCR QP01 and Shut Down occurs.
EXCESSIVE CURRENT DETECTION

9. 120V Deflection Power Supply (RP17, QP02, DP15, DP16 and DP18)
If an excessive current condition of the Deflection B+ is detected by RP17 a 0.47 ohm resistor, the base
of QP02 would drop. This would turn on QP02 and the high produced at the collector would fire zener
DP15. This High would be routed through DP16 through DP18 to the gate of the Shut Down SCR QP01
and Shut Down occurs.
10. 28V Vertical IC I601 Power Supply (R645, Q609, D615, and DP34)
If an excessive current condition of the Vertical B+ is detected by R645 a 0.68 ohm resistor, the base of
Q609 would drop. This would turn on Q609 and the high produced at the collector would be routed
through D615 through DP34 to the gate of the Shut Down SCR QP01 and Shut Down occurs.
PAGE 03-22
VOLTAGE TOO HIGH DETECTION
11. Excessive High Voltage Detection (DH31, RH54, RH55 and DH24). Sensed from the Heater Voltage
generated from pin (5) of the Flyback Transformer TH01. Also, (DH42) sends a high command to the
Horizontal Driver IC IH02, to defeat Horizontal Drive Output
The Flyback Transformer TH01 generates a pulse called Heater. (Note: This does not go to the CRTs as
heater voltage, its used for Excessive High Voltage Detection). If this voltage goes too high indicating an
excessive High Voltage condition, the voltage divider comprised of RH54 and RH55 would impress a
high on the cathode of DH31. This high is routed through DH34 to the gate of the Shut Down SCR
QP01 and a Shut Down occurs.
12. Side Pincushion failure generating a High. (D754, and D753)

The Side Pin Cushion circuit is comprised of I651, Q652 through Q657 If a problem occurred in this
circuit that creates a High on the cathode of D754, the High will be routed through D753 to the gate of
the Shut Down SCR QP01.
13. Deflection B+ Too High. (DP17, RP21 and RP22

RP21 and RP22 form a voltage divider. The top side of RP22 is monitored by DP17. If this voltage goes
too high, the zener DP17 will fire. This high is routed through DP18 to the gate of the Shut Down SCR
QP01 and Shut Down occurs.
14. Heater Voltage from the Deflection Power Supply Too High Detection. (DP27 and DP28)
The Heater Voltage for the CRTs filament is generated in the Deflection Power Supply. This voltage is
monitored by DP27. If this voltage goes too high, the zener DP27 will fire. This high is routed through
DP28 to the gate of the Shut Down SCR QP01 and Shut Down occurs.
PAGE 03-23
DP0X DEFLECTION POWER SUPPLY SHUTDOWN DIAGRAM
Deflection B+ (120V)
RP17
TP91 Excessive Current Det.
DP11 0.47 Deflection B+ 120V
13 CP33 Deflection B+ (120V)
RP21
S-901 Excessive Voltage Det.
QP02
Def. Power RP22 Vertical Circuit
Supply Relay
DP15 DP17 Excessive Current Det. Pin 10
SW+5V
I601
AC In 28V R645
S12V DP16
2 3 0.68
PQD2 DP18
Q911 Q609
1 4 QP01
5 ShutDown Flyback
PQD1 S.C.R. TH01
1 AC for Def. Spot

Off On DH24 D615 29.01V
Power Supply Killer
2 5 5OP
DH42 RH54
IH02 7 DH26 Doesn't
go to
OVP 23V CRT's
220V Short Det. Excessive High DH27
Voltage Det. DH31 RH55
DP31 DP32 DP34 DH30 Heater
220V Loss Det.
QP03 DP22 QH07
DP33 X-RAY Prevents
SW+8V SW+8V Short Det. PROTECT QH08 Protect
DP30 Misoperation
28V 28V Short Det. SW+12V
D753 D754
Side Pin Failure
DP24 DP29 DP28 High Det.
DP23 DP28 DP27 Q754

D760
RP27
RP31 RP30 RP26 RP25
Heater from Def. Power Supply.
-M28V +28V SW-8V SW+8V Side Pin
Goes to CRT's
9.01V Failure
-28V Loss Det. SW-8V Loss Det. Low Det.
Heater Too High Det.
D759 9.46V D757 D756

Deflection B+ 120V V1
Q777 6 7 9.36V
1 8 C769
Deflection Transformer
Inoperative Det.
T752
H.Blk
PAGE 03-24
VIDEO
INFORMATION
SECTION 4
Video Circuit Block Diagram Explanation
I401 - Luminance Audio Selector IC
Main Tuner (TV1V) in pin 63
Sub Tuner (TV2V) in pin 60
Video 1 in from Terminal PWB pin 8
S-Video 1 (Y) from Terminal PWB pin 10
S-Video 1 (C) from Terminal PWB pin 12
Video 3 in from Front Control PWB pin 15
S-Video 3 (Y) from Front Control PWB pin 17
S-Video 3 (C) from Front Control PWB pin 19
Yin1 PinP Luminance from 2L Comb filter pin 49
Cin1 PinP Chroma from 2L Comb filter pin 51
VOut1 PinP Video to 2L Comb filter pin 53

YOut1 PinP (Y) to Sub video processor pin 56
COut1 PinP (C) to Sub video processor pin 58
V/YOut2 Main Video or S-Video (Y) to 3DYC pin 44
COut2 S-Video (C) to 3DYC pin 47
VOut3 Video out to Monitor pin 41
YOut3 S-Video (Y) out to Monitor pin 39
COut3 S-Video (C) out to Monitor pin 37
I201 - Main Video Chroma Processor IC

Main video in (Y) pin 40
Main video in (C) pin 6
Y out pin 37
R-Y Out pin 48
B-Y Out pin 47
I403 - Sub Video Chroma Processor IC

Sub video in (Y) pin 40
Sub video in (C) pin 6
Y out pin 37
R-Y Out pin 48
B-Y Out pin 47
2 Line Comb Filter (PinP)

Video In pin 4
Y Out pin 1
C Out pin 3
3DYC Comb Filter (Main)

Video/Y in pin 11
C in pin 13
Y Out pin 9
C Out pin 7
Page 04-01
DP-0X SERIES CHASSIS VIDEO SIGNAL PATH (Main & Terminal)
Lum/Audio Selector IC
Front Control PWB

PFT I401 Q405 Q406 I403
PinP Yout1 PinP VY
3V V3V 56 40
10 15
Avx 3 In S Det.
Aux Input 3
S-Y3 PinP C Cout1 PinP C
5 17 58 6
S-3 In S-C3
3 19 Q403 Q404 Q408
VOut1 53 4 V In 2 Sub Video Route
Signal PWB 1 of 2 Terminal PWB
PinP YIn1 49 1 Y Out Line 37 Y
Q205 PST1 Video
U201
TV1V Comb 48 R-Y
18 14 63 CIn1 51 3 C Out Filter 47 B-Y
Main Tuner
Main
U202 Video
Q206 NTSC See Component Signal Flow
TV2V Q409 Monitor Out
PinP TUNER (Mono) 23 Diagram for Continuation
19 60
Always PinP Vout3 41
R-Y/CR
CR
Out
Q410 Q411 CB B-Y/CB Out
Yout3 39 Y Main Y/Video
V1 8 Y/S Monitor Out
S Det. S-Y1
10 Cout3 37
S-1 In S-C1
Aux Inputs
12
PST2 Q216 Q235 I201
Q402
V2 1 V/Yout2 Main Y 5 Main Y
S Det. S-Y2 44 /Video /Video
40 37
3
S-2 In S-C2 Q401 47
5 Main C
Cout2 47 7 6 48
Main C
Q213 Q214 Main
PYC1 Video/
Chroma
13
U204 11
PAGE 04-02
3DYC 9
Terminal PWB 7 Signal PWB 2 of 2
Component Video Circuit Block Diagram Explanation
I401 - Luminance/Audio Select IC
VIn4 Comp 1 (Y) When component video is 480i this is used for CCD, as well as the Auto Link function.
VIn5 Comp 2 (Y) When component video is 480i this is used for CCD, as well as the Auto Link function.
I406 - Main Component 1 / Component 2 Select IC

Selects either Component 1 or Component 2 (Y/CbPb/CrPr).
Outputs to I205.
I205 - Main Video / Component Select IC

Selects either Component 1 or 2 (Y/CbPb/CrPr) from I406 and Main (R-Y/B-Y/Y) from I201.
Outputs to Flex Converter Main inputs.
I407 - Sub Component 1 / Component 2 Select IC

Selects either Component 1 or Component 2 (Y/CbPb/CrPr).
Outputs to I404.
I404 - Sub Video / Component Select IC

Selects either Component 1 or 2 (Y/CbPb/CrPr) from I407 and Sub (R-Y/B-Y/Y) from I403.
Outputs to Flex Converter Sub inputs.
Flex Converter
Receives Main R-Y/B-Y/Y from I205 and Sub R-Y/B-Y/Y from I404.
Combines the two sets of signals (Main and Sub).
Converts output signals to 2H (31.75kHz) YCbCr unless signals are already 31.75kHz or higher.
YCbCr to YIQ Converter

Level/phase shifts color difference signals.
IX02 - YCbCr / YIQ Select IC

Selects either YCbCr or YIQ color difference signals.
YIQ is selected by microprocessor via I004 DAC2 sensing NTSC input on Comp 1 or 2.
Outputs to IX01.
IX01 - Rainforest IC
Receives the three color difference signals from IX02.
Outputs to the three CRT PWBs.
Page 04-03
DP-0X SERIES CHASSIS COMPONENT SIGNAL PATH (Main & Terminal)
Lum/Audio Selector IC U205
Terminal PWB Signal PWB
Component 2 I205 PFC1
I401 I406 PST2 Q232
Inputs Q439 1
Cr/Pr2 1 Cr/Pr Q427 1
Cr/Pr 1 21 5
Cr/Pr1 3 13 7 233 Q234
16 2
Q438 2 1 Q229
Cb/Pb2 1 Cb/Pb Q426 3
Cb/Pb 14 19 4
5 11 9 Q230 Q231
Comp 2 for 30 11 2
Auto Link 2 1 Q226
Y2 1 Y Q425 5
Y 8 15 3
6 9 11 Q227 Q228
Q437 9 2
FLEX CONVERTER
Component 1 Y1 2 Signal PWB
Inputs Q434 I407 Main R-Y Cr Out
Y 1 Cr/Pr
48
Comp 1for 22 1 Main B-Y Cb Out
Auto Link 3 47 I201 Main Picture
16 Q440 Main Y Out Preparation IC
Cb/Pb 2 37
Q435 1 Cb/Pb
14
5 PST2
Cr/Pr
11 Q441
2
Terminal Q436
8
1 Y I404
6 1 Q416
PWB 7 Sub R-Y Cr Out
9 Q442 21 19 19
2
1 Q417 Q418
Q414 2
Sub R-Y Cr Out 1 Q419
I403 48
Q413 Sub B-Y Cb Out
9
19 17
Sub B-Y Cb Out
18
47 3 Q420 Q421
2
1 Q422
11 Sub Y Out
Q412 Sub Y Out 15 15 17
37 5 Q423 Q424
2
Sub Picture PZC QX31 IX01 2H Video PWB PSZ2 PFC2

Y2 In
QX21
Preparation IC 53 2H Y
1 43 15 16
R 2H Y
Rain See Chroma After Flex Converter Sig. Diagram
QX36 CB/Q
forest
To CRT PWB 3 42 52 17 18 2H B
PAGE 04-04
G IX02 YCBCR to YIQ 2H CB

YCBCR/YIQ CONVERTER
QX41 CR/I 2H R
SELECTOR Q22~27 & 54,55
5 41 51 19 20
B 2H CR
DP-05 & DP-05F COMPONENT VIDEO CIRCUIT BLOCK DIAGRAM
DP-05 and DP-05F COMPONENT VIDEO CIRCUIT
BLOCK DIAGRAM DESCRIPTION
Refer to the DP-05 and DP-05F Component Signal Path (Main & Terminal) Circuit Diagram
The only difference between the DP-05 & DP-05F and the DP-06 or DP-07 Component Video Circuit Diagram
is;
• The DP-05 and DP-05F PinP circuit doesn’t route the Component inputs to the PinP Signal route into the
Flex Converter. Therefore, the PinP in the DP-05 and DP-05F only produces NTSC inputs routed through the
Selector IC.
• The Sub Component Selector IC (I407) is not used.
• The Sub Component/NTSC Signal Selector IC (I404) is not used.

PAGE 04-05
DP-05 and DP-05F SERIES CHASSIS COMPONENT SIGNAL PATH (Main & Terminal)
Lum/Audio Selector IC U205
Terminal PWB Signal PWB
Component 2 I205 PFC1
I401 Inputs I406 PST2 1 Q232
Q439
Cr/Pr2 1 Cr/Pr Q427 1
Cr/Pr 1 21 5
Cr/Pr1 3 13 7 233 Q234
16 2
Q438 2 1 Q229
Cb/Pb2 1 Cb/Pb Q426 3
Cb/Pb 14 19 4
5 11 9 Q230 Q231
Comp 2 for 30 11 2
Auto Link 2 1 Q226
Y2 1 Y Q425 5
Y 8 15 3
6 9 11 Q227 Q228
Q437 9 2
FLEX CONVERTER
Component 1 Y1 2
Signal PWB
Inputs Q434
Main R-Y Cr Out
Y 48
Comp 1for 22 Main B-Y Cb Out Main Picture
Auto Link 47 I201 Preparation IC
Cb/Pb Main Y Out
37
Q435
Terminal
PWB PST2
Cr/Pr
Q436
Q416
Q414 Sub R-Y Cr Out Sub R-Y Cr Out
48 19 19
I403 Q417 Q418
Q419
Q413 Sub B-Y Cb Out Sub B-Y Cb Out
47 17 18
Q420 Q421
Q422
Q412 Sub Y Out Sub Y Out
37 15 17
Q423 Q424
Sub Picture PZC QX31 IX01 2H Video PWB PSZ2 PFC2

Y2 In
QX21
Preparation IC 1 43 53 15 16 2H Y
R 2H Y
Rain See Chroma After Flex Converter Sig. Diagram
QX36 CB/Q
forest
To CRT PWB 3 42 52 17 18 2H B
PAGE 04-06
G IX02 YCBCR to YIQ 2H CB

YCBCR/YIQ CONVERTER
QX41 CR/I
SELECTOR Q22~27 & 54,55 2H R
5 41 51 19 20
B 2H CR
Chroma After Flex Converter Block Diagram Explanation
U205 - Flex Converter
Receives Main R-Y/B-Y/Y from I205 and Sub R-Y/B-Y/Y from I404.
Combines the two sets of signals (Main and Sub).
Converts output signals to 2H (31.75kHz) Y/Pb/Pr unless signals are already 31.75kHz or higher.
YCbCr to YIQ Converter

Consists of QX22-QX27, QX52-QX55
Level/phase shifts color difference signals.
IX02 - YCbCr / YIQ Select IC

Selects either YCbCr or YIQ color difference signals.
YIQ is selected by microprocessor via I004 DAC2 sensing NTSC input on Comp 1 or 2.
Outputs to IX01.
IX01 - Rainforest IC
Receives the three color difference signals from IX02.
Outputs to the three CRT PWBs.
Note: Three Color Difference signals can be:

RGB
R-Y/B-Y/Y
CrCbY
PrPbY
YIQ
YUV
(U, Q, and Blue all rhyme)
Page 04-07
DP-0X CHROMA ROTATION CIRCUIT EXPLANATION
QUESTION:
What is the function of QX22, QX23, QX24, QX25, QX26 and QX27 on the output of
the 3D Y/C Comb filter.
See Chroma After Flex Converter Diagram schematic for details.
FROM:
Alvie Rodgers C.E.T. Technical Trainer.
ANSWER:
The RGB Processor IX01 (TA1298AN) has a function called Skin Tone
correction. This circuit is also named “Auto Color or Auto Flesh Tone”.
The Auto Color function works only with Y/I-Q signals. The YUV signal out of the
Comb filter must be converted to YIQ before entering IX01 (Rainforest IC) in order to
use “Auto Color”. Y Pr/Pb YUV signals must be converted.
IQ signals are made from UV signal by giving them a 330 phase shift.
See figure below for details.
The Switching IC IX02 shown on the Chroma After Flex Converter Diagram selects
either the NTSC Y/IQ signal without rotation or the Y Pr/Pb with rotation as deter-
mined by the control signal Select 5 (SEL5).
Select 5 logic: High = Y/IQ (NTSC) and Low = YUV (Y/Pr/Pb).
Not shown is the input pin for Select 5 (SEL5) control signal. This control signal is in-
put via pin (5 and 12).
The V Signal is rotated 33 degrees to Convert it to an I signal.
(V)
(I) 900
1230 330
(Q)
330
(U) The U Signal is rotated 33 degrees to
00 Convert it to a Q signal.
PAGE 04-08
DP-0X SERIES CHASSIS CHROMA AFTER FLEX CONVERTER SIGNAL PATH
Signal PWB
YCBCR YIQ
U205 CONVERTER
PFC2 PSZ2
QX25 QX27
2H CB I
2H B 18 17
2H CB
FLEX CONVERTER
QX24
2H CR
QX55
QX23
2H CB
QX26
2H CR 2H CR QX22 Q
2H R 20 19
QX54
2H CR
2H CB
IX01 IX02
1
CR/I 14 QX52
V/I In 51 5 I I
11
2
CB/Q 1 2H CB
1 QX53
U/Q In 52 3 Q
Q
16
2
2
SEL5 High = NTSC Low = Y Pr/Pb
PAGE 04-09
12
Rainforest IC
RGB Processor
YCBCR/YIQ 2H VIDEO PWB
Selector
Sync Circuit Block Diagram Explanation
VOut1 PinP (Sub) Video to I005 Main/Sub Select IC and also to I001 microprocessor for Sub CCD.
V/YOut2 Main Video or S-Video (Y) to I005 Main/Sub Select IC and also to I001 microprocessor for
Main CCD.
VIn4 Component 1 Y in for CCD (480i only) and Auto Link.
VIn5 Component 2 Y in for CCD (480i only) and Auto Link.
Component Inputs (Y)

Component 1 (Y) to I015 Component 1 Sync Separator IC.
Component 2 (Y) to I016 Component 2 Sync Separator IC.
I015 - Component 1 Sync Separator IC

Vertical sync out goes to I001 microprocessor IC Comp 1 VFDet.
Horizontal sync out goes to I005 Main/Sub Select IC.
I016 - Component 2 Sync Separator IC

Vertical sync out goes to I001 microprocessor IC Comp 2 VFDet.
Horizontal sync out goes to I005 Main/Sub Select IC.
I005 - Main/Sub Select IC

Select control from I001 microprocessor SD Sel (Station Detect) Low = Main, High = Sub
Three separate sets of inputs/outputs, (only first two shown in graphic)
pin 3 Sub Video (In)
pin 5 Main Video (In)
pin 4 Sub/Main SD Det (Out)
pin 2 Comp 1 H sync (In)

pin 1 Comp 2 H sync (In)
pin 15 Comp 1/2 HFDet (Out)
pin 12 Sub AFC (In)

pin 13 Main AFC (In)
pin 14 Sub/Main AFC (Out)
I001 - Microprocessor IC
Sub video in on pin 30 for CCD.
Main video in on pin 28 for CCD.
Component 1 vertical frequency detect on pin 10, from I015.
Component 2 vertical frequency detect on pin 11, from I016.
Component 1/2 horizontal frequency detect on pin 22, from I005.
SD Select out on pin 50 to control I005 during Sub picture changes; example PinP CH up or down.
Main/Sub SD detect in on pin 24 from I005.
Page 04-10
DP-0X SERIES CHASSIS SYNC SIGNAL PATH
Lum/Audio Selector IC PST2 SIGNAL PWB 1 of 2

Aux Input 3 I005 Lo = MAIN
PFT I401 Q403 Q210 Hi Hi = SUB
Composite 3 Z1
3V V3V 53 3 3
10 15 Q019 Q018
Avx 3 In S Det.
S-Y3 Sub Video
4
5 17 Q402 Q208
S-3 In S-C3 Lo
3 19
44 5 5
Front Control PWB Z0
Q017
VOut1 Y0
Main Y Q046
Signal PWB 2 of 2 /Video 2
PST1 15
Q205 Main 1
U201 18 14 63 Y1
Video
Main Tuner NTSC VOut2
TV1V
U202
Q206 Sub for V. Chip
I001
TV2V Comp1/2
PinP TUNER (Mono) 23 19 60 PinP Data 22
Video FHDet
Always PinP Q031 Main Sub
Comp 2 H Out
Comp 1 H Out
30 SD Det
Micro 24
Processor
Composite 1 Aux Input 1 For 480i
V1 8 Comp SDA1 2
S Det. S-Y1 Sync Sep Comp 1
10 Only CCD
S-1 In S-C1 PST1
& V Chip
Aux Inputs
12 2 SCL1 3
I015
Composite 2 Aux Input 2 Comp1 In 22 8 1 Comp 1 4 10 Vert Freq
V2 1 Det Comp1
S Det. S-Y2
3 Sync Sep Comp 2
S-2 In S-C2
5
2 I016
Comp2 In 30 9 1 Comp 2 4 11 Vert Freq
Det Comp2
Q434 Q431
Component 1 Y Q021 Main for
28 CCD
PAGE 04-11
Component 2 Y Q437 Q433 I003

Q016
SCL1 15
Also, see Main/Component Sync Terminal PWB 2
DAC1
Separation Circuit Diagram YN Det SDA1 14
Component Sync Separation Block Diagram Explanation
I406 - Main Component 1 / Component 2 Select IC
Selected Y output on pin 6.
I207 - Main Component Sync Separator

Y in on pin 1
H out on pin 2
V Out on pin 4
I203 - Sync Inverter

H sync from I207 is inverted and applied to I202.
I201 - Main Video Chroma Processor (NTSC)

Main Video in (Y) on pin 40
Vertical sync out on pin 13
Horizontal sync out on pin 14
I202 - Main Sync Selector

Selects either Main NTSC H and V sync or Main Component H and V sync.
Select 3 controlled by DAC2 line from I201 Main Video Chroma Processor IC.
Outputs selected H and V sync to I203 Sync Inverter IC.
I407 - Sub Component 1 / Component 2 Select IC

Selected Y output on pin 6.
I408 - Sub Component Sync Separator

Y in on pin 1
H out on pin 2
V Out on pin 4

H sync from I408 is inverted and applied to I405.
I403 - Sub Video Chroma Processor (NTSC)

Main Video in (Y) on pin 40
Vertical sync out on pin 13
Horizontal sync out on pin 14
I405 - Sub Sync Selector

Selects either Sub NTSC H and V sync or Sub Component H and V sync.
Select 4 controlled by DCOut line from I401 Luminance Audio Select IC.
Outputs selected H and V sync to I203 Sync Inverter IC.

Inverts incoming signals
Outputs (Main H, Main V, Sub H, Sub V) go to Flex Converter for PinP timing purposes.
Main H labeled MHW at Flex Converter
Main V labeled MVW at Flex Converter
Sub H labeled SHW at Flex Converter
Sub V labeled SVW at Flex Converter
Page 04-12
DP-0X SERIES CHASSIS MAIN/COMPONENT SYNC SEPARATION SIGNAL PATH
I207 V.Sync Out I202

1
4 2
5
13 1
2
I201 10 Select 3 SIGNAL PWB
40 Main
Q223 Video/ 9 Select 3
1 Chroma
1
See Video 14 3
Signal Path 4
5 Select 3
2
Hi : Main NTSC
Q224 Lo : Main Component
H.Sync Out I203
2 5 6 Select 4
Hi : Sub NTSC
Lo : Sub Component
U205 MHW
8 10 11
Flex Converter
16 MVW
See 7 12 13
Component 18 Q428
Signal Path
PTS3 I405 I409
1
20 SHW Sub H. Sync 2 4 2
15 2 1 1 15
1
SVW 2
Sub V. Sync 10 Select 4 H.Out
14 4 3 3 Sub I403
Sync 14
Sub Video/
Chroma
Sel. 40
PTS2 9 Select 4 V.Out
1
9 3 13
4
5
TERMINAL PWB 2
PAGE 04-13
Q425 Q442 Q415 See Video

I406 I407 I408 V.Out
Signal Path
4
6 See Component See Component 6 1 Sync
Signal Path (Main) Signal Path (Sub) H.Out
Sep. 2
DP-05 & DP-05F COMPONENT SYNC SEPARATION BLOCK DIAGRAM
DP-05 and DP-05F COMPONENT SYNC SEPARATION

BLOCK DIAGRAM EXPLANATION
Refer to the DP-05 and DP-05F Component Sync Separation Circuit Diagram
The only difference between the DP-05 & DP-05F and the DP-06 or DP-07 Component Sync Separation Circuit
Diagram is;
• The DP-05 and DP-05F PinP circuit doesn’t route the Component inputs to the PinP Signal route into the
Flex Converter. Therefore, the PinP in the DP-05 and DP-05F only produces NTSC inputs routed through the
Selector IC.
• The Sub Component Selector IC (I407) is not used.
• The Sub Component Sync Separator IC (I408) is not used.
• The Sub Component or Main NTSC Sync Selection IC (I405) is not used.

PAGE 04-14
DP-05 and DP-05F SERIES CHASSIS MAIN/COMPONENT SYNC SEPARATION SIGNAL PATH
I207 V.Sync Out I202

1
4 2
5
13 1
2
I201 10 Select 3 SIGNAL PWB
40 Main
Q223 Video/ 9 Select 3
1 Chroma
1
See Video 14 3
Signal Path 4
5 Select 3
2
Hi : Main NTSC
Lo : Main Component
H.Sync Out I203 Q224
2 5 6 Select 4
Hi : Sub NTSC
Lo : Sub Component
U205 MHW
8 10 11
Flex Converter
16 MVW
See 7 12 13
Component 18 PTS3
Signal Path I403
20 SHW Sub H. Sync H.Out
15 2 1 1 14
Sub Video/ 40
SVW Sub V. Sync V.Out Chroma
14 4 3 3 13
Preparation
IC
PTS2
9
TERMINAL PWB
See Sub Video
PAGE 04-15
Q425 Signal Path

I406
6 See Main Component
Signal Path
Automatic Brightness Limiter (ABL) Circuit Block Diagram Explanation
The ABL voltage is generated from the ABL pin of the Flyback transformer, TH01. The ABL pull-up resistors
are RH58 and RH59. They receive their pull up voltage from the B+ 120V(V2 ) for Deflection line generated
from the Power Supply via TP91 pin 13, rectified by DP11, filtered by CP33 and then routed through the
excessive current sensing resistor RP17.
ABL VOLTAGE OPERATION

The ABL voltage is determined by the current draw through the Flyback transformer. As the picture brightness
becomes brighter or increases, the demand for replacement of the High Voltage being consumed is greater. In
this case, the flyback will work harder and the current through the Flyback increases. This in turn will decrease
the ABL voltage. The ABL voltage is inversely proportionate to screen brightness.
Also connected to the ABL voltage line is DH33. This zener diode acts as a clamp for the ABL voltage. If the
ABL voltage tries to increase above 12V due to a dark scene which decreases the current demand on the
flyback, the ABL voltage will rise to the point that DH33 dumps the excess voltage into the 12 line.
ACCL TRANSISTOR OPERATION

The ABL voltage is routed through the PSD3 connector, through the PSZ2 connector, to the base of QX13.
Under normal conditions, this transistor is nearly saturated. QX13 determines the voltage being supplied to the
cathode of DX05, which is connected to pin 45 of the Rainforest IC, IX01. During an ABL voltage decrease,
due to an excessive bright circumstance, the base of QX13 will go down, this will drop the emitter voltage
which in turn drops the cathode voltage of DX05. This in turn will pull voltage away from pin 45 of the
Rainforest IC, IX01. Internally, this reduces the contrast and brightness voltage which is being controlled by
the I2C bus data communication from the Microprocessor arriving at pin 27 and 28 of the Rainforest IC and
reduces the overall brightness, preventing blooming.
SUB BRIGHTNESS ADJUSTMENT - I2C Alignment

The purpose for the Sub Brightness Adjustment alignment is to set up the Lowest DC level to which the
Brightness control voltage can be set. Again, this voltage is controlled internally within IX01 via I2C bus data.
The adjustment is performed within the Service Menu. To enter this adjustment menu, with the set turned off,
press and hold the Input button, then press the Power button. This will bring up a Service Menu. Under the
P.01 menu, the 1st selection is Sub Bright Adj. Selection is made using the pq buttons and adjusting the data
values are made using the tu buttons.
Page 04-16
DP0X CHASSIS A.B.L. CIRCUIT DIAGRAM
QX13 SW +9V
PSZ2 RX34 IX01
RX32 RX33 RX35 DX05 RX37 ABL Rainforest
5 45 IC 2H Video
CX31 CX32 PWB
DX03 RX36
CX19 or
CX34 Signal Sub
PSZ1
PWB
SDA2
16 27 SDA2
SCL2
17 28 SCL2
See uP
Data
Signal TH01 To Anodes
Path High Voltage B+ 120V V2 B+
C To
Focus
To QH01 ABL RH67

Collector of High Voltage LH03
Output Transistor 3
CH25
ABL Pull-Up Resistors
Deflection PWB RH58 RH59 RH56
Deflection B+ 120V V1
[ Current Path ]
DH33
Sw +12V
PSD3
Clamp
CH31
1
PAGE 04-17
Signal
As Brightness goes Up, ABL Voltage goes Down. (Inverse Proportional)
PWB
Sweep Loss Detection Block Diagram Explanation
The key component in the Sweep Loss Detection circuit is QN04. This transistor is normally biased off. When
the base becomes more negative, it will be turned on, causing the Standby 11V to be applied to two different
circuits, the Spot circuit and the High Voltage Drive circuit.
SPOT CIRCUIT
When QN04 is turned on, the 11V standby will be applied to the anode of DN11, forward biasing it. This
voltage will then pass through DN11, get zenered by DN09, and go to pin 2 of PSD3, where it will activate the
Video Mute circuitry Q022 - Q024 on the Signal PWB. This is done to prevent CRT burn. Another input to
this circuit is the I701 DAC3 line. This will activate when accessing certain adjustment parameters in the
service mode; i.e. turning off vertical drive for making CRT drive or cut-off adjustments.
HIGH VOLTAGE DRIVE CIRCUIT

When QN04 is turned on, the 11V standby will also be applied to the High Voltage Drive IC IH02 pin 14 via
RN15 and DN13. When this occurs, the IC will stop generating the drive signal that is used to produce High
Voltage via QH08, the High Voltage Driver. Again, this is done to prevent CRT burn, especially during sweep
loss.
CONCERNING QN04
There are several factors that can affect the operation of QN04; namely loss of vertical or horizontal blanking
and spot killer or spot protect from a shutdown in the deflection power supply.
Loss of Vertical Blanking

When the 24Vpp positive vertical blanking pulse is missing from the base of QN01, it will be turned off, which
will cause the collector to go high. This in turn will cause QN02 to turn on, creating an increase of current flow
from emitter to collector and up through RN07, (which is located across the emitter base junction of QN04), to
the 11V standby supply. This increase of current flow through RN07 will bias on QN04 and the events
described previously will occur.
Loss of Horizontal Blanking

When the 11.6Vpp positive horizontal blanking pulse is missing from the base of QN05, it will be turned off,
which will cause the collector to go high. This in turn will cause QN03 to turn on, creating an increase of
current flow from emitter to collector, through RN06, and up through RN07. Again, this increase of current
flow through RN07 will bias on QN04 and the events described previously will occur.
SPOT PROTECT or SPOT KILLER

As mentioned earlier, when the deflection power supply goes into shutdown for whatever reason, a low
potential will be felt at the cathode of DN14, forward biasing it and causing current flow through RN07. Once
again, this increase of current flow through RN07 will bias on QN04 and the events described previously will
occur.
Page 04-18
DP0X SWEEP LOSS DETECTION CIRCUIT
SW+12V
Vertical RN05
RN03 RN04 QN02
Blanking See Deflection
From DN01 Power Supply
QN01 Circuit Diagram
Pin 11 I601
RN01
V. Blk. CN02
DN02 SPOTPROTECT
CN01
RN02 DN03
DN14
24V P/P DN15

RN10
RN07
RN10 Stby 11V
SW+12V
RN09 QN04
Horizontal
Blanking DN04 RN06
CN03
DN05 High Voltage
From QN03 RN08 Driver IC
Q755 Emitter
IH02
CN04 QN05
DN06 RN15 DN13
H. Blk. 14 Stops
RN11 Drive
RN13
RN12
11.6V P/P PSD3

DN11 DN12 RH60
Prevents CRT Burn
SPOT 2 1 Drive
DN09 RN14
Horizontal
and QH08
Stops High Voltage
Vertical High Voltage
Drive Signals From
Drive IC H Drive
being produced
I701 when Sweep Loss is
QN08 detected.
DAC3 24 QN07
When Vertical Drive
Spot Inhibit
is turned Off during
adjustment, I 2C.
HVcc
R718
PAGE 04-19
ZP-04 (Zenith) Video Circuit Block Diagram Explanation
Main Tuner (TV1V) in pin 63
Sub Tuner (TV2V) in pin 60
Video 3 in from Front Control PWB pin 15
S-Video 3 (Y) from Front Control PWB pin 17
S-Video 3 (C) from Front Control PWB pin 19
Yin1 PinP Luminance from 2L Comb filter pin 49
Cin1 PinP Chroma from 2L Comb filter pin 51
VOut1 PinP Video to 2L Comb filter pin 53

YOut1 PinP (Y) to Sub video processor pin 56
COut1 PinP (C) to Sub video processor pin 58
V/YOut2 Main Video or S-Video (Y) to 3DYC pin 44
COut2 S-Video (C) to 3DYC pin 47
VOut3 Video out to Monitor pin 41
YOut3 S-Video (Y) out to Monitor pin 39
COut3 S-Video (C) out to Monitor pin 37
I201 - Main Video Chroma Processor IC

Main video in (Y) pin 40
Main video in (C) pin 6
Y out pin 37
R-Y Out pin 48
B-Y Out pin 47
I403 - Sub Video Chroma Processor IC

Sub video in (Y) pin 40
Sub video in (C) pin 6
Y out pin 37
R-Y Out pin 48
B-Y Out pin 47
2 Line Comb Filter (PinP)

Video In pin 4
Y Out pin 1
C Out pin 3
3 Line Comb Filter (Main)

All discreet components
IJ01 Video In, Y and C out
IJ02 Selects either incoming S-video or IJ01 Y and C outputs
Page 04-20
ZP-04 SERIES CHASSIS VIDEO SIGNAL PATH (Main & Terminal)
Lum/Audio Selector IC
Aux Input 3 PFT I401 Q405 Q406 I403

Front Control PWB PinP Yout2 PinP VY
3V V3V 56 40
10 15 SUB
Avx 3 In S Det.
S-Y3
5 17
PinP C Cout2 PinP C VIDEO
32 6
S-3 In S-C3
3 19 Q404 Q408
Q403
VOut1 53 4 V In 2 Sub Video Route
Terminal PWB PinP
Signal PWB 1 of 2
PST1 Video
YIn1 49 1 Y Out Line 37 Y-Out
Q205 TV1V Comb 48 R-Y/CR Out
U201 18 14 63 CIn1 51 3 C Out Filter 47 B-Y/CB Out
Main Tuner
Main
U202 Video
NTSC See Component Signal Flow
Q206 TV2V Q409 Monitor Out Diagram for Continuation
PinP TUNER (Mono) 23 19 60 Vout
Always PinP 3
41
CB B-Y/CB Out
Q410 Q411 CR R-Y/CR Out
Yout
Aux Input 1 3
39 Y Main Y/Video
V1 8 Y/S Monitor Out
S Det. S-Y1
10 Cout3 37
S-1 In S-C1
Aux Inputs
12
PST2 I201
Aux Input 2 Q402 Main Q216 Q235
Main
V2 1 V/Yout2 44 5 40 37
S Det. S-Y2 Y Y
3 /Video /Video
S-2 In S-C2 Q401 48
5 Main C
Cout2 47 7 6 47
Terminal PWB Main C
Q213 Q214
3 Line Comb Filter
Main
IJ01 IJ02 PYC1 Video/
QJ06 S-CIn
8 25 25 8 6 10 1 5 3 13 Chroma
QJ08 QJ07 QJ05
Page 04-21
QJ10
QJ02 9
QJ04 QJ01 Signal PWB 2 of 2
QJ09
QJ03 7
QJ12 QJ11
11
Video In
AUDIO
INFORMATION
SECTION 5
Audio Circuit Block Diagram Explanation

Main Tuner TV1 Left in pin 62
Main Tuner TV1 Right in pin 64
Sub Tuner Mono in pin 59 and 61
Aux 1 Left in from Terminal PWB pin 9

Aux 1 Right in from Terminal PWB pin 11
Aux 2 Left in from Terminal PWB pin 2

Aux 2 Right in from Terminal PWB pin 4
Aux 3 Left in from Front Control PWB pin 16

Aux 3 Right in from Front Control PWB pin 18
Monitor Left out pin 38

Monitor Right out pin 40
Main (Selected) Out Left to Surround Sound PWB pin 43

Main (Selected) Out Right to Surround Sound PWB pin 45
Serial Clock 1 pin 33

Serial Data 1 pin 34
IC01 - Front Audio Output IC

Front Left in from Surround PWB pin 2
Front Right in from Surround PWB pin 4
Mute Line pin 11
Page 05-01
DP-0X CHASSIS AUDIO SIGNAL PATH
(Main, Terminal & Audio Output)
Left Monitor Out
I401 38
PFV Terminal
Front Control PWB Right Monitor Out
3L PWB 40
8 16
Avx 3 In Aux Input 3
3R
7 18 Lum/Audio
Selector IC
TV 1 Left
27 16 62
U201 Tuner
1 of 2 TV 1 Right Audio
Main Tuner 26 17 64
PST1 PST1 Signal PWB 2 of 2 PSU1
I001 SCL1 SCL1
43 11 Select L Left Select
11
3 6 33 Main Audio
Microprocessor Select R Right Select
2 SDA1
5 SDA1 34 45 12 12
(See Surround Audio Signal Path)

PST3 1L 9
AVX 1 2 of 2
Aux Inputs
1R 11
2L 2
AVX 2 PinP 55 PST2
Signal PWB 1 of 2 2R 4 Mono PinP
Audio 1
3L 51 In 61
AVX 3 20U202
3R 49
PinP Tuner
Terminal PWB
PL Front Output IC
Front Left
FL Front Left F L Out
2 12 IC01 2
Woofer 8
Main Audio
4 Front Right F R Out
4 9
Tweet DC02 Front Speaker Off
PR
PAGE 05-02
Front Right QC01 QC02 DC01

FR ERRMute
2 7
Woofer DC03
QC03
4 11 DC04 VMute2
Tweet
Surround Sound Circuit Block Diagram Explanation
IS19 - Perfect Volume IC
This IC receives main selected Left and Right audio and if the perfect volume feature is enabled via customer
controls, will act as a limiter/compressor to keep sound levels at the same relative level. Output is sent to the
DSP Module as well as to IS03 Front Audio Control IC.
Digital Signal Processor (DSP)

This Module is located on the Signal PWB. It receives Left and Right audio in from the Perfect Volume IC and
creates the following outputs; Front Right, Front Left, Rear Right, Rear Left, Center, and Sub. It also is
capable of receiving and processing a digital audio input signal, via either coaxial or optical inputs.
IS02 - Buffer IC
This IC receives the Front Left and Front Right signals from the DSP on it’s non-inverting inputs and outputs
them to the Front Audio Control IC.
IS03 - Front Audio Control IC

This IC receives both the non-DSP processed Left and Right signals as well as the DSP Front Left and Front
Right signals. Serial clock and data lines control various functions such as level and balance.
IS04 - Buffer IC
This IC receives the Front Left and Front Right signals from the Front Audio Control IC on it’s inverting inputs
and outputs them to the Front Audio Graphic Equalizer IC.
IS05 - Front Audio Graphic Equalizer IC

This IC receives the Front Left and Front Right signals from the Buffer IC IS04. Serial clock and data lines
control frequency response via the customer control interface. The output is sent back to the Signal PWB via
the PSU1 connector to the Front Audio Output IC. This output is also sent to QS12 - QS15 buffer stages to be
available as the HiFi outputs.
IS08 - Center Channel & Sub Woofer Audio Control IC

This IC receives the processed Center Channel and Subwoofer signals from the DSP. Serial clock and data
lines control various functions such as level and balance.
IS09 - Buffer IC
This IC receives each of the processed Center Channel and Subwoofer signals from IS08 on it’s inverting
inputs. The Subwoofer output is routed to QS18 and then on to the Subwoofer output connector. The Center
Channel output is sent to the Center Channel Graphic Equalizer IC IS10.
IS10 - Center Channel Graphic Equalizer IC

This IC receives the Center Channel signal from the Buffer IC IS09. Serial clock and data lines control
frequency response via the customer control interface. The output is sent to the Center Channel Audio Output
IC IS15.
IS15 - Center Channel Output IC

This IC receives a paralleled input and amplifies the signal (s) to be sent to the pair of center channel speakers.
There is also a mute line control input.
IS11 - Rear Audio Control

This IC receives the processed Rear Left and Rear Right signals from the DSP. Serial clock and data lines
control various functions such as level and balance.
IS12 - Buffer IC
This IC receives the Rear Left and Rear Right signals from the Rear Audio Control IC on it’s inverting inputs
and outputs them to the Rear Audio Output IC.
IS16 - Rear Audio Output

This IC receives the input from the Buffer IC IS12 and amplifies the signals to be sent to the rear speaker
output connector SP. There is also a mute line control input.
Page 05-03
DP0X CHASSIS SURROUND AUDIO SIGNAL PATH
See Audio Signal Path (Main & Terminal)
PSU1 FL FR
Out to Hi-Fi
QS13 QS12 QS14 QS15 Out to Hi-Fi
FR FR IS05
9 19
Front 30
FL FL
8 12 Graphic 1
FL 20 EQ
FR 11 IS03
PMU2 PMU3
Front
Audio
L FL IS02 Control IS04
11 1 IS19 3 1 1 6 - FL 6 - FL
Perfect 17 7
5 + 2 5 +
Volume FR FR
R 3 + 9 3 +
FR 14 1
12 10 8 3 2 2 - 2 -
S QS01
6 - G
+ 7 SW Sel 1
Coaxial Input Digital 5 D
Board Gnd IS06 - 2 14 SW
11 Optical Input HC4051 1 +
3
IS08 IS09 QS18 Sub Woofer
Gnd 9 3 +
QS01 1
IS18 JS03 SW Sel 2
- 3 2 -
1 + Center/
2
8 3 IS07 Sub IS10
2X SW 6 6 -
Center
PMU4 + 7 Woofer CL 6 - Cent.
Invert Sub Woofer Gnd 5 7 1 12
3 Audio 2 5 + Graphic
12 C 5 17 Control EQ
Center
IS17 FPFRX
5 3 IS11 IS16 SP PCR IS15
IS12
Digital Output Rear 6 - SL Rear 12 Cent 4
SL 3 17 7 2 1 2 7
to DSP Audio 2 5 + Audio Audio
Control 9 3 + SR Output PCL Output
Actual Input Coax SR 4 14 1 4 7 2 2
2 - IC 1 12 IC
Invert 1
QS10 QS06
PAGE 05-04
Invert 2 Mute 11 11 Mute

DS36 DS26
Optical Input Good, no Invert Rear Spk Off Cent Spk Off
DS37 DS27
V Mute
DP-05, DP-05F and ZP-04 (Zenith) SRS Circuit Block Diagram Explanation
IA02 - Perfect Volume IC

This IC receives main selected Left and Right audio and if the perfect volume feature is enabled via customer
controls, will act as a limiter/compressor to keep sound levels at the same relative level. Output is sent to the
SRS IC IA03.
IA03 - SRS Processor (Sound Retrieval System) IC

This IC is controlled by logic modes from the DAC IC IA01. It receives Left and Right audio in from the
Perfect Volume IC and creates Front Right and Front Left signals. The two Modes control whether SRS is
activated or not and whether its producing a monaural or stereo output.
IA05 - Front Audio Control IC

This IC receives the SRS processed Left and Right signals. The output is sent to the Buffer IC IA06. This
output is also sent to QA07 - QA10 buffer stages to be available as the HiFi outputs. Serial clock and data lines
control various functions such as level, tone, and balance.
IA06 - Buffer IC
This IC receives the Front Left and Front Right signals from the Front Audio Control IC on it’s inverting inputs
and the outputs are sent back to the Signal PWB via the PSU1 connector to the Front Audio Output IC.
Page 05-05
DP-05 AND DP-05F CHASSIS SRS AUDIO SIGNAL PATH
PSU1
FR
9
FL
8
IA06
IA03 IA05
See Audio Signal Path (Main & Terminal)
IA02 6 - FL
7
L Perfect SRS FL 5 5 +
11 1 Volume 3 22 14 2 Front
Audio
R FR Control 18 3 +
1
FR
12 10 8 21 13 21 2 -
11 12
10 11
SRS LOGIC
MODE MODE 1 QA07 QA08 FL
BYPASS (SRS Off) L Out to Hi-Fi
SRS SOUND H
MODE MODE 2
SRS STEREO L QA09 QA10 FR
SRS MONAURAL H Out to Hi-Fi
SRS1
SCL2 IA01 4
1 2
DAC3 SRS2
SDA2
2 3 5
PAGE 05-06
DIGITAL
CONVERGENCE
INFORMATION
SECTION 6
DIGITAL CONVERGENCE INTERCONNECT DESCRIPTION
Use this explanation in conjunction with the Digital Convergence Interconnect circuit diagram.
The Digital Convergence circuit is responsible for maintaining proper convergence of all three colors being pro-
duced by the CRTs. Many different abnormalities
The Digital convergence Interconnect Diagram depicts how the Digital Convergence Circuit is interfaced with the
rest of the Projection’s circuits. The main components and/or circuits are;
• THE DIGITAL CONVERGENCE UNIT (DCU)
• INFERRED REMOTE RECEIVER
• ON SCREEN DISPLAY PATH
• CONVERGENCE OUTPUT STKs
• CONVERGENCE YOKES
• MAGIC FOCUS SENSORS AND INTERFACE
• MICROPROCESSOR
• RAINFOREST IC (Video Processor).
• SERVICE ONLY SWITCH
• MAGIC FOCUS SWITCH
THE DIGITAL CONVERGENCE UNIT (DCU)

The DCU is the heart of the Digital convergence circuit. Held within are all the necessary components for gener-
ating the necessary waveforms for correction, and associated memories for the adjustment data and Magic Focus
Data.
Sensors (X8)
Technician's Eye
SCREEN
Adjust through observation
M
IR
RO
Light
R
Stored during Initialize
Stored Light Sensor Data
Remote EEPROM Timing
Control 2K Bit Controller
Data Comparator Serial-Parallel

between stored data A/D Sensor PWB
and light sensor data Converter
H
R
Error Data G
Infra-Red Decoder CRT B
V
To Video Circuits Digital Cross
Via O.S.D. CY CLAMP
Hatch Gen. Timing
Displays CrossHatch Controler
2nd S/H
CLAMP
1st S/H
LPF
One Chip CPU D/A

256 Adjusted
Points
Per/Color Serial/Parallel
8 bit Converter
128 Kbit X1 X6 X6 X6 X6
117 Points Per/Color
SLOW Gate Array 4000 gates
Addressable
by EEPROM Calculation of other 139 points per/color
Technician (2Kbit)
S-RAM INTERPOLATION DIGITAL
Also available; (256Kbit)
FAST CONVERGENCE
35 Adjustment Points Back Up
9 Adjustment Points CIRCUIT
117 Points Per/Color D/A Conv.

Static Centering
AC Applied, Copy from EEPROM, then caculations will be made. Time, approx. 20 sec.
Figure 1
The Block above shows the relationship of the DCU to the rest of the set. Note that the light being produced by
the CRTs is what is used by the sensors for Magic Focus. This allows the DCU to make adjustments regardless of
circuit changes, by actually using the light on the screen to make judgments.
EEPROM AND SRAM SHOWN IN FIGURE 1:

Each color can be adjusted in any one of 117 different locations. The internal workings of the DCU can actually
make 256 adjustment points per color. These adjustment points are actual digital data stored in memory. This data
PAGE 06-01
represents a specific correction signal for that specific location. When the Service Technician makes any adjust-
ment, the new information must be stored in memory, EEPROM. The EEPROM only stores the 117 different ad-
justment points data, the SRAM interpolates to come up the additional 139 adjustment points for a total of 256 per
color. The EEPROM data is slow in relationship to the actual deflection raster change. The SRAM is a very fast
memory. So, during the first application of AC power, the EEPROM data is read and the SRAM makes the inter-
polation and as long as power remains, interpolation no longer has to be made.
This can be seen during an adjustment. If the Interpolation key is pressed on the remote control, what is happen-
ing is that the SRAM must make those additional calculations beyond the 117 made by the Servicer and this is all
placed into memory.
INFERRED REMOTE CONTROL INPUT SHOWN IN FIGURE 1:

As can be seen in Figure 1, the Inferred Remote control signals actually manipulate the internal data when the
Service Only Switch is pressed on the Deflection PWB. This process actually prevents the Microprocessor from
responding to Remote commands, via a Busy line output from the DCU. (See Microprocessor Port Description
page for further details.)
INTERNEAL CONTROLLER, D/A CONVERTERS SHOWN IN FIGURE 1:

The internal controller, takes the stored data and converts it to a complicated Convergence correction waveform
for each color. The Data is converted through the D/A converter, 1st and 2nd sample and hold, the Low Pass Fil-
ter that smoothes out the parasitic harmonic pulses from the digital circuit and the output Clamp that fixes the DC
offset level.
The DC offset voltage is adjusted by several things.
• Raster Centering. The Raster Centering adjustment actually moves the DC offset voltage for Horizontal and
Vertical direction. This Offset voltage will move the entire raster Up or Down, Left or Right.
• Static Centering. This is accessed by holding down the Magic Focus button on the front control panel for
more that 10 Seconds. The word Static will come up on the screen, generated by the DCU, and using the re-
mote controls up/down/left or right cursor buttons, the Red or Blue raster can again be moved up/down/left or
right. This allows adjustment of the entire raster for Red or Blue to match the Green Raster.
By holding down the Magic Focus button for more that 5 seconds, but not more than 10, the word Center comes
up on screen. Again generated from the DCU. This adjustment only moves the center 60% of the raster for Red or
Blue. The assumption for this adjustment was related to the location of the Magic Focus sensors located on the
outside perimeter of the inside cabinet. It was assumed possible that the outside could have been corrected, but the
inside middle might not. This adjustment is rarely necessary if at all.
MAGIC FOCUS MEMORY SHOWN IN FIGURE 1:

NOTE: This set has two Digital Convergence Memories. On for Progressive display mode and one for HD dis-
play mode.
NOTE: This set has two Magic Focus Memories. On for Progressive display mode and one for HD display mode.
Progressive requires a complete Digital Convergence adjustment procedure along with Magic Focus Sensor Ini-
tialization and HD Mode does too!
When a complete Digital Convergence procedure has been performed and the adjustment information stored in
memory by pressing the PROG button twice (2), it is mandatory to run Sensor Initialization. This is done by
pressing the PROG button or the remote once (1), then pressing the PinP Ch button. This begins a prepro-
grammed production of different light patterns. Magic Focus memorizes the characteristics of the light pattern
produced by the digital convergence module. If a convergence touchup is required in the future, the customer
simply presses the Magic Focus button on the front panel and the set begins another preprogrammed production
of different light patterns. This automated process that duplicates the same light pattern it memorized from the
initialization process, re-aligns the set to the memorized convergence condition.
PAGE 06-02
MAGIC FOCUS SENSORS SHOWN ON FIGURE 1:
This process is a joint effort between the digital convergence module and 8 Photo-sensors, physically located on
the edge of the cabinet, just behind the screen. The physical placement of the sensors assures that they will not
produce a shadow on the screen that can be seen by the customer.
Magic Focus is activated when the set is on and by pressing the Magic Focus button inside the front control
panel door. An on-screen graphic will be displayed to confirm that the automatic convergence mode (Magic Fo-
cus) has begun.
The digital convergence module produces different patterns for each CRT, and the sensors pick up the transmitted
light, generate a DC voltage. This voltage is sent to the DCU and converted to digital data and compared with the
memorized sensor initialization data. Distinct patterns will be generated in each primary color. As the process
continues, the digital module manipulates the convergence correction waveforms that it is producing to force the
convergence back into the original memorized configuration.
When all cycles have been completed, the set will return to the original signal and the convergence will be
corrected. In most cases, activating the Magic Focus will allow the set to correct itself, without further
adjustments.
EXPLANATION OF THE DIGITAL CONVERGENCE INTERCONNECT DIAGRAM:

INFRARED RECEIVER:
During normal operations, the IR receiver directs it signal to the Main Microprocessor where it interprets the in-
coming signal and performs a predefined set of operations. However, when the Service Only Switch is pressed,
the Main Microprocessor must ignore remote control commands. Now the DCU receives theses commands and
interprets them accordingly. The Microprocessor is notified when the DCU begins it’s operation by the BUSY
line. As lone as the BUSY line is active, the Main Microprocessor ignores the IR signal.
ON SCREEN DISPLAY PATH:

MICROPROCESSOR SOURCE FOR OSD:
The On Screen Display signal path is shown with the normal OSD information such as Channel Numbers, Vol-
ume Graphic Bar, Main Menu, etc… sent from the Main Microprocessor to the Rainforest IC IX01 pins 14, 16
and 18. These are positive going pulses, about 5 V p/p and about 3uS in length dependant upon there actual hori-
zontal time for display. (See the On Screen Display Path Circuit Diagram Explanation for further details).
DCU SOURCE FOR OSD:
The DCU has to produce graphics as well. When the Service Only switch is pressed, the Main Microprocessor
knows the DCU is Busy as described before. Now the On Screen Display path is from the DCU to the Rainforest
IC IX01 pins 8, 10 and 12.
The output for the DCU OSD characters is pin (11 Dig Red, 12 Dig Green and 13 Dig Blue). These are routed
through their buffers (QK06 Dig Red, QK07 Dig Green and QK08 Dig Blue) to (QX01 Dig Red, QX02 Dig
Green and QX03 Dig Blue). Then it arrives at the Rainforest IC IX01 at pins (8 Dig Red, 10 Dig Green and 12
Dig Blue). When a character pulse arrives at any of these pins, the internal color amp is saturated and the output
is generated to the CRTs. Any combination for these inputs generates either the primary color Red, Green or Blue
or the complementary color Red and Green which creates Yellow, Red and Blue which creates Magenta or Green
and Blue which creates Cyan.
(See the On Screen Display Path Circuit Diagram Explanation for further details).
OUTPUT STKs:
These are output amplifiers that take the correction waveforms generated by the DCU and amplify them to be
used by the Convergence Yoke assemblies for each color.
RV is Red Vertical Convergence correction. Adjust the location either up or down for Red.
RH is Red Horizontal Convergence correction. Adjust the location either left or right for Red.
GV is Green Vertical Convergence correction. Adjust the location either up or down for Red.
GH is Green Horizontal Convergence correction. Adjust the location either left or right for Red.
BV is Blue Vertical Convergence correction. Adjust the location either up or down for Red.
BH is Blue Horizontal Convergence correction. Adjust the location either left or right for Red.
PAGE 06-03
CONVERGENCE YOKES:
Each CRT has a Deflection Yoke and a Convergence Yoke assembly. The Deflection manipulates the beam in
accordance to the waveforms produced within the Horizontal Deflection circuit or the Vertical Deflection circuit.
The Convergence Yoke assembly manipulates the Beam in accordance with the correction waveforms produced
by the DCU.
MAGIC FOCUS SENSORS AND INTERFACE:

Each of the eight photo cells, called solar batteries in the service manual, have their own amps which develop the
DC potential produced by the cells. Each amp is routed through the PDS1 connector and arrives at the PDS con-
nector on the DCU where the DCU converts this DC voltage to Digital signals. These digital signals are used only
when the Magic Focus Button is pressed and Magic Focus runs.
MICROPROCESSOR:
The Microprocessor is only involved in the Digital Convergence circuit related to IR (Inferred Remote Control
Signals). When the DCU is put into the Digital Convergence Adjustment Mode, DCAM, the Microprocessor ig-
nores IR pulses. This is accomplished by the Busy signal from the DCU.
RAINFOREST IC (Video Processor).

The Rainforest IC, IX01 is only involved with the Digital Convergence circuit related to OSD.\
SERVICE ONLY SWITCH:

The Service Only Switch is located just in front of the Flyback Transformer on the Deflection PWB. If the front
speaker grills are removed and the front access panel is opened, the switch will be on the far left hand side. When
this button is pressed with the TV ON, the DCU enters the Digital Convergence Adjustment Mode.
If the button is pressed and held down with the TV OFF and the power button is pressed, the Digital Convergence
RAM is cleared. This turns off any influence from the DCU related to beam deflection. Magnetic centering is per-
formed in the mode as well as the ability to enter the 3X3, (9 adjustment points) mode.
MAGIC FOCUS SWITCH:

When this button is pressed with the Set ON, the DCU enters the Magic Focus adjustment mode described earlier.
When this button is pressed with the Set ON and held for;
• 5 Seconds, the word CENTER comes up on screen and if the button is released, the center 60% of the raster
can be adjusted for Red and Blue up/down/left and right using the Remote control Cursor Buttons.
• 10 Seconds, the word STATIC comes up on screen and if the button is released, the entire raster can be ad-
justed for Red and Blue up/down/left and right using the Remote control Cursor Buttons.
NOTE: This set has two Digital Convergence Memories. On for Progressive display mode and one for HD dis-
play mode. Both have to be adjusted independently.
NOTE: This set has two Magic Focus Memories. On for Progressive display mode and one for HD display mode.
Progressive requires a complete Digital Convergence adjustment procedure along with Magic Focus Sensor Ini-
tialization and HD Mode does too! The Magic Focus button will correct for either mode.
PAGE 06-04
DP-0X CHASSIS "DIGITAL CONVERGENCE" INTERCONNECTION CIRCUIT DIAGRAM
Memory SDA 1
PSZ1 2H Video PWB
5 QX07
IX01 PZC
I002 6 I001 OSD B 39
OSD B
14 14 Rainforest QX41
OSD G QX08 41 5 B
OSD G 38 16 16
SCL 1 OSD R QX09
QX36
To CRTs
OSD R 37 18 18
SDA1
I004 14 2
QX01 42 3 G
DAC2
Main Dig OSD R
Dig OSD G
8
QX02
8
15 3 SCL1 QX31
10 IR In Up Dig OSD B
10
QX03
10
43 1 R
1 IR 12 12
Signal PCB
To Blue Convergence Yokes

Signal PWB -5V 1 PDG +28P 10 CYV+
PWB PDC BV
9 2
2 +33V 5
Deflection PWB BV + - CYV-
+5V 3 1 8 7 1
SK01 "DCAM" Digital
+5V SRAM 4 UKDG IK05 11
CYH+
4
Convergence Mode
BH
HMO1 PSD1 HBlk 5 HC2151 BH + - CYH-
IR Receiver BUSY 2 14 13 3
1 D Size 6
IR Out
3 2 1 PFS Dig R QK06

18
QM01 2 V Sync 7 GV
2 3
IR-In
8 GV + - PCG
IR-In QK07 4 15 16
Stby +5V Dig G 2
3 4 9
17 8 12 4 CYV+
Magic Focus
To Green Convergence Yokes

5 10
9 QK08 1
6
Dig B
11 Digital CYV-
SM09
5 MAG SW
7 12 Convergence
-28P -33V
Ft. Control 13
Unit
"DCU" Deflection PWB
PWB PDS1 MAG SW
14 3
+5V
1 15 17 8 12 4 CYH-
N/C
2
Gnd +5V SRAM
1 of 2 PDS "Mounted on GH
9
CYH+
4
3
Gnd Gnd Deflection 5
GH
6
+ -
7 PCR
4 1 PWB" IK04 CYV+
To Red Convergence Yokes

S7 S7
5 2 6 31/33 11 2
S6 S6 RV
6 3 RV + - CYV-
Sensor S5 S5 7 14 13 1
PWB 7 4 CYH+
S4 S4 8 4
8 5 RH
S3 S3 RH + - CYH-
LED 9 6 8 6 7 3
S0-S7 S2 S2
10 7 10 5
8 Total S1 S1
Sensors 11 8 Normal "Lo"
PAGE 06-05
+28P +33V
S0 S0 Mute
12 9 9 1 IK02 2 +28V
10
3
Deflection PWB 11
DP-05, DP-05F, DP-06, DP-07 REMOTE CONTROL CLU-572 TSI
Used with
43FDX01B, 53FDX01B, 000
53SDX01B, 61SDX01B, POWER
53SWX01W, 65DMX01W TV VCR CBL SAT

SOURCE
WIZARD
DVD AV1 AV2 AV3

CURSOR UP
CURSOR DOWN
1 2 3
CURSOR LEFT 4 5 6 CURSOR RIGHT
7 8 9
RED (7 X 5)
LAST
SLEEP 0 CH
RASTER PHASE
C.C. HELP ASPECT
C.S.
INPUT
BLUE (13X9)
CROSSHATCH
U EXIT
MEN VIDEO
REMOVE
COLOR
CORRECTION
VOL SELECT CH
BUTTONS
SV
MUT
E REC
ALL GREEN (3 X 3)
CS HD
SC
VCR
/TV
PLU IDE
S+ INFO GU
CALCULATE
CENTERING
PIP PIP CH FRZ
READ OLD
INITIALIZE PIP-MODE SWAP ROM DATA
PIP MODE + PRESS (2X)
PIP CH PROG TV/VCR SLOW
WRITE TO
ROM
REC
PRESS
(2X)
HITACHI
CLU-572TSI
PAGE 06-06
AP-93R REMOTE CONTROL CLU-573 TSI
000
Used with POWER
53SBX01B, 61DSBX01B TV VCR CBL SAT

SOURCE
WIZARD
DVD AV1 AV2 AV3
CURSOR
1 2 3
POSITION
BUTTONS 4 5 6
RED
7 8 9
7X5
LAST
SLEEP 0 CH RASTER
PHASE
BLUE INPUT
HELP
C.S.
13X9
CROSSHATCH
U EXIT
MEN VIDEO
REMOVE
COLOR
CORRECTION
VOL SELECT CH
BUTTONS
GREEN
MUT ALL
SV E REC 3X3
CS HD
SC
VCR V
/T
PLU IDE
S+ INFO GU
CALCULATE
PIP PIP CH FRZ
CENTERING
SWAP
READ FROM
INITIALIZE MOVE
ROM
PROG TV/VCR SLOW
WRITE TO
ROM
REC
HITACHI
CLU-573TSI
PAGE 06-07
DP85 SERIES CHASSIS "CLU-614MP" REMOTE CONTROL
REMOTE PERSONALITY WHILE IN THE
DIGITAL CONVERGENCE ADJUSTMENT MODE D.C.A.M.
To Clear R.A.M. data.

* Turn set OFF. D.C.A.M.
Press and hold the Service Button on Digital convergence adjustment
POWER
deflection P.W.B. Then Power mode
Button.
"SWAP" = "ROM WRITE"
"PIP" = "ROM READ"
(STORE)
Reads old R.O.M. data. TV CABLE SAT
Stores data into R.O.M..
(Last data stored in R.O.M.
(Press 2 times)
(Press 2 times)
DTV/SAT PIP SWAP
"PIP CH" = "INITIALIZE" "MOVE" = "RASTER ADJ"

Perform after Used to align Red and Blue
PIP CH ANT MOVE
STORE & before EXIT raster with Green.
[SWAP + PIP CH] TV / CABLE / SAT (2 Additional lines will Appear)
V C R
AUDIO
"ANT" = "PHASE"
* (Aligns Cursor to Grid)
LAST
"EXIT" = "ENTER & EXIT"

MUTE Enter or Exit the D.C.A.M.
VOL CH
"INFO" = "CALCULATION" Must initially enter D.C.A.M. with
(Calculates mid-points) Service Button on chassis.
L (Press 5X)
I Toggles between External Video
"MENU" = "REMOVE COLOR" G
INFO EXIT and Internally generated Cross
Removes color H
GUIDE T hatch. After exiting the DCAM,
not being adjusted.
set can change channels or
(Will NOT remove GREEN )
USER HELP external video source.
FAV MENU FAV
"USER" ="GREEN adjust" CH CH
Digital Cursor Blinks GREEN "CURSOR KEYS" =
3x3 adjustment mode "(ADJUSTMENT)"
* (Press 5 times), can only be Adjust the selected color at
SVCS SCHED
entered when R.A.M. is cleared. the current stopping position.
REC SELECT
Up
"MOVES DIGITAL CURSOR" Down
Moves Adjustment Point 1 2 3 Left
(2) Up, (4) Left, Right
(5) Down, (6) Right 4 5 6
" 0 " = "RED adjust"
7 8 9
"INPUT" = "BLUE adjust" Digital Cursor Blinks RED
INPUT C.S.
Digital Cursor Blinks BLUE 7x5 adjustment mode
0
13 x 9 adjustment mode (Press 5 times)
(Press 5 times) HITACHI
CLU-614MP
PAGE 06-08
CLU-436UI REMOTE CONTROL FOR AP-91 and AP-01 CHASSIS
Used With
50DX01B, 50EX01B, POWER
60EX01B, 43GX01B,
46GX01B, 50GX20B
TV CABLE VCR
HELP PIP CH TV/VCR

HELP:
Phase
PIP SWAP MOVE FRZ
FRZ: Raster Position
SWAP: MOVE: ROM Write

ROM Read (Store)
REC PAUSE
STOP
INPUT EXIT
LST-CH
CURSOR CONTROL
RECALL:
Green Adjust VOL MUTE CH

(3 X 3 Mode)
L
I
G
1 2 3 H 2: Cursor Up
I
4: Cursor Left 4 5 6 6: Cursor Right
5: Cursor Down
7 8 9 0:
INPUT: INPUT SLEEP Red Adjust

Blue Adjust 0 (7 X 5 Mode)
(13 X 9 Mode)
HITACHI
CLU-436UI
PAGE 06-09
DP-05 and 05F DIGITAL CONVERGENCE CIRCUIT DIAGRAM EXPLANATION
Refer to the DP-05 and 05F Digital Convergence Circuit Diagram

The only difference between the DP-05 & DP-05F and the DP-06 or DP-07 Digital Convergence Circuit Diagram
is;
• The DP-05 and 05F doesn’t have Magic Focus.
• There are no sensors around the inside of the cabinet behind the screen.
• There is no Magic Focus Switch on the front control panel.
• There is a Static Convergence Switch on the front control panel.
• When performing adjustment, there is no need for Sensor Initialization in either Progressive or HD mode.

PAGE 06-10
DP-05 and 05F CHASSIS "DIGITAL CONVERGENCE" INTERCONNECTION CIRCUIT DIAGRAM
Memory PSZ1 2H Video PWB
5
SDA 1
I001 OSD B 39 OSD B QX07
IX01 PZC
I002 6 14 14 Rainforest QX41
B
SCL 1
Main Up OSD G 38 OSD G
OSD R
16
QX08
16
41 5
QX09 QX36
To CRTs
SDA1 OSD R 37 18 18
I004 14 2 Dig OSD R
8
QX01
8
42 3 G
DAC2 15 3 SCL1 Dig OSD G QX02 QX31
IR In 10 10
Dig OSD B QX03 43 1 R
10 1 IR 12 12
Signal PCB
PWB Signal PWB -5V 1 PDC +28P 10 CYV+
PDG BV 9 2
2 +33V 5
Deflection PWB BV + - CYV-
+5V 3 1 8 7 1
To Blue Convergence Yokes

SK01
+5V SRAM 4 UKDG IK05 11
CYH+
4
PSD1 "DCAM" Digital BH
HMO1 Convergence Mode HBlk 5 HC2151 + -
IR Out
BUSY BH CYH-
IR Receiver 2 14 13 3
1 D Size 6
3 2 1
QM01
PFS Dig R QK06 18
2 V Sync 7 GV
IR-In
2 3 8 GV + - PCG
IR-In Dig G 4 15 16
Stby +5V QK07 2
4 9 CYV+
3 17 8 12 4
Static Conv.
5 10
9 Dig B 1
QK08 Digital CYV-
SM09 6 11
MAG SW
5 7 12 Convergence -28P -33V
Ft. Control Unit
To Green Convergence Yokes

13 Deflection PWB
PWB MAG SW "DCU"
14 3
CYH-
+5V SRAM 15 17 8 12 4
"Mounted on GH
9
CYH+
4
Deflection GH + -
5 6 7 PCR
PWB" IK04 CYV+
6 31/33 11 2
RV
+ - CYV-
RV
7 14 13 1
CYH+
To Red Convergence Yokes

No Magic Focus RH
8 4
RH + - CYH-
8 6 7 3
Deflection PWB
10 5
PAGE 06-11
Normal "Lo" +28P +33V

Mute
9 1 IK02 2 +28V
3
DEFLECTION
CIRCUIT
INFORMATION
SECTION 7
DEFLECTION DRIVER IC (I701) B+ GENERATION DESCRIPTION
DEFLECTION DRIVER IC B+ GENERATION CIRCUIT:
(See the Deflection Vcc Production Circuit Diagram for Details)
EXPLANATION:
The B+ for the Deflection Driver IC (I701) is switched On and Off with the TV. Control for this process is pre-
formed by the Microprocessor On/Off (Power On/Off) pin.
The Power On/Off pin (53) of the Microprocessor I001 is High when the set is turned On. This High is sent to the
low voltage Power Supplies on the Signal PWB via Q003 and Q004. This turns on the +9V Regulator I009, the
SW+5V Regulator I010 and the +5V Regulator IS13 on the Surround PWB.
The High from the Microprocessor is also routed through the Relay Driver transistor Q002 and inverted to a Low,
then through the connector PQS1 pin (8), to the Sub Power Supply. (Also called the Low Voltage Power Supply
PWB). Here it turns on the necessary circuits for the Sub Power Supply. (See the Power On/Off Circuit Descrip-
tion for detail).
This Low is now routed through the connector PQD2 pin (1), to the Deflection PWB. The Low forward biases
DP21 and pulls the base of QP04 Low which turns it On. The emitter of QP04 is connected to the Stby +11V
power supply via the connector PQD2 pin (3). When QP04 turns On, the collector goes high and is routed
through DP35 and DP36 to pin (8) of I701, the Horizontal Driver IC. When B+ is applied, the Driver IC begins
producing Horizontal Drive for the Deflection Circuit.
(See Deflection Circuit description for more details).
PAGE 07-01
DP0X DEFLECTION Vcc PRODUCTION CIRCUIT
SIGNAL PWB SUB POWER PWB DEFLECTION

Turns on I009 SW +9V Reg., PWB
IS13 +5V Reg on Surround PWB
PQD2
and I010 SW+5V Reg. Signal PWB From I906 Stby +11V
Reg.
Q003 Q004 STBY +11V
Stby +11V 3
Start Up Power
PQS1
I001
Micro Q002 QP04
Processor
Power On/Off
53 8 1
Power ON DP21
Driver Other Power
Power On by
On/Off Circuits
Remote Control or (Relay Driver) DP35
Front Power Key
Press
Horizontal Drive IC DP36
I701
HVcc 8
SUB DEFLECTION
PWB
PAGE 07-02
HORIZONTAL DRIVE CIRCUIT DESCRIPTION
HORIZONTAL DRIVE CIRCUIT DIAGRAM DESCRIPTION:
(Use the Horizontal Drive Circuit Diagram for details)
CIRCUIT DESCRIPTION
When B+ arrives at the Horizontal Driver IC I701 pin (8), horizontal drive is output from pin (15). The drive sig-
nal is routed to the Horizontal Driver Transistor Q751. This transistor switches the ground return for pin (8) of the
Driver transformer (T751). 28 volts is supplied to pin (5) and this switching allows EMF to develop. As this sig-
nal collapses, it creates a pulse on the output pin of (T751) at pin (4) to the base of the Deflection Horizontal out-
put transistor Q777. This transistor switches the primary windings of the Deflection Transformer T752.
This transformer produces the following output pulses;
• Deflection Pulse from pin (7): This pulse is used by;
1. The Side Pin Cushion Circuit: The Side Pin Cushion circuit for pin cushion correction.
2. The DF OUT Circuit: Generated from the Horizontal Blanking pulse. A Dynamic Focus waveform is
created. This is a parabolic waveform that is superimposed upon the static focus voltage to compensate
for beam shape abnormalities which occur on the outside edges of the screen because the beam has to
travel further to those locations.
3. To X-Ray Protect: This signal is monitored by the X-Ray Protect circuit to place the power supply into
shut down if the Deflection circuit doesn’t operate.
• +28V, M26V and RETRACE PULSE +28P and M28P: The positive 28V and the negative 28V is routed
to the Deflection transformer I752. They enter the transformer as a pure DC voltage then a 7.5V P/P horizon-
tal pulse is added to the DC voltage and leaves as +28P and M28P. From here these voltages are routed to the
Convergence output section and they are rectified. They become +33V and -33V respectively. This process
prevents the need for another power supply. (Note: the M stands for Minus voltage.)
Deflection Pulse from pin (7): The Horizontal Pulse is also routed to the Horizontal Blanking generation transis-
tor Q755. This transistor generates the 13V P/P called H Blk. This signal goes to the following circuits;
• To pin (10) of I701 as FBP In. Here this signal is used as a comparison signal. It is compared to the refer-
ence signal coming in at pin (3) Horizontal Sync. If there are any differences between these two signals, the
output Drive signal from pin (15) is corrected.
• To the Convergence circuit for correction waveform generation.
• Sweep Loss Circuit to shut off the CRTs if Horizontal deflection is lost.
• Through the connector PSD3 pin (6): The H Blk signal is routed from here to the Signal PWB to be used by
different circuits.
The Microprocessor uses this signal for OSD positioning and for Station Detection during Auto programming
within the coincidence detector.
The PinP unit uses this signal for switching purposes. Like the read/write clock, positioning, etc…
The Horizontal Blanking signal H Blk from Q755 is also sent to the High Voltage Driver IC IH01 pin (3). This
IC uses this signal as its reference signal to produce the High Voltage Drive waveform output from pin (1). This
output is routed to the driver transistors, QH08, QH09 and QH10. Then to the High Voltage Horizontal Output
Transistor QH01. This transistor switches the primary of the Flyback transformer TH01. 120V2 is sent through
pin (2) and output pin (10) to the collector of the Horizontal Output Transistor QH01.
A sample of the High Voltage is output from the Flyback transformer TH01 pin (12). This voltage is sent to pin
(9) of the High Voltage Driver IC IH01. This voltage is compared to the reference voltage available at pin (12). If
there is a difference between the two voltages, an error voltage is generated and output from pin (10) and input
again at pin (11) where it manipulates the PWM (Pulse With Modulation) signal producing the Horizontal Drive
signal output from pin (1).
It’s important to notice that the High Voltage circuit can not function without the Horizontal Deflection circuit
providing a drive signal.
PAGE 07-03
GENERAL INFORMATION:
The DP-0X deflection circuit differs from conventional Hitachi product. It utilizes in a sense, two horizontal out-
put circuits. One for Deflection and one for High Voltage. There are many terms around the Horizontal circuit
that are not shown on the Diagram. Some of these terms are explained first:
CUT OFF:
Cut of collapses the Vertical circuit during I2C Bus alignments, during CRT Set Up.
I2C:
Communication from the Microprocessor I001 to I701 during sweep variations due to Standard/NTSC 480P
(Progressive mode) and 1080I High Definition mode, (HD) and Service Adjustments.
ABL:
ABL voltage is generated by monitoring the current through the Flyback transformer. This voltage will fluctuate
down when the scene is bright and up when the scene is dark. The ABL voltage will manipulate the screen bright-
ness and contrast to prevent blooming under these conditions.
HV SYNC:
The composite sync is routed to the Sync processor inside the Horizontal Driver IC I701 which determines the
sweep frequency for the signal being provided. (Everything but HD is 31.5KHz and HD is 33.75KHz).
H and V BLK:
• H Blk: Horizontal and Vertical Blanking is developed within the Deflection circuit. The Horizontal Blanking
pulse operates around 13V P/P and is produced by taking a sample pulse from the Deflection transformer
T752.
• V Blk: The Vertical Blanking pulse is generated from the Vertical output IC, I601 pin (11). This pulse nor-
mally operates at 23V P/P.
IR:
The Infrared Pulses coming from the remote control are routed through the Deflection PWB to the Digital Con-
vergence Unit. During DCAM (Digital Convergence Adjustment Mode), the Remote Control provides manipula-
tion pulses for the DCU.
DIG RGB BUSY:

This indicates Digital RGB and BUSY.
• Digital RGB represents the On Screen Characters produced by the DCU for generating the Digital Conver-
gence adjustment grid and text produced during certain conditions such as Magic Focus, Sensor Initialization,
Data Storage, etc…
• Busy notifies the sub Microprocessor I901 which in turn notifies the DM-1 module that the DCU has entered
the DCAM. During this time, the DM-1 module ignores the remote control commands.
MAGIC SW:
When the customer presses the Magic Focus button on the front of the set, it produces a command for the DCU to
begin the Magic Focus process.
PAGE 07-04
D SIZE:
Digital Size is a control signal for raster enlargement when MAGIC FOCUS is operated. Raster enlargement is
required for the MAGIC FOCUS PATTERN to hit the photo sensors.
This signal is output from DCU and routed to the base of Q613 for enlarging horizontal size through the Pin
Cushion circuit and through Q608 to the Vertical Output IC I601 pin (4) to enlarge the vertical size.
In case of AP-85, this control signal is called "A.SIZE". It's the same function between DIG.SIZE and A.SIZE.
31/33:
31/33 represents the actual Deflection Frequency; 31 = 31.5KHz and 33 = 33.75KHz. The microprocessor knows
the actual frequency of the incoming signal via Sync supplied.
• To the Horizontal Driver IC I701: This tell the Driver IC what output frequency to operate at.
• To the DCU: This signal is sent to the DCU to tell it what frequency the Deflection circuit is running at so it
will know what memory to use. The DCU has two different memory modes. One for Progressive mode
31.5KHz and one for HD mode 33.75KHz.
• To the Dynamic Focus Circuit: This signal is also sent to the Dynamic Focus circuit Horizontal Parabola
generation circuit to compensate for the higher frequency.
TO CONVERGENCE YOKES:
The DCU provides compensation signal for deflection abnormalities to the convergence output IC. The Conver-
gence output IC in turn, amplify the signals and rout them to the convergence yokes.
+B 120V1:
The Deflection transformer receives the 120V V1 DC source.
+B 120V2:
The High Voltage Transformer TH01 (Flyback) receives the 120V V2 DC source.
HV PARABOLA:
See DF Out.
SCREEN 700V: 700V Supplied to the screen grids on the CRT’s.
FOCUS 9KV:
Focus voltage supplied to the CRT’s.
30Kv HV:
32,000 volts DC supplied to the CRT’s anodes.
TO DEFLECTION YOKES:
Horizontal and Vertical deflection wave forms driving the deflection yokes.
PAGE 07-05
DP0X SERIES CHASSIS HORIZONTAL DRIVE CIRCUIT
H. Def. Yoke R
I701
HVCC
10 FBP In VCC 8 Switched AVCC
H. Def. Yoke G
H. Def. Yoke B
HVCO 7
Osc.
15 H Out
HD 3 H. Sync In
To Side Pin Circuit
Def. To Dynamic Focus

Q751 Q777 T752
T751 H Pulse
8 4 1
To X-Ray Protect
7
5 1 6 8
28V 120V V1
+28V
11
12
+28P
PSD3 Q755
M28V
To I001 OSD 6 9
Position H.Blk. 10 M28P
To PinP
Unit To Convergence Circuit
TH01
To Sweep Loss Det. Circuit QN05 120V V2
High
IH02 9 Voltage
3 Gen QH08
Drive QH09
1 10
QH10
Clamp
QH01
11 E 12
r Ref. V.
r FBP In
o HV Sample
PAGE 07-06
10 r 9 12
ADJUSTMENT
INFORMATION
SECTION 8
DP-0X CHASSIS FACTORY RESET CONDITION
USER CONTROL INITIALIZE (FACTORY RESET)
FUNCTION INITIAL DATA/CONDITION

4 EVENT PROGRAM Not Registered
AI OFF
ASPECT RATIO 4X3
AUTO COLOR ON
AUTO LINK OFF
BRIGHTNESS ADJUST MODE
CCD CHANNEL CHANNEL 1
CCD MODE CAPTION
CCD ON/OFF OFF
CHANNEL ID Not Registered
CHANNEL MEMORY Not Registered
CLOCK SET Not Registered
COLOR ADJUST MODE
COLOR SYSTEM NTSC
COLOR TEMPERATURE COOL
CONTRAST ADJUST MODE
FAMILY FAVORITES Not Registered
INPUT ANT A
MENU BACKGROUND SHADED
MENU LANGUAGE ENGLISH
MULTI WINDOW MODE OFF
NOISE REDUCTION OFF
NTSC Channel (Main, Sub) Channel 03
PARENTAL CONTROL Not Registered
SHARPNESS ADJUST MODE
SIGNAL SOURCE AIR
TINT ADJUST MODE
V POSITION 0
AUDIO
MTS Mode STEREO
PERFECT VOLUME OFF
AUTO NOISE CANCEL OFF
LOUDNESS OFF
DYNAMIC BASS OFF
THEATER MODE SPORTS
FDX CHASSIS
BASS 1/2
TREBLE 1/2
BALANCE 1/2
SRS OFF
PAGE 08-01
DP-0X CHASSIS FACTORY RESET CONDITION
USER CONTROL INITIALIZE (FACTORY RESET)
FUNCTION INITIAL DATA/CONDITION

SWX CHASSIS
SCREEN FORMAT NORMAL
SDX and SWX MODELS
GRAPHIC EQUALIZER ALL 0dB (Reset)
SURROUND MODE STEREO
BALANCE (OFF/PCM) 1/2
MASTER VOLUME 20th STEP
VOLUME (FRONT L-STADIUM) 1/2
VOLUME (FRONT R-STADIUM) 1/2
VOLUME (L-ROCK ARENA) 1/2
VOLUME (R-ROCK ARENA) 1/2
VOLUME (L-JAZZ CLUB) 1/2
VOLUME (R-JAZZ CLUB) 1/2
VOLUME (L-DOLBY PRO-LOGIC) 1/2
VOLUME (R-DOLBY PRO-LOGIC) 1/2
VOLUME (L-DOLBY DIGITAL) 1/2
VOLUME (R-DOLBY DIGITAL) 1/2
VOLUME (CENTER-STADIUM) 1/2
VOLUME (CENTER-ROCK ARENA) 1/2
VOLUME (CENTER-JAZZ CLUB) 1/2
VOLUME (CENTER PRO-LOGIC) 1/2
VOLUME (CENTER-DOLBY DIGITAL) 1/2
VOLUME (SURROUND L-STADIUM) 1/2
VOLUME (SURROUND R-STADIUM) 1/2
VOLUME (SURROUND L-ROCK ARENA) 1/2
VOLUME (SURROUND R-ROCK ARENA) 1/2
VOLUME (SURROUND L-JAZZ CLUB) 1/2
VOLUME (SURROUND R-JAZZ CLUB) 1/2
VOLUME (SURROUND L-DOLBY PRO-LOGIC) 1/2
VOLUME (SURROUND R-DOLBY PRO-LOGIC) 1/2
VOLUME (SURROUND L-DOLBY DIGITAL) 1/2
VOLUME (SURROUND R-DOLBY DIGITAL) 1/2
VOLUME (SUB WOOFER-STEREO/PCM) 1/2
VOLUME (SUB WOOFER-STADIUM) 1/2
VOLUME (SUB WOOFER-ROCK ARENA) 1/2
VOLUME (SUB WOOFER-JAZZ CLUB) 1/2
VOLUME (SUB WOOFER-DOLBY PRO-LOGIC) 1/2
VOLUME (LFE-DOLBY DIGITAL) 1/2
TEST TONE OFF
SPEAKER SET UP INTERNAL INTERNAL
External SP W/
SURROUND YES
SUB WOOFER YES
LISTENING POSITION MID
LISTENING MODE STANDARD
INPUT SOURCE VID1 OPTICAL
VID2 COAXIAL
PAGE 08-02
DP0X CHASSIS SIGNAL PWB
MICROPROCESSOR
PFS
IC01
PR
I001
PP1
PL 2H
VIDEO
PWB
DIGITAL BOARD
HC4051
SURROUND PWB I011
I012
I007
I010
U205
FLEX
U201 U202 U204
Conv.
Main PinP 3D/
and
Tuner Tuner YC
PinP
Unit
QS4
TERMINAL PWB
REAR
VIEW
PAGE 08-03
DP0X CHASSIS DEFLECTION PWB
CONVERGENCE
HEAT SINK
SK01: Digital
SERVICE Convergence Unit
IK04 IK05
SWITCH
PSD1
IK01
QK01 PCR PCG PCB PDF
QF06
QH01
YOKE PLUGS
TH01
REAR
VIEW
PMR
R630 PMG
FBT
V.Size
Adj. PMB D656
D657 RH44
R686
High Voltage ADJ.
H.Size
Q657 RH44
Adj. HD
DP37
R683 DP29 Red LED
H.Size +B 120V Green LED
D752 Q777
Adj.
DP01
PQD2
IP01
PQD1
TP91
PDC1
Q701
I601
PSD1 PSD2 PSD3
PAGE 08-04
DP0X CHASSIS CONTROL PWB
DP0X CONTROL SUB P.W.B.
CH -
VOL VOL
MENU/
DOWN POWER
UP SELECT
INPUT
EFC1
CH +
R L V REMOTE CONTROL
S LIGHT RECEIVER
AUTO DIGICON
MO1 (MAGIC FOCUS) HM01
DM09
QM02
EFC1 POWER DIMMER CONTROL

DP0X CONTROL PWB LED LIGHT RECEIVER
FT FS
PAGE 08-05
DP0X CHASSIS SUB POWER PWB
1 9 1 10 7 1
PQU1 PQS1 PQD2 PQD1 PA
2 1
2 1
PQS2 PQU2
1 11 1 8 F901
6 Amp
D913
Audio R/C SW +29V
GREEN
3
PQS4
D912
Audio F SW +29V 1
S901
GREEN
I905
D901
D927 REAR
STBY +7V VIEW
GREEN
D903
IC POWER
D931 MONITOR RED
I907 SW +5V
GREEN
D949 I901
STBY +11V
GREEN
I906
T901
SWITCHING
S904 TRANSFORMER
S903
S902
= RED or GREEN LED USED FOR VISUAL TROUBLESHOOTING
PAGE 08-06
DP-0X CHASSIS CRT PWB
PGV
SHORT TO
P851
R879 KILL THE
COLOR
GND PTSG
P852
E831
Cathode
GREEN
W801
PRV
P801 SHORT TO
KILL THE
R829 COLOR
GND PTSR
E801 P802
Cathode
RED
W801
PVB
P8A1 SHORT TO
KILL THE
PTSB COLOR
GND
P8A2
E8A1
CATHODE
BLUE
PAGE 08-07
DP-0X CHASSIS CLOCK SPEED ACCELERATION PROCEDURE AND CHECK
Use the Clock Speed acceleration to confirm, clock advancement, On/Off Timer, etc.
1) Select Set Up from the Main Menu the Cursor Left and Cursor Right Buttons.
2) Select Clock Set using the Cursor Up and Cursor Down Buttons.
3) Press the Cursor Right button to select Clock Set
4) Set the clock using the Cursor Up, Cursor Down, Cursor Right buttons. The clock is started when
the Cursor Left button is pressed.
5) Connect the JIG (Diode) shown below between I001 Pins 13 and 35.
6) Check that the clock indicaiton is displayed using the RECALL button and the clock is advancing
1 minute per second.
Diode
13 35
DSP SO I Ref
I001
MicroProcessor
PAGE 08-08
DP-0X CHASSIS HIGH VOLTAGE ADJUSTMENT PROCEDURE
1) Connect High Voltage meter to 3) Receive an NTSC generator 6) Lock Paint the control. If avail-
FBT High Voltage output. signal. (Picture should be sta- able.
Connect Ground of High Volt- tionary for this adjustment.
age meter to CRT Ground or 4) Video Controls should be set to
FBT Ground. Factor Settings.
2) Check that the High Voltage 5) Adjust the High Voltage to the
adjustment VR (RH44) is set to following specifications by
it’s mechanical center on the turning RH44 slowly.
Deflection PWB. This VR is • ADJ. SPEC. = 31.5 kV +/ - 0.5
located just behind the Flyback kV for (DP07)
transformer as viewed from the • ADJ. SPEC. = 30.0 kV +/ - 0.5
Front of the set. (See diagram kV for (DP05/DP05F and
below) DP06)
FRONT DEFLECTION PWB
CONVERGENCE
TH01
HEAT SINK
FBT
RH44
High Voltage ADJ.
PAGE 08-09
DP-0X CHASSIS HIGH VOLTAGE LIMITER CHECK
Check Preparation: 1/8W resistor) to both After Checking:

ends of DH31 as shown 1) Unplug set and Remove
1) The set can face any di- in the diagram below. Jig. Allow set to remain
rection. (See Diagram Below) in the off condition for at
2) Receive the Cross-Hatch least 15 seconds.
Signal Checking Procedure : 2) Apply AC and confirm
3) VIDEO CONTROLS: the set returns to normal
Factory Preset. 1) Check that the picture is operation.
4) SCREEN FORMAT: turned off and the hori-
Should be PROGRES- zontal deflection circuit
SIVE mode. stops operation.
5) Attach the JIG (1k ohm
+50V Pulse Add JIG to check Hi

Volt Limit Circuit
DH24 JIG = 1k ohm 1/8W
CH30 RH54
DH31
RH55
PAGE 08-10
DP-0X CHASSIS FLYBACK PROTECTION CIRCUIT CHECK
Check Preparation: Check number (2): Checking Procedure :

Check number (1): 1) The set can face any di-
1) The set can face any direction. 1) Check that the picture is
rection. 2) Receive the Cross- turned off and the hori-
2) Receive the Cross- Hatch Signal zontal deflection circuit
Hatch Signal 3) VIDEO CONTROLS: stops operation.
3) VIDEO CONTROLS: Factory Preset.
Factory Preset. 4) SCREEN FORMAT: After Checking:
4) SCREEN FORMAT: Should be PROGRES- 1) Unplug set and Remove
Should be PROGRES- SIVE mode. Jig. Allow set to remain
SIVE mode. 5) Attach a 100 K ohm in the off condition for
5) Attach a 100 K ohm 1/16W ~ 1/8W resistor at least 15 seconds.
1/16W ~ 1/8W resistor between QH03 base and 2) Apply AC and confirm
between QP04 base and Gnd. the set returns to nor-
Gnd. (SD4 connector mal operation.
Pin 4).
PAGE 08-11
DP-0X CHASSIS SWEEP LOSS DETECTION CIRCUIT CHECK
C heck Preparation: Check Number (2): Checking Procedure :

Check Number (1): 1) T h e s e t c a n f a c e a n y 1) C h e c k t h a t t h e p i c t u r e
1) T h e s e t c a n f a c e a n y direction. is turned off in either
direction. 2) R e c e i v e t h e C r o s s- check.
2) R e c e i v e t h e C r o s s- Hatch Signal
Hatch Signal 3) V I D E O C O N T R O L S : After Checking:
3) V I D E O C O N T R O L S : Factory Preset. 1) R e m o v e J i g a f t e r e a c h
Factory Preset. 4) S C R E E N F O R M A T : check.
4) S C R E E N F O R M A T : S h o u l d b e P R O G R E S- 2) C o n f i r m t h e s e t r e-
S h o u l d b e P R O G R E S- SIVE m o d e . t u r n s t o n o r m a l o p e r a-
SIVE m o d e . 5) A t t a c h t h e J I G ( B ) tion.
5) A t t a c h t h e J I G ( A ) ( 1 0 0 o h m 1 / 8 W r e s i s-
( 1 0 0 o h m 1 / 8 W r e s i s- tor) to right hand side
tor) to right hand side of RN11 and to
of RN01 and to Ground as shown in
Ground as shown in the diagram below.
the diagram below. (See Jig (B) Diagram
(See Jig (A) Diagram Below)
Below)
CN01 CN04
QN01 RN01
QN05 RN11
RN02 RN12
A B
Add JIG to check Hi Add JIG to check Hi
Volt Limit Circuit Volt Limit Circuit
JIG = 100 ohm 1/8W JIG = 100 ohm 1/8W
PAGE 08-12
DP-0X CHASSIS VOLTAGE CHECK
POWER SUPPLY VOLTAGE CHECKS.

Set the AC input power supply to 120 Vac +/-1V.
Receive NTSC CrossHatch Signal
Set the Contrast and Brightness to MAX.
Measure after 30 Seconds of Set Operation.
Audio: MUTE
POWER Measuring Point NTSC CrossHatch Stand-By

SUPPLY PWB Mode
No. Description + Side Pin - Side Pin Voltage +/- Current Voltage +/-
1 SW +35 PQS1 1 PQS1 2 32.66 1.5 0.003
2 STBY +11V PQS1 3/4/5 PQS1 6/7 11.3 1.0 1.30 11.3 1.0
3 STBY +7V PQS2 1/2/3 PQS2 4/5/6 7.20 1.0 0.80 7.3 1.0
4 SW +5V PQS2 7/8 PQS2 9 5.6 0.5 0.66
5 SW +29V AQU1 1/2 AQU1 3/4 31.60 1.5 0.14
6 SW +29V AQU1 5/6 AQU1 3/4 32.20 1.5 0.06
7 SW +12V PQU2 1 PQU2 2 12.30 0.5 0.04
8 SW -12V PQU2 3 PQU2 2 -12.80 0.5 0.11
9 STBY +7V PQU2 5/6 PQU2 7/8 7.72 1.0 0.14 7.3 1.0
10 STBY +11V PQU2 3 PQU2 2 11.44 1.0 0.06 11.3 1.0
11 SW -12V PQU2 6 PQU2 4 -12.80 0.5 0.00
12 SW +12V PQU2 7 PQU2 4 12.20 0.5 0.09
DEFLEC- Measuring Point NTSC CrossHatch Input Stand-By

TION PWB Mode
No. Description + Side Pin - Side Pin Voltage +/- Current Voltage +/-
1 +200V PDC1 1 PDC1 4 223.0 2.0 0.12
2 +28V PDC1 3 PDC1 4 27.3 0.5 0.11
3 HEATER PDC1 5 PDC1 4 6.22 0.5 0.67
4 STBY+11V PQD2 3 PQD2 2 11.26 1.0 0.06 11.3 1.0
5 SW-12V PQD2 6 PQD2 4 -12.00 0.5 0.00
6 SW+12V PQD2 7 PQD2 4 12.3 0.5 0.00
7 SW+8V CP31 + CP31 - 8.77 0.5 0.24
8 SW-8 V CP32 + CP32 - -9.12 0.5 0.13
9 +B CP33 + CP33 - 119.74 1.0 0.72
10 +28V CP40 + CP40 - 27.75 1.0 1.25
11 -28V CP41 + CP41 - -23.11 1.0 0.48
PAGE 08-13
DP-0X MAGNET AND YOKE LOCATION
DP-0X MAGNETS
Adjustment Points
1 2 3
FRONT
RED CRT GREEN CRT BLUE CRT
4
4 6
4
5
5
5
(1) Centering magnet RED (5) Beam Alignment magnets

(2) Centering magnet GREEN (6) Focus Block Assembly
(3) Centering magnet BLUE RED, GREEN & BLUE FOCUS CONTROLS
(4) Beam Form Magnets Also: SCREEN CONTROLS for
RED, GREEN & BLUE
PAGE 08-14
DP-0X CHASSIS ADJUSTMENT ORDER
It is necessary to follow an order when doing adjustments in the DP-0X chassis.
DP-0X SERVICE ADJUSTMENT ORDER “PREHEAT BEFORE BEGINNING”

Order Adjustment Item Screen Format Signal DCU Data
Pre HEAT (30 Minutes) N/A NTSC N/A
1 Cut Off Progressive NTSC
2 Pre Focus Lens and Static Progressive NTSC
3 DCU Phase Data Setting Progressive NTSC
4 DCU Phase Data Setting HD 2.14H
5 Horz. Position Adj. (Coarse) Progressive NTSC
6 Horz. Position Adj. (Coarse) HD 2.14H
7 Raster Tilt Progressive NTSC CLEAR
8 Beam Alignment Progressive NTSC
9 Raster Position Progressive NTSC CLEAR
10 Horz. Size Adjust Progressive NTSC CLEAR
11 Vertical Size Adjust Progressive NTSC CLEAR
12 Beam Form Progressive NTSC
13 Lens Focus Adjust Progressive NTSC
14 Static Focus Adjust Progressive NTSC
15 Blue Defocus Progressive NTSC
16 White Balance Adjustment Progressive NTSC
17 Sub Brightness Adjustment Progressive NTSC Color Bar
Horz. Position Adjustment
18 Progressive NTSC
(Fine)
Horz. Position Adjustment
19 HD 2.14H
(Fine)
20 Convergence Alignment Progressive NTSC CLEAR to start
21 Convergence Alignment HD 2.14H

22 Magic Focus Initialize Progressive NTSC
23 Magic Focus Initialize HD 2.14H
It is necessary to follow the order when performing an alignment on the DP -0X chassis.
PAGE 08-15
DP-0X CHASSIS PRE-HEAT RUN ADJUSTMENTS
PRESET EACH Allow set to operate at

ADJUSTMENT VR TO 12~2 least 30 Minutes before
CONDITION AS SHOWN: beginning adjustments.
A) Before Pre Heat Run.
1) Red and Green Drive VR
on the CRT PWB. (Not DRIVE VR
on Blue CRT).
Pre set between the 12
o’clock and 2 o’clock
position.
2) SCREEN VR ON
FOCUS PACK.
Pre Set fully counter
SCREEN VR
clockwise.
3) Focus VR on focus pack

Pre Set fully clockwise.
FOCUS VR
Screen VR
R G B
Focus VR
R G B
FOCUS PACK
Projection Front View
PAGE 08-16
DP-0X CHASSIS CUT-OFF (SCREENS) ADJUSTMENT
ADJUSTMENT 2) Choose SERVICE item [2]

PREPARATION: of I2C ADJ. Mode. (Select
A) Pre Heat Run should be CURSOR RIGHT [u] and
finished. the Vertical will
collapses).
ADJUSTMENT 3) Adjust any Screen VR.
PROCEDURE: Screen VR should be
1) Go to I2C ADJ. Mode. turned clockwise gradually
(With power ON, press the until that particular color
TV/SAT and the CURSOR is barely visible.
DOWN [q] button. The 4) Repeat for the other two
Service Menu is colors.
displayed.)
Screen VR
R G B
Focus VR
R G B
FOCUS PACK
PAGE 08-17
DP-0X CHASSIS PRE-FOCUS ADJUSTMENT
ADJUSTMENT 2) Adjust the Focus VR for

PREPARATION: Red until Focus is
A) Pre Heat Run should be achieved. (A Fine Adjust-
finished. ment will be made later.)
3) Repeat for Blue and
FOCUS ADJUSTMENT: Green.
1) Short the 2pin sub- 4) To Return to Service
miniature connector on the Menu, press the CURSOR
CRT PWB (TS), to RIGHT [u] key on re-
remove any color not mote.
being adjusted and adjust
one color at a time. (The
adjustment order of R, G
and B is just an example.)
Screen VR
R G B
Focus VR
R G B
FOCUS PACK
PAGE 08-18
DP-0X CHASSIS DCU CROSSHATCH PHASE ADJUSTMENT
Adjustment Preparation: Exiting Adjustment Mode:

1) Cut Off adjustment should 6) Press Help key on remote
be finished. control.
2) Video Control: Brightness 7) Press SWAP key
90%, Contrast Max. TWICE to store the
3) information.
Adjustment Procedure: 8) When Green dots are
1) Receive any NTSC signal. displayed, press the 8 key
2) Screen Format is Progres- on remote.
sive 9) Press the SERVICE
3) Press and Hold the ONLY switch to return to
SERVICE ONLY switch normal mode.
on the deflection PWB.
4) Press the HELP key on HD Mode Adjustment
the Remote, then press the Mode:
EXIT key. (This is the 10) Change the Display
Phase adjustment mode). Format to HD 2.14H
5) Adjust data value using Mode.
the keys indicated in the 11) Repeat steps 3 through 9
chart, until the data for the HD 2.14H mode.
matches the values indi-
cated in the chart.
PHASE MODE Display Format Display Format

PROGRESSIVE HD
ADJUST USING Address Data Value Address Data Value
4 and 6 keys on Remote PH-H BB PH-H BB
2 and 5 keys on Remote PH-V 0C PH-V 07
Cursor Left t and Right u on Remote CR-H 4C CR-H 4C
Cursor Up p and Down q on Remote CR-V 00 CR-V 0C
PAGE 08-19
DP-0X CHASSIS HORIZONTAL PHASE (COARSE) ADJUSTMENT
Adjustment Preparation: 5) Enter the I 2C Bus align- 5) Enter the I 2C Bus align-
1) Cut Off, DCU Phase ad- ment menu and select ment menu and select
justments should be fin- Item [12] H POSI and ad- Item [12] H POSI and ad-
ished. just the data so that the just the data so that the
2) Video Control: Brightness center of Video matches center of Video matches
90%, Contrast Max. the location of the Digital the location of the Digital
Crosshatch pattern noted Crosshatch pattern noted
Adjustment Procedure in step {4}. in step {4}.
PROGRESSIVE MODE: 6) Exit from the I C Menu. 6) Exit from the I2C Menu.
2
1) Receive any NTSC cross-

hair signal. HD Mode Adjustment:
2) Screen Format is PRO- 1) Receive any 2.14H signal.
GRESSIVE. 2) Screen Format is HD.
3) Press the SERVICE 3) Press the SERVICE
ONLY switch on the de- ONLY switch on the de-
flection PWB and display flection PWB and display
the Digital Convergence the Digital Convergence
Crosshatch pattern. Crosshatch pattern.
4) Mark the center of the 4) Mark the center of the
Digital Convergence Digital Convergence
Crosshatch Pattern with Crosshatch Pattern with
finger and press the SER- finger and press the SER-
VICE ONLY switch to VICE ONLY switch to
return to normal mode. return to normal mode.
PAGE 08-20
DP-0X CHASSIS TILT (RASTER INCLINATION) ADJUSTMENT
Adjustment Preparation: hold the SERVICE ONLY RED:

1) The set can face any direc- switch, then press the 1) Remove cover from RED
tion. POWER button). CRT and align RED with
2) Receive the Cross-Hatch The Service Only switch is GREEN.
Signal on the Deflection PWB. 2) [+/- 1mm tolerance when
3) VIDEO CONTROLS: compared to Green]
Factory Preset. Adjustment Procedure :
4) SCREEN FORMAT: GREEN: BLUE:
should be PROGRES- 1) Apply covers to the RED 1) Remove cover from
SIVE mode. and BLUE lenses or short BLUE and cover the RED
5) The lens focus should the 2P Sub Mini connector CRT. Align BLUE with
have been coarse adjusted. [TS] on each CRT PWB GREEN.
6) The electrical focus to produce only GREEN. 2) [+/- 1mm tolerance when
should have been coarse 2) Turn the Green deflection compared to Green]
adjusted. yoke and adjust the TILT 3) REMOVE ALL COV-
7) The Digital Convergence until the green is level. ERS.
RAM should be cleared. 3) [+/- 2mm tolerance]. See 4) Turn the power off.
(Turn power off, press and diagram.
l =< 2mm
Vertical Center axis of

Cross-Hair signal
PAGE 08-21
DP-0X CHASSIS BEAM ALIGNMENT ADJUSTMENT
Preparation for adjustment: 2) Put Green (G) tube beam align- 8) Conduct beam alignment for
1) Pre Heat, Pre-optical focus, ment magnet to the cancel state Red and Blue in the same way.
DCU Phase Data, H. Pos as shown in Figure 1. (See Fig- 9) Red (R) focus on focus pack.
Course and Raster Tilt adjust- ure 1.) 10) Blue (B) focus on focus pack.
ment should be completed. 3) Turn the Green (G) static focus 11) Upon completion of adjust-
2) Brightness: 90% VR counterclockwise all the ment, place a small amount of
Contrast Max. way and make sure of position white paint on the beam align-
4) Receive cross hatch signals, or of cross hatch center on screen. ment magnets, to assure they
dot pattern 4) Turn Green (G) static focus VR don’t move. (If available).
RASTER TILT adjustment clockwise all the way.
should be finished. 5) Turn two Beam alignment mag-
5) SCREEN FORMAT should net in any desired direction and
be PROGRESSIVE mode. move cross hatch center to posi-
Adjustment procedure: tion found in step (3). (See Fig-
1) Green (G) tube beam alignment ure 2 below).
adjustment: 6) If image position does not shift
Short-circuit 2P subminiature when Green static focus VR is
connector plug pins of Red (R) turned, adjustment complete.
and Blue (B) on the CRT boards 7) If image position does move,
and project only Green (G). repeat steps [2] through [6].
ADJUSTMENT
Figure 1 TABS BEAM SHAPE &
PICTURE TUBE SIDE ALIGNMENT MAGNET
4-POLE BEAM SHAPE

CORRECTION MAGNET
ZERO FIELD SPACER

(NO ADJUSTMENT)
The figure shows that the long and
short knobs of the 2P magnet are 2-POLE BEAM
aligned, this is the cancel state. ALIGNMENT MAGNET
Figure 2
PAGE 08-22
DP-0X CHASSIS RED AND BLUE RASTER OFF SET ADJUSTMENT
INFORMATION:
Raster Off set is necessary to conserve Memory allocation.
It is very important to remember that the Red is off-set Left of Center and Blue is off-set Right of center.
Please use the following information to accurately offset Red and Blue from center.
Also see Overlay Dimensions for further details.
MODEL NUMBER RED OFFSET BLUE OFFSET ASPECT

LEFT OF CENTER RIGHT OF CENTER
43FDX01B 20mm 35mm 4X3
53FDX01B 15mm 25mm 4X3
53SDX01B 15mm 25mm 4X3
53SWX01B 15mm 25mm 16X9
61SDX01B 15mm 25mm 4X3
61SWX01B 15mm 25mm 16X9
Red Blue
Geometric Center
PAGE 08-23
DP-0X HORIZONTAL SIZE ADJUSTMENT
HORIZONTAL SIZE: FOR PROGRESSIVE Alternate Method:

(Display Mode PROGRES- MODE Adjust Horizontal Size until
SIVE or HD as Depicted) the size matches the chart be-
• Install the correct Overlay 1) Adjust R683 (Horz. Size low.
dependant upon the Dis- Adj. VR) to match marks
play Mode being adjusted. on the Overlay.
• Input any NTSC Signal.
• Digital Convergence FOR HD MODE
RAM should be cleared.
With Power Off, press and 2) Adjust using R686 (Horz.
hold the Service Only Size Adj. VR) to match
Switch on the Deflection marks on the Overlay.
PWB, then press Power. (See Figure Below)
• Project only the Green 3) Press “Power Off” to exit
raster. Service Menu.
L= DP06 DP06 DP05/05F DP05/O5F DP07 DP07
Progressive HD Mode Progressive HD Mode Progressive HD Mode

Mode Mode Mode
Size of Distance of l Distance of l Distance of l Distance of l Distance of l Distance of l
Screen
61 Inch 1200 +/- 5mm 1200 +/- 5mm - - 1305 +/- 5mm 1305 +/- 5mm
60 Inch - - 1190 +/- 5mm 1190 +/- 5mm - -
53 Inch 1050 +/- 5mm 1050 +/- 5mm 1050 +/- 5mm 1050 +/- 5mm 1135 +/- 5mm 1135 +/- 5mm
50 Inch - - 995 +/- 5mm 995 +/- 5mm - -
46 Inch - - - - - -
43 Inch - - 860 +/- 5mm 860 +/- 5mm - -
HORIZONTAL SIZE
l
Between Outside Lines
PAGE 08-24
DP-0X VERTICAL SIZE ADJUSTMENT
VERTICAL SIZE: 2) Press “Power Off” to exit NOTE: The Vertical Fre-
(Display Mode PROGRES- Service Menu. quency is shared between
SIVE or HD) Vertical rate Progressive and HD modes.
stays the same. NOTE: Centering magnet
may be moved to facilitate. Alternate Method:
1) Adjust using R630 Distance is important, not Adjust Vertical Size until the
(Vertical Size Adj. VR) to centering. size matches the chart below.
match marks on the Over-
lay. (See Figure Below)
L= DP06 DP05/05F DP07
Progressive Progressive Progressive

Mode Mode Mode
Size of Screen Distance of l Distance of l Distance of l
61 Inch 775 +/- 5mm - 635 +/- 5mm
60 Inch - 770 +/- 5mm -
53 Inch 670 +/- 5mm 670 +/- 5mm 550 +/- 5mm
50 Inch - 650 +/- 5mm -
46 Inch - - -
43 Inch - 550 +/- 5mm -
VERTICAL SIZE
PAGE 08-25
DP-0X BEAM FORM ADJUSTMENT
BEAM SHAPE (FORM) Adjustments procedure: 5) Also adjust the Red and Blue
Preparation for adjustment 1) Green CRT beam shape adjust- CRT beam shapes according to
IMPORTANT: Screen format ment. the steps (1) to (3).
should be “PROGRESSIVE“. 2) Short-circuit 2P sub-mini con- 6) After the adjustment is com-
1) Pre Heat, Cut-Off, Pre-optical nectors on Red and Blue CRT pleted, return R, G and B static
focus, DCU Phase Data, H. Pos PWB to project only the Green VRs to the Best Focus point.
Course, Raster Tilt, Beam beam.
Alignment, Raster Position, 3) Turn the green static focus VR
Vertical and Horizontal Size fully clockwise.
adjustment should be com- 4) Make the dot at the screen cen-
pleted. ter a true circle, using the 4-Pole
2) Brightness: 90%, Contrast: magnet shown in (Figure 2 be-
Max. low.)
3) Input a NTSC DOT signal.
ADJUSTMENT
TABS
PICTURE TUBE SIDE
b 4-POLE BEAM SHAPE

CORRECTION MAGNET
ZERO FIELD SPACER

(NO ADJUSTMENT)
a 2-POLE BEAM
ALIGNMENT MAGNET
Figure 1 Figure 2
PAGE 08-26
DP-0X LENS FOCUS ADJUSTMENT
Preparation for adjustment 7) (See Figure 1) Loosen the 9) After completing optical
fixing screw on the lens focus, tighten the fixing
1) Receive the Cross-hatch assembly so that the lens screws for each lens.
pattern signal. cylinder can be turned. 10)When adjusting the Green
2) The electrical focus adjust- (Be careful not to loosen Optical focus, be very
ment should have been the screw too much, as careful. Green is the most
completed. this may cause movement dominant of the color guns
3) Deflection Yoke tilt of the lens cylinder when and any error will be eas-
should have been adjusted. tightening.) ily seen.
4) Brightness = 50% 8) Rotate the cylinder back 11)Repeat Electrical Focus if
5) Contrast = 60% to 70% and forth to obtain the best necessary.
focus point, while observ-
Adjustment procedure ing the Cross-Hatch.
(Observe the center of the
6) Short the 2 pin sub- screen).
miniature connector on the
CRT P.W.B. TS, to pro- • Hint: Located just below
duce only the color being the screen are the two
adjusted and adjust one at wooden panels. Remove
a time. (The adjustment the panels to allow access
order of R, G and B is just to the focus rings on the
an example.) Lenses.
FIXING SCREW
r
de
in
yl
C
ns
Le
LENS ASSEMBLY R, G, B.
Figure 1
PAGE 08-27
DP-0X STATIC FOCUS ADJUSTMENT
ADJUSTMENT 2) Adjust the Focus VR for

PREPARATION: Red until maximum Focus
A) Pre Heat Run should be is achieved.
finished. 3) Repeat for Blue and
Green.
FOCUS ADJUSTMENT: 4) To Return to Service
1) Short the 2pin sub- Menu, press the CURSOR
miniature connector on the RIGHT [u] key on re-
CRT PWB (TS), to mote.
remove any color not
being adjusted and adjust
one color at a time. (The
adjustment order of R, G
and B is just an example.)
Screen VR
Screen VRs
R G B
Focus VR
Focus VRs
R G B
FOCUS PACK
PAGE 08-28
DP-0X BLUE DE-FOCUS ADJUSTMENT
Adjustment Preparation: Adjustment Procedure 1mm on each side equal-

ing 2mm total. See figure
1) Video Control: Brightness 1) Receive any NTSC cross- Below.
90%, Contrast Max. hatch signal.
2) SCREEN FORMAT 2) Turn the B FOCUS VR
should be PROGRES- fully clockwise.
SIVE mode. 3) Adjust BLUE defocus ac-
cording to the following
specifications.
Blue Defocus “Sticking Out”
Center of Blue crosshatch line Screen VR

Screen VRs
R G B
Focus VR
Focus VRs
R G B
FOCUS PACK
PAGE 08-29
DP-0X WHITE BALANCE ADJUSTMENT
Note: When Vertical is collapsed, make adjustments quickly, the image can burn the CRTs.
White balance adjustment 3) Gradually turn the screen 6) Turn the Brightness and
1) Screen adjustment adjustment VRs (red, Contrast OSD all the way
2) High brightness white green, blue) clockwise and up.
balance set them where the red,
3) Low brightness white green and blue lines are 7) Make the whites as white
balance equal and just barely visi- as possible using the drive
ble. adjustment VRs (Red
Adjustment VRs: 4) Return Service item on I 2C R829 and Green R879).
Screen adjustment VRs on ADJ to Off by Cursor 8) Set the Brightness and
Focus Block Right. Number [2]. Contrast to minimum.
Drive adjustment VRs on Adjust the Sub Brightness (10800 Kelvin)
CRT P.W.B. Number [1] SUBBRT us- 9) Adjust the low brightness
Red Drive = R829R ing I2C Bus alignment areas to black and white,
Green Drive = R879G procedure so only the using screen adjustment
Preparation for adjustment slightest white portions of VRs (red, green, blue).
1) Start adjustment 20 min- the raster can be seen. 10) Check the high brightness
utes or more after the 5) Input a gray scale signal whites again. If not OK,
power is turned on. into any Video input and repeat steps 6 through 9.
2) Turn the brightness and select that input using the 11) Press the MENU key on
black level OSD to mini- INPUT button on the re- remote to Exit Service
mum by remote control. mote or front control Menu.
3) Receive a tuner signal, panel.
(any channel, B/W would
be best).
4) Set the drive adjustment
Screen VR
VRs (Red R829R and Screen VRs
Green R879G) to their me-
R G B
chanical centers. Focus VR
Focus VRs
Adjustment procedure R G B
1) Go to I2C ADJ. Mode. FOCUS PACK

(With power ON, press
DTV/SAT and Cursor
Down buttons at the same
time. Service Menu is dis- RED CRT GREEN CRT BLUE CRT
played.)
2) Choose SERVICE item
Number [2] of I2C ADJ.
Mode. (Select ON by Cur-
sor Right and the Vertical
will collapses).
PAGE 08-30
DP-0X SUB BRIGHTNESS ADJUSTMENT
Note: When Vertical is collapsed, make adjustments quickly, the image can burn the CRTs.
ALTERNATE METHOD: ADJUSTMENT PROCE- 4) Press the MENU key to

ADJUSTMENT PREPA- DURE exit Service Menu
RATION: 1) Go to I2C ADJ. Mode.
(Coarse Adjustment) (With power ON, press USING A GENERATOR:
1) Start adjustment 20 min- TV/SAT and Cursor Down 1) Use the input signal
utes or more after the buttons at the same time. shown below, (GRAY
power is turned on. Service Menu is dis- SCALE)
2) Receive a tuner signal. played.) 2) Adjust Sub Brightness
3) Set the contrast and color 2) Adjust Sub Brightness Number [1] SUBBRT, so
controls to minimum. Number [1] SUBBRT, so that the points A1 and A2
4) Set the brightness to mini- that only the brightest sink to black and A3 is
mum position on the dis- points of the picture can be slightly visible, using I2C
play. seen on screen, using I 2C Bus alignment procedure.
5) The room light should be Bus alignment procedure. 3) Press the MENU key to
very low. 3) (Also see White Balance exit Service Menu
Tracking).
W Y CY G MG R BL
75% The background is set to black.
Perform the adjustment without
A7 A6 A5 A4 A3 A2 A1
observing the boundary parts.
B
The background is set to lighter
black.
D
Q I W 100% BLK
RED CRT GREEN CRT BLUE CRT Screen VR

Screen VRs
R G B
Focus VR
Focus VRs
R G B
FOCUS PACK
PAGE 08-31
DP-0X HORIZONTAL POSITIONS (FINE) ADJUSTMENT
Adjustment Preparation: 4) Adjust the data so that the 3) Enter the I 2C Bus align-
1) Video Control: Brightness Left and Right hand side ment menu and select Item
90%, Contrast Max. are equal as noted in the [12] HPOSI
Adjustment Procedure figure on the right. 4) Adjust the data using the
PROGRESSIVE MODE: 5) Press the “MENU” button left and right cursor keys
to exit from the Service and balance the Left and
1) Receive any NTSC circle Menu. Right hand side.
pattern signal. 5) Press the “MENU” button
2) Screen Format is PRO- HD Mode Adjustment: to exit from the Service
GRESSIVE 1) Receive any 2.14H Menu.
3) Enter the I 2C Bus align- 33.75kHZ signal.
ment menu and select 2) Display Format is HD
Item [12] HPOSI mode.
PROGRESSIVE MODE: HD MODE:

Balance left and right side display position. Balance left and right side display position.
PAGE 08-32
DP-05F OVERLAY DIMENSIONS FOR THE 43 INCH (4 x 3 Aspect) JIG
Red and Blue Centering Offset is necessary to free up memory in the Digital Convergence
Unit.
It is important to offset the Red and Blue centering during Magnet Centering. Failure to do
so, could produce a Memory Overrun error. Red Offset = 20mm and Blue Offset = 35mm
for Progressive and HD Mode.
Green is Geometrically centered.
(874)
(72) [874]
[72]
H. SIZE
(46.7)
[41.8]
(93.4)
[83.6]
R B
(656)
[656]
Centering Offset
(1.1)
[35.4]
V. SIZE Progressive ( )
(5)
HD [ ]
[5]
HORIZONTAL SIZE VERTICAL SIZE

Progressive Mode = 860 Progressive Mode = 550
HD Mode = 860 HD Mode = 550
Not for 43GX01B
Use: H310222 H312225 = Progressive Mode JIG Screen Kit
Overlay Jig H312226 = HD Mode JIG Screen Kit
PAGE 08-33
DP-05/06 OVERLAY DIMENSIONS FOR THE 53 INCH (4 x 3 Aspect) JIG
Unit.
(1078)
(88.8) [1078]
[88.8]
H. SIZE
(57.5)
[43.5]
(115)
[103]
R B
(808)
[808]
Centering Offset
(1.5)
[43.5]
(6.2) HD [ ]
[6.2]

Not for Other 53 Inch Models HD Mode = 1050 HD Mode = 670
Use:
H310359 Progressive
H312184 HD Mode H312223 = Progressive Mode JIG Screen Kit
Overlay Jigs H312224 = HD Mode JIG Screen Kit
PAGE 08-34
DP-06 OVERLAY DIMENSIONS FOR THE 61 INCH (4 x 3 Aspect) JIG
Unit.
(1200)
(102.1) [1200]
[102.1]
H. SIZE
(66.2)
[50]
(132.4)
[118.6]
R B
(930)
[930]
Centering Offset
(1.6)
[50]
(7.4) HD [ ]
[7.4]

H310355 = Progressive Mode JIG Screen Kit

H312181 = HD Mode JIG Screen Kit
PAGE 08-35
Unit.
Grid show is NOT in proper (16X9) aspect, however values are correct. 16X9
(1173.2)
(96.6) [1173.2]
[96.6]
H. SIZE
(46.9)
[42.1]
(94.0)
[84.1]
R B
(660)
[660]
Centering Offset
(1.1)
[35.6]
(7.0) HD [ ]
[7.0]

Unknown = Full Mode JIG Screen Kit

Unknown = Smooth/Widel Mode JIG Screen Kit
PAGE 08-36
Unit.
16X9
Grid show is NOT in proper (16X9) aspect, however values are correct.
(1350)
(111.2) [1350]
[111.2]
H. SIZE
(54.2)
[48.6]
(108.5)
[97.1]
R B
(762)
[762]
Centering Offset
(1.3)
[41.1]
(7.8)
HD [ ]
[7.8]

Unknown = Full Mode JIG Screen Kit

Unknown = Smooth/Widel Mode JIG Screen Kit
PAGE 08-37
DP-0X DIGITAL CONVERGENCE ADJUSTMENT POINT (3X3 and 5X7)
STOPPING POSITIONS
3 X 3 MODE (9 stopping positions)

(NOTE: This mode can only be activated when the Digital RAM is cleared.)
To clear the RAM: Press and Hold the SERVICE ONLY SWITCH
(Service only switch is located on the deflection PWB), then press the POWER BUTTON.
Set will have no convergence correction.
Press RECALL 5 times on the CLU-572TSI to access the 3 X 3 Mode.
NOTE: Old ROM data can be restored by pressing the SWAP button TWICE.
The set will be restored to the last condition when data was stored.
3 2 9
This mode should

only be needed
when a complete Begin with Green
1
Digital 4 8 in this mode
convergence
adjustment is
nece s sary.
5 6 7
MUST USE OVERLAY IN THIS MODE

DIGITAL CONVERGENCE CURSOR STOPPING POINTS.
Press the 0 button on the remote 5 times. The raster will blink and the cursor will flash indicating 5 X 7
MODE.
19 18 17 16 35 34 33
20 10 3 2 9 15 32
21 11 4 1 8 14 31
22 12 5 6 7 13 30
23 24 25 26 27 28 29
Note: Grid will actually be slightly different than shown.
PAGE 08-38
DP-0X DIGITAL CONVERGENCE ADJUSTMENT POINT (13X9)
STOPPING POSITIONS
Press the INPUT button on the CLU-572TSI remote 5 times to activate the 117 stopping positions.
The raster will blink and the cursor will flash indicating 13 X 9 MODE.
NOTE:
This is the normal mode when entering the digital convergence adjustment mode.
84 83 82 81 80 79 78 117 116 115 114 113 112

85 51 50 49 48 47 46 77 76 75 74 73 111
86 52 36 26 12 11 10 25 24 35 45 72 110
87 53 37 27 13 3 2 9 23 34 44 71 109
88 54 38 28 14 4 1 8 22 33 43 70 108
89 55 39 29 15 5 6 7 21 32 42 69 107
90 56 40 30 16 17 18 19 20 31 41 68 106
91 57 58 59 60 61 62 63 64 65 66 67 105
92 93 94 95 96 97 98 99 100 101 102 103 104
Sometimes during adjustment, S-Distortion can occur. This is when the line has a noticeable wavy
appearance at a certain locatio n. If this is encountered, enter the (5X7) mode and readjust the line. Then
perform Calculation. It may be necessary to return to the (3X3) mode as well.
Note: Store will also perform Calculation.
PAGE 08-39
DP-0X DIGITAL CONVERGENCE ALIGNMENT PROCEDURES
Digital Convergence Alignment
Center the Overlay Jig geometrically on the screen
Receive any NTSC signal (Crosshair if possible)

Set SCREEN FORMAT TO PROGRESSIVE mode
Clear RAM data (DCU RAM)
Service only
Internal
switch
Digital
is on the Press and hold the SERVICE SWITCH
"Cross Hatch
deflection Button, then press the POWER Button
Signal" is
PWB. simultaneously until the set is on.
projected
When video appears, press SERVICE
SWITCH again.
No DCU Correction added

results in severe
pincushion distortion
Center Magnet Adjustments
Select the External Center Cross Signal by

pressing the EXIT button 5 times, then the
Remote INPUT button .
Use the Centering A l i g n t h e G , R , B

External Selected Center
Magnets closest to individual center crosses
Cross with no DCU center
the Yoke to their respective marks
data
on the Overlay using the
Yoke Center Magnets
R G B
Red = Blue =
Front View Left 15mm Right 25mm
R G B
Green =
Center
A Geometric Center of Screen
PAGE 08-40
Static Centering Alignments

(Moves Entire Raster)
Internal Cross
Hatch Signal
selected
Press the Remote FRZ button
(extra lines will appear at top
and bottom )
Extra Lines
appear
indicating
Raster
Mode
Remote
Adjust Color Up
Press the Remote Cursor buttons to
match the selected Crosshatch
Adjust Adjust
(red and blue) to the green. SELE
Color Color
CT
Left Right
Input Selects BLUE Adjust Color Down

0 Selects RED
Align Red and Blue static centers
Green should already be centered
Press the Remote

FRZ button
to exit Static Centering.
(extra lines will disappear)
B
PAGE 08-41
Convergence 3x3 Point Adjustment Mode

(Green Coarse Alignment)
Press the Remote R E C A L L

button to enter the Green
Adjustment Mode (The 3X3 Mode
can only be
Press the Remote R E C A L L entered when
button 5 times to enter the the DCU RAM
3X3 Adjustment Mode data is cleared)
RECALL Button
is used for Green Only
selecting the
3X3 Press the Remote
Adjustment MENU button to
Mode (when project the green
pressed 5 tube only
times).
Remote
ALL
REC
Use the Remote 2 , 4, 5, 6 number

buttons to move the Adjustment Selects GREEN
3X3 Mode =
Point location (intersection of
9 Adjustment Points
blinking cursor) and the Cursor
Remote
Cursor blinks Buttons to adjust the lines so that
at intervals the green cross hatch align
of 3 to with the Overlay (Jig) SEL
ECT
indicate the
3X3
Before Adjustment
Adjustment
Adjusted by cursor keys
Mode
After Adjustment
Remote
4 5 6
Lines symmetrically
Moves location of
aligned at Adjustment
Adjustment Point
Points
(Intersection of
blinking cursor)
C
Continue on next page
PAGE 08-42
C
Before Calculation
Press the Remote "INFO " button

to Calculate points in between the
adjustment points
averages the error between the

Calculation
points to prevent"S" Distortion
Convergence 3x3 Mode (9 Point) Adjustment

(Red / Blue Coarse Alignment)
After interpolation, press the Remote 0 button to

Green always select the Red Convergence Adjustment Mode
projected
Remote
Cursor
blinks RED 4 5 6
7 8 9
0
0 Selects RED
Press the Remote 2,4,5,6 buttons to move

Crosshatch is the adjustment point, and the Cursor buttons
yellow when the to converge the selected color onto green
red and green
crosshatches align
Cursor Blinks Blue
Press the Remote

INFO button to
interpolate as often as
necessary
Remote
4 5 6
Selects 7 8 9
Has the Blue Blue 0

3x3 Convergence INPUT C.S.
Mode been
aligned? Press the Remote
No
INPUT button to
Select the Blue
Crosshatch is cyan when the blue Convergence
and green crosshatches align Yes Adjustment Mode
White internal crosshatch

should be projected
Press Menu
Button D
PAGE 08-43
Convergence 7x5 Point Adjustment

(Green Only Alignment)
Remote
4 5 6
7 8 9
Press the Remote 0 button five 0

times to enter the 7X5 mode
Selects the 7X5

mode
Remote
Press the Remote R E C A L L button LL

RECA
to project the green only
Selects GREEN
Use the Remote Cursor and 2,4,5,6 buttons to

perform convergence point adjustment at every
other intersection of the crosshatch
35 convergence adjustment
points in 7X5 mode
Remote
Adjust Color Up
Adjust Adjust
Color SEL
Color
Left ECT
Right
Adjust Color Down
Press the Remote INFO button to

interpolate points in between the
adjustment points
PAGE 08-44
E
Remote
Convergence 7x5 Point Adjustment 4 5 6
(Red/Blue Alignment) 7 8 9
0
Press the Remote 0 button to project

the Red/GreenCrosshatch
Press the Remote Cursor and 2,4,5,6

buttons to perform convergence
point adjustment at every other
Perform intersection of the crosshatch
adjustment
at every
other Cursor Blinks Blue
intersection
Press the
Remote INFO
button to
interpolate as
often as
necessary
Cursor blinks red
at intervals of 2
to indicate the Press the Remote INPUT
7x5 mode button to select the Blue
Convergence Adjustment
Mode
Remote
Has the Blue 4 5 6

7X5 Convergence Mode 7 8 9
been aligned?
0
White Internal
Input
Crosshatch
should be
projected Yes
Press Menu Button Selects Blue for

adjustment
F
PAGE 08-45
Convergence 13X9 Point Adjustment

(Green Only Alignment)
Press the Remote INPUT

button five times to
enter the 13X9 mode
Remote
Remote
INPUT
RECALL Press the Remote RECALL
button to project
the green only
Selects GREEN
Selects the
13X9 mode
Use the Remote Cursor and 2,4,5,6

buttons to perform convergence
point adjustment at every other
intersection of the crosshatch
117 convergence
adjustment points in
13X9 mode Remote
Adjust Color Up
Adjust Adjust
Color SEL
Color
Left ECT
Right
Adjust Color Down
Press the Remote INFO button to

interpolate points in between the
adjustment points G
PAGE 08-46
Convergence 13X9 (117 Point)

Remote
Adjustment (Red/Blue Alignment) 4 5 6
7 8 9
0
Press the Remote " 0 " button to enter RED Adjustment

Mode and to project the Red/GreenCrosshatch
Press the Remote Cursor and

2,4,5,6 buttons to perform
Perform convergence point adjustment at
adjustment every intersection of the
at every crosshatch Cursor Blinks Blue
intersection
Press the
Remote INFO
button to
interpolate as
often as
necessary
Cursor blinks red
indicating the
13X9 mode
Press the Remote INPUT
button to select the Blue
Remote Convergence Adjustment
Adjust Color Up Mode
Adjust Adjust
Color SEL Remote
ECT Color
Left Right
Has the Blue INPUT
13X9 Convergence No
Adjust Color Down
Mode been
aligned?
White Internal
Selects Blue for
Crosshatch
adjustment
should be
projected
Yes
Press the Menu Button

to Display all colors
PAGE 08-47
Store New Convergence Data in Rom
Press the Remote MOVE button

twice to begin the ROM Write
mode = STORE
1
ROM WRITE? 2
This screen is projected at the first

press of MOVE button
3 Screen goes blank for several

seconds at the second push of
the MOVE button
!!!! WARNING !!!!

Initialization must be done after a
Write to Rom, (STORE) in order
for MAGIC FOCUS to operate.
This screen appears with a series of If this is not done, when the
green dots indicating a successful MAGIC FOCUS button is pressed,
Write to Rom or Store. the Static Centering Mode
Note: If Red dots appear, retry the will be entered.
process. If Red dots appear the Return to the Digital Conv.
second time, replace the Digital Adjustment Mode and Initialize
Convergence module. the Magic focus.
Press the Remote MOVE button to

return to the Digital Convergence
Adjustment mode
I
PAGE 08-48
DP-0X
DP-85 DIGITAL
DIGITAL CONVERGENCE
CONVERGENCE ALIGNMENT
ALIGNMENT PROCEDURES
PROCEDURES
Magic Focus Initialization
Press the Remote MOVE button once
1
ROM WRITE?
Again the screen projects

ROM WRITE at the first
press of MOVE button
Press the Remote PIP CH button to

begin the Initialization Mode
This screen appears with a series of

green dots indicating successful 2
sensor Data Initialization
MAGIC FOCUS
3
Screen projects different light
patterns during the
Initialization Mode
Press the Menu Button to return to Crosshatch. Finished

with Digital Convergence Setup for PROGRESSIVE.
Press the Service Only Switch to Exit to Normal Mode
Change the screen format to HD mode.

Install the HD Overlay. Press the Service
Only switch to enter the DCAM.
Return to (D) and align to the Overlay.
After completing PROGRESSIVE AND

HD mode adjustments, operation complete.
PAGE 08-49
Additional MINOR Adjustments

Available to the Service Technician
CENTER Static or Center STATIC

alignment
is off.
Screen goes black

for several seconds.
Press and Hold Magic Focus Press and hold the Magic Focus
button for 5 seconds until button for 10 seconds until
CENTER appears on Screen STATIC appears on Screen.
Release Button Release Button
Internal Crosshair or Internal crosshatch

Center Cross should appear. Remote should appear.
Adjust Color Up
Adjust Adjust
Color SELECT Color
Left Right
CENTER STATIC
Adjust Color ADJUSTMENT
ADJUSTMENT
Down
Center Cross will blink indicating which

Center Cross will blink indicating Color can be adjusted. Adjust using the
which Color can be adjusted. cursor keys on the Remote.
Adjust using the cursor keys on the Remote. To select other color, press the Menu
To select other color, press the Menu Button. Button.
Press "MAGIC FOCUS Button" to Exit to normal Mode
PAGE 08-50
Convergence Touchup
Overlays NOT required!
Convergence Point Adjustment

IMPORTANT: Begin in PROGRESSIVE mode.
Enter the Service Mode by pressing the

Service Only Switch on Deflection PWB.
Press "0" five times to select the 7X5 Mode

Press "INPUT" five times to select the 13X9 Mode
Note: 3X3 mode can not be entered without clearing ROM data.
Press the MENU button to Remove

colors not being adjusted.
Press "2, 4, 5, 6" to move Adjustment Point

Press cursor Up / Down / Left / Right to Adjust Convergence
When adjustment is complete, STORE the New

DATA by pressing the MOVE button twice.
After Storing, initialize the MAGIC FOCUS

by pressing the MOVE button ONCE
and then press the PIP CH button.
See "Complete Digital Convergence
Alignment procedure" for more details.
1 2
Press the Service Only Switch After HD
to Exit to PROGRESSIVE mode. has been completed
Set display mode Touch Up

to HD mode complete
PAGE 08-51
KEY COMPONENT
INFORMATION
SECTION 9
DP-06 KEY COMPONENTS
DESCRIPTION IDENTIFICATION PART NUMBER

SIGNAL SUB PWB Comes with Signal PWB JT20471
RAINFOREST IC TA1298AN IX01 CP05662U
RED OUTPUT QX23 2325691R
GREEN OUTPUT QX28 2325691R
BLUE OUTPUT QX33 2325691R
VM OUTPUT QX41 2320637M
POWER / DEFLECTION PWB JT20491
Bridge Rectifier RBV-406M (60V) DP01 2338313
RAW 150 Vdc Protector EP91 AZ00109M
220V (Screen Voltage) Protector EP92 AZ00107M
Regulator Protector EP93 AZ00101M
Heater and SW+8V Protector EP94 AZ00109M
SW-8V Protector EP95 AZ00109M
+28V Protector (Convergence) EP96 AZ00421M
M28V Protector (Convergence) EP97 AZ00421M
120V Protector (Deflection) EP98 AZ00106M
High Voltage Driver IC (Regulator) M62501P IH02 CP07091
+5V Regulator (for DCU) IK01 CP05571
Convergence Mute IC IK02 CP01631R
+5V Regulator (for SRAM DCU) IK03 CP05571
Convergence Output (RH, RV & GV) IK04 CZ00431
Convergence Output (GH, BH & BV) IK05 CZ00431
Switching Regulator (Driver IC) IP01 CZ00865
Heater Regulator IP02 CP05141
120V Regulator IP03 2381349
120V Regulator (Photo Coupler) IP04 2000465
Vertical Output I601 CP06891
Side Pin Cushion (Comparator) I651 2365452
Horizontal Driver IC (TA1300AN) I701 CP06551
Horizontal Output (High Voltage) QH01 CF02541
Shut Down SCR QP01 2323782R
120V B+ Excessive Current Sensor QP02 2321112M
Short Detection Sensor Transistor QP03 2320637M
Horizontal Vcc ON/OFF SW QP04 2327461
Horizontal Output (Deflection) Q777 CF02511F
Deflection Horizontal Output Driver Q751 2326216
Deflection Power Supply Relay (On Sub Power PWB) S901 FJ00142
Flyback Transformer (High Voltage) TH01 BW00634
MAIN CHASSIS UE07341
SIGNAL PWB JT20471
MICROPROCESSOR (MN102H51KHPP) I001 CP07162U
MEMORY EEPROM I002 CK32542R
RESET IC I006 CP06941R
FRONT AUDIO OUTPUT IC IC01 2004751
POWER ON / OFF Relay Driver Q002 2320647M
+3.3 Volt REGULATOR Micro. B+ Q029 2312171
MAIN TUNER V6-A30FT U001 HC00311
PinP TUNER V8-A68CT U002 HC00401
3D/YC COMB FILTER KC-301S U204 HP00705
FLEX CONVERTER (HC5611) U205 CS00491
PAGE 09-01
TERMINAL PWB JT20481

A/V SELECT IC I401 CK30941U
2-Line COMB FILTER for PinP Only I402 CW00022
SUB VIDEO A/V SELECTOR IC (TA1270BF) I403 CK07923U
SURROUND PWB JT20531
SURROUND DAC IC IS01 CK31071R
FRONT AUDIO CONTROL IS03 CK33691R
FRONT GRAPHIC EQUALIZATION IS05 CP06901U
CENTER/SUBWOOFER AUDIO CONTROL IS08 CK33691R
CENTER GRAPHIC EQUALIZER IS10 CP06901U
REAR AUDIO CONTROL IS11 CK33691R
CENTER AUDIO OUTPUT IC IS15 2004751
REAR AUDIO OUTPUT IC IS16 2004751
COAXIAL/OPTICAL IC IS17 CK32011R
COAXIAL/OPTICAL INVERTER IC IS18 CK34031R
PERFECT VOLUME IS19 CP02601
DIGITAL Convergence Unit (HC2151) UKDG CS00451
SUB POWER PWB Signal Power (Low Voltage) JT20501
BRIDGE RECTIFIER D901 2338313
RAW 150V PROTECTOR E991 AZ00109M
FRONT/REAR AUDIO +28V PROTECTOR E992 AZ00109M
CENTER +28V PROTECTOR E993 AZ00109M
STBY+35V PROTECTOR E994 AZ00108M
-14V PROTECTOR E995 AZ00108M
MAIN FUSE F901 2722359
SWITCHING REGULATOR I901 CZ00864
REGULATOR FEEDBACK (Photo Coupler) I902 2000465
SHUT DOWN (Photo Coupler) I903 2000465
CLOCK (AC Photo Coupler) I904 2000465
STANDBY +7V REGULATOR I905 CP03922F
STANDBY +11V REGULATOR I906 CP03923F
STAND BY 12V (A12V) REGULATOR I907 CP03922F
ON/OFF CONTROL Q903 2320591M
SHUT DOWN SCR Q905 2323782R
AUDIO RELAY DRIVER Q911 2320591M
ON/OFF RELAY (Deflection B+) S901 FJ00142
AUDIO RELAY S902 FJ00142
STANDBY +35 VOLT RELAY S903 FJ00142
DIGITAL SURROUND PROCESSOR HC4051 US01 CS00481
CONTROL PANEL PWB
INFRARED RECEIVER HM01 CZ00941
VELOCITY MODULATION PWB Comes with CRT PWBs JT20511
CRT PWB Comes with Velocity Modulation PWB JT20511
RED DRIVER Q805 2312372F
GREEN DRIVER Q855 2312372F
BLUE DRIVER Q8A5 2312372F
RED CRT SOCKET E801 EY00941
GREEN CRT SOCKET E851 EY00941
BLUE CRT SOCKET E8A1 EY00941
PAGE 09-02
ADDITIONAL PARTS INFORMATION

REMOTE CONTROL CLU-752TSI HL01322
SCREEN ASSY. 53” KR01162
SCREEN ASSY. 61” KR01161
BLUE CRT ASSY. 53” UE07893
GREEN CRT ASSY 53” UE07892
RED CRT ASSY 53” UE07891
BLUE CRT ASSY. 61” UE07896
GREEN CRT ASSY 61” UE07895
RED CRT ASSY 61” UE07894
MIRROR GLASS (61”) GLASS KS00163
MIRROR GLASS (53”) GLASS KS02021
FOCUS PACK TYPE MHF116 AZ0006
DEFLECTION YOKE BY01551
SOLAR BATTERY (MF Sensors) FT00011
CONVERGENCE JIG OVERLAY (Progressive) H310359
CONVERGENCE JIG OVERLAY (HD) H312184
SBB LENS Assy. BLUE 53” KQ00371K
SBB LENS Assy. BLUE 61” KQ00431K
SBB LENS Assy. GREEN 53” KQ00374K
SBB LENS Assy. GREEN 61” KQ00434K
SBB LENS Assy. RED 53” KQ00375K
SBB LENS Assy. RED 61” KQ00435K
ULTRA SHIELD 61” KR01573
ULTRA SHIELD 53” KR01291
SPEAKER GRILLE 61SDX01B PH06772
SPEAKER GRILLE ASSY 53SDX01B PH07412
ANTENNA SWITCH HP00771
ANTENNA SWITCH HP00771
PAGE 09-03

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JANUARY 19, 2001 Training Materials Prepared by: ALVIE RODGERS C.E.T.

CONTENTS... 2000 DP-0X Chassis Projection Television Information

DP-0X CHASSIS TABLE OF CONTENTS

DP-0X CHASSIS TABLE OF CONTENTS

SECTION (4) VIDEO CIRCUIT INFORMATION:

SECTION (5) AUDIO CIRCUIT INFORMATION:

SECTION (6) DIGITAL CONVERGENCE CIRCUIT INFORMATION:

DP-0X CHASSIS TABLE OF CONTENTS

SECTION (7) DEFLECTION CIRCUIT:

SECTION (8) ADJUSTMENTS:

SECTION (9) KEY COMPONENTS:

S Input Yes Yes Yes Yes Yes Yes Yes Yes

ModelNo Chassis ModelNo Chassis ModelNo Chassis

Chassis ModelNo Chassis ModelNo Chassis ModelNo

ModelNo Chassis ModelNo Chassis ModelNo Chassis

Chassis ModelNo Chassis ModelNo Chassis ModelNo

(MONO) PBCB (MONO) PBCB (MONO)

(MONO) PBCB (MONO) PBCB (MONO)

CONTROL OF THE PROJECTION TELEVISION:

The following section will explain the controls listed above.

Continued on Next Page

Receiving Infrared Remote Control Commands:

Receiving Key Input Commands:

Interaction between the Customer’s Menu and Chassis controls.

Outputting On Screen Display information.

PINS CONTROLLED ICs

B+ Distribution Video Det Video

Data Clock Load AFC

Actual Signal After passing through a capacitor After Time Compression

Figure 3 Figure 4 Figure 5

Original Signal Transition Point pulses Transition Pulses Added

Figure 6 Figure 7 Figure 8

Controlling the Audio Circuits when directed by the Customer.

35 IREF Internal function of the Microprocessor. DC

64 VSS Ground. N/A

Power On/Off 53 I014

Rear Audio SDA 57 SDA3 DSP S0 13

SCL IRef 35 SCL

P Blk. 56 DSPSS 15 N/A

VMute 45 DSPRST 19 N/A

SCL SCL2 60 SCL

Ft. Panel Control Keys 5 AD

ON THE SIGNAL PWB:

ON THE TERMINAL PWB:

ON THE DEFLECTION PWB:

ON THE SUB VIDEO PWB (2H VIDEO):

ON THE SURROUND PWB:

PinP Tuner U202

Flex Converter U205

(Continued on page 15)

Level Shift I014

Main Video Chroma I201

(Continued on page 16)

Sub Video Chroma I403

ON THE DEFLECTION PWB:

ON THE SUB VIDEO PWB (2H VIDEO):

ON THE SURROUND PWB:

(Continued on page 17)

Front Audio Control IS03

Center/LFE (Low Frequency Effects) Audio Control IS08

Front Equalizer IS05

Center Equalizer IS10

Rear Audio Control IS11